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review.evervolv.com / android_kernel_oneplus_msm8996 / a679128d30d0303bbf5cac839c8f6f45793ea775 / . / drivers / net / wireless / wl12xx / reg.h
blob: e421643215cdb0bcab4aadc048cdd54649de7ca1 [file] [log] [blame]
Kalle Valo2f01a1f2009-04-29 23:33:31 +0300[diff] [blame]1/*
2 * This file is part of wl12xx
3 *
4 * Copyright (c) 1998-2007 Texas Instruments Incorporated
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * Contact: Kalle Valo <kalle.valo@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef __REG_H__
26#define __REG_H__
27
28#include <linux/bitops.h>
29#include "wl12xx.h"
30
31#define REGISTERS_BASE 0x00300000
32#define DRPW_BASE 0x00310000
33
34#define REGISTERS_DOWN_SIZE 0x00008800
35#define REGISTERS_WORK_SIZE 0x0000b000
36
37#define HW_ACCESS_ELP_CTRL_REG_ADDR 0x1FFFC
38
39/* ELP register commands */
40#define ELPCTRL_WAKE_UP 0x1
41#define ELPCTRL_WAKE_UP_WLAN_READY 0x5
42#define ELPCTRL_SLEEP 0x0
43/* ELP WLAN_READY bit */
44#define ELPCTRL_WLAN_READY 0x2
45
46/*
47 * Interrupt registers.
48 * 64 bit interrupt sources registers ws ced.
49 * sme interupts were removed and new ones were added.
50 * Order was changed.
51 */
52#define FIQ_MASK (REGISTERS_BASE + 0x0400)
53#define FIQ_MASK_L (REGISTERS_BASE + 0x0400)
54#define FIQ_MASK_H (REGISTERS_BASE + 0x0404)
55#define FIQ_MASK_SET (REGISTERS_BASE + 0x0408)
56#define FIQ_MASK_SET_L (REGISTERS_BASE + 0x0408)
57#define FIQ_MASK_SET_H (REGISTERS_BASE + 0x040C)
58#define FIQ_MASK_CLR (REGISTERS_BASE + 0x0410)
59#define FIQ_MASK_CLR_L (REGISTERS_BASE + 0x0410)
60#define FIQ_MASK_CLR_H (REGISTERS_BASE + 0x0414)
61#define IRQ_MASK (REGISTERS_BASE + 0x0418)
62#define IRQ_MASK_L (REGISTERS_BASE + 0x0418)
63#define IRQ_MASK_H (REGISTERS_BASE + 0x041C)
64#define IRQ_MASK_SET (REGISTERS_BASE + 0x0420)
65#define IRQ_MASK_SET_L (REGISTERS_BASE + 0x0420)
66#define IRQ_MASK_SET_H (REGISTERS_BASE + 0x0424)
67#define IRQ_MASK_CLR (REGISTERS_BASE + 0x0428)
68#define IRQ_MASK_CLR_L (REGISTERS_BASE + 0x0428)
69#define IRQ_MASK_CLR_H (REGISTERS_BASE + 0x042C)
70#define ECPU_MASK (REGISTERS_BASE + 0x0448)
71#define FIQ_STS_L (REGISTERS_BASE + 0x044C)
72#define FIQ_STS_H (REGISTERS_BASE + 0x0450)
73#define IRQ_STS_L (REGISTERS_BASE + 0x0454)
74#define IRQ_STS_H (REGISTERS_BASE + 0x0458)
75#define INT_STS_ND (REGISTERS_BASE + 0x0464)
76#define INT_STS_RAW_L (REGISTERS_BASE + 0x0464)
77#define INT_STS_RAW_H (REGISTERS_BASE + 0x0468)
78#define INT_STS_CLR (REGISTERS_BASE + 0x04B4)
79#define INT_STS_CLR_L (REGISTERS_BASE + 0x04B4)
80#define INT_STS_CLR_H (REGISTERS_BASE + 0x04B8)
81#define INT_ACK (REGISTERS_BASE + 0x046C)
82#define INT_ACK_L (REGISTERS_BASE + 0x046C)
83#define INT_ACK_H (REGISTERS_BASE + 0x0470)
84#define INT_TRIG (REGISTERS_BASE + 0x0474)
85#define INT_TRIG_L (REGISTERS_BASE + 0x0474)
86#define INT_TRIG_H (REGISTERS_BASE + 0x0478)
87#define HOST_STS_L (REGISTERS_BASE + 0x045C)
88#define HOST_STS_H (REGISTERS_BASE + 0x0460)
89#define HOST_MASK (REGISTERS_BASE + 0x0430)
90#define HOST_MASK_L (REGISTERS_BASE + 0x0430)
91#define HOST_MASK_H (REGISTERS_BASE + 0x0434)
92#define HOST_MASK_SET (REGISTERS_BASE + 0x0438)
93#define HOST_MASK_SET_L (REGISTERS_BASE + 0x0438)
94#define HOST_MASK_SET_H (REGISTERS_BASE + 0x043C)
95#define HOST_MASK_CLR (REGISTERS_BASE + 0x0440)
96#define HOST_MASK_CLR_L (REGISTERS_BASE + 0x0440)
97#define HOST_MASK_CLR_H (REGISTERS_BASE + 0x0444)
98
99/* Host Interrupts*/
100#define HINT_MASK (REGISTERS_BASE + 0x0494)
101#define HINT_MASK_SET (REGISTERS_BASE + 0x0498)
102#define HINT_MASK_CLR (REGISTERS_BASE + 0x049C)
103#define HINT_STS_ND_MASKED (REGISTERS_BASE + 0x04A0)
104/*1150 spec calls this HINT_STS_RAW*/
105#define HINT_STS_ND (REGISTERS_BASE + 0x04B0)
106#define HINT_STS_CLR (REGISTERS_BASE + 0x04A4)
107#define HINT_ACK (REGISTERS_BASE + 0x04A8)
108#define HINT_TRIG (REGISTERS_BASE + 0x04AC)
109
110/* Device Configuration registers*/
111#define SOR_CFG (REGISTERS_BASE + 0x0800)
112#define ECPU_CTRL (REGISTERS_BASE + 0x0804)
113#define HI_CFG (REGISTERS_BASE + 0x0808)
114#define EE_START (REGISTERS_BASE + 0x080C)
115
116#define CHIP_ID_B (REGISTERS_BASE + 0x5674)
117
118#define CHIP_ID_1251_PG10 (0x7010101)
119#define CHIP_ID_1251_PG11 (0x7020101)
120#define CHIP_ID_1251_PG12 (0x7030101)
121
122#define ENABLE (REGISTERS_BASE + 0x5450)
123
124/* Power Management registers */
125#define ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
126#define ELP_CMD (REGISTERS_BASE + 0x5808)
127#define PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
128#define CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
129#define CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
130
131#define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
132
133/* Scratch Pad registers*/
134#define SCR_PAD0 (REGISTERS_BASE + 0x5608)
135#define SCR_PAD1 (REGISTERS_BASE + 0x560C)
136#define SCR_PAD2 (REGISTERS_BASE + 0x5610)
137#define SCR_PAD3 (REGISTERS_BASE + 0x5614)
138#define SCR_PAD4 (REGISTERS_BASE + 0x5618)
139#define SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
140#define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
141#define SCR_PAD5 (REGISTERS_BASE + 0x5624)
142#define SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
143#define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
144#define SCR_PAD6 (REGISTERS_BASE + 0x5630)
145#define SCR_PAD7 (REGISTERS_BASE + 0x5634)
146#define SCR_PAD8 (REGISTERS_BASE + 0x5638)
147#define SCR_PAD9 (REGISTERS_BASE + 0x563C)
148
149/* Spare registers*/
150#define SPARE_A1 (REGISTERS_BASE + 0x0994)
151#define SPARE_A2 (REGISTERS_BASE + 0x0998)
152#define SPARE_A3 (REGISTERS_BASE + 0x099C)
153#define SPARE_A4 (REGISTERS_BASE + 0x09A0)
154#define SPARE_A5 (REGISTERS_BASE + 0x09A4)
155#define SPARE_A6 (REGISTERS_BASE + 0x09A8)
156#define SPARE_A7 (REGISTERS_BASE + 0x09AC)
157#define SPARE_A8 (REGISTERS_BASE + 0x09B0)
158#define SPARE_B1 (REGISTERS_BASE + 0x5420)
159#define SPARE_B2 (REGISTERS_BASE + 0x5424)
160#define SPARE_B3 (REGISTERS_BASE + 0x5428)
161#define SPARE_B4 (REGISTERS_BASE + 0x542C)
162#define SPARE_B5 (REGISTERS_BASE + 0x5430)
163#define SPARE_B6 (REGISTERS_BASE + 0x5434)
164#define SPARE_B7 (REGISTERS_BASE + 0x5438)
165#define SPARE_B8 (REGISTERS_BASE + 0x543C)
166
167enum wl12xx_acx_int_reg {
168 ACX_REG_INTERRUPT_TRIG,
169 ACX_REG_INTERRUPT_TRIG_H,
170
171/*=============================================
172 Host Interrupt Mask Register - 32bit (RW)
173 ------------------------------------------
174 Setting a bit in this register masks the
175 corresponding interrupt to the host.
176 0 - RX0 - Rx first dubble buffer Data Interrupt
177 1 - TXD - Tx Data Interrupt
178 2 - TXXFR - Tx Transfer Interrupt
179 3 - RX1 - Rx second dubble buffer Data Interrupt
180 4 - RXXFR - Rx Transfer Interrupt
181 5 - EVENT_A - Event Mailbox interrupt
182 6 - EVENT_B - Event Mailbox interrupt
183 7 - WNONHST - Wake On Host Interrupt
184 8 - TRACE_A - Debug Trace interrupt
185 9 - TRACE_B - Debug Trace interrupt
186 10 - CDCMP - Command Complete Interrupt
187 11 -
188 12 -
189 13 -
190 14 - ICOMP - Initialization Complete Interrupt
191 16 - SG SE - Soft Gemini - Sense enable interrupt
192 17 - SG SD - Soft Gemini - Sense disable interrupt
193 18 - -
194 19 - -
195 20 - -
196 21- -
197 Default: 0x0001
198*==============================================*/
199 ACX_REG_INTERRUPT_MASK,
200
201/*=============================================
202 Host Interrupt Mask Set 16bit, (Write only)
203 ------------------------------------------
204 Setting a bit in this register sets
205 the corresponding bin in ACX_HINT_MASK register
206 without effecting the mask
207 state of other bits (0 = no effect).
208==============================================*/
209 ACX_REG_HINT_MASK_SET,
210
211/*=============================================
212 Host Interrupt Mask Clear 16bit,(Write only)
213 ------------------------------------------
214 Setting a bit in this register clears
215 the corresponding bin in ACX_HINT_MASK register
216 without effecting the mask
217 state of other bits (0 = no effect).
218=============================================*/
219 ACX_REG_HINT_MASK_CLR,
220
221/*=============================================
222 Host Interrupt Status Nondestructive Read
223 16bit,(Read only)
224 ------------------------------------------
225 The host can read this register to determine
226 which interrupts are active.
227 Reading this register doesn't
228 effect its content.
229=============================================*/
230 ACX_REG_INTERRUPT_NO_CLEAR,
231
232/*=============================================
233 Host Interrupt Status Clear on Read Register
234 16bit,(Read only)
235 ------------------------------------------
236 The host can read this register to determine
237 which interrupts are active.
238 Reading this register clears it,
239 thus making all interrupts inactive.
240==============================================*/
241 ACX_REG_INTERRUPT_CLEAR,
242
243/*=============================================
244 Host Interrupt Acknowledge Register
245 16bit,(Write only)
246 ------------------------------------------
247 The host can set individual bits in this
248 register to clear (acknowledge) the corresp.
249 interrupt status bits in the HINT_STS_CLR and
250 HINT_STS_ND registers, thus making the
251 assotiated interrupt inactive. (0-no effect)
252==============================================*/
253 ACX_REG_INTERRUPT_ACK,
254
255/*===============================================
256 Host Software Reset - 32bit RW
257 ------------------------------------------
258 [31:1] Reserved
259 0 SOFT_RESET Soft Reset - When this bit is set,
260 it holds the Wlan hardware in a soft reset state.
261 This reset disables all MAC and baseband processor
262 clocks except the CardBus/PCI interface clock.
263 It also initializes all MAC state machines except
264 the host interface. It does not reload the
265 contents of the EEPROM. When this bit is cleared
266 (not self-clearing), the Wlan hardware
267 exits the software reset state.
268===============================================*/
269 ACX_REG_SLV_SOFT_RESET,
270
271/*===============================================
272 EEPROM Burst Read Start - 32bit RW
273 ------------------------------------------
274 [31:1] Reserved
275 0 ACX_EE_START - EEPROM Burst Read Start 0
276 Setting this bit starts a burst read from
277 the external EEPROM.
278 If this bit is set (after reset) before an EEPROM read/write,
279 the burst read starts at EEPROM address 0.
280 Otherwise, it starts at the address
281 following the address of the previous access.
282 TheWlan hardware hardware clears this bit automatically.
283
284 Default: 0x00000000
285*================================================*/
286 ACX_REG_EE_START,
287
288/* Embedded ARM CPU Control */
289
290/*===============================================
291 Halt eCPU - 32bit RW
292 ------------------------------------------
293 0 HALT_ECPU Halt Embedded CPU - This bit is the
294 compliment of bit 1 (MDATA2) in the SOR_CFG register.
295 During a hardware reset, this bit holds
296 the inverse of MDATA2.
297 When downloading firmware from the host,
298 set this bit (pull down MDATA2).
299 The host clears this bit after downloading the firmware into
300 zero-wait-state SSRAM.
301 When loading firmware from Flash, clear this bit (pull up MDATA2)
302 so that the eCPU can run the bootloader code in Flash
303 HALT_ECPU eCPU State
304 --------------------
305 1 halt eCPU
306 0 enable eCPU
307 ===============================================*/
308 ACX_REG_ECPU_CONTROL,
309
310 ACX_REG_TABLE_LEN
311};
312
313#define ACX_SLV_SOFT_RESET_BIT BIT(1)
314#define ACX_REG_EEPROM_START_BIT BIT(1)
315
316/* Command/Information Mailbox Pointers */
317
318/*===============================================
319 Command Mailbox Pointer - 32bit RW
320 ------------------------------------------
321 This register holds the start address of
322 the command mailbox located in the Wlan hardware memory.
323 The host must read this pointer after a reset to
324 find the location of the command mailbox.
325 The Wlan hardware initializes the command mailbox
326 pointer with the default address of the command mailbox.
327 The command mailbox pointer is not valid until after
328 the host receives the Init Complete interrupt from
329 the Wlan hardware.
330 ===============================================*/
331#define REG_COMMAND_MAILBOX_PTR (SCR_PAD0)
332
333/*===============================================
334 Information Mailbox Pointer - 32bit RW
335 ------------------------------------------
336 This register holds the start address of
337 the information mailbox located in the Wlan hardware memory.
338 The host must read this pointer after a reset to find
339 the location of the information mailbox.
340 The Wlan hardware initializes the information mailbox pointer
341 with the default address of the information mailbox.
342 The information mailbox pointer is not valid
343 until after the host receives the Init Complete interrupt from
344 the Wlan hardware.
345 ===============================================*/
346#define REG_EVENT_MAILBOX_PTR (SCR_PAD1)
347
348
349/* Misc */
350
351#define REG_ENABLE_TX_RX (ENABLE)
352/*
353 * Rx configuration (filter) information element
354 * ---------------------------------------------
355 */
356#define REG_RX_CONFIG (RX_CFG)
357#define REG_RX_FILTER (RX_FILTER_CFG)
358
359
360#define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002
361
362/* promiscuous - receives all valid frames */
363#define RX_CFG_PROMISCUOUS 0x0008
364
365/* receives frames from any BSSID */
366#define RX_CFG_BSSID 0x0020
367
368/* receives frames destined to any MAC address */
369#define RX_CFG_MAC 0x0010
370
371#define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010
372#define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000
373#define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020
374#define RX_CFG_ENABLE_ANY_BSSID 0x0000
375
376/* discards all broadcast frames */
377#define RX_CFG_DISABLE_BCAST 0x0200
378
379#define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400
380#define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800
381#define RX_CFG_COPY_RX_STATUS 0x2000
382#define RX_CFG_TSF 0x10000
383
384#define RX_CONFIG_OPTION_ANY_DST_MY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \
385 RX_CFG_ENABLE_ONLY_MY_BSSID)
386
387#define RX_CONFIG_OPTION_MY_DST_ANY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
388 | RX_CFG_ENABLE_ANY_BSSID)
389
390#define RX_CONFIG_OPTION_ANY_DST_ANY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \
391 RX_CFG_ENABLE_ANY_BSSID)
392
393#define RX_CONFIG_OPTION_MY_DST_MY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
394 | RX_CFG_ENABLE_ONLY_MY_BSSID)
395
396#define RX_CONFIG_OPTION_FOR_SCAN (RX_CFG_ENABLE_PHY_HEADER_PLCP \
397 | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR \
398 | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF)
399
400#define RX_CONFIG_OPTION_FOR_MEASUREMENT (RX_CFG_ENABLE_ANY_DEST_MAC)
401
402#define RX_CONFIG_OPTION_FOR_JOIN (RX_CFG_ENABLE_ONLY_MY_BSSID | \
403 RX_CFG_ENABLE_ONLY_MY_DEST_MAC)
404
405#define RX_CONFIG_OPTION_FOR_IBSS_JOIN (RX_CFG_ENABLE_ONLY_MY_SSID | \
406 RX_CFG_ENABLE_ONLY_MY_DEST_MAC)
407
408#define RX_FILTER_OPTION_DEF (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
409 | CFG_RX_CTL_EN | CFG_RX_BCN_EN\
410 | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)
411
412#define RX_FILTER_OPTION_FILTER_ALL 0
413
414#define RX_FILTER_OPTION_DEF_PRSP_BCN (CFG_RX_PRSP_EN | CFG_RX_MGMT_EN\
415 | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN)
416
417#define RX_FILTER_OPTION_JOIN (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
418 | CFG_RX_BCN_EN | CFG_RX_AUTH_EN\
419 | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK\
420 | CFG_RX_PRSP_EN)
421
422
423/*===============================================
424 Phy regs
425 ===============================================*/
426#define ACX_PHY_ADDR_REG SBB_ADDR
427#define ACX_PHY_DATA_REG SBB_DATA
428#define ACX_PHY_CTRL_REG SBB_CTL
429#define ACX_PHY_REG_WR_MASK 0x00000001ul
430#define ACX_PHY_REG_RD_MASK 0x00000002ul
431
432
433/*===============================================
434 EEPROM Read/Write Request 32bit RW
435 ------------------------------------------
436 1 EE_READ - EEPROM Read Request 1 - Setting this bit
437 loads a single byte of data into the EE_DATA
438 register from the EEPROM location specified in
439 the EE_ADDR register.
440 The Wlan hardware hardware clears this bit automatically.
441 EE_DATA is valid when this bit is cleared.
442
443 0 EE_WRITE - EEPROM Write Request - Setting this bit
444 writes a single byte of data from the EE_DATA register into the
445 EEPROM location specified in the EE_ADDR register.
446 The Wlan hardware hardware clears this bit automatically.
447*===============================================*/
448#define ACX_EE_CTL_REG EE_CTL
449#define EE_WRITE 0x00000001ul
450#define EE_READ 0x00000002ul
451
452/*===============================================
453 EEPROM Address - 32bit RW
454 ------------------------------------------
455 This register specifies the address
456 within the EEPROM from/to which to read/write data.
457 ===============================================*/
458#define ACX_EE_ADDR_REG EE_ADDR
459
460/*===============================================
461 EEPROM Data - 32bit RW
462 ------------------------------------------
463 This register either holds the read 8 bits of
464 data from the EEPROM or the write data
465 to be written to the EEPROM.
466 ===============================================*/
467#define ACX_EE_DATA_REG EE_DATA
468
469/*===============================================
470 EEPROM Base Address - 32bit RW
471 ------------------------------------------
472 This register holds the upper nine bits
473 [23:15] of the 24-bit Wlan hardware memory
474 address for burst reads from EEPROM accesses.
475 The EEPROM provides the lower 15 bits of this address.
476 The MSB of the address from the EEPROM is ignored.
477 ===============================================*/
478#define ACX_EE_CFG EE_CFG
479
480/*===============================================
481 GPIO Output Values -32bit, RW
482 ------------------------------------------
483 [31:16] Reserved
484 [15: 0] Specify the output values (at the output driver inputs) for
485 GPIO[15:0], respectively.
486 ===============================================*/
487#define ACX_GPIO_OUT_REG GPIO_OUT
488#define ACX_MAX_GPIO_LINES 15
489
490/*===============================================
491 Contention window -32bit, RW
492 ------------------------------------------
493 [31:26] Reserved
494 [25:16] Max (0x3ff)
495 [15:07] Reserved
496 [06:00] Current contention window value - default is 0x1F
497 ===============================================*/
498#define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG
499#define ACX_CONT_WIND_MIN_MASK 0x0000007f
500#define ACX_CONT_WIND_MAX 0x03ff0000
501
502/*
503 * Indirect slave register/memory registers
504 * ----------------------------------------
505 */
506#define HW_SLAVE_REG_ADDR_REG 0x00000004
507#define HW_SLAVE_REG_DATA_REG 0x00000008
508#define HW_SLAVE_REG_CTRL_REG 0x0000000c
509
510#define SLAVE_AUTO_INC 0x00010000
511#define SLAVE_NO_AUTO_INC 0x00000000
512#define SLAVE_HOST_LITTLE_ENDIAN 0x00000000
513
514#define HW_SLAVE_MEM_ADDR_REG SLV_MEM_ADDR
515#define HW_SLAVE_MEM_DATA_REG SLV_MEM_DATA
516#define HW_SLAVE_MEM_CTRL_REG SLV_MEM_CTL
517#define HW_SLAVE_MEM_ENDIAN_REG SLV_END_CTL
518
519#define HW_FUNC_EVENT_INT_EN 0x8000
520#define HW_FUNC_EVENT_MASK_REG 0x00000034
521
522#define ACX_MAC_TIMESTAMP_REG (MAC_TIMESTAMP)
523
524/*===============================================
525 HI_CFG Interface Configuration Register Values
526 ------------------------------------------
527 ===============================================*/
528#define HI_CFG_UART_ENABLE 0x00000004
529#define HI_CFG_RST232_ENABLE 0x00000008
530#define HI_CFG_CLOCK_REQ_SELECT 0x00000010
531#define HI_CFG_HOST_INT_ENABLE 0x00000020
532#define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040
533#define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080
534#define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100
535#define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200
536#define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400
537
538/*
539 * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile
540 * for platforms using active high interrupt level
541 */
542#ifdef USE_ACTIVE_HIGH
543#define HI_CFG_DEF_VAL \
544 (HI_CFG_UART_ENABLE | \
545 HI_CFG_RST232_ENABLE | \
546 HI_CFG_CLOCK_REQ_SELECT | \
547 HI_CFG_HOST_INT_ENABLE)
548#else
549#define HI_CFG_DEF_VAL \
550 (HI_CFG_UART_ENABLE | \
551 HI_CFG_RST232_ENABLE | \
552 HI_CFG_CLOCK_REQ_SELECT | \
553 HI_CFG_HOST_INT_ENABLE)
554
555#endif
556
557#define REF_FREQ_19_2 0
558#define REF_FREQ_26_0 1
559#define REF_FREQ_38_4 2
560#define REF_FREQ_40_0 3
561#define REF_FREQ_33_6 4
562#define REF_FREQ_NUM 5
563
564#define LUT_PARAM_INTEGER_DIVIDER 0
565#define LUT_PARAM_FRACTIONAL_DIVIDER 1
566#define LUT_PARAM_ATTN_BB 2
567#define LUT_PARAM_ALPHA_BB 3
568#define LUT_PARAM_STOP_TIME_BB 4
569#define LUT_PARAM_BB_PLL_LOOP_FILTER 5
570#define LUT_PARAM_NUM 6
571
572#define ACX_EEPROMLESS_IND_REG (SCR_PAD4)
573#define USE_EEPROM 0
574#define SOFT_RESET_MAX_TIME 1000000
575#define SOFT_RESET_STALL_TIME 1000
576#define NVS_DATA_BUNDARY_ALIGNMENT 4
577
578
579/* Firmware image load chunk size */
580#define CHUNK_SIZE 512
581
582/* Firmware image header size */
583#define FW_HDR_SIZE 8
584
585#define ECPU_CONTROL_HALT 0x00000101
586
587
588/******************************************************************************
589
590 CHANNELS, BAND & REG DOMAINS definitions
591
592******************************************************************************/
593
594
595enum {
596 RADIO_BAND_2_4GHZ = 0, /* 2.4 Ghz band */
597 RADIO_BAND_5GHZ = 1, /* 5 Ghz band */
598 RADIO_BAND_JAPAN_4_9_GHZ = 2,
599 DEFAULT_BAND = RADIO_BAND_2_4GHZ,
600 INVALID_BAND = 0xFE,
601 MAX_RADIO_BANDS = 0xFF
602};
603
604enum {
605 NO_RATE = 0,
606 RATE_1MBPS = 0x0A,
607 RATE_2MBPS = 0x14,
608 RATE_5_5MBPS = 0x37,
609 RATE_6MBPS = 0x0B,
610 RATE_9MBPS = 0x0F,
611 RATE_11MBPS = 0x6E,
612 RATE_12MBPS = 0x0A,
613 RATE_18MBPS = 0x0E,
614 RATE_22MBPS = 0xDC,
615 RATE_24MBPS = 0x09,
616 RATE_36MBPS = 0x0D,
617 RATE_48MBPS = 0x08,
618 RATE_54MBPS = 0x0C
619};
620
621enum {
622 RATE_INDEX_1MBPS = 0,
623 RATE_INDEX_2MBPS = 1,
624 RATE_INDEX_5_5MBPS = 2,
625 RATE_INDEX_6MBPS = 3,
626 RATE_INDEX_9MBPS = 4,
627 RATE_INDEX_11MBPS = 5,
628 RATE_INDEX_12MBPS = 6,
629 RATE_INDEX_18MBPS = 7,
630 RATE_INDEX_22MBPS = 8,
631 RATE_INDEX_24MBPS = 9,
632 RATE_INDEX_36MBPS = 10,
633 RATE_INDEX_48MBPS = 11,
634 RATE_INDEX_54MBPS = 12,
635 RATE_INDEX_MAX = RATE_INDEX_54MBPS,
636 MAX_RATE_INDEX,
637 INVALID_RATE_INDEX = MAX_RATE_INDEX,
638 RATE_INDEX_ENUM_MAX_SIZE = 0x7FFFFFFF
639};
640
641enum {
642 RATE_MASK_1MBPS = 0x1,
643 RATE_MASK_2MBPS = 0x2,
644 RATE_MASK_5_5MBPS = 0x4,
645 RATE_MASK_11MBPS = 0x20,
646};
647
648#define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */
649#define OFDM_RATE_BIT BIT(6)
650#define PBCC_RATE_BIT BIT(7)
651
652enum {
653 CCK_LONG = 0,
654 CCK_SHORT = SHORT_PREAMBLE_BIT,
655 PBCC_LONG = PBCC_RATE_BIT,
656 PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT,
657 OFDM = OFDM_RATE_BIT
658};
659
660/******************************************************************************
661
662Transmit-Descriptor RATE-SET field definitions...
663
664Define a new "Rate-Set" for TX path that incorporates the
665Rate & Modulation info into a single 16-bit field.
666
667TxdRateSet_t:
668b15 - Indicates Preamble type (1=SHORT, 0=LONG).
669 Notes:
670 Must be LONG (0) for 1Mbps rate.
671 Does not apply (set to 0) for RevG-OFDM rates.
672b14 - Indicates PBCC encoding (1=PBCC, 0=not).
673 Notes:
674 Does not apply (set to 0) for rates 1 and 2 Mbps.
675 Does not apply (set to 0) for RevG-OFDM rates.
676b13 - Unused (set to 0).
677b12-b0 - Supported Rate indicator bits as defined below.
678
679******************************************************************************/
680
681
682#define TNETW1251_CHIP_ID_PG1_0 0x07010101
683#define TNETW1251_CHIP_ID_PG1_1 0x07020101
684#define TNETW1251_CHIP_ID_PG1_2 0x07030101
685
686/*************************************************************************
687
688 Interrupt Trigger Register (Host -> WiLink)
689
690**************************************************************************/
691
692/* Hardware to Embedded CPU Interrupts - first 32-bit register set */
693
694/*
695 * Host Command Interrupt. Setting this bit masks
696 * the interrupt that the host issues to inform
697 * the FW that it has sent a command
698 * to the Wlan hardware Command Mailbox.
699 */
700#define INTR_TRIG_CMD BIT(0)
701
702/*
703 * Host Event Acknowlegde Interrupt. The host
704 * sets this bit to acknowledge that it received
705 * the unsolicited information from the event
706 * mailbox.
707 */
708#define INTR_TRIG_EVENT_ACK BIT(1)
709
710/*
711 * The host sets this bit to inform the Wlan
712 * FW that a TX packet is in the XFER
713 * Buffer #0.
714 */
715#define INTR_TRIG_TX_PROC0 BIT(2)
716
717/*
718 * The host sets this bit to inform the FW
719 * that it read a packet from RX XFER
720 * Buffer #0.
721 */
722#define INTR_TRIG_RX_PROC0 BIT(3)
723
724#define INTR_TRIG_DEBUG_ACK BIT(4)
725
726#define INTR_TRIG_STATE_CHANGED BIT(5)
727
728
729/* Hardware to Embedded CPU Interrupts - second 32-bit register set */
730
731/*
732 * The host sets this bit to inform the FW
733 * that it read a packet from RX XFER
734 * Buffer #1.
735 */
736#define INTR_TRIG_RX_PROC1 BIT(17)
737
738/*
739 * The host sets this bit to inform the Wlan
740 * hardware that a TX packet is in the XFER
741 * Buffer #1.
742 */
743#define INTR_TRIG_TX_PROC1 BIT(18)
744
745#endif