| Thomas Petazzoni | 9ae6f74 | 2012-06-13 19:01:28 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Include file for Marvell Armada 370 and Armada XP SoC |
| 3 | * |
| 4 | * Copyright (C) 2012 Marvell |
| 5 | * |
| 6 | * Lior Amsalem <alior@marvell.com> |
| 7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> |
| 8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| 9 | * Ben Dooks <ben.dooks@codethink.co.uk> |
| 10 | * |
| 11 | * This file is licensed under the terms of the GNU General Public |
| 12 | * License version 2. This program is licensed "as is" without any |
| 13 | * warranty of any kind, whether express or implied. |
| 14 | * |
| 15 | * This file contains the definitions that are common to the Armada |
| 16 | * 370 and Armada XP SoC. |
| 17 | */ |
| 18 | |
| 19 | /include/ "skeleton.dtsi" |
| 20 | |
| 21 | / { |
| 22 | model = "Marvell Armada 370 and XP SoC"; |
| 23 | compatible = "marvell,armada_370_xp"; |
| 24 | |
| 25 | cpus { |
| 26 | cpu@0 { |
| 27 | compatible = "marvell,sheeva-v7"; |
| 28 | }; |
| 29 | }; |
| 30 | |
| 31 | mpic: interrupt-controller@d0020000 { |
| 32 | compatible = "marvell,mpic"; |
| 33 | #interrupt-cells = <1>; |
| 34 | #address-cells = <1>; |
| 35 | #size-cells = <1>; |
| 36 | interrupt-controller; |
| 37 | }; |
| 38 | |
| 39 | soc { |
| 40 | #address-cells = <1>; |
| 41 | #size-cells = <1>; |
| 42 | compatible = "simple-bus"; |
| 43 | interrupt-parent = <&mpic>; |
| 44 | ranges; |
| 45 | |
| 46 | serial@d0012000 { |
| 47 | compatible = "ns16550"; |
| 48 | reg = <0xd0012000 0x100>; |
| 49 | reg-shift = <2>; |
| 50 | interrupts = <41>; |
| 51 | status = "disabled"; |
| 52 | }; |
| 53 | serial@d0012100 { |
| 54 | compatible = "ns16550"; |
| 55 | reg = <0xd0012100 0x100>; |
| 56 | reg-shift = <2>; |
| 57 | interrupts = <42>; |
| 58 | status = "disabled"; |
| 59 | }; |
| 60 | |
| 61 | timer@d0020300 { |
| 62 | compatible = "marvell,armada-370-xp-timer"; |
| 63 | reg = <0xd0020300 0x30>; |
| 64 | interrupts = <37>, <38>, <39>, <40>; |
| Gregory CLEMENT | 307c2bf | 2012-11-17 15:22:25 +0100 | [diff] [blame] | 65 | clocks = <&coreclk 2>; |
| Thomas Petazzoni | 9ae6f74 | 2012-06-13 19:01:28 +0200 | [diff] [blame] | 66 | }; |
| Thomas Petazzoni | 5b40bae | 2012-09-11 14:27:30 +0200 | [diff] [blame] | 67 | |
| 68 | addr-decoding@d0020000 { |
| 69 | compatible = "marvell,armada-addr-decoding-controller"; |
| 70 | reg = <0xd0020000 0x258>; |
| 71 | }; |
| Gregory CLEMENT | a6a6de1 | 2012-10-26 14:30:47 +0200 | [diff] [blame^] | 72 | |
| 73 | sata@d00a0000 { |
| 74 | compatible = "marvell,orion-sata"; |
| 75 | reg = <0xd00a0000 0x2400>; |
| 76 | interrupts = <55>; |
| 77 | clocks = <&gateclk 15>, <&gateclk 30>; |
| 78 | clock-names = "0", "1"; |
| 79 | status = "disabled"; |
| 80 | }; |
| 81 | |
| Thomas Petazzoni | 9ae6f74 | 2012-06-13 19:01:28 +0200 | [diff] [blame] | 82 | }; |
| 83 | }; |
| 84 | |