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Jacob Panaf2730f2010-02-12 10:31:47 -08001/*
2 * mrst.h: Intel Moorestown platform specific setup code
3 *
4 * (C) Copyright 2009 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; version 2
9 * of the License.
10 */
11#ifndef _ASM_X86_MRST_H
12#define _ASM_X86_MRST_H
13extern int pci_mrst_init(void);
Jacob Pana0c173b2010-05-19 12:01:24 -070014extern int mrst_identify_cpu(void);
Jacob Pana875c012010-05-19 12:01:25 -070015extern int mrst_timer_options __cpuinitdata;
Feng Tangcf089452010-02-12 03:37:38 -080016int __init sfi_parse_mrtc(struct sfi_table_header *table);
Jacob Panaf2730f2010-02-12 10:31:47 -080017
Jacob Pana0c173b2010-05-19 12:01:24 -070018/*
19 * Medfield is the follow-up of Moorestown, it combines two chip solution into
20 * one. Other than that it also added always-on and constant tsc and lapic
21 * timers. Medfield is the platform name, and the chip name is called Penwell
22 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
23 * identified via MSRs.
24 */
25enum mrst_cpu_type {
26 MRST_CPU_CHIP_LINCROFT = 1,
27 MRST_CPU_CHIP_PENWELL,
28};
29
30enum mrst_timer_options {
31 MRST_TIMER_DEFAULT,
32 MRST_TIMER_APBT_ONLY,
33 MRST_TIMER_LAPIC_APBT,
34};
35
Jacob Pan16ab5392010-02-12 03:08:30 -080036#define SFI_MTMR_MAX_NUM 8
Feng Tangcf089452010-02-12 03:37:38 -080037#define SFI_MRTC_MAX 8
Jacob Pan16ab5392010-02-12 03:08:30 -080038
Jacob Panaf2730f2010-02-12 10:31:47 -080039#endif /* _ASM_X86_MRST_H */