blob: a75ae40184aa3a5d35e08668e71022230ee087bc [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
Ralf Baechle36ccf1c2006-02-14 21:04:54 +00006 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +010011 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
Steven J. Hill2a0b24f2013-03-25 12:15:55 -050012 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 */
Ralf Baechle8e8a52e2007-05-31 14:00:19 +010014#include <linux/bug.h>
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +010015#include <linux/compiler.h>
Ralf Baechle7aa1c8f2012-10-11 18:14:58 +020016#include <linux/kexec.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/init.h>
Nathan Lynch8742cd22011-09-30 13:49:35 -050018#include <linux/kernel.h>
Paul Gortmakerf9ded5692012-02-28 19:24:46 -050019#include <linux/module.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/mm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/sched.h>
22#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#include <linux/spinlock.h>
24#include <linux/kallsyms.h>
Ralf Baechlee01402b2005-07-14 15:57:16 +000025#include <linux/bootmem.h>
Maxime Bizond4fd1982006-07-20 18:52:02 +020026#include <linux/interrupt.h>
Ralf Baechle39b8d522008-04-28 17:14:26 +010027#include <linux/ptrace.h>
Jason Wessel88547002008-07-29 15:58:53 -050028#include <linux/kgdb.h>
29#include <linux/kdebug.h>
David Daneyc1bf2072010-08-03 11:22:20 -070030#include <linux/kprobes.h>
Ralf Baechle69f3a7d2009-11-24 01:24:58 +000031#include <linux/notifier.h>
Jason Wessel5dd11d52010-05-20 21:04:26 -050032#include <linux/kdb.h>
David Howellsca4d3e672010-10-07 14:08:54 +010033#include <linux/irq.h>
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +080034#include <linux/perf_event.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
36#include <asm/bootinfo.h>
37#include <asm/branch.h>
38#include <asm/break.h>
Ralf Baechle69f3a7d2009-11-24 01:24:58 +000039#include <asm/cop2.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <asm/cpu.h>
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +000041#include <asm/dsp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070042#include <asm/fpu.h>
Ralf Baechleba3049e2008-10-28 17:38:42 +000043#include <asm/fpu_emulator.h>
Ralf Baechlebdc92d742013-05-21 16:59:19 +020044#include <asm/idle.h>
Ralf Baechle340ee4b2005-08-17 17:44:08 +000045#include <asm/mipsregs.h>
46#include <asm/mipsmtregs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <asm/module.h>
48#include <asm/pgtable.h>
49#include <asm/ptrace.h>
50#include <asm/sections.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070051#include <asm/tlbdebug.h>
52#include <asm/traps.h>
53#include <asm/uaccess.h>
David Daneyb67b2b72008-09-23 00:08:45 -070054#include <asm/watch.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070055#include <asm/mmu_context.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056#include <asm/types.h>
Atsushi Nemoto1df0f0f2006-09-26 23:44:01 +090057#include <asm/stacktrace.h>
Florian Fainelli92bbe1b2010-01-28 15:22:37 +010058#include <asm/uasm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070059
Atsushi Nemotoc65a5482007-11-12 02:05:18 +090060extern void check_wait(void);
Atsushi Nemotoc65a5482007-11-12 02:05:18 +090061extern asmlinkage void rollback_handle_int(void);
Ralf Baechlee4ac58a2006-04-03 17:56:36 +010062extern asmlinkage void handle_int(void);
Ralf Baechle86a17082013-02-08 01:21:34 +010063extern u32 handle_tlbl[];
64extern u32 handle_tlbs[];
65extern u32 handle_tlbm[];
Linus Torvalds1da177e2005-04-16 15:20:36 -070066extern asmlinkage void handle_adel(void);
67extern asmlinkage void handle_ades(void);
68extern asmlinkage void handle_ibe(void);
69extern asmlinkage void handle_dbe(void);
70extern asmlinkage void handle_sys(void);
71extern asmlinkage void handle_bp(void);
72extern asmlinkage void handle_ri(void);
Atsushi Nemoto5b104962006-09-11 17:50:29 +090073extern asmlinkage void handle_ri_rdhwr_vivt(void);
74extern asmlinkage void handle_ri_rdhwr(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070075extern asmlinkage void handle_cpu(void);
76extern asmlinkage void handle_ov(void);
77extern asmlinkage void handle_tr(void);
78extern asmlinkage void handle_fpe(void);
79extern asmlinkage void handle_mdmx(void);
80extern asmlinkage void handle_watch(void);
Ralf Baechle340ee4b2005-08-17 17:44:08 +000081extern asmlinkage void handle_mt(void);
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +000082extern asmlinkage void handle_dsp(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070083extern asmlinkage void handle_mcheck(void);
84extern asmlinkage void handle_reserved(void);
85
Linus Torvalds1da177e2005-04-16 15:20:36 -070086void (*board_be_init)(void);
87int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
Ralf Baechlee01402b2005-07-14 15:57:16 +000088void (*board_nmi_handler_setup)(void);
89void (*board_ejtag_handler_setup)(void);
90void (*board_bind_eic_interrupt)(int irq, int regset);
Kevin Cernekee6fb97ef2011-11-16 01:25:45 +000091void (*board_ebase_setup)(void);
David Daneyfcbf1df2012-05-15 00:04:46 -070092void __cpuinitdata(*board_cache_error_setup)(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -070093
Franck Bui-Huu4d157d52006-08-03 09:29:21 +020094static void show_raw_backtrace(unsigned long reg29)
Atsushi Nemotoe889d782006-07-25 23:51:36 +090095{
Ralf Baechle39b8d522008-04-28 17:14:26 +010096 unsigned long *sp = (unsigned long *)(reg29 & ~3);
Atsushi Nemotoe889d782006-07-25 23:51:36 +090097 unsigned long addr;
98
99 printk("Call Trace:");
100#ifdef CONFIG_KALLSYMS
101 printk("\n");
102#endif
Thomas Bogendoerfer10220c82008-05-12 17:58:48 +0200103 while (!kstack_end(sp)) {
104 unsigned long __user *p =
105 (unsigned long __user *)(unsigned long)sp++;
106 if (__get_user(addr, p)) {
107 printk(" (Bad stack address)");
108 break;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100109 }
Thomas Bogendoerfer10220c82008-05-12 17:58:48 +0200110 if (__kernel_text_address(addr))
111 print_ip_sym(addr);
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900112 }
Thomas Bogendoerfer10220c82008-05-12 17:58:48 +0200113 printk("\n");
Atsushi Nemotoe889d782006-07-25 23:51:36 +0900114}
115
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900116#ifdef CONFIG_KALLSYMS
Atsushi Nemoto1df0f0f2006-09-26 23:44:01 +0900117int raw_show_trace;
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900118static int __init set_raw_show_trace(char *str)
119{
120 raw_show_trace = 1;
121 return 1;
122}
123__setup("raw_show_trace", set_raw_show_trace);
Atsushi Nemoto1df0f0f2006-09-26 23:44:01 +0900124#endif
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200125
Ralf Baechleeae23f22007-10-14 23:27:21 +0100126static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900127{
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200128 unsigned long sp = regs->regs[29];
129 unsigned long ra = regs->regs[31];
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900130 unsigned long pc = regs->cp0_epc;
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900131
Vincent Wene909be82012-07-19 09:11:16 +0200132 if (!task)
133 task = current;
134
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900135 if (raw_show_trace || !__kernel_text_address(pc)) {
Franck Bui-Huu87151ae2006-08-03 09:29:17 +0200136 show_raw_backtrace(sp);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900137 return;
138 }
139 printk("Call Trace:\n");
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200140 do {
Franck Bui-Huu87151ae2006-08-03 09:29:17 +0200141 print_ip_sym(pc);
Atsushi Nemoto19246002006-09-29 18:02:51 +0900142 pc = unwind_stack(task, &sp, pc, &ra);
Franck Bui-Huu4d157d52006-08-03 09:29:21 +0200143 } while (pc);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900144 printk("\n");
145}
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900146
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147/*
148 * This routine abuses get_user()/put_user() to reference pointers
149 * with at least a bit of error checking ...
150 */
Ralf Baechleeae23f22007-10-14 23:27:21 +0100151static void show_stacktrace(struct task_struct *task,
152 const struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153{
154 const int field = 2 * sizeof(unsigned long);
155 long stackdata;
156 int i;
Atsushi Nemoto5e0373b2007-07-13 23:02:42 +0900157 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158
159 printk("Stack :");
160 i = 0;
161 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
162 if (i && ((i % (64 / field)) == 0))
Ralf Baechle70342282013-01-22 12:59:30 +0100163 printk("\n ");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164 if (i > 39) {
165 printk(" ...");
166 break;
167 }
168
169 if (__get_user(stackdata, sp++)) {
170 printk(" (Bad stack address)");
171 break;
172 }
173
174 printk(" %0*lx", field, stackdata);
175 i++;
176 }
177 printk("\n");
Franck Bui-Huu87151ae2006-08-03 09:29:17 +0200178 show_backtrace(task, regs);
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900179}
180
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900181void show_stack(struct task_struct *task, unsigned long *sp)
182{
183 struct pt_regs regs;
184 if (sp) {
185 regs.regs[29] = (unsigned long)sp;
186 regs.regs[31] = 0;
187 regs.cp0_epc = 0;
188 } else {
189 if (task && task != current) {
190 regs.regs[29] = task->thread.reg29;
191 regs.regs[31] = 0;
192 regs.cp0_epc = task->thread.reg31;
Jason Wessel5dd11d52010-05-20 21:04:26 -0500193#ifdef CONFIG_KGDB_KDB
194 } else if (atomic_read(&kgdb_active) != -1 &&
195 kdb_current_regs) {
196 memcpy(&regs, kdb_current_regs, sizeof(regs));
197#endif /* CONFIG_KGDB_KDB */
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900198 } else {
199 prepare_frametrace(&regs);
200 }
201 }
202 show_stacktrace(task, &regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203}
204
Atsushi Nemotoe1bb8282007-07-13 23:51:46 +0900205static void show_code(unsigned int __user *pc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206{
207 long i;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100208 unsigned short __user *pc16 = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209
210 printk("\nCode:");
211
Ralf Baechle39b8d522008-04-28 17:14:26 +0100212 if ((unsigned long)pc & 1)
213 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 for(i = -3 ; i < 6 ; i++) {
215 unsigned int insn;
Ralf Baechle39b8d522008-04-28 17:14:26 +0100216 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700217 printk(" (Bad address in epc)\n");
218 break;
219 }
Ralf Baechle39b8d522008-04-28 17:14:26 +0100220 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 }
222}
223
Ralf Baechleeae23f22007-10-14 23:27:21 +0100224static void __show_regs(const struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225{
226 const int field = 2 * sizeof(unsigned long);
227 unsigned int cause = regs->cp0_cause;
228 int i;
229
Tejun Heoa43cb952013-04-30 15:27:17 -0700230 show_regs_print_info(KERN_DEFAULT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231
232 /*
233 * Saved main processor registers
234 */
235 for (i = 0; i < 32; ) {
236 if ((i % 4) == 0)
237 printk("$%2d :", i);
238 if (i == 0)
239 printk(" %0*lx", field, 0UL);
240 else if (i == 26 || i == 27)
241 printk(" %*s", field, "");
242 else
243 printk(" %0*lx", field, regs->regs[i]);
244
245 i++;
246 if ((i % 4) == 0)
247 printk("\n");
248 }
249
Franck Bui-Huu9693a852007-02-02 17:41:47 +0100250#ifdef CONFIG_CPU_HAS_SMARTMIPS
251 printk("Acx : %0*lx\n", field, regs->acx);
252#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 printk("Hi : %0*lx\n", field, regs->hi);
254 printk("Lo : %0*lx\n", field, regs->lo);
255
256 /*
257 * Saved cp0 registers
258 */
Ralf Baechleb012cff2008-07-15 18:44:33 +0100259 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
260 (void *) regs->cp0_epc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261 printk(" %s\n", print_tainted());
Ralf Baechleb012cff2008-07-15 18:44:33 +0100262 printk("ra : %0*lx %pS\n", field, regs->regs[31],
263 (void *) regs->regs[31]);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264
Ralf Baechle70342282013-01-22 12:59:30 +0100265 printk("Status: %08x ", (uint32_t) regs->cp0_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700266
Maciej W. Rozycki3b2396d2005-06-22 20:43:29 +0000267 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
268 if (regs->cp0_status & ST0_KUO)
269 printk("KUo ");
270 if (regs->cp0_status & ST0_IEO)
271 printk("IEo ");
272 if (regs->cp0_status & ST0_KUP)
273 printk("KUp ");
274 if (regs->cp0_status & ST0_IEP)
275 printk("IEp ");
276 if (regs->cp0_status & ST0_KUC)
277 printk("KUc ");
278 if (regs->cp0_status & ST0_IEC)
279 printk("IEc ");
280 } else {
281 if (regs->cp0_status & ST0_KX)
282 printk("KX ");
283 if (regs->cp0_status & ST0_SX)
284 printk("SX ");
285 if (regs->cp0_status & ST0_UX)
286 printk("UX ");
287 switch (regs->cp0_status & ST0_KSU) {
288 case KSU_USER:
289 printk("USER ");
290 break;
291 case KSU_SUPERVISOR:
292 printk("SUPERVISOR ");
293 break;
294 case KSU_KERNEL:
295 printk("KERNEL ");
296 break;
297 default:
298 printk("BAD_MODE ");
299 break;
300 }
301 if (regs->cp0_status & ST0_ERL)
302 printk("ERL ");
303 if (regs->cp0_status & ST0_EXL)
304 printk("EXL ");
305 if (regs->cp0_status & ST0_IE)
306 printk("IE ");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700307 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308 printk("\n");
309
310 printk("Cause : %08x\n", cause);
311
312 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
313 if (1 <= cause && cause <= 5)
314 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
315
Ralf Baechle9966db252007-10-11 23:46:17 +0100316 printk("PrId : %08x (%s)\n", read_c0_prid(),
317 cpu_name_string());
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318}
319
Ralf Baechleeae23f22007-10-14 23:27:21 +0100320/*
321 * FIXME: really the generic show_regs should take a const pointer argument.
322 */
323void show_regs(struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324{
Ralf Baechleeae23f22007-10-14 23:27:21 +0100325 __show_regs((struct pt_regs *)regs);
326}
327
David Daneyc1bf2072010-08-03 11:22:20 -0700328void show_registers(struct pt_regs *regs)
Ralf Baechleeae23f22007-10-14 23:27:21 +0100329{
Ralf Baechle39b8d522008-04-28 17:14:26 +0100330 const int field = 2 * sizeof(unsigned long);
331
Ralf Baechleeae23f22007-10-14 23:27:21 +0100332 __show_regs(regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 print_modules();
Ralf Baechle39b8d522008-04-28 17:14:26 +0100334 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
335 current->comm, current->pid, current_thread_info(), current,
336 field, current_thread_info()->tp_value);
337 if (cpu_has_userlocal) {
338 unsigned long tls;
339
340 tls = read_c0_userlocal();
341 if (tls != current_thread_info()->tp_value)
342 printk("*HwTLS: %0*lx\n", field, tls);
343 }
344
Atsushi Nemotof66686f2006-07-29 23:27:20 +0900345 show_stacktrace(current, regs);
Atsushi Nemotoe1bb8282007-07-13 23:51:46 +0900346 show_code((unsigned int __user *) regs->cp0_epc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347 printk("\n");
348}
349
David Daney70dc6f02010-08-03 15:44:43 -0700350static int regs_to_trapnr(struct pt_regs *regs)
351{
352 return (regs->cp0_cause >> 2) & 0x1f;
353}
354
Wu Zhangjin4d85f6a2011-07-23 12:41:24 +0000355static DEFINE_RAW_SPINLOCK(die_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356
David Daney70dc6f02010-08-03 15:44:43 -0700357void __noreturn die(const char *str, struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358{
359 static int die_counter;
Yury Polyanskiyce384d82010-04-26 00:53:10 -0400360 int sig = SIGSEGV;
Ralf Baechle41c594a2006-04-05 09:45:45 +0100361#ifdef CONFIG_MIPS_MT_SMTC
Nathan Lynch8742cd22011-09-30 13:49:35 -0500362 unsigned long dvpret;
Ralf Baechle41c594a2006-04-05 09:45:45 +0100363#endif /* CONFIG_MIPS_MT_SMTC */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364
Nathan Lynch8742cd22011-09-30 13:49:35 -0500365 oops_enter();
366
Ralf Baechle10423c92011-05-13 10:33:28 +0100367 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
368 sig = 0;
Jason Wessel5dd11d52010-05-20 21:04:26 -0500369
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 console_verbose();
Wu Zhangjin4d85f6a2011-07-23 12:41:24 +0000371 raw_spin_lock_irq(&die_lock);
Nathan Lynch8742cd22011-09-30 13:49:35 -0500372#ifdef CONFIG_MIPS_MT_SMTC
373 dvpret = dvpe();
374#endif /* CONFIG_MIPS_MT_SMTC */
Ralf Baechle41c594a2006-04-05 09:45:45 +0100375 bust_spinlocks(1);
376#ifdef CONFIG_MIPS_MT_SMTC
377 mips_mt_regdump(dvpret);
378#endif /* CONFIG_MIPS_MT_SMTC */
Yury Polyanskiyce384d82010-04-26 00:53:10 -0400379
Ralf Baechle178086c2005-10-13 17:07:54 +0100380 printk("%s[#%d]:\n", str, ++die_counter);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381 show_registers(regs);
Rusty Russell373d4d092013-01-21 17:17:39 +1030382 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
Wu Zhangjin4d85f6a2011-07-23 12:41:24 +0000383 raw_spin_unlock_irq(&die_lock);
Maxime Bizond4fd1982006-07-20 18:52:02 +0200384
Nathan Lynch8742cd22011-09-30 13:49:35 -0500385 oops_exit();
386
Maxime Bizond4fd1982006-07-20 18:52:02 +0200387 if (in_interrupt())
388 panic("Fatal exception in interrupt");
389
390 if (panic_on_oops) {
Ralf Baechleab75dc02011-11-17 15:07:31 +0000391 printk(KERN_EMERG "Fatal exception: panic in 5 seconds");
Maxime Bizond4fd1982006-07-20 18:52:02 +0200392 ssleep(5);
393 panic("Fatal exception");
394 }
395
Ralf Baechle7aa1c8f2012-10-11 18:14:58 +0200396 if (regs && kexec_should_crash(current))
397 crash_kexec(regs);
398
Yury Polyanskiyce384d82010-04-26 00:53:10 -0400399 do_exit(sig);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400}
401
Thomas Bogendoerfer05106172008-08-04 19:44:34 +0200402extern struct exception_table_entry __start___dbe_table[];
403extern struct exception_table_entry __stop___dbe_table[];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404
Ralf Baechleb6dcec92007-02-18 15:57:09 +0000405__asm__(
406" .section __dbe_table, \"a\"\n"
407" .previous \n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408
409/* Given an address, look for it in the exception tables. */
410static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
411{
412 const struct exception_table_entry *e;
413
414 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
415 if (!e)
416 e = search_module_dbetables(addr);
417 return e;
418}
419
420asmlinkage void do_be(struct pt_regs *regs)
421{
422 const int field = 2 * sizeof(unsigned long);
423 const struct exception_table_entry *fixup = NULL;
424 int data = regs->cp0_cause & 4;
425 int action = MIPS_BE_FATAL;
426
Ralf Baechle70342282013-01-22 12:59:30 +0100427 /* XXX For now. Fixme, this searches the wrong table ... */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428 if (data && !user_mode(regs))
429 fixup = search_dbe_tables(exception_epc(regs));
430
431 if (fixup)
432 action = MIPS_BE_FIXUP;
433
434 if (board_be_handler)
Atsushi Nemoto28fc5822007-07-13 01:49:49 +0900435 action = board_be_handler(regs, fixup != NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436
437 switch (action) {
438 case MIPS_BE_DISCARD:
439 return;
440 case MIPS_BE_FIXUP:
441 if (fixup) {
442 regs->cp0_epc = fixup->nextinsn;
443 return;
444 }
445 break;
446 default:
447 break;
448 }
449
450 /*
451 * Assume it would be too dangerous to continue ...
452 */
453 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
454 data ? "Data" : "Instruction",
455 field, regs->cp0_epc, field, regs->regs[31]);
David Daney70dc6f02010-08-03 15:44:43 -0700456 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
Jason Wessel88547002008-07-29 15:58:53 -0500457 == NOTIFY_STOP)
458 return;
459
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460 die_if_kernel("Oops", regs);
461 force_sig(SIGBUS, current);
462}
463
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464/*
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100465 * ll/sc, rdhwr, sync emulation
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466 */
467
468#define OPCODE 0xfc000000
469#define BASE 0x03e00000
470#define RT 0x001f0000
471#define OFFSET 0x0000ffff
472#define LL 0xc0000000
473#define SC 0xe0000000
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100474#define SPEC0 0x00000000
Ralf Baechle3c370262005-04-13 17:43:59 +0000475#define SPEC3 0x7c000000
476#define RD 0x0000f800
477#define FUNC 0x0000003f
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100478#define SYNC 0x0000000f
Ralf Baechle3c370262005-04-13 17:43:59 +0000479#define RDHWR 0x0000003b
Linus Torvalds1da177e2005-04-16 15:20:36 -0700480
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500481/* microMIPS definitions */
482#define MM_POOL32A_FUNC 0xfc00ffff
483#define MM_RDHWR 0x00006b3c
484#define MM_RS 0x001f0000
485#define MM_RT 0x03e00000
486
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487/*
488 * The ll_bit is cleared by r*_switch.S
489 */
490
Ralf Baechlef1e39a42009-09-17 02:25:05 +0200491unsigned int ll_bit;
492struct task_struct *ll_task;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700493
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100494static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495{
Ralf Baechlefe00f942005-03-01 19:22:29 +0000496 unsigned long value, __user *vaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497 long offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498
499 /*
500 * analyse the ll instruction that just caused a ri exception
501 * and put the referenced address to addr.
502 */
503
504 /* sign extend offset */
505 offset = opcode & OFFSET;
506 offset <<= 16;
507 offset >>= 16;
508
Ralf Baechlefe00f942005-03-01 19:22:29 +0000509 vaddr = (unsigned long __user *)
Steven J. Hillb9688312013-01-12 23:29:27 +0000510 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100512 if ((unsigned long)vaddr & 3)
513 return SIGBUS;
514 if (get_user(value, vaddr))
515 return SIGSEGV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700516
517 preempt_disable();
518
519 if (ll_task == NULL || ll_task == current) {
520 ll_bit = 1;
521 } else {
522 ll_bit = 0;
523 }
524 ll_task = current;
525
526 preempt_enable();
527
528 regs->regs[(opcode & RT) >> 16] = value;
529
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100530 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700531}
532
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100533static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534{
Ralf Baechlefe00f942005-03-01 19:22:29 +0000535 unsigned long __user *vaddr;
536 unsigned long reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 long offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538
539 /*
540 * analyse the sc instruction that just caused a ri exception
541 * and put the referenced address to addr.
542 */
543
544 /* sign extend offset */
545 offset = opcode & OFFSET;
546 offset <<= 16;
547 offset >>= 16;
548
Ralf Baechlefe00f942005-03-01 19:22:29 +0000549 vaddr = (unsigned long __user *)
Steven J. Hillb9688312013-01-12 23:29:27 +0000550 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700551 reg = (opcode & RT) >> 16;
552
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100553 if ((unsigned long)vaddr & 3)
554 return SIGBUS;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555
556 preempt_disable();
557
558 if (ll_bit == 0 || ll_task != current) {
559 regs->regs[reg] = 0;
560 preempt_enable();
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100561 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562 }
563
564 preempt_enable();
565
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100566 if (put_user(regs->regs[reg], vaddr))
567 return SIGSEGV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568
569 regs->regs[reg] = 1;
570
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100571 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700572}
573
574/*
575 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
576 * opcodes are supposed to result in coprocessor unusable exceptions if
577 * executed on ll/sc-less processors. That's the theory. In practice a
578 * few processors such as NEC's VR4100 throw reserved instruction exceptions
579 * instead, so we're doing the emulation thing in both exception handlers.
580 */
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100581static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700582{
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800583 if ((opcode & OPCODE) == LL) {
584 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200585 1, regs, 0);
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100586 return simulate_ll(regs, opcode);
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800587 }
588 if ((opcode & OPCODE) == SC) {
589 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200590 1, regs, 0);
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100591 return simulate_sc(regs, opcode);
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800592 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100594 return -1; /* Must be something else ... */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595}
596
Ralf Baechle3c370262005-04-13 17:43:59 +0000597/*
598 * Simulate trapping 'rdhwr' instructions to provide user accessible
Chris Dearman1f5826b2006-05-08 18:02:16 +0100599 * registers not implemented in hardware.
Ralf Baechle3c370262005-04-13 17:43:59 +0000600 */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500601static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
Ralf Baechle3c370262005-04-13 17:43:59 +0000602{
Al Virodc8f6022006-01-12 01:06:07 -0800603 struct thread_info *ti = task_thread_info(current);
Ralf Baechle3c370262005-04-13 17:43:59 +0000604
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500605 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
606 1, regs, 0);
607 switch (rd) {
608 case 0: /* CPU number */
609 regs->regs[rt] = smp_processor_id();
610 return 0;
611 case 1: /* SYNCI length */
612 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
613 current_cpu_data.icache.linesz);
614 return 0;
615 case 2: /* Read count register */
616 regs->regs[rt] = read_c0_count();
617 return 0;
618 case 3: /* Count register resolution */
619 switch (current_cpu_data.cputype) {
620 case CPU_20KC:
621 case CPU_25KF:
622 regs->regs[rt] = 1;
623 break;
624 default:
625 regs->regs[rt] = 2;
626 }
627 return 0;
628 case 29:
629 regs->regs[rt] = ti->tp_value;
630 return 0;
631 default:
632 return -1;
633 }
634}
635
636static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
637{
Ralf Baechle3c370262005-04-13 17:43:59 +0000638 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
639 int rd = (opcode & RD) >> 11;
640 int rt = (opcode & RT) >> 16;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500641
642 simulate_rdhwr(regs, rd, rt);
643 return 0;
644 }
645
646 /* Not ours. */
647 return -1;
648}
649
650static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)
651{
652 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
653 int rd = (opcode & MM_RS) >> 16;
654 int rt = (opcode & MM_RT) >> 21;
655 simulate_rdhwr(regs, rd, rt);
656 return 0;
Ralf Baechle3c370262005-04-13 17:43:59 +0000657 }
658
Daniel Jacobowitz56ebd512005-11-26 22:34:41 -0500659 /* Not ours. */
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100660 return -1;
661}
Ralf Baechlee5679882006-11-30 01:14:47 +0000662
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100663static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
664{
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800665 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
666 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +0200667 1, regs, 0);
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100668 return 0;
Deng-Cheng Zhu7f788d22010-10-12 19:37:21 +0800669 }
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100670
671 return -1; /* Must be something else ... */
Ralf Baechle3c370262005-04-13 17:43:59 +0000672}
673
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674asmlinkage void do_ov(struct pt_regs *regs)
675{
676 siginfo_t info;
677
Ralf Baechle36ccf1c2006-02-14 21:04:54 +0000678 die_if_kernel("Integer overflow", regs);
679
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680 info.si_code = FPE_INTOVF;
681 info.si_signo = SIGFPE;
682 info.si_errno = 0;
Ralf Baechlefe00f942005-03-01 19:22:29 +0000683 info.si_addr = (void __user *) regs->cp0_epc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700684 force_sig_info(SIGFPE, &info, current);
685}
686
Leonid Yegoshin102cedc2013-03-25 12:09:02 -0500687int process_fpemu_return(int sig, void __user *fault_addr)
David Daney515b0292010-10-21 16:32:26 -0700688{
689 if (sig == SIGSEGV || sig == SIGBUS) {
690 struct siginfo si = {0};
691 si.si_addr = fault_addr;
692 si.si_signo = sig;
693 if (sig == SIGSEGV) {
694 if (find_vma(current->mm, (unsigned long)fault_addr))
695 si.si_code = SEGV_ACCERR;
696 else
697 si.si_code = SEGV_MAPERR;
698 } else {
699 si.si_code = BUS_ADRERR;
700 }
701 force_sig_info(sig, &si, current);
702 return 1;
703 } else if (sig) {
704 force_sig(sig, current);
705 return 1;
706 } else {
707 return 0;
708 }
709}
710
Linus Torvalds1da177e2005-04-16 15:20:36 -0700711/*
712 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
713 */
714asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
715{
David Daney515b0292010-10-21 16:32:26 -0700716 siginfo_t info = {0};
Thiemo Seufer948a34c2007-08-22 01:42:04 +0100717
David Daney70dc6f02010-08-03 15:44:43 -0700718 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
Jason Wessel88547002008-07-29 15:58:53 -0500719 == NOTIFY_STOP)
720 return;
Chris Dearman57725f92006-06-30 23:35:28 +0100721 die_if_kernel("FP exception in kernel code", regs);
722
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723 if (fcr31 & FPU_CSR_UNI_X) {
724 int sig;
David Daney515b0292010-10-21 16:32:26 -0700725 void __user *fault_addr = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726
Linus Torvalds1da177e2005-04-16 15:20:36 -0700727 /*
Ralf Baechlea3dddd52006-03-11 08:18:41 +0000728 * Unimplemented operation exception. If we've got the full
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729 * software emulator on-board, let's use it...
730 *
731 * Force FPU to dump state into task/thread context. We're
732 * moving a lot of data here for what is probably a single
733 * instruction, but the alternative is to pre-decode the FP
734 * register operands before invoking the emulator, which seems
735 * a bit extreme for what should be an infrequent event.
736 */
Ralf Baechlecd21dfc2005-04-28 13:39:10 +0000737 /* Ensure 'resume' not overwrite saved fp context again. */
Atsushi Nemoto53dc8022007-03-10 01:07:45 +0900738 lose_fpu(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700739
740 /* Run the emulator */
David Daney515b0292010-10-21 16:32:26 -0700741 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
742 &fault_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743
744 /*
745 * We can't allow the emulated instruction to leave any of
746 * the cause bit set in $fcr31.
747 */
Atsushi Nemotoeae89072006-05-16 01:26:03 +0900748 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749
750 /* Restore the hardware register state */
Ralf Baechle70342282013-01-22 12:59:30 +0100751 own_fpu(1); /* Using the FPU again. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752
753 /* If something went wrong, signal */
David Daney515b0292010-10-21 16:32:26 -0700754 process_fpemu_return(sig, fault_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755
756 return;
Thiemo Seufer948a34c2007-08-22 01:42:04 +0100757 } else if (fcr31 & FPU_CSR_INV_X)
758 info.si_code = FPE_FLTINV;
759 else if (fcr31 & FPU_CSR_DIV_X)
760 info.si_code = FPE_FLTDIV;
761 else if (fcr31 & FPU_CSR_OVF_X)
762 info.si_code = FPE_FLTOVF;
763 else if (fcr31 & FPU_CSR_UDF_X)
764 info.si_code = FPE_FLTUND;
765 else if (fcr31 & FPU_CSR_INE_X)
766 info.si_code = FPE_FLTRES;
767 else
768 info.si_code = __SI_FAULT;
769 info.si_signo = SIGFPE;
770 info.si_errno = 0;
771 info.si_addr = (void __user *) regs->cp0_epc;
772 force_sig_info(SIGFPE, &info, current);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773}
774
Ralf Baechledf270052008-04-20 16:28:54 +0100775static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
776 const char *str)
777{
778 siginfo_t info;
779 char b[40];
780
Jason Wessel5dd11d52010-05-20 21:04:26 -0500781#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
David Daney70dc6f02010-08-03 15:44:43 -0700782 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
Jason Wessel5dd11d52010-05-20 21:04:26 -0500783 return;
784#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
785
David Daney70dc6f02010-08-03 15:44:43 -0700786 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
Jason Wessel88547002008-07-29 15:58:53 -0500787 return;
788
Ralf Baechledf270052008-04-20 16:28:54 +0100789 /*
790 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
791 * insns, even for trap and break codes that indicate arithmetic
792 * failures. Weird ...
793 * But should we continue the brokenness??? --macro
794 */
795 switch (code) {
796 case BRK_OVERFLOW:
797 case BRK_DIVZERO:
798 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
799 die_if_kernel(b, regs);
800 if (code == BRK_DIVZERO)
801 info.si_code = FPE_INTDIV;
802 else
803 info.si_code = FPE_INTOVF;
804 info.si_signo = SIGFPE;
805 info.si_errno = 0;
806 info.si_addr = (void __user *) regs->cp0_epc;
807 force_sig_info(SIGFPE, &info, current);
808 break;
809 case BRK_BUG:
810 die_if_kernel("Kernel bug detected", regs);
811 force_sig(SIGTRAP, current);
812 break;
Ralf Baechleba3049e2008-10-28 17:38:42 +0000813 case BRK_MEMU:
814 /*
815 * Address errors may be deliberately induced by the FPU
816 * emulator to retake control of the CPU after executing the
817 * instruction in the delay slot of an emulated branch.
818 *
819 * Terminate if exception was recognized as a delay slot return
820 * otherwise handle as normal.
821 */
822 if (do_dsemulret(regs))
823 return;
824
825 die_if_kernel("Math emu break/trap", regs);
826 force_sig(SIGTRAP, current);
827 break;
Ralf Baechledf270052008-04-20 16:28:54 +0100828 default:
829 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
830 die_if_kernel(b, regs);
831 force_sig(SIGTRAP, current);
832 }
833}
834
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835asmlinkage void do_bp(struct pt_regs *regs)
836{
837 unsigned int opcode, bcode;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500838 unsigned long epc;
839 u16 instr[2];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500841 if (get_isa16_mode(regs->cp0_epc)) {
842 /* Calculate EPC. */
843 epc = exception_epc(regs);
844 if (cpu_has_mmips) {
845 if ((__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)) ||
846 (__get_user(instr[1], (u16 __user *)msk_isa16_mode(epc + 2)))))
847 goto out_sigsegv;
848 opcode = (instr[0] << 16) | instr[1];
849 } else {
850 /* MIPS16e mode */
851 if (__get_user(instr[0], (u16 __user *)msk_isa16_mode(epc)))
852 goto out_sigsegv;
853 bcode = (instr[0] >> 6) & 0x3f;
854 do_trap_or_bp(regs, bcode, "Break");
855 return;
856 }
857 } else {
858 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
859 goto out_sigsegv;
860 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861
862 /*
863 * There is the ancient bug in the MIPS assemblers that the break
864 * code starts left to bit 16 instead to bit 6 in the opcode.
865 * Gas is bug-compatible, but not always, grrr...
866 * We handle both cases with a simple heuristics. --macro
867 */
868 bcode = ((opcode >> 6) & ((1 << 20) - 1));
Ralf Baechledf270052008-04-20 16:28:54 +0100869 if (bcode >= (1 << 10))
870 bcode >>= 10;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871
David Daneyc1bf2072010-08-03 11:22:20 -0700872 /*
873 * notify the kprobe handlers, if instruction is likely to
874 * pertain to them.
875 */
876 switch (bcode) {
877 case BRK_KPROBE_BP:
David Daney70dc6f02010-08-03 15:44:43 -0700878 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
David Daneyc1bf2072010-08-03 11:22:20 -0700879 return;
880 else
881 break;
882 case BRK_KPROBE_SSTEPBP:
David Daney70dc6f02010-08-03 15:44:43 -0700883 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
David Daneyc1bf2072010-08-03 11:22:20 -0700884 return;
885 else
886 break;
887 default:
888 break;
889 }
890
Ralf Baechledf270052008-04-20 16:28:54 +0100891 do_trap_or_bp(regs, bcode, "Break");
Atsushi Nemoto90fccb12007-02-06 16:02:21 +0900892 return;
Ralf Baechlee5679882006-11-30 01:14:47 +0000893
894out_sigsegv:
895 force_sig(SIGSEGV, current);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896}
897
898asmlinkage void do_tr(struct pt_regs *regs)
899{
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +0000900 u32 opcode, tcode = 0;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500901 u16 instr[2];
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +0000902 unsigned long epc = msk_isa16_mode(exception_epc(regs));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +0000904 if (get_isa16_mode(regs->cp0_epc)) {
905 if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
906 __get_user(instr[1], (u16 __user *)(epc + 2)))
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500907 goto out_sigsegv;
Maciej W. Rozyckia9a6e7a2013-05-23 14:31:23 +0000908 opcode = (instr[0] << 16) | instr[1];
909 /* Immediate versions don't provide a code. */
910 if (!(opcode & OPCODE))
911 tcode = (opcode >> 12) & ((1 << 4) - 1);
912 } else {
913 if (__get_user(opcode, (u32 __user *)epc))
914 goto out_sigsegv;
915 /* Immediate versions don't provide a code. */
916 if (!(opcode & OPCODE))
917 tcode = (opcode >> 6) & ((1 << 10) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500918 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700919
Ralf Baechledf270052008-04-20 16:28:54 +0100920 do_trap_or_bp(regs, tcode, "Trap");
Atsushi Nemoto90fccb12007-02-06 16:02:21 +0900921 return;
Ralf Baechlee5679882006-11-30 01:14:47 +0000922
923out_sigsegv:
924 force_sig(SIGSEGV, current);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925}
926
927asmlinkage void do_ri(struct pt_regs *regs)
928{
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100929 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
930 unsigned long old_epc = regs->cp0_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500931 unsigned long old31 = regs->regs[31];
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100932 unsigned int opcode = 0;
933 int status = -1;
934
David Daney70dc6f02010-08-03 15:44:43 -0700935 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
Jason Wessel88547002008-07-29 15:58:53 -0500936 == NOTIFY_STOP)
937 return;
938
Linus Torvalds1da177e2005-04-16 15:20:36 -0700939 die_if_kernel("Reserved instruction in kernel code", regs);
940
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100941 if (unlikely(compute_return_epc(regs) < 0))
Ralf Baechle3c370262005-04-13 17:43:59 +0000942 return;
943
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500944 if (get_isa16_mode(regs->cp0_epc)) {
945 unsigned short mmop[2] = { 0 };
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100946
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500947 if (unlikely(get_user(mmop[0], epc) < 0))
948 status = SIGSEGV;
949 if (unlikely(get_user(mmop[1], epc) < 0))
950 status = SIGSEGV;
951 opcode = (mmop[0] << 16) | mmop[1];
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100952
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500953 if (status < 0)
954 status = simulate_rdhwr_mm(regs, opcode);
955 } else {
956 if (unlikely(get_user(opcode, epc) < 0))
957 status = SIGSEGV;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100958
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500959 if (!cpu_has_llsc && status < 0)
960 status = simulate_llsc(regs, opcode);
961
962 if (status < 0)
963 status = simulate_rdhwr_normal(regs, opcode);
964
965 if (status < 0)
966 status = simulate_sync(regs, opcode);
967 }
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100968
969 if (status < 0)
970 status = SIGILL;
971
972 if (unlikely(status > 0)) {
973 regs->cp0_epc = old_epc; /* Undo skip-over. */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -0500974 regs->regs[31] = old31;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +0100975 force_sig(status, current);
976 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700977}
978
Ralf Baechled223a862007-07-10 17:33:02 +0100979/*
980 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
981 * emulated more than some threshold number of instructions, force migration to
982 * a "CPU" that has FP support.
983 */
984static void mt_ase_fp_affinity(void)
985{
986#ifdef CONFIG_MIPS_MT_FPAFF
987 if (mt_fpemul_threshold > 0 &&
988 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
989 /*
990 * If there's no FPU present, or if the application has already
991 * restricted the allowed set to exclude any CPUs with FPUs,
992 * we'll skip the procedure.
993 */
994 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
995 cpumask_t tmask;
996
Kevin D. Kissell9cc12362008-09-09 21:33:36 +0200997 current->thread.user_cpus_allowed
998 = current->cpus_allowed;
999 cpus_and(tmask, current->cpus_allowed,
1000 mt_fpu_cpumask);
Julia Lawalled1bbde2010-03-26 23:03:07 +01001001 set_cpus_allowed_ptr(current, &tmask);
Ralf Baechle293c5bd2007-07-25 16:19:33 +01001002 set_thread_flag(TIF_FPUBOUND);
Ralf Baechled223a862007-07-10 17:33:02 +01001003 }
1004 }
1005#endif /* CONFIG_MIPS_MT_FPAFF */
1006}
1007
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001008/*
1009 * No lock; only written during early bootup by CPU 0.
1010 */
1011static RAW_NOTIFIER_HEAD(cu2_chain);
1012
1013int __ref register_cu2_notifier(struct notifier_block *nb)
1014{
1015 return raw_notifier_chain_register(&cu2_chain, nb);
1016}
1017
1018int cu2_notifier_call_chain(unsigned long val, void *v)
1019{
1020 return raw_notifier_call_chain(&cu2_chain, val, v);
1021}
1022
1023static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
Ralf Baechle70342282013-01-22 12:59:30 +01001024 void *data)
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001025{
1026 struct pt_regs *regs = data;
1027
1028 switch (action) {
1029 default:
1030 die_if_kernel("Unhandled kernel unaligned access or invalid "
1031 "instruction", regs);
Ralf Baechle70342282013-01-22 12:59:30 +01001032 /* Fall through */
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001033
1034 case CU2_EXCEPTION:
1035 force_sig(SIGILL, current);
1036 }
1037
1038 return NOTIFY_OK;
1039}
1040
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041asmlinkage void do_cpu(struct pt_regs *regs)
1042{
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001043 unsigned int __user *epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001044 unsigned long old_epc, old31;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001045 unsigned int opcode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046 unsigned int cpid;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001047 int status;
David Daneyf9bb4cf2008-12-11 15:33:23 -08001048 unsigned long __maybe_unused flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049
Atsushi Nemoto53231802007-04-14 02:37:26 +09001050 die_if_kernel("do_cpu invoked from kernel context!", regs);
1051
Linus Torvalds1da177e2005-04-16 15:20:36 -07001052 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
1053
1054 switch (cpid) {
1055 case 0:
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001056 epc = (unsigned int __user *)exception_epc(regs);
1057 old_epc = regs->cp0_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001058 old31 = regs->regs[31];
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001059 opcode = 0;
1060 status = -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001061
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001062 if (unlikely(compute_return_epc(regs) < 0))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063 return;
Ralf Baechle3c370262005-04-13 17:43:59 +00001064
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001065 if (get_isa16_mode(regs->cp0_epc)) {
1066 unsigned short mmop[2] = { 0 };
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001067
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001068 if (unlikely(get_user(mmop[0], epc) < 0))
1069 status = SIGSEGV;
1070 if (unlikely(get_user(mmop[1], epc) < 0))
1071 status = SIGSEGV;
1072 opcode = (mmop[0] << 16) | mmop[1];
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001073
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001074 if (status < 0)
1075 status = simulate_rdhwr_mm(regs, opcode);
1076 } else {
1077 if (unlikely(get_user(opcode, epc) < 0))
1078 status = SIGSEGV;
1079
1080 if (!cpu_has_llsc && status < 0)
1081 status = simulate_llsc(regs, opcode);
1082
1083 if (status < 0)
1084 status = simulate_rdhwr_normal(regs, opcode);
1085 }
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001086
1087 if (status < 0)
1088 status = SIGILL;
1089
1090 if (unlikely(status > 0)) {
1091 regs->cp0_epc = old_epc; /* Undo skip-over. */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001092 regs->regs[31] = old31;
Maciej W. Rozycki60b0d652007-10-16 18:43:26 +01001093 force_sig(status, current);
1094 }
1095
1096 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001098 case 3:
1099 /*
1100 * Old (MIPS I and MIPS II) processors will set this code
1101 * for COP1X opcode instructions that replaced the original
Ralf Baechle70342282013-01-22 12:59:30 +01001102 * COP3 space. We don't limit COP1 space instructions in
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001103 * the emulator according to the CPU ISA, so we want to
1104 * treat COP1X instructions consistently regardless of which
Ralf Baechle70342282013-01-22 12:59:30 +01001105 * code the CPU chose. Therefore we redirect this trap to
Maciej W. Rozycki051ff442012-03-06 20:28:54 +00001106 * the FP emulator too.
1107 *
1108 * Then some newer FPU-less processors use this code
1109 * erroneously too, so they are covered by this choice
1110 * as well.
1111 */
1112 if (raw_cpu_has_fpu)
1113 break;
1114 /* Fall through. */
1115
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116 case 1:
Ralf Baechle70342282013-01-22 12:59:30 +01001117 if (used_math()) /* Using the FPU again. */
Atsushi Nemoto53dc8022007-03-10 01:07:45 +09001118 own_fpu(1);
Ralf Baechle70342282013-01-22 12:59:30 +01001119 else { /* First time FPU user. */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120 init_fpu();
1121 set_used_math();
1122 }
1123
Atsushi Nemoto53231802007-04-14 02:37:26 +09001124 if (!raw_cpu_has_fpu) {
Atsushi Nemotoe04582b2006-10-09 00:10:01 +09001125 int sig;
David Daney515b0292010-10-21 16:32:26 -07001126 void __user *fault_addr = NULL;
Atsushi Nemotoe04582b2006-10-09 00:10:01 +09001127 sig = fpu_emulator_cop1Handler(regs,
David Daney515b0292010-10-21 16:32:26 -07001128 &current->thread.fpu,
1129 0, &fault_addr);
1130 if (!process_fpemu_return(sig, fault_addr))
Ralf Baechled223a862007-07-10 17:33:02 +01001131 mt_ase_fp_affinity();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001132 }
1133
Linus Torvalds1da177e2005-04-16 15:20:36 -07001134 return;
1135
1136 case 2:
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001137 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
Jesper Nilsson55dc9d52010-06-17 15:25:54 +02001138 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001139 }
1140
1141 force_sig(SIGILL, current);
1142}
1143
1144asmlinkage void do_mdmx(struct pt_regs *regs)
1145{
1146 force_sig(SIGILL, current);
1147}
1148
David Daney8bc6d052009-01-05 15:29:58 -08001149/*
1150 * Called with interrupts disabled.
1151 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001152asmlinkage void do_watch(struct pt_regs *regs)
1153{
David Daneyb67b2b72008-09-23 00:08:45 -07001154 u32 cause;
1155
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156 /*
David Daneyb67b2b72008-09-23 00:08:45 -07001157 * Clear WP (bit 22) bit of cause register so we don't loop
1158 * forever.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001159 */
David Daneyb67b2b72008-09-23 00:08:45 -07001160 cause = read_c0_cause();
1161 cause &= ~(1 << 22);
1162 write_c0_cause(cause);
1163
1164 /*
1165 * If the current thread has the watch registers loaded, save
1166 * their values and send SIGTRAP. Otherwise another thread
1167 * left the registers set, clear them and continue.
1168 */
1169 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1170 mips_read_watch_registers();
David Daney8bc6d052009-01-05 15:29:58 -08001171 local_irq_enable();
David Daneyb67b2b72008-09-23 00:08:45 -07001172 force_sig(SIGTRAP, current);
David Daney8bc6d052009-01-05 15:29:58 -08001173 } else {
David Daneyb67b2b72008-09-23 00:08:45 -07001174 mips_clear_watch_registers();
David Daney8bc6d052009-01-05 15:29:58 -08001175 local_irq_enable();
1176 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001177}
1178
1179asmlinkage void do_mcheck(struct pt_regs *regs)
1180{
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001181 const int field = 2 * sizeof(unsigned long);
1182 int multi_match = regs->cp0_status & ST0_TS;
1183
Linus Torvalds1da177e2005-04-16 15:20:36 -07001184 show_regs(regs);
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001185
1186 if (multi_match) {
Ralf Baechle70342282013-01-22 12:59:30 +01001187 printk("Index : %0x\n", read_c0_index());
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001188 printk("Pagemask: %0x\n", read_c0_pagemask());
1189 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1190 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1191 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1192 printk("\n");
1193 dump_tlb_all();
1194 }
1195
Atsushi Nemotoe1bb8282007-07-13 23:51:46 +09001196 show_code((unsigned int __user *) regs->cp0_epc);
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001197
Linus Torvalds1da177e2005-04-16 15:20:36 -07001198 /*
1199 * Some chips may have other causes of machine check (e.g. SB1
1200 * graduation timer)
1201 */
1202 panic("Caught Machine Check exception - %scaused by multiple "
1203 "matching entries in the TLB.",
Ralf Baechlecac4bcb2006-05-24 16:51:02 +01001204 (multi_match) ? "" : "not ");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001205}
1206
Ralf Baechle340ee4b2005-08-17 17:44:08 +00001207asmlinkage void do_mt(struct pt_regs *regs)
1208{
Ralf Baechle41c594a2006-04-05 09:45:45 +01001209 int subcode;
1210
Ralf Baechle41c594a2006-04-05 09:45:45 +01001211 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1212 >> VPECONTROL_EXCPT_SHIFT;
1213 switch (subcode) {
1214 case 0:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001215 printk(KERN_DEBUG "Thread Underflow\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001216 break;
1217 case 1:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001218 printk(KERN_DEBUG "Thread Overflow\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001219 break;
1220 case 2:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001221 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001222 break;
1223 case 3:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001224 printk(KERN_DEBUG "Gating Storage Exception\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001225 break;
1226 case 4:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001227 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001228 break;
1229 case 5:
Masanari Iidaf232c7e2012-02-08 21:53:14 +09001230 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
Ralf Baechle41c594a2006-04-05 09:45:45 +01001231 break;
1232 default:
Chris Dearmane35a5e32006-06-30 14:19:45 +01001233 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
Ralf Baechle41c594a2006-04-05 09:45:45 +01001234 subcode);
1235 break;
1236 }
Ralf Baechle340ee4b2005-08-17 17:44:08 +00001237 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1238
1239 force_sig(SIGILL, current);
1240}
1241
1242
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +00001243asmlinkage void do_dsp(struct pt_regs *regs)
1244{
1245 if (cpu_has_dsp)
Ralf Baechleab75dc02011-11-17 15:07:31 +00001246 panic("Unexpected DSP exception");
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +00001247
1248 force_sig(SIGILL, current);
1249}
1250
Linus Torvalds1da177e2005-04-16 15:20:36 -07001251asmlinkage void do_reserved(struct pt_regs *regs)
1252{
1253 /*
Ralf Baechle70342282013-01-22 12:59:30 +01001254 * Game over - no way to handle this if it ever occurs. Most probably
Linus Torvalds1da177e2005-04-16 15:20:36 -07001255 * caused by a new unknown cpu type or after another deadly
1256 * hard/software error.
1257 */
1258 show_regs(regs);
1259 panic("Caught reserved exception %ld - should not happen.",
1260 (regs->cp0_cause & 0x7f) >> 2);
1261}
1262
Ralf Baechle39b8d522008-04-28 17:14:26 +01001263static int __initdata l1parity = 1;
1264static int __init nol1parity(char *s)
1265{
1266 l1parity = 0;
1267 return 1;
1268}
1269__setup("nol1par", nol1parity);
1270static int __initdata l2parity = 1;
1271static int __init nol2parity(char *s)
1272{
1273 l2parity = 0;
1274 return 1;
1275}
1276__setup("nol2par", nol2parity);
1277
Linus Torvalds1da177e2005-04-16 15:20:36 -07001278/*
1279 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1280 * it different ways.
1281 */
1282static inline void parity_protection_init(void)
1283{
Ralf Baechle10cc3522007-10-11 23:46:15 +01001284 switch (current_cpu_type()) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285 case CPU_24K:
Nigel Stephens98a41de2006-04-27 15:50:32 +01001286 case CPU_34K:
Ralf Baechle39b8d522008-04-28 17:14:26 +01001287 case CPU_74K:
1288 case CPU_1004K:
1289 {
1290#define ERRCTL_PE 0x80000000
1291#define ERRCTL_L2P 0x00800000
1292 unsigned long errctl;
1293 unsigned int l1parity_present, l2parity_present;
1294
1295 errctl = read_c0_ecc();
1296 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1297
1298 /* probe L1 parity support */
1299 write_c0_ecc(errctl | ERRCTL_PE);
1300 back_to_back_c0_hazard();
1301 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1302
1303 /* probe L2 parity support */
1304 write_c0_ecc(errctl|ERRCTL_L2P);
1305 back_to_back_c0_hazard();
1306 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1307
1308 if (l1parity_present && l2parity_present) {
1309 if (l1parity)
1310 errctl |= ERRCTL_PE;
1311 if (l1parity ^ l2parity)
1312 errctl |= ERRCTL_L2P;
1313 } else if (l1parity_present) {
1314 if (l1parity)
1315 errctl |= ERRCTL_PE;
1316 } else if (l2parity_present) {
1317 if (l2parity)
1318 errctl |= ERRCTL_L2P;
1319 } else {
1320 /* No parity available */
1321 }
1322
1323 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1324
1325 write_c0_ecc(errctl);
1326 back_to_back_c0_hazard();
1327 errctl = read_c0_ecc();
1328 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1329
1330 if (l1parity_present)
1331 printk(KERN_INFO "Cache parity protection %sabled\n",
1332 (errctl & ERRCTL_PE) ? "en" : "dis");
1333
1334 if (l2parity_present) {
1335 if (l1parity_present && l1parity)
1336 errctl ^= ERRCTL_L2P;
1337 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1338 (errctl & ERRCTL_L2P) ? "en" : "dis");
1339 }
1340 }
1341 break;
1342
Linus Torvalds1da177e2005-04-16 15:20:36 -07001343 case CPU_5KC:
Leonid Yegoshin78d48032012-07-06 21:56:01 +02001344 case CPU_5KE:
Kelvin Cheung2fa36392012-06-20 20:05:32 +01001345 case CPU_LOONGSON1:
Ralf Baechle14f18b72005-03-01 18:15:08 +00001346 write_c0_ecc(0x80000000);
1347 back_to_back_c0_hazard();
1348 /* Set the PE bit (bit 31) in the c0_errctl register. */
1349 printk(KERN_INFO "Cache parity protection %sabled\n",
1350 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351 break;
1352 case CPU_20KC:
1353 case CPU_25KF:
1354 /* Clear the DE bit (bit 16) in the c0_status register. */
1355 printk(KERN_INFO "Enable cache parity protection for "
1356 "MIPS 20KC/25KF CPUs.\n");
1357 clear_c0_status(ST0_DE);
1358 break;
1359 default:
1360 break;
1361 }
1362}
1363
1364asmlinkage void cache_parity_error(void)
1365{
1366 const int field = 2 * sizeof(unsigned long);
1367 unsigned int reg_val;
1368
1369 /* For the moment, report the problem and hang. */
1370 printk("Cache error exception:\n");
1371 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1372 reg_val = read_c0_cacheerr();
1373 printk("c0_cacheerr == %08x\n", reg_val);
1374
1375 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1376 reg_val & (1<<30) ? "secondary" : "primary",
1377 reg_val & (1<<31) ? "data" : "insn");
1378 printk("Error bits: %s%s%s%s%s%s%s\n",
1379 reg_val & (1<<29) ? "ED " : "",
1380 reg_val & (1<<28) ? "ET " : "",
1381 reg_val & (1<<26) ? "EE " : "",
1382 reg_val & (1<<25) ? "EB " : "",
1383 reg_val & (1<<24) ? "EI " : "",
1384 reg_val & (1<<23) ? "E1 " : "",
1385 reg_val & (1<<22) ? "E0 " : "");
1386 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1387
Ralf Baechleec917c2c2005-10-07 16:58:15 +01001388#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001389 if (reg_val & (1<<22))
1390 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1391
1392 if (reg_val & (1<<23))
1393 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1394#endif
1395
1396 panic("Can't handle the cache error!");
1397}
1398
1399/*
1400 * SDBBP EJTAG debug exception handler.
1401 * We skip the instruction and return to the next instruction.
1402 */
1403void ejtag_exception_handler(struct pt_regs *regs)
1404{
1405 const int field = 2 * sizeof(unsigned long);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001406 unsigned long depc, old_epc, old_ra;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407 unsigned int debug;
1408
Chris Dearman70ae6122006-06-30 12:32:37 +01001409 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410 depc = read_c0_depc();
1411 debug = read_c0_debug();
Chris Dearman70ae6122006-06-30 12:32:37 +01001412 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413 if (debug & 0x80000000) {
1414 /*
1415 * In branch delay slot.
1416 * We cheat a little bit here and use EPC to calculate the
1417 * debug return address (DEPC). EPC is restored after the
1418 * calculation.
1419 */
1420 old_epc = regs->cp0_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001421 old_ra = regs->regs[31];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001422 regs->cp0_epc = depc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001423 compute_return_epc(regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001424 depc = regs->cp0_epc;
1425 regs->cp0_epc = old_epc;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001426 regs->regs[31] = old_ra;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001427 } else
1428 depc += 4;
1429 write_c0_depc(depc);
1430
1431#if 0
Chris Dearman70ae6122006-06-30 12:32:37 +01001432 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433 write_c0_debug(debug | 0x100);
1434#endif
1435}
1436
1437/*
1438 * NMI exception handler.
Kevin Cernekee34bd92e2011-11-16 01:25:44 +00001439 * No lock; only written during early bootup by CPU 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001440 */
Kevin Cernekee34bd92e2011-11-16 01:25:44 +00001441static RAW_NOTIFIER_HEAD(nmi_chain);
1442
1443int register_nmi_notifier(struct notifier_block *nb)
1444{
1445 return raw_notifier_chain_register(&nmi_chain, nb);
1446}
1447
Joe Perchesff2d8b12012-01-12 17:17:21 -08001448void __noreturn nmi_exception_handler(struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449{
Kevin Cernekee34bd92e2011-11-16 01:25:44 +00001450 raw_notifier_call_chain(&nmi_chain, 0, regs);
Ralf Baechle41c594a2006-04-05 09:45:45 +01001451 bust_spinlocks(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001452 printk("NMI taken!!!!\n");
1453 die("NMI", regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454}
1455
Ralf Baechlee01402b2005-07-14 15:57:16 +00001456#define VECTORSPACING 0x100 /* for EI/VI mode */
1457
1458unsigned long ebase;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001459unsigned long exception_handlers[32];
Ralf Baechlee01402b2005-07-14 15:57:16 +00001460unsigned long vi_handlers[64];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461
Florian Fainelli2d1b6e92010-01-28 15:21:42 +01001462void __init *set_except_vector(int n, void *addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463{
1464 unsigned long handler = (unsigned long) addr;
Ralf Baechleb22d1b62013-05-09 17:57:30 +02001465 unsigned long old_handler;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001466
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001467#ifdef CONFIG_CPU_MICROMIPS
1468 /*
1469 * Only the TLB handlers are cache aligned with an even
1470 * address. All other handlers are on an odd address and
1471 * require no modification. Otherwise, MIPS32 mode will
1472 * be entered when handling any TLB exceptions. That
1473 * would be bad...since we must stay in microMIPS mode.
1474 */
1475 if (!(handler & 0x1))
1476 handler |= 1;
1477#endif
Ralf Baechleb22d1b62013-05-09 17:57:30 +02001478 old_handler = xchg(&exception_handlers[n], handler);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001479
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480 if (n == 0 && cpu_has_divec) {
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001481#ifdef CONFIG_CPU_MICROMIPS
1482 unsigned long jump_mask = ~((1 << 27) - 1);
1483#else
Florian Fainelli92bbe1b2010-01-28 15:22:37 +01001484 unsigned long jump_mask = ~((1 << 28) - 1);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001485#endif
Florian Fainelli92bbe1b2010-01-28 15:22:37 +01001486 u32 *buf = (u32 *)(ebase + 0x200);
1487 unsigned int k0 = 26;
1488 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1489 uasm_i_j(&buf, handler & ~jump_mask);
1490 uasm_i_nop(&buf);
1491 } else {
1492 UASM_i_LA(&buf, k0, handler);
1493 uasm_i_jr(&buf, k0);
1494 uasm_i_nop(&buf);
1495 }
1496 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001497 }
1498 return (void *)old_handler;
1499}
1500
Ralf Baechle86a17082013-02-08 01:21:34 +01001501static void do_default_vi(void)
Atsushi Nemoto6ba07e52007-05-21 23:45:38 +09001502{
1503 show_regs(get_irq_regs());
1504 panic("Caught unexpected vectored interrupt.");
1505}
1506
Ralf Baechleef300e42007-05-06 18:31:18 +01001507static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
Ralf Baechlee01402b2005-07-14 15:57:16 +00001508{
1509 unsigned long handler;
1510 unsigned long old_handler = vi_handlers[n];
Ralf Baechlef6771db2007-11-08 18:02:29 +00001511 int srssets = current_cpu_data.srsets;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001512 u16 *h;
Ralf Baechlee01402b2005-07-14 15:57:16 +00001513 unsigned char *b;
1514
Ralf Baechleb72b7092009-03-30 14:49:44 +02001515 BUG_ON(!cpu_has_veic && !cpu_has_vint);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001516 BUG_ON((n < 0) && (n > 9));
Ralf Baechlee01402b2005-07-14 15:57:16 +00001517
1518 if (addr == NULL) {
1519 handler = (unsigned long) do_default_vi;
1520 srs = 0;
Ralf Baechle41c594a2006-04-05 09:45:45 +01001521 } else
Ralf Baechlee01402b2005-07-14 15:57:16 +00001522 handler = (unsigned long) addr;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001523 vi_handlers[n] = handler;
Ralf Baechlee01402b2005-07-14 15:57:16 +00001524
1525 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1526
Ralf Baechlef6771db2007-11-08 18:02:29 +00001527 if (srs >= srssets)
Ralf Baechlee01402b2005-07-14 15:57:16 +00001528 panic("Shadow register set %d not supported", srs);
1529
1530 if (cpu_has_veic) {
1531 if (board_bind_eic_interrupt)
Ralf Baechle49a89ef2007-10-11 23:46:15 +01001532 board_bind_eic_interrupt(n, srs);
Ralf Baechle41c594a2006-04-05 09:45:45 +01001533 } else if (cpu_has_vint) {
Ralf Baechlee01402b2005-07-14 15:57:16 +00001534 /* SRSMap is only defined if shadow sets are implemented */
Ralf Baechlef6771db2007-11-08 18:02:29 +00001535 if (srssets > 1)
Ralf Baechle49a89ef2007-10-11 23:46:15 +01001536 change_c0_srsmap(0xf << n*4, srs << n*4);
Ralf Baechlee01402b2005-07-14 15:57:16 +00001537 }
1538
1539 if (srs == 0) {
1540 /*
1541 * If no shadow set is selected then use the default handler
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001542 * that does normal register saving and standard interrupt exit
Ralf Baechlee01402b2005-07-14 15:57:16 +00001543 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00001544 extern char except_vec_vi, except_vec_vi_lui;
1545 extern char except_vec_vi_ori, except_vec_vi_end;
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09001546 extern char rollback_except_vec_vi;
Ralf Baechlef94d9a82013-05-21 17:30:36 +02001547 char *vec_start = using_rollback_handler() ?
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09001548 &rollback_except_vec_vi : &except_vec_vi;
Ralf Baechle41c594a2006-04-05 09:45:45 +01001549#ifdef CONFIG_MIPS_MT_SMTC
1550 /*
1551 * We need to provide the SMTC vectored interrupt handler
1552 * not only with the address of the handler, but with the
1553 * Status.IM bit to be masked before going there.
1554 */
1555 extern char except_vec_vi_mori;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001556#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1557 const int mori_offset = &except_vec_vi_mori - vec_start + 2;
1558#else
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09001559 const int mori_offset = &except_vec_vi_mori - vec_start;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001560#endif
Ralf Baechle41c594a2006-04-05 09:45:45 +01001561#endif /* CONFIG_MIPS_MT_SMTC */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001562#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
1563 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
1564 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
1565#else
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09001566 const int lui_offset = &except_vec_vi_lui - vec_start;
1567 const int ori_offset = &except_vec_vi_ori - vec_start;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001568#endif
1569 const int handler_len = &except_vec_vi_end - vec_start;
Ralf Baechlee01402b2005-07-14 15:57:16 +00001570
1571 if (handler_len > VECTORSPACING) {
1572 /*
1573 * Sigh... panicing won't help as the console
1574 * is probably not configured :(
1575 */
Ralf Baechle49a89ef2007-10-11 23:46:15 +01001576 panic("VECTORSPACING too small");
Ralf Baechlee01402b2005-07-14 15:57:16 +00001577 }
1578
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001579 set_handler(((unsigned long)b - ebase), vec_start,
1580#ifdef CONFIG_CPU_MICROMIPS
1581 (handler_len - 1));
1582#else
1583 handler_len);
1584#endif
Ralf Baechle41c594a2006-04-05 09:45:45 +01001585#ifdef CONFIG_MIPS_MT_SMTC
Ralf Baechle8e8a52e2007-05-31 14:00:19 +01001586 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1587
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001588 h = (u16 *)(b + mori_offset);
1589 *h = (0x100 << n);
Ralf Baechle41c594a2006-04-05 09:45:45 +01001590#endif /* CONFIG_MIPS_MT_SMTC */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001591 h = (u16 *)(b + lui_offset);
1592 *h = (handler >> 16) & 0xffff;
1593 h = (u16 *)(b + ori_offset);
1594 *h = (handler & 0xffff);
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02001595 local_flush_icache_range((unsigned long)b,
1596 (unsigned long)(b+handler_len));
Ralf Baechlee01402b2005-07-14 15:57:16 +00001597 }
1598 else {
1599 /*
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001600 * In other cases jump directly to the interrupt handler. It
1601 * is the handler's responsibility to save registers if required
1602 * (eg hi/lo) and return from the exception using "eret".
Ralf Baechlee01402b2005-07-14 15:57:16 +00001603 */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001604 u32 insn;
1605
1606 h = (u16 *)b;
1607 /* j handler */
1608#ifdef CONFIG_CPU_MICROMIPS
1609 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
1610#else
1611 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
1612#endif
1613 h[0] = (insn >> 16) & 0xffff;
1614 h[1] = insn & 0xffff;
1615 h[2] = 0;
1616 h[3] = 0;
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02001617 local_flush_icache_range((unsigned long)b,
1618 (unsigned long)(b+8));
Ralf Baechlee01402b2005-07-14 15:57:16 +00001619 }
1620
1621 return (void *)old_handler;
1622}
1623
Ralf Baechleef300e42007-05-06 18:31:18 +01001624void *set_vi_handler(int n, vi_handler_t addr)
Ralf Baechlee01402b2005-07-14 15:57:16 +00001625{
Ralf Baechleff3eab22006-03-29 14:12:58 +01001626 return set_vi_srs_handler(n, addr, 0);
Ralf Baechlee01402b2005-07-14 15:57:16 +00001627}
Ralf Baechlef41ae0b2006-06-05 17:24:46 +01001628
Linus Torvalds1da177e2005-04-16 15:20:36 -07001629extern void tlb_init(void);
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001630extern void flush_tlb_handlers(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001631
Ralf Baechle42f77542007-10-18 17:48:11 +01001632/*
1633 * Timer interrupt
1634 */
1635int cp0_compare_irq;
Ralf Baechle68b63522012-07-19 09:13:52 +02001636EXPORT_SYMBOL_GPL(cp0_compare_irq);
David VomLehn010c1082009-12-21 17:49:22 -08001637int cp0_compare_irq_shift;
Ralf Baechle42f77542007-10-18 17:48:11 +01001638
1639/*
1640 * Performance counter IRQ or -1 if shared with timer
1641 */
1642int cp0_perfcount_irq;
1643EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1644
Chris Dearmanbdc94eb2007-10-03 10:43:56 +01001645static int __cpuinitdata noulri;
1646
1647static int __init ulri_disable(char *s)
1648{
1649 pr_info("Disabling ulri\n");
1650 noulri = 1;
1651
1652 return 1;
1653}
1654__setup("noulri", ulri_disable);
1655
David Daney6650df32012-05-15 00:04:50 -07001656void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001657{
1658 unsigned int cpu = smp_processor_id();
1659 unsigned int status_set = ST0_CU0;
Kevin Cernekee18d693b2010-10-16 14:22:38 -07001660 unsigned int hwrena = cpu_hwrena_impl_bits;
Ralf Baechle41c594a2006-04-05 09:45:45 +01001661#ifdef CONFIG_MIPS_MT_SMTC
1662 int secondaryTC = 0;
1663 int bootTC = (cpu == 0);
1664
1665 /*
1666 * Only do per_cpu_trap_init() for first TC of Each VPE.
1667 * Note that this hack assumes that the SMTC init code
1668 * assigns TCs consecutively and in ascending order.
1669 */
1670
1671 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1672 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1673 secondaryTC = 1;
1674#endif /* CONFIG_MIPS_MT_SMTC */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001675
1676 /*
1677 * Disable coprocessors and select 32-bit or 64-bit addressing
1678 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1679 * flag that some firmware may have left set and the TS bit (for
1680 * IP27). Set XX for ISA IV code to work.
1681 */
Ralf Baechle875d43e2005-09-03 15:56:16 -07001682#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001683 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1684#endif
Deng-Cheng Zhuadb37892013-04-01 18:14:28 +00001685 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001686 status_set |= ST0_XX;
Chris Dearmanbbaf2382007-12-13 22:42:19 +00001687 if (cpu_has_dsp)
1688 status_set |= ST0_MX;
1689
Ralf Baechleb38c7392006-02-07 01:20:43 +00001690 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001691 status_set);
1692
Kevin Cernekee18d693b2010-10-16 14:22:38 -07001693 if (cpu_has_mips_r2)
1694 hwrena |= 0x0000000f;
Ralf Baechlea3692022007-07-10 17:33:02 +01001695
Kevin Cernekee18d693b2010-10-16 14:22:38 -07001696 if (!noulri && cpu_has_userlocal)
1697 hwrena |= (1 << 29);
Ralf Baechlea3692022007-07-10 17:33:02 +01001698
Kevin Cernekee18d693b2010-10-16 14:22:38 -07001699 if (hwrena)
1700 write_c0_hwrena(hwrena);
Ralf Baechlee01402b2005-07-14 15:57:16 +00001701
Ralf Baechle41c594a2006-04-05 09:45:45 +01001702#ifdef CONFIG_MIPS_MT_SMTC
1703 if (!secondaryTC) {
1704#endif /* CONFIG_MIPS_MT_SMTC */
1705
Ralf Baechlee01402b2005-07-14 15:57:16 +00001706 if (cpu_has_veic || cpu_has_vint) {
Chris Dearman9fb4c2b2009-03-20 15:33:55 -07001707 unsigned long sr = set_c0_status(ST0_BEV);
Ralf Baechle49a89ef2007-10-11 23:46:15 +01001708 write_c0_ebase(ebase);
Chris Dearman9fb4c2b2009-03-20 15:33:55 -07001709 write_c0_status(sr);
Ralf Baechlee01402b2005-07-14 15:57:16 +00001710 /* Setting vector spacing enables EI/VI mode */
Ralf Baechle49a89ef2007-10-11 23:46:15 +01001711 change_c0_intctl(0x3e0, VECTORSPACING);
Ralf Baechlee01402b2005-07-14 15:57:16 +00001712 }
Ralf Baechled03d0a52005-08-17 13:44:26 +00001713 if (cpu_has_divec) {
1714 if (cpu_has_mipsmt) {
1715 unsigned int vpflags = dvpe();
1716 set_c0_cause(CAUSEF_IV);
1717 evpe(vpflags);
1718 } else
1719 set_c0_cause(CAUSEF_IV);
1720 }
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01001721
1722 /*
1723 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1724 *
1725 * o read IntCtl.IPTI to determine the timer interrupt
1726 * o read IntCtl.IPPCI to determine the performance counter interrupt
1727 */
1728 if (cpu_has_mips_r2) {
David VomLehn010c1082009-12-21 17:49:22 -08001729 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1730 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1731 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
Chris Dearmanc3e838a2007-06-21 12:59:57 +01001732 if (cp0_perfcount_irq == cp0_compare_irq)
1733 cp0_perfcount_irq = -1;
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01001734 } else {
1735 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
Ralf Baechlec6a4ebb2012-07-06 23:56:00 +02001736 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
Chris Dearmanc3e838a2007-06-21 12:59:57 +01001737 cp0_perfcount_irq = -1;
Ralf Baechle3b1d4ed2007-06-20 22:27:10 +01001738 }
1739
Ralf Baechle41c594a2006-04-05 09:45:45 +01001740#ifdef CONFIG_MIPS_MT_SMTC
1741 }
1742#endif /* CONFIG_MIPS_MT_SMTC */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001743
David Daney48c4ac92013-05-13 13:56:44 -07001744 if (!cpu_data[cpu].asid_cache)
1745 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001746
1747 atomic_inc(&init_mm.mm_count);
1748 current->active_mm = &init_mm;
1749 BUG_ON(current->mm);
1750 enter_lazy_tlb(&init_mm, current);
1751
Ralf Baechle41c594a2006-04-05 09:45:45 +01001752#ifdef CONFIG_MIPS_MT_SMTC
1753 if (bootTC) {
1754#endif /* CONFIG_MIPS_MT_SMTC */
David Daney6650df32012-05-15 00:04:50 -07001755 /* Boot CPU's cache setup in setup_arch(). */
1756 if (!is_boot_cpu)
1757 cpu_cache_init();
Ralf Baechle41c594a2006-04-05 09:45:45 +01001758 tlb_init();
1759#ifdef CONFIG_MIPS_MT_SMTC
Ralf Baechle6a058882007-05-31 14:03:45 +01001760 } else if (!secondaryTC) {
1761 /*
1762 * First TC in non-boot VPE must do subset of tlb_init()
1763 * for MMU countrol registers.
1764 */
1765 write_c0_pagemask(PM_DEFAULT_MASK);
1766 write_c0_wired(0);
Ralf Baechle41c594a2006-04-05 09:45:45 +01001767 }
1768#endif /* CONFIG_MIPS_MT_SMTC */
David Daney3d8bfdd2010-12-21 14:19:11 -08001769 TLBMISS_HANDLER_SETUP();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001770}
1771
Ralf Baechlee01402b2005-07-14 15:57:16 +00001772/* Install CPU exception handler */
David Daneye3dc81f2012-05-15 00:04:47 -07001773void __cpuinit set_handler(unsigned long offset, void *addr, unsigned long size)
Ralf Baechlee01402b2005-07-14 15:57:16 +00001774{
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001775#ifdef CONFIG_CPU_MICROMIPS
1776 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
1777#else
Ralf Baechlee01402b2005-07-14 15:57:16 +00001778 memcpy((void *)(ebase + offset), addr, size);
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001779#endif
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02001780 local_flush_icache_range(ebase + offset, ebase + offset + size);
Ralf Baechlee01402b2005-07-14 15:57:16 +00001781}
1782
Ralf Baechle234fcd12008-03-08 09:56:28 +00001783static char panic_null_cerr[] __cpuinitdata =
Ralf Baechle641e97f2007-10-11 23:46:05 +01001784 "Trying to set NULL cache error exception handler";
1785
Ralf Baechle42fe7ee2009-01-28 18:48:23 +00001786/*
1787 * Install uncached CPU exception handler.
1788 * This is suitable only for the cache error exception which is the only
1789 * exception handler that is being run uncached.
1790 */
Ralf Baechle234fcd12008-03-08 09:56:28 +00001791void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1792 unsigned long size)
Ralf Baechlee01402b2005-07-14 15:57:16 +00001793{
Sebastian Andrzej Siewior4f81b012010-04-27 22:53:30 +02001794 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
Ralf Baechlee01402b2005-07-14 15:57:16 +00001795
Ralf Baechle641e97f2007-10-11 23:46:05 +01001796 if (!addr)
1797 panic(panic_null_cerr);
1798
Ralf Baechlee01402b2005-07-14 15:57:16 +00001799 memcpy((void *)(uncached_ebase + offset), addr, size);
1800}
1801
Atsushi Nemoto5b104962006-09-11 17:50:29 +09001802static int __initdata rdhwr_noopt;
1803static int __init set_rdhwr_noopt(char *str)
1804{
1805 rdhwr_noopt = 1;
1806 return 1;
1807}
1808
1809__setup("rdhwr_noopt", set_rdhwr_noopt);
1810
Linus Torvalds1da177e2005-04-16 15:20:36 -07001811void __init trap_init(void)
1812{
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001813 extern char except_vec3_generic;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814 extern char except_vec4;
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001815 extern char except_vec3_r4000;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001816 unsigned long i;
Atsushi Nemotoc65a5482007-11-12 02:05:18 +09001817
1818 check_wait();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001819
Jason Wessel88547002008-07-29 15:58:53 -05001820#if defined(CONFIG_KGDB)
1821 if (kgdb_early_setup)
Ralf Baechle70342282013-01-22 12:59:30 +01001822 return; /* Already done */
Jason Wessel88547002008-07-29 15:58:53 -05001823#endif
1824
Chris Dearman9fb4c2b2009-03-20 15:33:55 -07001825 if (cpu_has_veic || cpu_has_vint) {
1826 unsigned long size = 0x200 + VECTORSPACING*64;
1827 ebase = (unsigned long)
1828 __alloc_bootmem(size, 1 << fls(size), 0);
1829 } else {
Sanjay Lal9843b032012-11-21 18:34:03 -08001830#ifdef CONFIG_KVM_GUEST
1831#define KVM_GUEST_KSEG0 0x40000000
1832 ebase = KVM_GUEST_KSEG0;
1833#else
1834 ebase = CKSEG0;
1835#endif
David Daney566f74f2008-10-23 17:56:35 -07001836 if (cpu_has_mips_r2)
1837 ebase += (read_c0_ebase() & 0x3ffff000);
1838 }
Ralf Baechlee01402b2005-07-14 15:57:16 +00001839
Kevin Cernekee6fb97ef2011-11-16 01:25:45 +00001840 if (board_ebase_setup)
1841 board_ebase_setup();
David Daney6650df32012-05-15 00:04:50 -07001842 per_cpu_trap_init(true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001843
1844 /*
1845 * Copy the generic exception handlers to their final destination.
1846 * This will be overriden later as suitable for a particular
1847 * configuration.
1848 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00001849 set_handler(0x180, &except_vec3_generic, 0x80);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001850
1851 /*
1852 * Setup default vectors
1853 */
1854 for (i = 0; i <= 31; i++)
1855 set_except_vector(i, handle_reserved);
1856
1857 /*
1858 * Copy the EJTAG debug exception vector handler code to it's final
1859 * destination.
1860 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00001861 if (cpu_has_ejtag && board_ejtag_handler_setup)
Ralf Baechle49a89ef2007-10-11 23:46:15 +01001862 board_ejtag_handler_setup();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001863
1864 /*
1865 * Only some CPUs have the watch exceptions.
1866 */
1867 if (cpu_has_watch)
1868 set_except_vector(23, handle_watch);
1869
1870 /*
Ralf Baechlee01402b2005-07-14 15:57:16 +00001871 * Initialise interrupt handlers
Linus Torvalds1da177e2005-04-16 15:20:36 -07001872 */
Ralf Baechlee01402b2005-07-14 15:57:16 +00001873 if (cpu_has_veic || cpu_has_vint) {
1874 int nvec = cpu_has_veic ? 64 : 8;
1875 for (i = 0; i < nvec; i++)
Ralf Baechleff3eab22006-03-29 14:12:58 +01001876 set_vi_handler(i, NULL);
Ralf Baechlee01402b2005-07-14 15:57:16 +00001877 }
1878 else if (cpu_has_divec)
1879 set_handler(0x200, &except_vec4, 0x8);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001880
1881 /*
1882 * Some CPUs can enable/disable for cache parity detection, but does
1883 * it different ways.
1884 */
1885 parity_protection_init();
1886
1887 /*
1888 * The Data Bus Errors / Instruction Bus Errors are signaled
1889 * by external hardware. Therefore these two exceptions
1890 * may have board specific handlers.
1891 */
1892 if (board_be_init)
1893 board_be_init();
1894
Ralf Baechlef94d9a82013-05-21 17:30:36 +02001895 set_except_vector(0, using_rollback_handler() ? rollback_handle_int
1896 : handle_int);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001897 set_except_vector(1, handle_tlbm);
1898 set_except_vector(2, handle_tlbl);
1899 set_except_vector(3, handle_tlbs);
1900
1901 set_except_vector(4, handle_adel);
1902 set_except_vector(5, handle_ades);
1903
1904 set_except_vector(6, handle_ibe);
1905 set_except_vector(7, handle_dbe);
1906
1907 set_except_vector(8, handle_sys);
1908 set_except_vector(9, handle_bp);
Atsushi Nemoto5b104962006-09-11 17:50:29 +09001909 set_except_vector(10, rdhwr_noopt ? handle_ri :
1910 (cpu_has_vtag_icache ?
1911 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001912 set_except_vector(11, handle_cpu);
1913 set_except_vector(12, handle_ov);
1914 set_except_vector(13, handle_tr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001915
Ralf Baechle10cc3522007-10-11 23:46:15 +01001916 if (current_cpu_type() == CPU_R6000 ||
1917 current_cpu_type() == CPU_R6000A) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001918 /*
1919 * The R6000 is the only R-series CPU that features a machine
1920 * check exception (similar to the R4000 cache error) and
1921 * unaligned ldc1/sdc1 exception. The handlers have not been
Ralf Baechle70342282013-01-22 12:59:30 +01001922 * written yet. Well, anyway there is no R6000 machine on the
Linus Torvalds1da177e2005-04-16 15:20:36 -07001923 * current list of targets for Linux/MIPS.
1924 * (Duh, crap, there is someone with a triple R6k machine)
1925 */
1926 //set_except_vector(14, handle_mc);
1927 //set_except_vector(15, handle_ndc);
1928 }
1929
Ralf Baechlee01402b2005-07-14 15:57:16 +00001930
1931 if (board_nmi_handler_setup)
1932 board_nmi_handler_setup();
1933
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +00001934 if (cpu_has_fpu && !cpu_has_nofpuex)
1935 set_except_vector(15, handle_fpe);
1936
1937 set_except_vector(22, handle_mdmx);
1938
1939 if (cpu_has_mcheck)
1940 set_except_vector(24, handle_mcheck);
1941
Ralf Baechle340ee4b2005-08-17 17:44:08 +00001942 if (cpu_has_mipsmt)
1943 set_except_vector(25, handle_mt);
1944
Chris Dearmanacaec422007-05-24 22:30:18 +01001945 set_except_vector(26, handle_dsp);
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +00001946
David Daneyfcbf1df2012-05-15 00:04:46 -07001947 if (board_cache_error_setup)
1948 board_cache_error_setup();
1949
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +00001950 if (cpu_has_vce)
1951 /* Special exception: R4[04]00 uses also the divec space. */
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001952 set_handler(0x180, &except_vec3_r4000, 0x100);
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +00001953 else if (cpu_has_4kex)
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001954 set_handler(0x180, &except_vec3_generic, 0x80);
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +00001955 else
Steven J. Hill2a0b24f2013-03-25 12:15:55 -05001956 set_handler(0x080, &except_vec3_generic, 0x80);
Ralf Baechlee50c0a8f2005-05-31 11:49:19 +00001957
Thomas Bogendoerfere0cee3e2008-08-04 20:53:57 +02001958 local_flush_icache_range(ebase, ebase + 0x400);
Ralf Baechle1d40cfc2005-07-15 15:23:23 +00001959 flush_tlb_handlers();
Thomas Bogendoerfer05106172008-08-04 19:44:34 +02001960
1961 sort_extable(__start___dbe_table, __stop___dbe_table);
Ralf Baechle69f3a7d2009-11-24 01:24:58 +00001962
Ralf Baechle4483b152010-08-05 13:25:59 +01001963 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001964}