| Arnd Bergmann | cebf589 | 2005-06-23 09:43:43 +1000 | [diff] [blame] | 1 | #ifndef ASM_BPA_IIC_H |
| 2 | #define ASM_BPA_IIC_H |
| 3 | #ifdef __KERNEL__ |
| 4 | /* |
| 5 | * Mapping of IIC pending bits into per-node |
| 6 | * interrupt numbers. |
| 7 | * |
| 8 | * IRQ FF CC SS PP FF CC SS PP Description |
| 9 | * |
| 10 | * 00-3f 80 02 +0 00 - 80 02 +0 3f South Bridge |
| 11 | * 00-3f 80 02 +b 00 - 80 02 +b 3f South Bridge |
| 12 | * 41-4a 80 00 +1 ** - 80 00 +a ** SPU Class 0 |
| 13 | * 51-5a 80 01 +1 ** - 80 01 +a ** SPU Class 1 |
| 14 | * 61-6a 80 02 +1 ** - 80 02 +a ** SPU Class 2 |
| 15 | * 70-7f C0 ** ** 00 - C0 ** ** 0f IPI |
| 16 | * |
| 17 | * F flags |
| 18 | * C class |
| 19 | * S source |
| 20 | * P Priority |
| 21 | * + node number |
| 22 | * * don't care |
| 23 | * |
| 24 | * A node consists of a Broadband Engine and an optional |
| 25 | * south bridge device providing a maximum of 64 IRQs. |
| 26 | * The south bridge may be connected to either IOIF0 |
| 27 | * or IOIF1. |
| 28 | * Each SPE is represented as three IRQ lines, one per |
| 29 | * interrupt class. |
| 30 | * 16 IRQ numbers are reserved for inter processor |
| 31 | * interruptions, although these are only used in the |
| 32 | * range of the first node. |
| 33 | * |
| 34 | * This scheme needs 128 IRQ numbers per BIF node ID, |
| 35 | * which means that with the total of 512 lines |
| 36 | * available, we can have a maximum of four nodes. |
| 37 | */ |
| 38 | |
| 39 | enum { |
| 40 | IIC_EXT_OFFSET = 0x00, /* Start of south bridge IRQs */ |
| 41 | IIC_NUM_EXT = 0x40, /* Number of south bridge IRQs */ |
| 42 | IIC_SPE_OFFSET = 0x40, /* Start of SPE interrupts */ |
| 43 | IIC_CLASS_STRIDE = 0x10, /* SPE IRQs per class */ |
| 44 | IIC_IPI_OFFSET = 0x70, /* Start of IPI IRQs */ |
| 45 | IIC_NUM_IPIS = 0x10, /* IRQs reserved for IPI */ |
| 46 | IIC_NODE_STRIDE = 0x80, /* Total IRQs per node */ |
| 47 | }; |
| 48 | |
| 49 | extern void iic_init_IRQ(void); |
| 50 | extern int iic_get_irq(struct pt_regs *regs); |
| 51 | extern void iic_cause_IPI(int cpu, int mesg); |
| 52 | extern void iic_request_IPIs(void); |
| 53 | extern void iic_setup_cpu(void); |
| 54 | extern void iic_local_enable(void); |
| 55 | extern void iic_local_disable(void); |
| 56 | |
| 57 | |
| 58 | extern void spider_init_IRQ(void); |
| 59 | extern int spider_get_irq(unsigned long int_pending); |
| 60 | |
| 61 | #endif |
| 62 | #endif /* ASM_BPA_IIC_H */ |