blob: 7750da27628412bc4eb7e406ec2a14669d2fa265 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
3 * Copyright (C) 2003, 2004 Paul Mundt
4 * Copyright (C) 2004 Richard Curnow
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * Support functions for the SH5 PCI hardware.
10 */
11
Linus Torvalds1da177e2005-04-16 15:20:36 -070012#include <linux/kernel.h>
13#include <linux/rwsem.h>
14#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <linux/interrupt.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/types.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/irq.h>
Paul Mundtf15cbe62008-07-29 08:09:44 +090022#include <cpu/irq.h>
Paul Mundtb6d7b662007-11-22 16:29:10 +090023#include <asm/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <asm/io.h>
Paul Mundtb6d7b662007-11-22 16:29:10 +090025#include "pci-sh5.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
Paul Mundtb6d7b662007-11-22 16:29:10 +090027unsigned long pcicr_virt;
28unsigned long PCI_IO_AREA;
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Magnus Dammd0e3db42009-03-11 15:46:14 +090030int __init sh5_pci_init(struct pci_channel *chan)
31{
32 pr_debug("PCI: Starting intialization.\n");
33 return pcibios_init_platform();
34}
35
Linus Torvalds1da177e2005-04-16 15:20:36 -070036/* Rounds a number UP to the nearest power of two. Used for
37 * sizing the PCI window.
38 */
39static u32 __init r2p2(u32 num)
40{
41 int i = 31;
42 u32 tmp = num;
43
44 if (num == 0)
45 return 0;
46
47 do {
48 if (tmp & (1 << 31))
49 break;
50 i--;
51 tmp <<= 1;
52 } while (i >= 0);
53
54 tmp = 1 << i;
55 /* If the original number isn't a power of 2, round it up */
56 if (tmp != num)
57 tmp <<= 1;
58
59 return tmp;
60}
61
Paul Mundta226d332007-05-14 09:10:01 +090062static irqreturn_t pcish5_err_irq(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -070063{
Paul Mundta226d332007-05-14 09:10:01 +090064 struct pt_regs *regs = get_irq_regs();
Linus Torvalds1da177e2005-04-16 15:20:36 -070065 unsigned pci_int, pci_air, pci_cir, pci_aint;
66
67 pci_int = SH5PCI_READ(INT);
68 pci_cir = SH5PCI_READ(CIR);
69 pci_air = SH5PCI_READ(AIR);
70
71 if (pci_int) {
72 printk("PCI INTERRUPT (at %08llx)!\n", regs->pc);
73 printk("PCI INT -> 0x%x\n", pci_int & 0xffff);
74 printk("PCI AIR -> 0x%x\n", pci_air);
75 printk("PCI CIR -> 0x%x\n", pci_cir);
76 SH5PCI_WRITE(INT, ~0);
77 }
78
79 pci_aint = SH5PCI_READ(AINT);
80 if (pci_aint) {
81 printk("PCI ARB INTERRUPT!\n");
82 printk("PCI AINT -> 0x%x\n", pci_aint);
83 printk("PCI AIR -> 0x%x\n", pci_air);
84 printk("PCI CIR -> 0x%x\n", pci_cir);
85 SH5PCI_WRITE(AINT, ~0);
86 }
87
88 return IRQ_HANDLED;
89}
90
Paul Mundta226d332007-05-14 09:10:01 +090091static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -070092{
93 printk("SERR IRQ\n");
94
95 return IRQ_NONE;
96}
97
Paul Mundtb6d7b662007-11-22 16:29:10 +090098int __init sh5pci_init(unsigned long memStart, unsigned long memSize)
Linus Torvalds1da177e2005-04-16 15:20:36 -070099{
Paul Mundtb6d7b662007-11-22 16:29:10 +0900100 u32 lsr0;
101 u32 uval;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103 if (request_irq(IRQ_ERR, pcish5_err_irq,
Thomas Gleixner5fb55ae2006-07-01 19:29:24 -0700104 IRQF_DISABLED, "PCI Error",NULL) < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 printk(KERN_ERR "PCISH5: Cannot hook PCI_PERR interrupt\n");
106 return -EINVAL;
107 }
108
109 if (request_irq(IRQ_SERR, pcish5_serr_irq,
Thomas Gleixner5fb55ae2006-07-01 19:29:24 -0700110 IRQF_DISABLED, "PCI SERR interrupt", NULL) < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 printk(KERN_ERR "PCISH5: Cannot hook PCI_SERR interrupt\n");
112 return -EINVAL;
113 }
114
Paul Mundtb6d7b662007-11-22 16:29:10 +0900115 pcicr_virt = onchip_remap(SH5PCI_ICR_BASE, 1024, "PCICR");
116 if (!pcicr_virt) {
117 panic("Unable to remap PCICR\n");
118 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119
Paul Mundtb6d7b662007-11-22 16:29:10 +0900120 PCI_IO_AREA = onchip_remap(SH5PCI_IO_BASE, 0x10000, "PCIIO");
121 if (!PCI_IO_AREA) {
122 panic("Unable to remap PCIIO\n");
123 }
124
125 /* Clear snoop registers */
126 SH5PCI_WRITE(CSCR0, 0);
127 SH5PCI_WRITE(CSCR1, 0);
128
129 /* Switch off interrupts */
130 SH5PCI_WRITE(INTM, 0);
131 SH5PCI_WRITE(AINTM, 0);
132 SH5PCI_WRITE(PINTM, 0);
133
134 /* Set bus active, take it out of reset */
135 uval = SH5PCI_READ(CR);
136
137 /* Set command Register */
138 SH5PCI_WRITE(CR, uval | CR_LOCK_MASK | CR_CFINT| CR_FTO | CR_PFE |
139 CR_PFCS | CR_BMAM);
140
141 uval=SH5PCI_READ(CR);
142
143 /* Allow it to be a master */
144 /* NB - WE DISABLE I/O ACCESS to stop overlap */
145 /* set WAIT bit to enable stepping, an attempt to improve stability */
146 SH5PCI_WRITE_SHORT(CSR_CMD,
147 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
148 PCI_COMMAND_WAIT);
149
150 /*
151 ** Set translation mapping memory in order to convert the address
152 ** used for the main bus, to the PCI internal address.
153 */
154 SH5PCI_WRITE(MBR,0x40000000);
155
156 /* Always set the max size 512M */
157 SH5PCI_WRITE(MBMR, PCISH5_MEM_SIZCONV(512*1024*1024));
158
159 /*
160 ** I/O addresses are mapped at internal PCI specific address
161 ** as is described into the configuration bridge table.
162 ** These are changed to 0, to allow cards that have legacy
163 ** io such as vga to function correctly. We set the SH5 IOBAR to
164 ** 256K, which is a bit big as we can only have 64K of address space
165 */
166
167 SH5PCI_WRITE(IOBR,0x0);
168
169 /* Set up a 256K window. Totally pointless waste of address space */
170 SH5PCI_WRITE(IOBMR,0);
171
172 /* The SH5 has a HUGE 256K I/O region, which breaks the PCI spec.
173 * Ideally, we would want to map the I/O region somewhere, but it
174 * is so big this is not that easy!
175 */
176 SH5PCI_WRITE(CSR_IBAR0,~0);
177 /* Set memory size value */
178 memSize = memory_end - memory_start;
179
180 /* Now we set up the mbars so the PCI bus can see the memory of
181 * the machine */
182 if (memSize < (1024 * 1024)) {
183 printk(KERN_ERR "PCISH5: Ridiculous memory size of 0x%lx?\n",
184 memSize);
185 return -EINVAL;
186 }
187
188 /* Set LSR 0 */
189 lsr0 = (memSize > (512 * 1024 * 1024)) ? 0x1ff00001 :
190 ((r2p2(memSize) - 0x100000) | 0x1);
191 SH5PCI_WRITE(LSR0, lsr0);
192
193 /* Set MBAR 0 */
194 SH5PCI_WRITE(CSR_MBAR0, memory_start);
195 SH5PCI_WRITE(LAR0, memory_start);
196
197 SH5PCI_WRITE(CSR_MBAR1,0);
198 SH5PCI_WRITE(LAR1,0);
199 SH5PCI_WRITE(LSR1,0);
200
201 /* Enable the PCI interrupts on the device */
202 SH5PCI_WRITE(INTM, ~0);
203 SH5PCI_WRITE(AINTM, ~0);
204 SH5PCI_WRITE(PINTM, ~0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205
206 return 0;
207}
208
Magnus Damm710fa3c2009-03-11 15:47:23 +0900209#define xPCIBIOS_MIN_IO board_pci_channels->io_resource->start
210#define xPCIBIOS_MIN_MEM board_pci_channels->mem_resource->start
211
Paul Mundtbeeea6d2007-07-20 13:14:07 +0900212void __devinit pcibios_fixup_bus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213{
214 struct pci_dev *dev = bus->self;
215 int i;
216
Paul Mundtb6d7b662007-11-22 16:29:10 +0900217 if (dev) {
218 for (i= 0; i < 3; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 bus->resource[i] =
220 &dev->resource[PCI_BRIDGE_RESOURCES+i];
221 bus->resource[i]->name = bus->name;
222 }
223 bus->resource[0]->flags |= IORESOURCE_IO;
224 bus->resource[1]->flags |= IORESOURCE_MEM;
225
226 /* For now, propagate host limits to the bus;
227 * we'll adjust them later. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228 bus->resource[0]->end = 64*1024 - 1 ;
Magnus Damm710fa3c2009-03-11 15:47:23 +0900229 bus->resource[1]->end = xPCIBIOS_MIN_MEM+(256*1024*1024)-1;
230 bus->resource[0]->start = xPCIBIOS_MIN_IO;
231 bus->resource[1]->start = xPCIBIOS_MIN_MEM;
Paul Mundtb6d7b662007-11-22 16:29:10 +0900232
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233 /* Turn off downstream PF memory address range by default */
234 bus->resource[2]->start = 1024*1024;
235 bus->resource[2]->end = bus->resource[2]->start - 1;
236 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237}