| Arthur Kepner | a75b0a2 | 2008-04-29 01:00:31 -0700 | [diff] [blame] | 1 | 			DMA attributes | 
 | 2 | 			============== | 
 | 3 |  | 
 | 4 | This document describes the semantics of the DMA attributes that are | 
 | 5 | defined in linux/dma-attrs.h. | 
 | 6 |  | 
 | 7 | DMA_ATTR_WRITE_BARRIER | 
 | 8 | ---------------------- | 
 | 9 |  | 
 | 10 | DMA_ATTR_WRITE_BARRIER is a (write) barrier attribute for DMA.  DMA | 
 | 11 | to a memory region with the DMA_ATTR_WRITE_BARRIER attribute forces | 
 | 12 | all pending DMA writes to complete, and thus provides a mechanism to | 
 | 13 | strictly order DMA from a device across all intervening busses and | 
 | 14 | bridges.  This barrier is not specific to a particular type of | 
 | 15 | interconnect, it applies to the system as a whole, and so its | 
 | 16 | implementation must account for the idiosyncracies of the system all | 
 | 17 | the way from the DMA device to memory. | 
 | 18 |  | 
 | 19 | As an example of a situation where DMA_ATTR_WRITE_BARRIER would be | 
 | 20 | useful, suppose that a device does a DMA write to indicate that data is | 
 | 21 | ready and available in memory.  The DMA of the "completion indication" | 
 | 22 | could race with data DMA.  Mapping the memory used for completion | 
 | 23 | indications with DMA_ATTR_WRITE_BARRIER would prevent the race. | 
 | 24 |  | 
| Mark Nelson | 1ed6af7 | 2008-07-18 23:03:34 +1000 | [diff] [blame] | 25 | DMA_ATTR_WEAK_ORDERING | 
 | 26 | ---------------------- | 
 | 27 |  | 
 | 28 | DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping | 
 | 29 | may be weakly ordered, that is that reads and writes may pass each other. | 
 | 30 |  | 
 | 31 | Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING, | 
 | 32 | those that do not will simply ignore the attribute and exhibit default | 
 | 33 | behavior. |