blob: 3a9d32cff52968bcd3dbc9b756167f4abb3d0395 [file] [log] [blame]
Richard Zhao3c8276c2011-12-14 09:26:46 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx6q.dtsi"
15
16/ {
17 model = "Freescale i.MX6 Quad SABRE Lite Board";
18 compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x40000000>;
22 };
23
24 soc {
25 aips-bus@02100000 { /* AIPS2 */
26 enet@02188000 {
27 phy-mode = "rgmii";
28 phy-reset-gpios = <&gpio3 23 0>;
29 status = "okay";
30 };
31
32 usdhc@02198000 { /* uSDHC3 */
33 cd-gpios = <&gpio7 0 0>;
34 wp-gpios = <&gpio7 1 0>;
35 status = "okay";
36 };
37
38 usdhc@0219c000 { /* uSDHC4 */
39 cd-gpios = <&gpio2 6 0>;
40 wp-gpios = <&gpio2 7 0>;
41 status = "okay";
42 };
43
44 uart2: uart@021e8000 {
45 status = "okay";
46 };
Richard Zhaoadcec4c2012-02-02 10:12:03 +080047
48 i2c@021a0000 { /* I2C1 */
49 status = "okay";
50 clock-frequency = <100000>;
51
52 codec: sgtl5000@0a {
53 compatible = "fsl,sgtl5000";
54 reg = <0x0a>;
55 VDDA-supply = <&reg_2p5v>;
56 VDDIO-supply = <&reg_3p3v>;
57 };
58 };
Richard Zhao3c8276c2011-12-14 09:26:46 +080059 };
60 };
Richard Zhaocf37a8e2012-02-02 10:12:02 +080061
62 regulators {
63 compatible = "simple-bus";
64
65 reg_2p5v: 2p5v {
66 compatible = "regulator-fixed";
67 regulator-name = "2P5V";
68 regulator-min-microvolt = <2500000>;
69 regulator-max-microvolt = <2500000>;
70 regulator-always-on;
71 };
72
73 reg_3p3v: 3p3v {
74 compatible = "regulator-fixed";
75 regulator-name = "3P3V";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
78 regulator-always-on;
79 };
80 };
Richard Zhao3c8276c2011-12-14 09:26:46 +080081};