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Thomas Petazzoni9ae6f742012-06-13 19:01:28 +02001/*
2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * This file contains the definitions that are common to the Armada
16 * 370 and Armada XP SoC.
17 */
18
19/include/ "skeleton.dtsi"
20
21/ {
22 model = "Marvell Armada 370 and XP SoC";
Thomas Petazzoni92ece1c2012-11-09 16:29:17 +010023 compatible = "marvell,armada-370-xp";
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020024
25 cpus {
26 cpu@0 {
27 compatible = "marvell,sheeva-v7";
28 };
29 };
30
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020031 soc {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "simple-bus";
35 interrupt-parent = <&mpic>;
36 ranges;
37
Thomas Petazzonib18ea4d2013-04-12 16:29:07 +020038 mpic: interrupt-controller@d0020000 {
39 compatible = "marvell,mpic";
40 #interrupt-cells = <1>;
41 #size-cells = <1>;
42 interrupt-controller;
43 };
44
45 coherency-fabric@d0020200 {
46 compatible = "marvell,coherency-fabric";
47 reg = <0xd0020200 0xb0>,
48 <0xd0021810 0x1c>;
49 };
50
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020051 serial@d0012000 {
Gregory CLEMENTb24212f2012-12-04 18:04:59 +010052 compatible = "snps,dw-apb-uart";
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020053 reg = <0xd0012000 0x100>;
54 reg-shift = <2>;
55 interrupts = <41>;
Heikki Krogeruse3661542013-03-06 11:23:33 +010056 reg-io-width = <1>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020057 status = "disabled";
58 };
59 serial@d0012100 {
Gregory CLEMENTb24212f2012-12-04 18:04:59 +010060 compatible = "snps,dw-apb-uart";
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020061 reg = <0xd0012100 0x100>;
62 reg-shift = <2>;
63 interrupts = <42>;
Heikki Krogeruse3661542013-03-06 11:23:33 +010064 reg-io-width = <1>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020065 status = "disabled";
66 };
67
68 timer@d0020300 {
69 compatible = "marvell,armada-370-xp-timer";
Gregory CLEMENTe1dd4642013-01-25 18:32:44 +010070 reg = <0xd0020300 0x30>,
71 <0xd0021040 0x30>;
72 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
Gregory CLEMENT307c2bf2012-11-17 15:22:25 +010073 clocks = <&coreclk 2>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020074 };
Thomas Petazzoni5b40bae2012-09-11 14:27:30 +020075
Gregory CLEMENTa6a6de12012-10-26 14:30:47 +020076 sata@d00a0000 {
77 compatible = "marvell,orion-sata";
78 reg = <0xd00a0000 0x2400>;
79 interrupts = <55>;
80 clocks = <&gateclk 15>, <&gateclk 30>;
81 clock-names = "0", "1";
82 status = "disabled";
83 };
84
Thomas Petazzoni323c1012012-09-04 15:06:43 +020085 mdio {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 compatible = "marvell,orion-mdio";
89 reg = <0xd0072004 0x4>;
90 };
91
92 ethernet@d0070000 {
93 compatible = "marvell,armada-370-neta";
94 reg = <0xd0070000 0x2500>;
95 interrupts = <8>;
Thomas Petazzoni4aa935a2012-11-19 14:18:09 +010096 clocks = <&gateclk 4>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +020097 status = "disabled";
98 };
99
100 ethernet@d0074000 {
101 compatible = "marvell,armada-370-neta";
102 reg = <0xd0074000 0x2500>;
103 interrupts = <10>;
Thomas Petazzoni4aa935a2012-11-19 14:18:09 +0100104 clocks = <&gateclk 3>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +0200105 status = "disabled";
106 };
Nobuhiro Iwamatsu539eb5b2012-10-30 19:41:23 +0900107
108 i2c0: i2c@d0011000 {
109 compatible = "marvell,mv64xxx-i2c";
110 reg = <0xd0011000 0x20>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 interrupts = <31>;
114 timeout-ms = <1000>;
115 clocks = <&coreclk 0>;
116 status = "disabled";
117 };
118
119 i2c1: i2c@d0011100 {
120 compatible = "marvell,mv64xxx-i2c";
121 reg = <0xd0011100 0x20>;
122 #address-cells = <1>;
123 #size-cells = <0>;
124 interrupts = <32>;
125 timeout-ms = <1000>;
126 clocks = <&coreclk 0>;
127 status = "disabled";
128 };
Gregory CLEMENT0db98542012-12-12 10:06:24 +0100129
130 rtc@10300 {
131 compatible = "marvell,orion-rtc";
132 reg = <0xd0010300 0x20>;
133 interrupts = <50>;
134 };
Thomas Petazzoni42bb5312012-12-21 15:49:04 +0100135
136 mvsdio@d00d4000 {
137 compatible = "marvell,orion-sdio";
138 reg = <0xd00d4000 0x200>;
139 interrupts = <54>;
140 clocks = <&gateclk 17>;
141 status = "disabled";
142 };
Ezequiel Garciab2bb8062013-01-23 12:26:30 -0300143
144 usb@d0050000 {
145 compatible = "marvell,orion-ehci";
146 reg = <0xd0050000 0x500>;
147 interrupts = <45>;
148 status = "disabled";
149 };
150
151 usb@d0051000 {
152 compatible = "marvell,orion-ehci";
153 reg = <0xd0051000 0x500>;
154 interrupts = <46>;
155 status = "disabled";
156 };
157
Ezequiel Garciad5dc0352013-02-06 10:06:21 -0300158 spi0: spi@d0010600 {
159 compatible = "marvell,orion-spi";
160 reg = <0xd0010600 0x28>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 cell-index = <0>;
164 interrupts = <30>;
165 clocks = <&coreclk 0>;
166 status = "disabled";
167 };
168
169 spi1: spi@d0010680 {
170 compatible = "marvell,orion-spi";
171 reg = <0xd0010680 0x28>;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 cell-index = <1>;
175 interrupts = <92>;
176 clocks = <&coreclk 0>;
177 status = "disabled";
178 };
Ezequiel Garcia3d76e1f2013-04-10 16:04:01 -0300179
180 devbus-bootcs@d0010400 {
181 compatible = "marvell,mvebu-devbus";
182 reg = <0xd0010400 0x8>;
183 #address-cells = <1>;
184 #size-cells = <1>;
185 clocks = <&coreclk 0>;
186 status = "disabled";
187 };
188
189 devbus-cs0@d0010408 {
190 compatible = "marvell,mvebu-devbus";
191 reg = <0xd0010408 0x8>;
192 #address-cells = <1>;
193 #size-cells = <1>;
194 clocks = <&coreclk 0>;
195 status = "disabled";
196 };
197
198 devbus-cs1@d0010410 {
199 compatible = "marvell,mvebu-devbus";
200 reg = <0xd0010410 0x8>;
201 #address-cells = <1>;
202 #size-cells = <1>;
203 clocks = <&coreclk 0>;
204 status = "disabled";
205 };
206
207 devbus-cs2@d0010418 {
208 compatible = "marvell,mvebu-devbus";
209 reg = <0xd0010418 0x8>;
210 #address-cells = <1>;
211 #size-cells = <1>;
212 clocks = <&coreclk 0>;
213 status = "disabled";
214 };
215
216 devbus-cs3@d0010420 {
217 compatible = "marvell,mvebu-devbus";
218 reg = <0xd0010420 0x8>;
219 #address-cells = <1>;
220 #size-cells = <1>;
221 clocks = <&coreclk 0>;
222 status = "disabled";
223 };
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200224 };
225};
226