blob: 5b4103db70f5c25025241672c19e48be6c583eaa [file] [log] [blame]
Sten Wang7a47dd72007-11-12 21:31:11 -08001/*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
Francois Romieu5ac5d612007-11-28 23:02:33 +01006 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
Florian Fainelli1caf09d2012-04-11 07:18:43 +00007 * Copyright (C) 2007-2012 Florian Fainelli <florian@openwrt.org>
Sten Wang7a47dd72007-11-12 21:31:11 -08008 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23*/
24
25#include <linux/kernel.h>
26#include <linux/module.h>
Sten Wang7a47dd72007-11-12 21:31:11 -080027#include <linux/moduleparam.h>
28#include <linux/string.h>
29#include <linux/timer.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
Sten Wang7a47dd72007-11-12 21:31:11 -080032#include <linux/interrupt.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/skbuff.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/mii.h>
40#include <linux/ethtool.h>
41#include <linux/crc32.h>
42#include <linux/spinlock.h>
Jeff Garzik092427b2007-11-23 21:49:27 -050043#include <linux/bitops.h>
44#include <linux/io.h>
45#include <linux/irq.h>
46#include <linux/uaccess.h>
Florian Fainelli38318612010-05-31 09:18:57 +000047#include <linux/phy.h>
Sten Wang7a47dd72007-11-12 21:31:11 -080048
49#include <asm/processor.h>
Sten Wang7a47dd72007-11-12 21:31:11 -080050
51#define DRV_NAME "r6040"
Florian Fainelli5bdc4f52011-10-06 23:36:28 +000052#define DRV_VERSION "0.28"
53#define DRV_RELDATE "07Oct2011"
Sten Wang7a47dd72007-11-12 21:31:11 -080054
Sten Wang7a47dd72007-11-12 21:31:11 -080055/* Time in jiffies before concluding the transmitter is hung. */
Francois Romieu5ac5d612007-11-28 23:02:33 +010056#define TX_TIMEOUT (6000 * HZ / 1000)
Sten Wang7a47dd72007-11-12 21:31:11 -080057
58/* RDC MAC I/O Size */
59#define R6040_IO_SIZE 256
60
61/* MAX RDC MAC */
62#define MAX_MAC 2
63
64/* MAC registers */
65#define MCR0 0x00 /* Control register 0 */
Florian Fainelli4e16d6e2012-01-04 08:59:34 +000066#define MCR0_RCVEN 0x0002 /* Receive enable */
Shawn Linc60c9c72011-03-07 00:09:40 +000067#define MCR0_PROMISC 0x0020 /* Promiscuous mode */
68#define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
Florian Fainelli4e16d6e2012-01-04 08:59:34 +000069#define MCR0_XMTEN 0x1000 /* Transmission enable */
70#define MCR0_FD 0x8000 /* Full/Half duplex */
Sten Wang7a47dd72007-11-12 21:31:11 -080071#define MCR1 0x04 /* Control register 1 */
72#define MAC_RST 0x0001 /* Reset the MAC */
73#define MBCR 0x08 /* Bus control */
74#define MT_ICR 0x0C /* TX interrupt control */
75#define MR_ICR 0x10 /* RX interrupt control */
76#define MTPR 0x14 /* TX poll command register */
Florian Fainelli940ff7e2012-04-11 07:18:41 +000077#define TM2TX 0x0001 /* Trigger MAC to transmit */
Sten Wang7a47dd72007-11-12 21:31:11 -080078#define MR_BSR 0x18 /* RX buffer size */
79#define MR_DCR 0x1A /* RX descriptor control */
80#define MLSR 0x1C /* Last status */
Florian Fainelli8dd87a22012-04-11 07:18:40 +000081#define TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */
82#define TX_EXCEEDC 0x2000 /* Transmit exceed collision */
83#define TX_LATEC 0x4000 /* Transmit late collision */
Sten Wang7a47dd72007-11-12 21:31:11 -080084#define MMDIO 0x20 /* MDIO control register */
85#define MDIO_WRITE 0x4000 /* MDIO write */
86#define MDIO_READ 0x2000 /* MDIO read */
87#define MMRD 0x24 /* MDIO read data register */
88#define MMWD 0x28 /* MDIO write data register */
89#define MTD_SA0 0x2C /* TX descriptor start address 0 */
90#define MTD_SA1 0x30 /* TX descriptor start address 1 */
91#define MRD_SA0 0x34 /* RX descriptor start address 0 */
92#define MRD_SA1 0x38 /* RX descriptor start address 1 */
93#define MISR 0x3C /* Status register */
94#define MIER 0x40 /* INT enable register */
95#define MSK_INT 0x0000 /* Mask off interrupts */
Florian Fainelli3d254342008-07-13 14:28:27 +020096#define RX_FINISH 0x0001 /* RX finished */
97#define RX_NO_DESC 0x0002 /* No RX descriptor available */
98#define RX_FIFO_FULL 0x0004 /* RX FIFO full */
99#define RX_EARLY 0x0008 /* RX early */
100#define TX_FINISH 0x0010 /* TX finished */
101#define TX_EARLY 0x0080 /* TX early */
102#define EVENT_OVRFL 0x0100 /* Event counter overflow */
103#define LINK_CHANGED 0x0200 /* PHY link changed */
Sten Wang7a47dd72007-11-12 21:31:11 -0800104#define ME_CISR 0x44 /* Event counter INT status */
105#define ME_CIER 0x48 /* Event counter INT enable */
106#define MR_CNT 0x50 /* Successfully received packet counter */
107#define ME_CNT0 0x52 /* Event counter 0 */
108#define ME_CNT1 0x54 /* Event counter 1 */
109#define ME_CNT2 0x56 /* Event counter 2 */
110#define ME_CNT3 0x58 /* Event counter 3 */
111#define MT_CNT 0x5A /* Successfully transmit packet counter */
112#define ME_CNT4 0x5C /* Event counter 4 */
113#define MP_CNT 0x5E /* Pause frame counter register */
114#define MAR0 0x60 /* Hash table 0 */
115#define MAR1 0x62 /* Hash table 1 */
116#define MAR2 0x64 /* Hash table 2 */
117#define MAR3 0x66 /* Hash table 3 */
118#define MID_0L 0x68 /* Multicast address MID0 Low */
119#define MID_0M 0x6A /* Multicast address MID0 Medium */
120#define MID_0H 0x6C /* Multicast address MID0 High */
121#define MID_1L 0x70 /* MID1 Low */
122#define MID_1M 0x72 /* MID1 Medium */
123#define MID_1H 0x74 /* MID1 High */
124#define MID_2L 0x78 /* MID2 Low */
125#define MID_2M 0x7A /* MID2 Medium */
126#define MID_2H 0x7C /* MID2 High */
127#define MID_3L 0x80 /* MID3 Low */
128#define MID_3M 0x82 /* MID3 Medium */
129#define MID_3H 0x84 /* MID3 High */
130#define PHY_CC 0x88 /* PHY status change configuration register */
Florian Fainelli31171ae2012-04-11 07:18:42 +0000131#define SCEN 0x8000 /* PHY status change enable */
132#define PHYAD_SHIFT 8 /* PHY address shift */
133#define TMRDIV_SHIFT 0 /* Timer divider shift */
Sten Wang7a47dd72007-11-12 21:31:11 -0800134#define PHY_ST 0x8A /* PHY status register */
135#define MAC_SM 0xAC /* MAC status machine */
Florian Fainellie1477632012-01-04 08:59:36 +0000136#define MAC_SM_RST 0x0002 /* MAC status machine reset */
Sten Wang7a47dd72007-11-12 21:31:11 -0800137#define MAC_ID 0xBE /* Identifier register */
138
139#define TX_DCNT 0x80 /* TX descriptor count */
140#define RX_DCNT 0x80 /* RX descriptor count */
141#define MAX_BUF_SIZE 0x600
Francois Romieu6c323102007-11-28 22:31:00 +0100142#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
143#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
Sten Wang7a47dd72007-11-12 21:31:11 -0800144#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
Florian Fainelli3bcf8222010-04-07 16:50:58 -0700145#define MCAST_MAX 3 /* Max number multicast addresses to filter */
Sten Wang7a47dd72007-11-12 21:31:11 -0800146
Florian Fainelli2fa15bb2012-04-11 07:18:38 +0000147#define MAC_DEF_TIMEOUT 2048 /* Default MAC read/write operation timeout */
148
Florian Fainelli32f565d2008-07-13 14:34:15 +0200149/* Descriptor status */
150#define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
151#define DSC_RX_OK 0x4000 /* RX was successful */
152#define DSC_RX_ERR 0x0800 /* RX PHY error */
153#define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
154#define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
155#define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
156#define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
157#define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
158#define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
159#define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
160#define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
161#define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
162#define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
163
Sten Wang7a47dd72007-11-12 21:31:11 -0800164MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
165 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
166 "Florian Fainelli <florian@openwrt.org>");
167MODULE_LICENSE("GPL");
168MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
Florian Fainellibc4de262009-04-08 15:50:43 -0700169MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
Sten Wang7a47dd72007-11-12 21:31:11 -0800170
Florian Fainelli3d254342008-07-13 14:28:27 +0200171/* RX and TX interrupts that we handle */
Florian Fainellie24ddf32008-07-13 14:35:32 +0200172#define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
173#define TX_INTS (TX_FINISH)
174#define INT_MASK (RX_INTS | TX_INTS)
Sten Wang7a47dd72007-11-12 21:31:11 -0800175
176struct r6040_descriptor {
177 u16 status, len; /* 0-3 */
178 __le32 buf; /* 4-7 */
179 __le32 ndesc; /* 8-B */
180 u32 rev1; /* C-F */
181 char *vbufp; /* 10-13 */
182 struct r6040_descriptor *vndescp; /* 14-17 */
183 struct sk_buff *skb_ptr; /* 18-1B */
184 u32 rev2; /* 1C-1F */
Florian Fainelli853d5dc2012-01-04 08:59:37 +0000185} __aligned(32);
Sten Wang7a47dd72007-11-12 21:31:11 -0800186
187struct r6040_private {
188 spinlock_t lock; /* driver lock */
Sten Wang7a47dd72007-11-12 21:31:11 -0800189 struct pci_dev *pdev;
190 struct r6040_descriptor *rx_insert_ptr;
191 struct r6040_descriptor *rx_remove_ptr;
192 struct r6040_descriptor *tx_insert_ptr;
193 struct r6040_descriptor *tx_remove_ptr;
Francois Romieu6c323102007-11-28 22:31:00 +0100194 struct r6040_descriptor *rx_ring;
195 struct r6040_descriptor *tx_ring;
196 dma_addr_t rx_ring_dma;
197 dma_addr_t tx_ring_dma;
Florian Fainelli49f26722012-01-04 08:59:33 +0000198 u16 tx_free_desc;
Florian Fainelli0db0cfc2012-04-11 07:18:37 +0000199 u16 mcr0;
Sten Wang7a47dd72007-11-12 21:31:11 -0800200 struct net_device *dev;
Florian Fainelli38318612010-05-31 09:18:57 +0000201 struct mii_bus *mii_bus;
Sten Wang7a47dd72007-11-12 21:31:11 -0800202 struct napi_struct napi;
Sten Wang7a47dd72007-11-12 21:31:11 -0800203 void __iomem *base;
Florian Fainelli38318612010-05-31 09:18:57 +0000204 struct phy_device *phydev;
205 int old_link;
206 int old_duplex;
Sten Wang7a47dd72007-11-12 21:31:11 -0800207};
208
Bill Pembertonf1e24262012-12-03 09:23:30 -0500209static char version[] = DRV_NAME
Sten Wang7a47dd72007-11-12 21:31:11 -0800210 ": RDC R6040 NAPI net driver,"
Florian Fainelli9a48ce82009-01-08 11:00:52 -0800211 "version "DRV_VERSION " (" DRV_RELDATE ")";
Sten Wang7a47dd72007-11-12 21:31:11 -0800212
Sten Wang7a47dd72007-11-12 21:31:11 -0800213/* Read a word data from PHY Chip */
Florian Fainellic6e69bb2008-07-13 13:39:32 +0200214static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
Sten Wang7a47dd72007-11-12 21:31:11 -0800215{
Florian Fainelli2fa15bb2012-04-11 07:18:38 +0000216 int limit = MAC_DEF_TIMEOUT;
Sten Wang7a47dd72007-11-12 21:31:11 -0800217 u16 cmd;
218
219 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
220 /* Wait for the read bit to be cleared */
221 while (limit--) {
222 cmd = ioread16(ioaddr + MMDIO);
Joe Chou11e5e8f2008-12-22 19:38:17 -0800223 if (!(cmd & MDIO_READ))
Sten Wang7a47dd72007-11-12 21:31:11 -0800224 break;
225 }
226
227 return ioread16(ioaddr + MMRD);
228}
229
230/* Write a word data from PHY Chip */
Florian Fainelli2154c7042010-08-08 10:08:44 +0000231static void r6040_phy_write(void __iomem *ioaddr,
232 int phy_addr, int reg, u16 val)
Sten Wang7a47dd72007-11-12 21:31:11 -0800233{
Florian Fainelli2fa15bb2012-04-11 07:18:38 +0000234 int limit = MAC_DEF_TIMEOUT;
Sten Wang7a47dd72007-11-12 21:31:11 -0800235 u16 cmd;
236
237 iowrite16(val, ioaddr + MMWD);
238 /* Write the command to the MDIO bus */
239 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
240 /* Wait for the write bit to be cleared */
241 while (limit--) {
242 cmd = ioread16(ioaddr + MMDIO);
Joe Chou11e5e8f2008-12-22 19:38:17 -0800243 if (!(cmd & MDIO_WRITE))
Sten Wang7a47dd72007-11-12 21:31:11 -0800244 break;
245 }
246}
247
Florian Fainelli38318612010-05-31 09:18:57 +0000248static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
Sten Wang7a47dd72007-11-12 21:31:11 -0800249{
Florian Fainelli38318612010-05-31 09:18:57 +0000250 struct net_device *dev = bus->priv;
Sten Wang7a47dd72007-11-12 21:31:11 -0800251 struct r6040_private *lp = netdev_priv(dev);
252 void __iomem *ioaddr = lp->base;
253
Florian Fainelli38318612010-05-31 09:18:57 +0000254 return r6040_phy_read(ioaddr, phy_addr, reg);
Sten Wang7a47dd72007-11-12 21:31:11 -0800255}
256
Florian Fainelli38318612010-05-31 09:18:57 +0000257static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
258 int reg, u16 value)
Sten Wang7a47dd72007-11-12 21:31:11 -0800259{
Florian Fainelli38318612010-05-31 09:18:57 +0000260 struct net_device *dev = bus->priv;
Sten Wang7a47dd72007-11-12 21:31:11 -0800261 struct r6040_private *lp = netdev_priv(dev);
262 void __iomem *ioaddr = lp->base;
263
Florian Fainelli38318612010-05-31 09:18:57 +0000264 r6040_phy_write(ioaddr, phy_addr, reg, value);
265
266 return 0;
267}
268
269static int r6040_mdiobus_reset(struct mii_bus *bus)
270{
271 return 0;
Sten Wang7a47dd72007-11-12 21:31:11 -0800272}
273
Florian Fainellib4f12552007-12-12 22:55:34 +0100274static void r6040_free_txbufs(struct net_device *dev)
275{
276 struct r6040_private *lp = netdev_priv(dev);
277 int i;
278
279 for (i = 0; i < TX_DCNT; i++) {
280 if (lp->tx_insert_ptr->skb_ptr) {
Al Viroed773b42008-03-16 22:43:06 +0000281 pci_unmap_single(lp->pdev,
282 le32_to_cpu(lp->tx_insert_ptr->buf),
Florian Fainellib4f12552007-12-12 22:55:34 +0100283 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
284 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
Florian Fainelli3b060be2008-09-24 21:16:40 +0200285 lp->tx_insert_ptr->skb_ptr = NULL;
Florian Fainellib4f12552007-12-12 22:55:34 +0100286 }
287 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
288 }
289}
290
291static void r6040_free_rxbufs(struct net_device *dev)
292{
293 struct r6040_private *lp = netdev_priv(dev);
294 int i;
295
296 for (i = 0; i < RX_DCNT; i++) {
297 if (lp->rx_insert_ptr->skb_ptr) {
Al Viroed773b42008-03-16 22:43:06 +0000298 pci_unmap_single(lp->pdev,
299 le32_to_cpu(lp->rx_insert_ptr->buf),
Florian Fainellib4f12552007-12-12 22:55:34 +0100300 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
301 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
302 lp->rx_insert_ptr->skb_ptr = NULL;
303 }
304 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
305 }
306}
307
Florian Fainellib4f12552007-12-12 22:55:34 +0100308static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
309 dma_addr_t desc_dma, int size)
310{
311 struct r6040_descriptor *desc = desc_ring;
312 dma_addr_t mapping = desc_dma;
313
314 while (size-- > 0) {
Julia Lawall3f6602a2008-06-23 23:12:31 +0200315 mapping += sizeof(*desc);
Florian Fainellib4f12552007-12-12 22:55:34 +0100316 desc->ndesc = cpu_to_le32(mapping);
317 desc->vndescp = desc + 1;
318 desc++;
319 }
320 desc--;
321 desc->ndesc = cpu_to_le32(desc_dma);
322 desc->vndescp = desc_ring;
323}
324
Florian Fainelli3d463412008-07-13 14:32:18 +0200325static void r6040_init_txbufs(struct net_device *dev)
Florian Fainellib4f12552007-12-12 22:55:34 +0100326{
327 struct r6040_private *lp = netdev_priv(dev);
Florian Fainellib4f12552007-12-12 22:55:34 +0100328
329 lp->tx_free_desc = TX_DCNT;
330
331 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
332 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
Florian Fainellib4f12552007-12-12 22:55:34 +0100333}
334
Florian Fainelli3d463412008-07-13 14:32:18 +0200335static int r6040_alloc_rxbufs(struct net_device *dev)
Florian Fainellib4f12552007-12-12 22:55:34 +0100336{
337 struct r6040_private *lp = netdev_priv(dev);
Florian Fainelli3d463412008-07-13 14:32:18 +0200338 struct r6040_descriptor *desc;
339 struct sk_buff *skb;
340 int rc;
Florian Fainellib4f12552007-12-12 22:55:34 +0100341
342 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
343 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
344
Florian Fainelli3d463412008-07-13 14:32:18 +0200345 /* Allocate skbs for the rx descriptors */
346 desc = lp->rx_ring;
347 do {
348 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
349 if (!skb) {
Florian Fainelli7d53b802010-04-07 21:39:27 +0000350 netdev_err(dev, "failed to alloc skb for rx\n");
Florian Fainelli3d463412008-07-13 14:32:18 +0200351 rc = -ENOMEM;
352 goto err_exit;
353 }
354 desc->skb_ptr = skb;
355 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
Florian Fainelli2154c7042010-08-08 10:08:44 +0000356 desc->skb_ptr->data,
357 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
Florian Fainelli32f565d2008-07-13 14:34:15 +0200358 desc->status = DSC_OWNER_MAC;
Florian Fainelli3d463412008-07-13 14:32:18 +0200359 desc = desc->vndescp;
360 } while (desc != lp->rx_ring);
361
362 return 0;
363
364err_exit:
365 /* Deallocate all previously allocated skbs */
366 r6040_free_rxbufs(dev);
367 return rc;
Florian Fainellifec3a232008-07-13 14:29:20 +0200368}
Florian Fainellib4f12552007-12-12 22:55:34 +0100369
Florian Fainelli90f750a2012-04-11 07:18:36 +0000370static void r6040_reset_mac(struct r6040_private *lp)
Florian Fainellifec3a232008-07-13 14:29:20 +0200371{
Florian Fainellifec3a232008-07-13 14:29:20 +0200372 void __iomem *ioaddr = lp->base;
Florian Fainelli2fa15bb2012-04-11 07:18:38 +0000373 int limit = MAC_DEF_TIMEOUT;
Florian Fainellifec3a232008-07-13 14:29:20 +0200374 u16 cmd;
375
Florian Fainellifec3a232008-07-13 14:29:20 +0200376 iowrite16(MAC_RST, ioaddr + MCR1);
377 while (limit--) {
378 cmd = ioread16(ioaddr + MCR1);
Florian Fainelli58dbc692012-01-04 08:59:35 +0000379 if (cmd & MAC_RST)
Florian Fainellifec3a232008-07-13 14:29:20 +0200380 break;
381 }
Florian Fainelli90f750a2012-04-11 07:18:36 +0000382
Florian Fainellifec3a232008-07-13 14:29:20 +0200383 /* Reset internal state machine */
Florian Fainellie1477632012-01-04 08:59:36 +0000384 iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
Florian Fainellifec3a232008-07-13 14:29:20 +0200385 iowrite16(0, ioaddr + MAC_SM);
Florian Fainellic1d69932008-09-03 16:50:03 +0200386 mdelay(5);
Florian Fainelli90f750a2012-04-11 07:18:36 +0000387}
388
389static void r6040_init_mac_regs(struct net_device *dev)
390{
391 struct r6040_private *lp = netdev_priv(dev);
392 void __iomem *ioaddr = lp->base;
393
394 /* Mask Off Interrupt */
395 iowrite16(MSK_INT, ioaddr + MIER);
396
397 /* Reset RDC MAC */
398 r6040_reset_mac(lp);
Florian Fainellifec3a232008-07-13 14:29:20 +0200399
400 /* MAC Bus Control Register */
401 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
402
403 /* Buffer Size Register */
404 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
405
406 /* Write TX ring start address */
407 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
408 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
409
410 /* Write RX ring start address */
Florian Fainellib4f12552007-12-12 22:55:34 +0100411 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
412 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
Florian Fainellifec3a232008-07-13 14:29:20 +0200413
414 /* Set interrupt waiting time and packet numbers */
Florian Fainelli31718de2008-07-13 14:35:00 +0200415 iowrite16(0, ioaddr + MT_ICR);
416 iowrite16(0, ioaddr + MR_ICR);
Florian Fainellifec3a232008-07-13 14:29:20 +0200417
418 /* Enable interrupts */
419 iowrite16(INT_MASK, ioaddr + MIER);
420
421 /* Enable TX and RX */
Florian Fainelli4e16d6e2012-01-04 08:59:34 +0000422 iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr);
Florian Fainellifec3a232008-07-13 14:29:20 +0200423
424 /* Let TX poll the descriptors
425 * we may got called by r6040_tx_timeout which has left
426 * some unsent tx buffers */
Florian Fainelli940ff7e2012-04-11 07:18:41 +0000427 iowrite16(TM2TX, ioaddr + MTPR);
Florian Fainellib4f12552007-12-12 22:55:34 +0100428}
Sten Wang7a47dd72007-11-12 21:31:11 -0800429
Florian Fainelli106adf32007-12-12 23:01:33 +0100430static void r6040_tx_timeout(struct net_device *dev)
431{
432 struct r6040_private *priv = netdev_priv(dev);
433 void __iomem *ioaddr = priv->base;
434
Florian Fainelli7d53b802010-04-07 21:39:27 +0000435 netdev_warn(dev, "transmit timed out, int enable %4.4x "
Florian Fainelli38318612010-05-31 09:18:57 +0000436 "status %4.4x\n",
Florian Fainelli7d53b802010-04-07 21:39:27 +0000437 ioread16(ioaddr + MIER),
Florian Fainelli38318612010-05-31 09:18:57 +0000438 ioread16(ioaddr + MISR));
Florian Fainelli106adf32007-12-12 23:01:33 +0100439
Florian Fainelli106adf32007-12-12 23:01:33 +0100440 dev->stats.tx_errors++;
Florian Fainellifec3a232008-07-13 14:29:20 +0200441
442 /* Reset MAC and re-init all registers */
443 r6040_init_mac_regs(dev);
Florian Fainelli106adf32007-12-12 23:01:33 +0100444}
445
Sten Wang7a47dd72007-11-12 21:31:11 -0800446static struct net_device_stats *r6040_get_stats(struct net_device *dev)
447{
448 struct r6040_private *priv = netdev_priv(dev);
449 void __iomem *ioaddr = priv->base;
450 unsigned long flags;
451
452 spin_lock_irqsave(&priv->lock, flags);
Florian Fainellid248fd72007-12-12 22:34:55 +0100453 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
454 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
Sten Wang7a47dd72007-11-12 21:31:11 -0800455 spin_unlock_irqrestore(&priv->lock, flags);
456
Florian Fainellid248fd72007-12-12 22:34:55 +0100457 return &dev->stats;
Sten Wang7a47dd72007-11-12 21:31:11 -0800458}
459
460/* Stop RDC MAC and Free the allocated resource */
461static void r6040_down(struct net_device *dev)
462{
463 struct r6040_private *lp = netdev_priv(dev);
464 void __iomem *ioaddr = lp->base;
Sten Wang7a47dd72007-11-12 21:31:11 -0800465 u16 *adrp;
Sten Wang7a47dd72007-11-12 21:31:11 -0800466
467 /* Stop MAC */
468 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
Florian Fainelli90f750a2012-04-11 07:18:36 +0000469
470 /* Reset RDC MAC */
471 r6040_reset_mac(lp);
Sten Wang7a47dd72007-11-12 21:31:11 -0800472
473 /* Restore MAC Address to MIDx */
474 adrp = (u16 *) dev->dev_addr;
475 iowrite16(adrp[0], ioaddr + MID_0L);
476 iowrite16(adrp[1], ioaddr + MID_0M);
477 iowrite16(adrp[2], ioaddr + MID_0H);
Florian Fainelli06e92c32011-10-06 23:36:22 +0000478
479 phy_stop(lp->phydev);
Sten Wang7a47dd72007-11-12 21:31:11 -0800480}
481
Francois Romieu5ac5d612007-11-28 23:02:33 +0100482static int r6040_close(struct net_device *dev)
Sten Wang7a47dd72007-11-12 21:31:11 -0800483{
484 struct r6040_private *lp = netdev_priv(dev);
Florian Fainelli58854c62009-01-09 23:19:26 -0800485 struct pci_dev *pdev = lp->pdev;
Sten Wang7a47dd72007-11-12 21:31:11 -0800486
Sten Wang7a47dd72007-11-12 21:31:11 -0800487 spin_lock_irq(&lp->lock);
Florian Fainelli129cf9a2008-07-13 14:32:45 +0200488 napi_disable(&lp->napi);
Sten Wang7a47dd72007-11-12 21:31:11 -0800489 netif_stop_queue(dev);
490 r6040_down(dev);
Florian Fainelli58854c62009-01-09 23:19:26 -0800491
492 free_irq(dev->irq, dev);
493
494 /* Free RX buffer */
495 r6040_free_rxbufs(dev);
496
497 /* Free TX buffer */
498 r6040_free_txbufs(dev);
499
Sten Wang7a47dd72007-11-12 21:31:11 -0800500 spin_unlock_irq(&lp->lock);
501
Florian Fainelli58854c62009-01-09 23:19:26 -0800502 /* Free Descriptor memory */
503 if (lp->rx_ring) {
Florian Fainelli2154c7042010-08-08 10:08:44 +0000504 pci_free_consistent(pdev,
505 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
Hannes Eder5b5103e2009-02-14 11:14:04 +0000506 lp->rx_ring = NULL;
Florian Fainelli58854c62009-01-09 23:19:26 -0800507 }
508
509 if (lp->tx_ring) {
Florian Fainelli2154c7042010-08-08 10:08:44 +0000510 pci_free_consistent(pdev,
511 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
Hannes Eder5b5103e2009-02-14 11:14:04 +0000512 lp->tx_ring = NULL;
Florian Fainelli58854c62009-01-09 23:19:26 -0800513 }
514
Sten Wang7a47dd72007-11-12 21:31:11 -0800515 return 0;
516}
517
Sten Wang7a47dd72007-11-12 21:31:11 -0800518static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
519{
520 struct r6040_private *lp = netdev_priv(dev);
Sten Wang7a47dd72007-11-12 21:31:11 -0800521
Florian Fainelli38318612010-05-31 09:18:57 +0000522 if (!lp->phydev)
Sten Wang7a47dd72007-11-12 21:31:11 -0800523 return -EINVAL;
Florian Fainelli38318612010-05-31 09:18:57 +0000524
David S. Miller4cfa5802010-07-21 21:10:49 -0700525 return phy_mii_ioctl(lp->phydev, rq, cmd);
Sten Wang7a47dd72007-11-12 21:31:11 -0800526}
527
528static int r6040_rx(struct net_device *dev, int limit)
529{
530 struct r6040_private *priv = netdev_priv(dev);
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200531 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
532 struct sk_buff *skb_ptr, *new_skb;
533 int count = 0;
Sten Wang7a47dd72007-11-12 21:31:11 -0800534 u16 err;
535
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200536 /* Limit not reached and the descriptor belongs to the CPU */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200537 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200538 /* Read the descriptor status */
539 err = descptr->status;
540 /* Global error status set */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200541 if (err & DSC_RX_ERR) {
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200542 /* RX dribble */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200543 if (err & DSC_RX_ERR_DRI)
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200544 dev->stats.rx_frame_errors++;
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300545 /* Buffer length exceeded */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200546 if (err & DSC_RX_ERR_BUF)
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200547 dev->stats.rx_length_errors++;
548 /* Packet too long */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200549 if (err & DSC_RX_ERR_LONG)
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200550 dev->stats.rx_length_errors++;
551 /* Packet < 64 bytes */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200552 if (err & DSC_RX_ERR_RUNT)
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200553 dev->stats.rx_length_errors++;
554 /* CRC error */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200555 if (err & DSC_RX_ERR_CRC) {
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200556 spin_lock(&priv->lock);
557 dev->stats.rx_crc_errors++;
558 spin_unlock(&priv->lock);
Sten Wang7a47dd72007-11-12 21:31:11 -0800559 }
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200560 goto next_descr;
Sten Wang7a47dd72007-11-12 21:31:11 -0800561 }
Florian Fainelli2154c7042010-08-08 10:08:44 +0000562
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200563 /* Packet successfully received */
564 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
565 if (!new_skb) {
566 dev->stats.rx_dropped++;
567 goto next_descr;
568 }
569 skb_ptr = descptr->skb_ptr;
570 skb_ptr->dev = priv->dev;
Florian Fainelli2154c7042010-08-08 10:08:44 +0000571
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200572 /* Do not count the CRC */
573 skb_put(skb_ptr, descptr->len - 4);
574 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
575 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
576 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
Florian Fainelli2154c7042010-08-08 10:08:44 +0000577
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200578 /* Send to upper layer */
579 netif_receive_skb(skb_ptr);
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200580 dev->stats.rx_packets++;
581 dev->stats.rx_bytes += descptr->len - 4;
582
583 /* put new skb into descriptor */
584 descptr->skb_ptr = new_skb;
585 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
586 descptr->skb_ptr->data,
587 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
588
589next_descr:
590 /* put the descriptor back to the MAC */
Florian Fainelli32f565d2008-07-13 14:34:15 +0200591 descptr->status = DSC_OWNER_MAC;
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200592 descptr = descptr->vndescp;
593 count++;
Sten Wang7a47dd72007-11-12 21:31:11 -0800594 }
Florian Fainelli9ca28dc2008-07-13 14:33:36 +0200595 priv->rx_remove_ptr = descptr;
Sten Wang7a47dd72007-11-12 21:31:11 -0800596
597 return count;
598}
599
600static void r6040_tx(struct net_device *dev)
601{
602 struct r6040_private *priv = netdev_priv(dev);
603 struct r6040_descriptor *descptr;
604 void __iomem *ioaddr = priv->base;
605 struct sk_buff *skb_ptr;
606 u16 err;
607
608 spin_lock(&priv->lock);
609 descptr = priv->tx_remove_ptr;
610 while (priv->tx_free_desc < TX_DCNT) {
611 /* Check for errors */
612 err = ioread16(ioaddr + MLSR);
613
Florian Fainelli8dd87a22012-04-11 07:18:40 +0000614 if (err & TX_FIFO_UNDR)
Florian Fainelli3440ecc2012-04-11 07:18:39 +0000615 dev->stats.tx_fifo_errors++;
Florian Fainelli8dd87a22012-04-11 07:18:40 +0000616 if (err & (TX_EXCEEDC | TX_LATEC))
Florian Fainellid248fd72007-12-12 22:34:55 +0100617 dev->stats.tx_carrier_errors++;
Sten Wang7a47dd72007-11-12 21:31:11 -0800618
Florian Fainelli32f565d2008-07-13 14:34:15 +0200619 if (descptr->status & DSC_OWNER_MAC)
Florian Fainelliec6d2d42007-12-12 23:13:15 +0100620 break; /* Not complete */
Sten Wang7a47dd72007-11-12 21:31:11 -0800621 skb_ptr = descptr->skb_ptr;
Al Viroed773b42008-03-16 22:43:06 +0000622 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
Sten Wang7a47dd72007-11-12 21:31:11 -0800623 skb_ptr->len, PCI_DMA_TODEVICE);
624 /* Free buffer */
625 dev_kfree_skb_irq(skb_ptr);
626 descptr->skb_ptr = NULL;
627 /* To next descriptor */
628 descptr = descptr->vndescp;
629 priv->tx_free_desc++;
630 }
631 priv->tx_remove_ptr = descptr;
632
633 if (priv->tx_free_desc)
634 netif_wake_queue(dev);
635 spin_unlock(&priv->lock);
636}
637
638static int r6040_poll(struct napi_struct *napi, int budget)
639{
640 struct r6040_private *priv =
641 container_of(napi, struct r6040_private, napi);
642 struct net_device *dev = priv->dev;
643 void __iomem *ioaddr = priv->base;
644 int work_done;
645
646 work_done = r6040_rx(dev, budget);
647
648 if (work_done < budget) {
Ben Hutchings288379f2009-01-19 16:43:59 -0800649 napi_complete(napi);
Sten Wang7a47dd72007-11-12 21:31:11 -0800650 /* Enable RX interrupt */
Florian Fainellie24ddf32008-07-13 14:35:32 +0200651 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
Sten Wang7a47dd72007-11-12 21:31:11 -0800652 }
653 return work_done;
654}
655
656/* The RDC interrupt handler. */
657static irqreturn_t r6040_interrupt(int irq, void *dev_id)
658{
659 struct net_device *dev = dev_id;
660 struct r6040_private *lp = netdev_priv(dev);
661 void __iomem *ioaddr = lp->base;
Joe Chou3e7c4692008-12-22 19:40:02 -0800662 u16 misr, status;
Sten Wang7a47dd72007-11-12 21:31:11 -0800663
Joe Chou3e7c4692008-12-22 19:40:02 -0800664 /* Save MIER */
665 misr = ioread16(ioaddr + MIER);
Sten Wang7a47dd72007-11-12 21:31:11 -0800666 /* Mask off RDC MAC interrupt */
667 iowrite16(MSK_INT, ioaddr + MIER);
668 /* Read MISR status and clear */
669 status = ioread16(ioaddr + MISR);
670
Florian Fainelli35976d42009-07-08 03:05:14 +0000671 if (status == 0x0000 || status == 0xffff) {
672 /* Restore RDC MAC interrupt */
673 iowrite16(misr, ioaddr + MIER);
Sten Wang7a47dd72007-11-12 21:31:11 -0800674 return IRQ_NONE;
Florian Fainelli35976d42009-07-08 03:05:14 +0000675 }
Sten Wang7a47dd72007-11-12 21:31:11 -0800676
677 /* RX interrupt request */
Florian Fainellie24ddf32008-07-13 14:35:32 +0200678 if (status & RX_INTS) {
679 if (status & RX_NO_DESC) {
680 /* RX descriptor unavailable */
681 dev->stats.rx_dropped++;
682 dev->stats.rx_missed_errors++;
683 }
684 if (status & RX_FIFO_FULL)
685 dev->stats.rx_fifo_errors++;
686
Michael Thalmeier0d9b6e72011-07-15 01:28:26 +0000687 if (likely(napi_schedule_prep(&lp->napi))) {
688 /* Mask off RX interrupt */
689 misr &= ~RX_INTS;
690 __napi_schedule(&lp->napi);
691 }
Sten Wang7a47dd72007-11-12 21:31:11 -0800692 }
693
694 /* TX interrupt request */
Florian Fainellie24ddf32008-07-13 14:35:32 +0200695 if (status & TX_INTS)
Sten Wang7a47dd72007-11-12 21:31:11 -0800696 r6040_tx(dev);
697
Joe Chou3e7c4692008-12-22 19:40:02 -0800698 /* Restore RDC MAC interrupt */
699 iowrite16(misr, ioaddr + MIER);
700
Florian Fainelliec6d2d42007-12-12 23:13:15 +0100701 return IRQ_HANDLED;
Sten Wang7a47dd72007-11-12 21:31:11 -0800702}
703
704#ifdef CONFIG_NET_POLL_CONTROLLER
705static void r6040_poll_controller(struct net_device *dev)
706{
707 disable_irq(dev->irq);
Francois Romieu5ac5d612007-11-28 23:02:33 +0100708 r6040_interrupt(dev->irq, dev);
Sten Wang7a47dd72007-11-12 21:31:11 -0800709 enable_irq(dev->irq);
710}
711#endif
712
Sten Wang7a47dd72007-11-12 21:31:11 -0800713/* Init RDC MAC */
Florian Fainelli3d463412008-07-13 14:32:18 +0200714static int r6040_up(struct net_device *dev)
Sten Wang7a47dd72007-11-12 21:31:11 -0800715{
716 struct r6040_private *lp = netdev_priv(dev);
Sten Wang7a47dd72007-11-12 21:31:11 -0800717 void __iomem *ioaddr = lp->base;
Florian Fainelli3d463412008-07-13 14:32:18 +0200718 int ret;
Sten Wang7a47dd72007-11-12 21:31:11 -0800719
Florian Fainellib4f12552007-12-12 22:55:34 +0100720 /* Initialise and alloc RX/TX buffers */
Florian Fainelli3d463412008-07-13 14:32:18 +0200721 r6040_init_txbufs(dev);
722 ret = r6040_alloc_rxbufs(dev);
723 if (ret)
724 return ret;
Sten Wang7a47dd72007-11-12 21:31:11 -0800725
Sten Wang7a47dd72007-11-12 21:31:11 -0800726 /* improve performance (by RDC guys) */
Florian Fainelli2154c7042010-08-08 10:08:44 +0000727 r6040_phy_write(ioaddr, 30, 17,
728 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
729 r6040_phy_write(ioaddr, 30, 17,
730 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
Florian Fainellic6e69bb2008-07-13 13:39:32 +0200731 r6040_phy_write(ioaddr, 0, 19, 0x0000);
732 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
Sten Wang7a47dd72007-11-12 21:31:11 -0800733
Florian Fainellifec3a232008-07-13 14:29:20 +0200734 /* Initialize all MAC registers */
735 r6040_init_mac_regs(dev);
Florian Fainelli3d463412008-07-13 14:32:18 +0200736
Florian Fainelli06e92c32011-10-06 23:36:22 +0000737 phy_start(lp->phydev);
738
Florian Fainelli3d463412008-07-13 14:32:18 +0200739 return 0;
Sten Wang7a47dd72007-11-12 21:31:11 -0800740}
741
Sten Wang7a47dd72007-11-12 21:31:11 -0800742
743/* Read/set MAC address routines */
744static void r6040_mac_address(struct net_device *dev)
745{
746 struct r6040_private *lp = netdev_priv(dev);
747 void __iomem *ioaddr = lp->base;
748 u16 *adrp;
749
Florian Fainelli48529682012-01-04 08:59:38 +0000750 /* Reset MAC */
Florian Fainelli90f750a2012-04-11 07:18:36 +0000751 r6040_reset_mac(lp);
Sten Wang7a47dd72007-11-12 21:31:11 -0800752
753 /* Restore MAC Address */
754 adrp = (u16 *) dev->dev_addr;
755 iowrite16(adrp[0], ioaddr + MID_0L);
756 iowrite16(adrp[1], ioaddr + MID_0M);
757 iowrite16(adrp[2], ioaddr + MID_0H);
758}
759
Francois Romieu5ac5d612007-11-28 23:02:33 +0100760static int r6040_open(struct net_device *dev)
Sten Wang7a47dd72007-11-12 21:31:11 -0800761{
Francois Romieu5ac5d612007-11-28 23:02:33 +0100762 struct r6040_private *lp = netdev_priv(dev);
Sten Wang7a47dd72007-11-12 21:31:11 -0800763 int ret;
764
765 /* Request IRQ and Register interrupt handler */
Julia Lawall91dcbf32009-11-18 08:23:00 +0000766 ret = request_irq(dev->irq, r6040_interrupt,
Sten Wang7a47dd72007-11-12 21:31:11 -0800767 IRQF_SHARED, dev->name, dev);
768 if (ret)
Denis Kirjanovced1de42010-08-24 23:57:55 +0000769 goto out;
Sten Wang7a47dd72007-11-12 21:31:11 -0800770
771 /* Set MAC address */
772 r6040_mac_address(dev);
773
774 /* Allocate Descriptor memory */
Francois Romieu6c323102007-11-28 22:31:00 +0100775 lp->rx_ring =
776 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
Denis Kirjanovced1de42010-08-24 23:57:55 +0000777 if (!lp->rx_ring) {
778 ret = -ENOMEM;
779 goto err_free_irq;
780 }
Sten Wang7a47dd72007-11-12 21:31:11 -0800781
Francois Romieu6c323102007-11-28 22:31:00 +0100782 lp->tx_ring =
783 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
784 if (!lp->tx_ring) {
Denis Kirjanovced1de42010-08-24 23:57:55 +0000785 ret = -ENOMEM;
786 goto err_free_rx_ring;
Francois Romieu6c323102007-11-28 22:31:00 +0100787 }
788
Florian Fainelli3d463412008-07-13 14:32:18 +0200789 ret = r6040_up(dev);
Denis Kirjanovced1de42010-08-24 23:57:55 +0000790 if (ret)
791 goto err_free_tx_ring;
Sten Wang7a47dd72007-11-12 21:31:11 -0800792
793 napi_enable(&lp->napi);
794 netif_start_queue(dev);
795
Sten Wang7a47dd72007-11-12 21:31:11 -0800796 return 0;
Denis Kirjanovced1de42010-08-24 23:57:55 +0000797
798err_free_tx_ring:
799 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
800 lp->tx_ring_dma);
801err_free_rx_ring:
802 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
803 lp->rx_ring_dma);
804err_free_irq:
805 free_irq(dev->irq, dev);
806out:
807 return ret;
Sten Wang7a47dd72007-11-12 21:31:11 -0800808}
809
Stephen Hemminger613573252009-08-31 19:50:58 +0000810static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
811 struct net_device *dev)
Sten Wang7a47dd72007-11-12 21:31:11 -0800812{
813 struct r6040_private *lp = netdev_priv(dev);
814 struct r6040_descriptor *descptr;
815 void __iomem *ioaddr = lp->base;
816 unsigned long flags;
Sten Wang7a47dd72007-11-12 21:31:11 -0800817
818 /* Critical Section */
819 spin_lock_irqsave(&lp->lock, flags);
820
821 /* TX resource check */
822 if (!lp->tx_free_desc) {
823 spin_unlock_irqrestore(&lp->lock, flags);
Jeff Garzik092427b2007-11-23 21:49:27 -0500824 netif_stop_queue(dev);
Florian Fainelli7d53b802010-04-07 21:39:27 +0000825 netdev_err(dev, ": no tx descriptor\n");
Stephen Hemminger613573252009-08-31 19:50:58 +0000826 return NETDEV_TX_BUSY;
Sten Wang7a47dd72007-11-12 21:31:11 -0800827 }
828
829 /* Statistic Counter */
830 dev->stats.tx_packets++;
831 dev->stats.tx_bytes += skb->len;
832 /* Set TX descriptor & Transmit it */
833 lp->tx_free_desc--;
834 descptr = lp->tx_insert_ptr;
835 if (skb->len < MISR)
836 descptr->len = MISR;
837 else
838 descptr->len = skb->len;
839
840 descptr->skb_ptr = skb;
841 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
842 skb->data, skb->len, PCI_DMA_TODEVICE));
Florian Fainelli32f565d2008-07-13 14:34:15 +0200843 descptr->status = DSC_OWNER_MAC;
Richard Cochran2aa8f4c2011-06-19 03:31:42 +0000844
845 skb_tx_timestamp(skb);
846
Sten Wang7a47dd72007-11-12 21:31:11 -0800847 /* Trigger the MAC to check the TX descriptor */
Florian Fainelli940ff7e2012-04-11 07:18:41 +0000848 iowrite16(TM2TX, ioaddr + MTPR);
Sten Wang7a47dd72007-11-12 21:31:11 -0800849 lp->tx_insert_ptr = descptr->vndescp;
850
851 /* If no tx resource, stop */
852 if (!lp->tx_free_desc)
853 netif_stop_queue(dev);
854
Sten Wang7a47dd72007-11-12 21:31:11 -0800855 spin_unlock_irqrestore(&lp->lock, flags);
Stephen Hemminger613573252009-08-31 19:50:58 +0000856
857 return NETDEV_TX_OK;
Sten Wang7a47dd72007-11-12 21:31:11 -0800858}
859
Francois Romieu5ac5d612007-11-28 23:02:33 +0100860static void r6040_multicast_list(struct net_device *dev)
Sten Wang7a47dd72007-11-12 21:31:11 -0800861{
862 struct r6040_private *lp = netdev_priv(dev);
863 void __iomem *ioaddr = lp->base;
Sten Wang7a47dd72007-11-12 21:31:11 -0800864 unsigned long flags;
Jiri Pirko22bedad2010-04-01 21:22:57 +0000865 struct netdev_hw_addr *ha;
Sten Wang7a47dd72007-11-12 21:31:11 -0800866 int i;
Shawn Linc60c9c72011-03-07 00:09:40 +0000867 u16 *adrp;
868 u16 hash_table[4] = { 0 };
Sten Wang7a47dd72007-11-12 21:31:11 -0800869
Shawn Linc60c9c72011-03-07 00:09:40 +0000870 spin_lock_irqsave(&lp->lock, flags);
871
872 /* Keep our MAC Address */
Sten Wang7a47dd72007-11-12 21:31:11 -0800873 adrp = (u16 *)dev->dev_addr;
874 iowrite16(adrp[0], ioaddr + MID_0L);
875 iowrite16(adrp[1], ioaddr + MID_0M);
876 iowrite16(adrp[2], ioaddr + MID_0H);
877
Sten Wang7a47dd72007-11-12 21:31:11 -0800878 /* Clear AMCP & PROM bits */
Shawn Linc60c9c72011-03-07 00:09:40 +0000879 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
Sten Wang7a47dd72007-11-12 21:31:11 -0800880
Shawn Linc60c9c72011-03-07 00:09:40 +0000881 /* Promiscuous mode */
882 if (dev->flags & IFF_PROMISC)
883 lp->mcr0 |= MCR0_PROMISC;
Sten Wang7a47dd72007-11-12 21:31:11 -0800884
Shawn Linc60c9c72011-03-07 00:09:40 +0000885 /* Enable multicast hash table function to
886 * receive all multicast packets. */
887 else if (dev->flags & IFF_ALLMULTI) {
888 lp->mcr0 |= MCR0_HASH_EN;
889
890 for (i = 0; i < MCAST_MAX ; i++) {
891 iowrite16(0, ioaddr + MID_1L + 8 * i);
892 iowrite16(0, ioaddr + MID_1M + 8 * i);
893 iowrite16(0, ioaddr + MID_1H + 8 * i);
894 }
Sten Wang7a47dd72007-11-12 21:31:11 -0800895
896 for (i = 0; i < 4; i++)
Shawn Linc60c9c72011-03-07 00:09:40 +0000897 hash_table[i] = 0xffff;
898 }
899 /* Use internal multicast address registers if the number of
900 * multicast addresses is not greater than MCAST_MAX. */
901 else if (netdev_mc_count(dev) <= MCAST_MAX) {
902 i = 0;
Jiri Pirko22bedad2010-04-01 21:22:57 +0000903 netdev_for_each_mc_addr(ha, dev) {
Shawn Linc60c9c72011-03-07 00:09:40 +0000904 u16 *adrp = (u16 *) ha->addr;
905 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
906 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
907 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
908 i++;
Sten Wang7a47dd72007-11-12 21:31:11 -0800909 }
Shawn Linc60c9c72011-03-07 00:09:40 +0000910 while (i < MCAST_MAX) {
911 iowrite16(0, ioaddr + MID_1L + 8 * i);
912 iowrite16(0, ioaddr + MID_1M + 8 * i);
913 iowrite16(0, ioaddr + MID_1H + 8 * i);
914 i++;
915 }
916 }
917 /* Otherwise, Enable multicast hash table function. */
918 else {
919 u32 crc;
920
921 lp->mcr0 |= MCR0_HASH_EN;
922
923 for (i = 0; i < MCAST_MAX ; i++) {
924 iowrite16(0, ioaddr + MID_1L + 8 * i);
925 iowrite16(0, ioaddr + MID_1M + 8 * i);
926 iowrite16(0, ioaddr + MID_1H + 8 * i);
927 }
928
929 /* Build multicast hash table */
930 netdev_for_each_mc_addr(ha, dev) {
931 u8 *addrs = ha->addr;
932
933 crc = ether_crc(ETH_ALEN, addrs);
934 crc >>= 26;
935 hash_table[crc >> 4] |= 1 << (crc & 0xf);
936 }
937 }
938
939 iowrite16(lp->mcr0, ioaddr + MCR0);
940
941 /* Fill the MAC hash tables with their values */
Florian Fainellibbc13ab2011-11-16 06:00:08 +0000942 if (lp->mcr0 & MCR0_HASH_EN) {
Sten Wang7a47dd72007-11-12 21:31:11 -0800943 iowrite16(hash_table[0], ioaddr + MAR0);
944 iowrite16(hash_table[1], ioaddr + MAR1);
945 iowrite16(hash_table[2], ioaddr + MAR2);
946 iowrite16(hash_table[3], ioaddr + MAR3);
947 }
Shawn Linc60c9c72011-03-07 00:09:40 +0000948
949 spin_unlock_irqrestore(&lp->lock, flags);
Sten Wang7a47dd72007-11-12 21:31:11 -0800950}
951
952static void netdev_get_drvinfo(struct net_device *dev,
953 struct ethtool_drvinfo *info)
954{
955 struct r6040_private *rp = netdev_priv(dev);
956
Jiri Pirko7826d432013-01-06 00:44:26 +0000957 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
958 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
959 strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info));
Sten Wang7a47dd72007-11-12 21:31:11 -0800960}
961
962static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
963{
964 struct r6040_private *rp = netdev_priv(dev);
Sten Wang7a47dd72007-11-12 21:31:11 -0800965
Florian Fainelli38318612010-05-31 09:18:57 +0000966 return phy_ethtool_gset(rp->phydev, cmd);
Sten Wang7a47dd72007-11-12 21:31:11 -0800967}
968
969static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
970{
971 struct r6040_private *rp = netdev_priv(dev);
Sten Wang7a47dd72007-11-12 21:31:11 -0800972
Florian Fainelli38318612010-05-31 09:18:57 +0000973 return phy_ethtool_sset(rp->phydev, cmd);
Sten Wang7a47dd72007-11-12 21:31:11 -0800974}
975
Stephen Hemmingera7bd89c2008-11-21 17:34:56 -0800976static const struct ethtool_ops netdev_ethtool_ops = {
Sten Wang7a47dd72007-11-12 21:31:11 -0800977 .get_drvinfo = netdev_get_drvinfo,
978 .get_settings = netdev_get_settings,
979 .set_settings = netdev_set_settings,
Florian Fainelli38318612010-05-31 09:18:57 +0000980 .get_link = ethtool_op_get_link,
Richard Cochrand88e1022012-04-03 22:59:34 +0000981 .get_ts_info = ethtool_op_get_ts_info,
Sten Wang7a47dd72007-11-12 21:31:11 -0800982};
983
Stephen Hemmingera7bd89c2008-11-21 17:34:56 -0800984static const struct net_device_ops r6040_netdev_ops = {
985 .ndo_open = r6040_open,
986 .ndo_stop = r6040_close,
987 .ndo_start_xmit = r6040_start_xmit,
988 .ndo_get_stats = r6040_get_stats,
Jiri Pirkoafc4b132011-08-16 06:29:01 +0000989 .ndo_set_rx_mode = r6040_multicast_list,
Stephen Hemmingera7bd89c2008-11-21 17:34:56 -0800990 .ndo_change_mtu = eth_change_mtu,
991 .ndo_validate_addr = eth_validate_addr,
Florian Fainelli2154c7042010-08-08 10:08:44 +0000992 .ndo_set_mac_address = eth_mac_addr,
Stephen Hemmingera7bd89c2008-11-21 17:34:56 -0800993 .ndo_do_ioctl = r6040_ioctl,
994 .ndo_tx_timeout = r6040_tx_timeout,
995#ifdef CONFIG_NET_POLL_CONTROLLER
996 .ndo_poll_controller = r6040_poll_controller,
997#endif
998};
999
Florian Fainelli38318612010-05-31 09:18:57 +00001000static void r6040_adjust_link(struct net_device *dev)
1001{
1002 struct r6040_private *lp = netdev_priv(dev);
1003 struct phy_device *phydev = lp->phydev;
1004 int status_changed = 0;
1005 void __iomem *ioaddr = lp->base;
1006
1007 BUG_ON(!phydev);
1008
1009 if (lp->old_link != phydev->link) {
1010 status_changed = 1;
1011 lp->old_link = phydev->link;
1012 }
1013
1014 /* reflect duplex change */
1015 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
Florian Fainelli4e16d6e2012-01-04 08:59:34 +00001016 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);
Florian Fainelli38318612010-05-31 09:18:57 +00001017 iowrite16(lp->mcr0, ioaddr);
1018
1019 status_changed = 1;
1020 lp->old_duplex = phydev->duplex;
1021 }
1022
1023 if (status_changed) {
1024 pr_info("%s: link %s", dev->name, phydev->link ?
1025 "UP" : "DOWN");
1026 if (phydev->link)
1027 pr_cont(" - %d/%s", phydev->speed,
1028 DUPLEX_FULL == phydev->duplex ? "full" : "half");
1029 pr_cont("\n");
1030 }
1031}
1032
1033static int r6040_mii_probe(struct net_device *dev)
1034{
1035 struct r6040_private *lp = netdev_priv(dev);
1036 struct phy_device *phydev = NULL;
1037
1038 phydev = phy_find_first(lp->mii_bus);
1039 if (!phydev) {
1040 dev_err(&lp->pdev->dev, "no PHY found\n");
1041 return -ENODEV;
1042 }
1043
1044 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link,
Florian Fainellif9a8f832013-01-14 00:52:52 +00001045 PHY_INTERFACE_MODE_MII);
Florian Fainelli38318612010-05-31 09:18:57 +00001046
1047 if (IS_ERR(phydev)) {
1048 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1049 return PTR_ERR(phydev);
1050 }
1051
1052 /* mask with MAC supported features */
1053 phydev->supported &= (SUPPORTED_10baseT_Half
1054 | SUPPORTED_10baseT_Full
1055 | SUPPORTED_100baseT_Half
1056 | SUPPORTED_100baseT_Full
1057 | SUPPORTED_Autoneg
1058 | SUPPORTED_MII
1059 | SUPPORTED_TP);
1060
1061 phydev->advertising = phydev->supported;
1062 lp->phydev = phydev;
1063 lp->old_link = 0;
1064 lp->old_duplex = -1;
1065
1066 dev_info(&lp->pdev->dev, "attached PHY driver [%s] "
1067 "(mii_bus:phy_addr=%s)\n",
1068 phydev->drv->name, dev_name(&phydev->dev));
1069
1070 return 0;
1071}
1072
Greg Kroah-Hartman1dd06ae2012-12-06 14:30:56 +00001073static int r6040_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Sten Wang7a47dd72007-11-12 21:31:11 -08001074{
1075 struct net_device *dev;
1076 struct r6040_private *lp;
1077 void __iomem *ioaddr;
1078 int err, io_size = R6040_IO_SIZE;
1079 static int card_idx = -1;
1080 int bar = 0;
Sten Wang7a47dd72007-11-12 21:31:11 -08001081 u16 *adrp;
Florian Fainelli38318612010-05-31 09:18:57 +00001082 int i;
Sten Wang7a47dd72007-11-12 21:31:11 -08001083
Florian Fainelli2154c7042010-08-08 10:08:44 +00001084 pr_info("%s\n", version);
Sten Wang7a47dd72007-11-12 21:31:11 -08001085
1086 err = pci_enable_device(pdev);
1087 if (err)
Florian Fainellib0e45392008-07-21 12:32:29 +02001088 goto err_out;
Sten Wang7a47dd72007-11-12 21:31:11 -08001089
1090 /* this should always be supported */
Yang Hongyang284901a2009-04-06 19:01:15 -07001091 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Florian Fainellib0e45392008-07-21 12:32:29 +02001092 if (err) {
Florian Fainelli7d53b802010-04-07 21:39:27 +00001093 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
Sten Wang7a47dd72007-11-12 21:31:11 -08001094 "not supported by the card\n");
Devendra Nagaacaf8272012-05-29 13:38:42 +00001095 goto err_out_disable_dev;
Sten Wang7a47dd72007-11-12 21:31:11 -08001096 }
Yang Hongyang284901a2009-04-06 19:01:15 -07001097 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Florian Fainellib0e45392008-07-21 12:32:29 +02001098 if (err) {
Florian Fainelli7d53b802010-04-07 21:39:27 +00001099 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
Jeff Garzik092427b2007-11-23 21:49:27 -05001100 "not supported by the card\n");
Devendra Nagaacaf8272012-05-29 13:38:42 +00001101 goto err_out_disable_dev;
Jeff Garzik092427b2007-11-23 21:49:27 -05001102 }
Sten Wang7a47dd72007-11-12 21:31:11 -08001103
1104 /* IO Size check */
Michael Opdenacker6f5bec12009-06-24 21:05:09 +00001105 if (pci_resource_len(pdev, bar) < io_size) {
Florian Fainelli7d53b802010-04-07 21:39:27 +00001106 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
Florian Fainellib0e45392008-07-21 12:32:29 +02001107 err = -EIO;
Devendra Nagaacaf8272012-05-29 13:38:42 +00001108 goto err_out_disable_dev;
Sten Wang7a47dd72007-11-12 21:31:11 -08001109 }
1110
Sten Wang7a47dd72007-11-12 21:31:11 -08001111 pci_set_master(pdev);
1112
1113 dev = alloc_etherdev(sizeof(struct r6040_private));
1114 if (!dev) {
Florian Fainellib0e45392008-07-21 12:32:29 +02001115 err = -ENOMEM;
Devendra Nagaacaf8272012-05-29 13:38:42 +00001116 goto err_out_disable_dev;
Sten Wang7a47dd72007-11-12 21:31:11 -08001117 }
1118 SET_NETDEV_DEV(dev, &pdev->dev);
1119 lp = netdev_priv(dev);
Sten Wang7a47dd72007-11-12 21:31:11 -08001120
Florian Fainellib0e45392008-07-21 12:32:29 +02001121 err = pci_request_regions(pdev, DRV_NAME);
1122
1123 if (err) {
Florian Fainelli7d53b802010-04-07 21:39:27 +00001124 dev_err(&pdev->dev, "Failed to request PCI regions\n");
Florian Fainellib0e45392008-07-21 12:32:29 +02001125 goto err_out_free_dev;
Sten Wang7a47dd72007-11-12 21:31:11 -08001126 }
1127
1128 ioaddr = pci_iomap(pdev, bar, io_size);
1129 if (!ioaddr) {
Florian Fainelli7d53b802010-04-07 21:39:27 +00001130 dev_err(&pdev->dev, "ioremap failed for device\n");
Florian Fainellib0e45392008-07-21 12:32:29 +02001131 err = -EIO;
1132 goto err_out_free_res;
Sten Wang7a47dd72007-11-12 21:31:11 -08001133 }
Florian Fainelli31171ae2012-04-11 07:18:42 +00001134
Florian Fainelli84314bf2009-01-08 11:01:58 -08001135 /* If PHY status change register is still set to zero it means the
Florian Fainelli31171ae2012-04-11 07:18:42 +00001136 * bootloader didn't initialize it, so we set it to:
1137 * - enable phy status change
1138 * - enable all phy addresses
1139 * - set to lowest timer divider */
Florian Fainelli84314bf2009-01-08 11:01:58 -08001140 if (ioread16(ioaddr + PHY_CC) == 0)
Florian Fainelli31171ae2012-04-11 07:18:42 +00001141 iowrite16(SCEN | PHY_MAX_ADDR << PHYAD_SHIFT |
1142 7 << TMRDIV_SHIFT, ioaddr + PHY_CC);
Sten Wang7a47dd72007-11-12 21:31:11 -08001143
1144 /* Init system & device */
Sten Wang7a47dd72007-11-12 21:31:11 -08001145 lp->base = ioaddr;
1146 dev->irq = pdev->irq;
1147
1148 spin_lock_init(&lp->lock);
1149 pci_set_drvdata(pdev, dev);
1150
1151 /* Set MAC address */
1152 card_idx++;
1153
1154 adrp = (u16 *)dev->dev_addr;
1155 adrp[0] = ioread16(ioaddr + MID_0L);
1156 adrp[1] = ioread16(ioaddr + MID_0M);
1157 adrp[2] = ioread16(ioaddr + MID_0H);
1158
Florian Fainelli1d2b1a72009-01-08 11:02:30 -08001159 /* Some bootloader/BIOSes do not initialize
1160 * MAC address, warn about that */
Florian Fainelli9f113612009-01-08 15:04:45 +00001161 if (!(adrp[0] || adrp[1] || adrp[2])) {
Florian Fainelli2154c7042010-08-08 10:08:44 +00001162 netdev_warn(dev, "MAC address not initialized, "
1163 "generating random\n");
Danny Kukawkaf2cedb62012-02-15 06:45:39 +00001164 eth_hw_addr_random(dev);
Florian Fainelli9f113612009-01-08 15:04:45 +00001165 }
Florian Fainelli1d2b1a72009-01-08 11:02:30 -08001166
Sten Wang7a47dd72007-11-12 21:31:11 -08001167 /* Link new device into r6040_root_dev */
1168 lp->pdev = pdev;
Florian Fainelli129cf9a2008-07-13 14:32:45 +02001169 lp->dev = dev;
Sten Wang7a47dd72007-11-12 21:31:11 -08001170
1171 /* Init RDC private data */
Cesar Eduardo Barros77e1e432012-01-07 05:13:17 +00001172 lp->mcr0 = MCR0_XMTEN | MCR0_RCVEN;
Sten Wang7a47dd72007-11-12 21:31:11 -08001173
1174 /* The RDC-specific entries in the device structure. */
Stephen Hemmingera7bd89c2008-11-21 17:34:56 -08001175 dev->netdev_ops = &r6040_netdev_ops;
Sten Wang7a47dd72007-11-12 21:31:11 -08001176 dev->ethtool_ops = &netdev_ethtool_ops;
Sten Wang7a47dd72007-11-12 21:31:11 -08001177 dev->watchdog_timeo = TX_TIMEOUT;
Stephen Hemmingera7bd89c2008-11-21 17:34:56 -08001178
Sten Wang7a47dd72007-11-12 21:31:11 -08001179 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
Sten Wang7a47dd72007-11-12 21:31:11 -08001180
Florian Fainelli38318612010-05-31 09:18:57 +00001181 lp->mii_bus = mdiobus_alloc();
1182 if (!lp->mii_bus) {
1183 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
Axel Lin9c86c0f2011-01-04 22:40:04 +00001184 err = -ENOMEM;
Mark Kellye03f6142009-08-20 01:26:20 +00001185 goto err_out_unmap;
1186 }
1187
Florian Fainelli38318612010-05-31 09:18:57 +00001188 lp->mii_bus->priv = dev;
1189 lp->mii_bus->read = r6040_mdiobus_read;
1190 lp->mii_bus->write = r6040_mdiobus_write;
1191 lp->mii_bus->reset = r6040_mdiobus_reset;
1192 lp->mii_bus->name = "r6040_eth_mii";
Florian Fainelli817380e2012-01-04 08:50:40 +00001193 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1194 dev_name(&pdev->dev), card_idx);
Joe Perchesb2adaca2013-02-03 17:43:58 +00001195 lp->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
Florian Fainelli38318612010-05-31 09:18:57 +00001196 if (!lp->mii_bus->irq) {
Axel Lin9c86c0f2011-01-04 22:40:04 +00001197 err = -ENOMEM;
Florian Fainelli38318612010-05-31 09:18:57 +00001198 goto err_out_mdio;
1199 }
1200
1201 for (i = 0; i < PHY_MAX_ADDR; i++)
1202 lp->mii_bus->irq[i] = PHY_POLL;
1203
1204 err = mdiobus_register(lp->mii_bus);
1205 if (err) {
1206 dev_err(&pdev->dev, "failed to register MII bus\n");
1207 goto err_out_mdio_irq;
1208 }
1209
1210 err = r6040_mii_probe(dev);
1211 if (err) {
1212 dev_err(&pdev->dev, "failed to probe MII bus\n");
1213 goto err_out_mdio_unregister;
1214 }
1215
Sten Wang7a47dd72007-11-12 21:31:11 -08001216 /* Register net device. After this dev->name assign */
1217 err = register_netdev(dev);
1218 if (err) {
Florian Fainelli7d53b802010-04-07 21:39:27 +00001219 dev_err(&pdev->dev, "Failed to register net device\n");
Florian Fainelli38318612010-05-31 09:18:57 +00001220 goto err_out_mdio_unregister;
Sten Wang7a47dd72007-11-12 21:31:11 -08001221 }
1222 return 0;
1223
Florian Fainelli38318612010-05-31 09:18:57 +00001224err_out_mdio_unregister:
1225 mdiobus_unregister(lp->mii_bus);
1226err_out_mdio_irq:
1227 kfree(lp->mii_bus->irq);
1228err_out_mdio:
1229 mdiobus_free(lp->mii_bus);
Florian Fainellib0e45392008-07-21 12:32:29 +02001230err_out_unmap:
Devendra Naga20571d82012-05-29 13:43:34 +00001231 netif_napi_del(&lp->napi);
1232 pci_set_drvdata(pdev, NULL);
Florian Fainellib0e45392008-07-21 12:32:29 +02001233 pci_iounmap(pdev, ioaddr);
1234err_out_free_res:
Sten Wang7a47dd72007-11-12 21:31:11 -08001235 pci_release_regions(pdev);
Florian Fainellib0e45392008-07-21 12:32:29 +02001236err_out_free_dev:
Sten Wang7a47dd72007-11-12 21:31:11 -08001237 free_netdev(dev);
Devendra Nagaacaf8272012-05-29 13:38:42 +00001238err_out_disable_dev:
1239 pci_disable_device(pdev);
Florian Fainellib0e45392008-07-21 12:32:29 +02001240err_out:
Sten Wang7a47dd72007-11-12 21:31:11 -08001241 return err;
1242}
1243
Bill Pembertonf1e24262012-12-03 09:23:30 -05001244static void r6040_remove_one(struct pci_dev *pdev)
Sten Wang7a47dd72007-11-12 21:31:11 -08001245{
1246 struct net_device *dev = pci_get_drvdata(pdev);
Florian Fainelli38318612010-05-31 09:18:57 +00001247 struct r6040_private *lp = netdev_priv(dev);
Sten Wang7a47dd72007-11-12 21:31:11 -08001248
1249 unregister_netdev(dev);
Florian Fainelli38318612010-05-31 09:18:57 +00001250 mdiobus_unregister(lp->mii_bus);
1251 kfree(lp->mii_bus->irq);
1252 mdiobus_free(lp->mii_bus);
Devendra Naga20571d82012-05-29 13:43:34 +00001253 netif_napi_del(&lp->napi);
Devendra Naga20571d82012-05-29 13:43:34 +00001254 pci_iounmap(pdev, lp->base);
Sten Wang7a47dd72007-11-12 21:31:11 -08001255 pci_release_regions(pdev);
1256 free_netdev(dev);
1257 pci_disable_device(pdev);
1258 pci_set_drvdata(pdev, NULL);
1259}
1260
1261
Alexey Dobriyana3aa1882010-01-07 11:58:11 +00001262static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
Francois Romieu5ac5d612007-11-28 23:02:33 +01001263 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1264 { 0 }
Sten Wang7a47dd72007-11-12 21:31:11 -08001265};
1266MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1267
1268static struct pci_driver r6040_driver = {
Francois Romieu5ac5d612007-11-28 23:02:33 +01001269 .name = DRV_NAME,
Sten Wang7a47dd72007-11-12 21:31:11 -08001270 .id_table = r6040_pci_tbl,
1271 .probe = r6040_init_one,
Bill Pembertonf1e24262012-12-03 09:23:30 -05001272 .remove = r6040_remove_one,
Sten Wang7a47dd72007-11-12 21:31:11 -08001273};
1274
Devendra Naga36efc942012-07-08 05:57:57 +00001275module_pci_driver(r6040_driver);