Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 1 | /* |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 2 | * Copyright 2004-2009 Analog Devices Inc. |
| 3 | * 2007 David Rowe |
| 4 | * 2006 Intratrade Ltd. |
| 5 | * Ivan Danov <idanov@gmail.com> |
| 6 | * 2005 National ICT Australia (NICTA) |
| 7 | * Aidan Williams <aidan@nicta.com.au> |
Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 8 | * |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 9 | * Licensed under the GPL-2 or later. |
Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <linux/device.h> |
| 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/mtd/mtd.h> |
| 15 | #include <linux/mtd/partitions.h> |
| 16 | #include <linux/spi/spi.h> |
| 17 | #include <linux/spi/flash.h> |
| 18 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
| 19 | #include <linux/usb/isp1362.h> |
| 20 | #endif |
| 21 | #include <asm/irq.h> |
| 22 | #include <asm/bfin5xx_spi.h> |
| 23 | |
| 24 | /* |
| 25 | * Name the Board for the /proc/cpuinfo |
| 26 | */ |
| 27 | const char bfin_board_name[] = "IP04/IP08"; |
| 28 | |
| 29 | /* |
| 30 | * Driver needs to know address, irq and flag pin. |
| 31 | */ |
| 32 | #if defined(CONFIG_BFIN532_IP0X) |
| 33 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) |
| 34 | |
| 35 | #include <linux/dm9000.h> |
| 36 | |
| 37 | static struct resource dm9000_resource1[] = { |
| 38 | { |
| 39 | .start = 0x20100000, |
| 40 | .end = 0x20100000 + 1, |
| 41 | .flags = IORESOURCE_MEM |
| 42 | },{ |
| 43 | .start = 0x20100000 + 2, |
| 44 | .end = 0x20100000 + 3, |
| 45 | .flags = IORESOURCE_MEM |
| 46 | },{ |
| 47 | .start = IRQ_PF15, |
| 48 | .end = IRQ_PF15, |
| 49 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
| 50 | } |
| 51 | }; |
| 52 | |
| 53 | static struct resource dm9000_resource2[] = { |
| 54 | { |
| 55 | .start = 0x20200000, |
| 56 | .end = 0x20200000 + 1, |
| 57 | .flags = IORESOURCE_MEM |
| 58 | },{ |
| 59 | .start = 0x20200000 + 2, |
| 60 | .end = 0x20200000 + 3, |
| 61 | .flags = IORESOURCE_MEM |
| 62 | },{ |
| 63 | .start = IRQ_PF14, |
| 64 | .end = IRQ_PF14, |
| 65 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
| 66 | } |
| 67 | }; |
| 68 | |
| 69 | /* |
| 70 | * for the moment we limit ourselves to 16bit IO until some |
| 71 | * better IO routines can be written and tested |
| 72 | */ |
| 73 | static struct dm9000_plat_data dm9000_platdata1 = { |
| 74 | .flags = DM9000_PLATF_16BITONLY, |
| 75 | }; |
| 76 | |
| 77 | static struct platform_device dm9000_device1 = { |
| 78 | .name = "dm9000", |
| 79 | .id = 0, |
| 80 | .num_resources = ARRAY_SIZE(dm9000_resource1), |
| 81 | .resource = dm9000_resource1, |
| 82 | .dev = { |
| 83 | .platform_data = &dm9000_platdata1, |
| 84 | } |
| 85 | }; |
| 86 | |
| 87 | static struct dm9000_plat_data dm9000_platdata2 = { |
| 88 | .flags = DM9000_PLATF_16BITONLY, |
| 89 | }; |
| 90 | |
| 91 | static struct platform_device dm9000_device2 = { |
| 92 | .name = "dm9000", |
| 93 | .id = 1, |
| 94 | .num_resources = ARRAY_SIZE(dm9000_resource2), |
| 95 | .resource = dm9000_resource2, |
| 96 | .dev = { |
| 97 | .platform_data = &dm9000_platdata2, |
| 98 | } |
| 99 | }; |
| 100 | |
| 101 | #endif |
| 102 | #endif |
| 103 | |
| 104 | |
| 105 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| 106 | /* all SPI peripherals info goes here */ |
| 107 | |
Michael Hennerich | f3f704d | 2009-03-06 00:27:57 +0800 | [diff] [blame] | 108 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 109 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 110 | /* |
| 111 | * CPOL (Clock Polarity) |
| 112 | * 0 - Active high SCK |
| 113 | * 1 - Active low SCK |
| 114 | * CPHA (Clock Phase) Selects transfer format and operation mode |
| 115 | * 0 - SCLK toggles from middle of the first data bit, slave select |
| 116 | * pins controlled by hardware. |
| 117 | * 1 - SCLK toggles from beginning of first data bit, slave select |
| 118 | * pins controller by user software. |
| 119 | * .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work |
| 120 | * NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0 |
| 121 | * NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1 |
| 122 | */ |
| 123 | .ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */ |
| 124 | .enable_dma = 0, /* if 1 - block!!! */ |
| 125 | .bits_per_word = 8, |
Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 126 | }; |
| 127 | #endif |
| 128 | |
| 129 | /* Notice: for blackfin, the speed_hz is the value of register |
| 130 | * SPI_BAUD, not the real baudrate */ |
| 131 | static struct spi_board_info bfin_spi_board_info[] __initdata = { |
Michael Hennerich | f3f704d | 2009-03-06 00:27:57 +0800 | [diff] [blame] | 132 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 133 | { |
Michael Hennerich | f3f704d | 2009-03-06 00:27:57 +0800 | [diff] [blame] | 134 | .modalias = "mmc_spi", |
Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 135 | .max_speed_hz = 2, |
| 136 | .bus_num = 1, |
Michael Hennerich | f3f704d | 2009-03-06 00:27:57 +0800 | [diff] [blame] | 137 | .chip_select = 5, |
| 138 | .controller_data = &mmc_spi_chip_info, |
Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 139 | }, |
| 140 | #endif |
| 141 | }; |
| 142 | |
| 143 | /* SPI controller data */ |
| 144 | static struct bfin5xx_spi_master spi_bfin_master_info = { |
| 145 | .num_chipselect = 8, |
| 146 | .enable_dma = 1, /* master has the ability to do dma transfer */ |
| 147 | }; |
| 148 | |
| 149 | static struct platform_device spi_bfin_master_device = { |
| 150 | .name = "bfin-spi-master", |
| 151 | .id = 1, /* Bus number */ |
| 152 | .dev = { |
| 153 | .platform_data = &spi_bfin_master_info, /* Passed to driver */ |
| 154 | }, |
| 155 | }; |
| 156 | #endif /* spi master and devices */ |
| 157 | |
| 158 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) |
| 159 | static struct resource bfin_uart_resources[] = { |
| 160 | { |
| 161 | .start = 0xFFC00400, |
| 162 | .end = 0xFFC004FF, |
| 163 | .flags = IORESOURCE_MEM, |
| 164 | }, |
| 165 | }; |
| 166 | |
| 167 | static struct platform_device bfin_uart_device = { |
| 168 | .name = "bfin-uart", |
| 169 | .id = 1, |
| 170 | .num_resources = ARRAY_SIZE(bfin_uart_resources), |
| 171 | .resource = bfin_uart_resources, |
| 172 | }; |
| 173 | #endif |
| 174 | |
Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 175 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 176 | #ifdef CONFIG_BFIN_SIR0 |
Graf Yang | 42bd8bc | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 177 | static struct resource bfin_sir0_resources[] = { |
Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 178 | { |
| 179 | .start = 0xFFC00400, |
| 180 | .end = 0xFFC004FF, |
| 181 | .flags = IORESOURCE_MEM, |
| 182 | }, |
Graf Yang | 42bd8bc | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 183 | { |
| 184 | .start = IRQ_UART0_RX, |
| 185 | .end = IRQ_UART0_RX+1, |
| 186 | .flags = IORESOURCE_IRQ, |
| 187 | }, |
| 188 | { |
| 189 | .start = CH_UART0_RX, |
| 190 | .end = CH_UART0_RX+1, |
| 191 | .flags = IORESOURCE_DMA, |
| 192 | }, |
Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 193 | }; |
| 194 | |
Graf Yang | 42bd8bc | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 195 | static struct platform_device bfin_sir0_device = { |
Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 196 | .name = "bfin_sir", |
| 197 | .id = 0, |
Graf Yang | 42bd8bc | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 198 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), |
| 199 | .resource = bfin_sir0_resources, |
Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 200 | }; |
| 201 | #endif |
Graf Yang | 42bd8bc | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 202 | #endif |
Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 203 | |
Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 204 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
| 205 | static struct resource isp1362_hcd_resources[] = { |
| 206 | { |
| 207 | .start = 0x20300000, |
| 208 | .end = 0x20300000 + 1, |
| 209 | .flags = IORESOURCE_MEM, |
| 210 | },{ |
| 211 | .start = 0x20300000 + 2, |
| 212 | .end = 0x20300000 + 3, |
| 213 | .flags = IORESOURCE_MEM, |
| 214 | },{ |
| 215 | .start = IRQ_PF11, |
| 216 | .end = IRQ_PF11, |
| 217 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, |
| 218 | }, |
| 219 | }; |
| 220 | |
| 221 | static struct isp1362_platform_data isp1362_priv = { |
| 222 | .sel15Kres = 1, |
| 223 | .clknotstop = 0, |
| 224 | .oc_enable = 0, /* external OC */ |
| 225 | .int_act_high = 0, |
| 226 | .int_edge_triggered = 0, |
| 227 | .remote_wakeup_connected = 0, |
| 228 | .no_power_switching = 1, |
| 229 | .power_switching_mode = 0, |
| 230 | }; |
| 231 | |
| 232 | static struct platform_device isp1362_hcd_device = { |
| 233 | .name = "isp1362-hcd", |
| 234 | .id = 0, |
| 235 | .dev = { |
| 236 | .platform_data = &isp1362_priv, |
| 237 | }, |
| 238 | .num_resources = ARRAY_SIZE(isp1362_hcd_resources), |
| 239 | .resource = isp1362_hcd_resources, |
| 240 | }; |
| 241 | #endif |
| 242 | |
| 243 | |
| 244 | static struct platform_device *ip0x_devices[] __initdata = { |
| 245 | #if defined(CONFIG_BFIN532_IP0X) |
| 246 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) |
| 247 | &dm9000_device1, |
| 248 | &dm9000_device2, |
| 249 | #endif |
| 250 | #endif |
| 251 | |
| 252 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| 253 | &spi_bfin_master_device, |
| 254 | #endif |
| 255 | |
| 256 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) |
| 257 | &bfin_uart_device, |
| 258 | #endif |
Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 259 | |
| 260 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) |
Graf Yang | 42bd8bc | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 261 | #ifdef CONFIG_BFIN_SIR0 |
| 262 | &bfin_sir0_device, |
| 263 | #endif |
Graf Yang | 5be36d2 | 2008-04-25 03:09:15 +0800 | [diff] [blame] | 264 | #endif |
| 265 | |
Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 266 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) |
| 267 | &isp1362_hcd_device, |
| 268 | #endif |
| 269 | }; |
| 270 | |
| 271 | static int __init ip0x_init(void) |
| 272 | { |
| 273 | int i; |
| 274 | |
| 275 | printk(KERN_INFO "%s(): registering device resources\n", __func__); |
| 276 | platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices)); |
| 277 | |
| 278 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| 279 | for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) { |
| 280 | int j = 1 << bfin_spi_board_info[i].chip_select; |
| 281 | /* set spi cs to 1 */ |
| 282 | bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j); |
| 283 | bfin_write_FIO_FLAG_S(j); |
| 284 | } |
| 285 | spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); |
| 286 | #endif |
| 287 | |
| 288 | return 0; |
| 289 | } |
| 290 | |
| 291 | arch_initcall(ip0x_init); |