blob: 4fc7a8e4916808faaf4361f75c93292003c8bab3 [file] [log] [blame]
Jason Cooper3d468b62012-02-27 16:07:13 +00001/include/ "skeleton.dtsi"
2
3/ {
Andrew Lunn77843502012-07-18 19:22:54 +02004 compatible = "marvell,kirkwood";
Andrew Lunn278b45b2012-06-27 13:40:04 +02005 interrupt-parent = <&intc>;
6
7 intc: interrupt-controller {
8 compatible = "marvell,orion-intc", "marvell,intc";
9 interrupt-controller;
10 #interrupt-cells = <1>;
11 reg = <0xf1020204 0x04>,
12 <0xf1020214 0x04>;
13 };
Jason Cooper3d468b62012-02-27 16:07:13 +000014
Jason Cooper163f2ce2012-03-15 01:00:27 +000015 ocp@f1000000 {
16 compatible = "simple-bus";
Andrew Lunnf37fbd32012-09-03 20:29:34 +020017 ranges = <0x00000000 0xf1000000 0x4000000
18 0xf5000000 0xf5000000 0x0000400>;
Jason Cooper163f2ce2012-03-15 01:00:27 +000019 #address-cells = <1>;
20 #size-cells = <1>;
21
Andrew Lunn278b45b2012-06-27 13:40:04 +020022 gpio0: gpio@10100 {
23 compatible = "marvell,orion-gpio";
24 #gpio-cells = <2>;
25 gpio-controller;
26 reg = <0x10100 0x40>;
27 ngpio = <32>;
28 interrupts = <35>, <36>, <37>, <38>;
29 };
30
31 gpio1: gpio@10140 {
32 compatible = "marvell,orion-gpio";
33 #gpio-cells = <2>;
34 gpio-controller;
35 reg = <0x10140 0x40>;
36 ngpio = <18>;
37 interrupts = <39>, <40>, <41>;
38 };
39
Jason Cooper163f2ce2012-03-15 01:00:27 +000040 serial@12000 {
41 compatible = "ns16550a";
42 reg = <0x12000 0x100>;
43 reg-shift = <2>;
44 interrupts = <33>;
45 /* set clock-frequency in board dts */
46 status = "disabled";
47 };
48
49 serial@12100 {
50 compatible = "ns16550a";
51 reg = <0x12100 0x100>;
52 reg-shift = <2>;
53 interrupts = <34>;
54 /* set clock-frequency in board dts */
55 status = "disabled";
56 };
Jason Coopere871b872012-03-06 23:55:04 +000057
58 rtc@10300 {
Andrew Lunn77843502012-07-18 19:22:54 +020059 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
Jason Coopere871b872012-03-06 23:55:04 +000060 reg = <0x10300 0x20>;
61 interrupts = <53>;
62 };
Jamie Lentin858156b2012-04-18 11:06:42 +010063
Michael Walle76372122012-06-06 20:30:57 +020064 spi@10600 {
65 compatible = "marvell,orion-spi";
66 #address-cells = <1>;
67 #size-cells = <0>;
68 cell-index = <0>;
69 interrupts = <23>;
70 reg = <0x10600 0x28>;
71 status = "disabled";
72 };
73
Andrew Lunn1e7bad02012-06-10 15:20:06 +020074 wdt@20300 {
75 compatible = "marvell,orion-wdt";
76 reg = <0x20300 0x28>;
77 status = "okay";
78 };
79
Andrew Lunnb6cf8072012-10-20 13:10:01 +020080 ehci@50000 {
81 compatible = "marvell,orion-ehci";
82 reg = <0x50000 0x1000>;
83 interrupts = <19>;
84 status = "okay";
85 };
86
Andrew Lunn97b414e2012-06-10 16:45:37 +020087 sata@80000 {
88 compatible = "marvell,orion-sata";
89 reg = <0x80000 0x5000>;
90 interrupts = <21>;
91 status = "disabled";
92 };
93
Jamie Lentin858156b2012-04-18 11:06:42 +010094 nand@3000000 {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 cle = <0>;
98 ale = <1>;
99 bank-width = <1>;
Andrew Lunn77843502012-07-18 19:22:54 +0200100 compatible = "marvell,orion-nand";
Jamie Lentin858156b2012-04-18 11:06:42 +0100101 reg = <0x3000000 0x400>;
102 chip-delay = <25>;
103 /* set partition map and/or chip-delay in board dts */
104 status = "disabled";
105 };
Andrew Lunne91cac02012-07-20 13:51:55 +0200106
107 i2c@11000 {
108 compatible = "marvell,mv64xxx-i2c";
109 reg = <0x11000 0x20>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 interrupts = <29>;
113 clock-frequency = <100000>;
114 status = "disabled";
115 };
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200116
117 crypto@30000 {
118 compatible = "marvell,orion-crypto";
119 reg = <0x30000 0x10000>,
120 <0xf5000000 0x800>;
121 reg-names = "regs", "sram";
122 interrupts = <22>;
123 status = "okay";
124 };
Jason Cooper163f2ce2012-03-15 01:00:27 +0000125 };
126};