blob: 1a65d6514237dd59ac24c8deb89f1afce27a4e3d [file] [log] [blame]
Dan Williams6f231dd2011-07-02 22:56:22 -07001/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * BSD LICENSE
25 *
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27 * All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
Dan Williamsac668c62011-06-07 18:50:55 -070055#include <linux/circ_buf.h>
Dan Williamscc9203b2011-05-08 17:34:44 -070056#include <linux/device.h>
57#include <scsi/sas.h>
58#include "host.h"
Dan Williams6f231dd2011-07-02 22:56:22 -070059#include "isci.h"
Dan Williams6f231dd2011-07-02 22:56:22 -070060#include "port.h"
Dan Williams6f231dd2011-07-02 22:56:22 -070061#include "host.h"
Dan Williamsd044af12011-03-08 09:52:49 -080062#include "probe_roms.h"
Dan Williamscc9203b2011-05-08 17:34:44 -070063#include "remote_device.h"
64#include "request.h"
Dan Williamscc9203b2011-05-08 17:34:44 -070065#include "scu_completion_codes.h"
66#include "scu_event_codes.h"
Dan Williams63a3a152011-05-08 21:36:46 -070067#include "registers.h"
Dan Williamscc9203b2011-05-08 17:34:44 -070068#include "scu_remote_node_context.h"
69#include "scu_task_context.h"
Dan Williams6f231dd2011-07-02 22:56:22 -070070
Dan Williamscc9203b2011-05-08 17:34:44 -070071#define SCU_CONTEXT_RAM_INIT_STALL_TIME 200
72
Dan Williams7c78da32011-06-01 16:00:01 -070073#define smu_max_ports(dcc_value) \
Dan Williamscc9203b2011-05-08 17:34:44 -070074 (\
75 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
76 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
77 )
78
Dan Williams7c78da32011-06-01 16:00:01 -070079#define smu_max_task_contexts(dcc_value) \
Dan Williamscc9203b2011-05-08 17:34:44 -070080 (\
81 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
82 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
83 )
84
Dan Williams7c78da32011-06-01 16:00:01 -070085#define smu_max_rncs(dcc_value) \
Dan Williamscc9203b2011-05-08 17:34:44 -070086 (\
87 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
88 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
89 )
90
Dan Williamscc9203b2011-05-08 17:34:44 -070091#define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100
92
93/**
94 *
95 *
96 * The number of milliseconds to wait while a given phy is consuming power
97 * before allowing another set of phys to consume power. Ultimately, this will
98 * be specified by OEM parameter.
99 */
100#define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
101
102/**
103 * NORMALIZE_PUT_POINTER() -
104 *
105 * This macro will normalize the completion queue put pointer so its value can
106 * be used as an array inde
107 */
108#define NORMALIZE_PUT_POINTER(x) \
109 ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
110
111
112/**
113 * NORMALIZE_EVENT_POINTER() -
114 *
115 * This macro will normalize the completion queue event entry so its value can
116 * be used as an index.
117 */
118#define NORMALIZE_EVENT_POINTER(x) \
119 (\
120 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
121 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
122 )
123
124/**
Dan Williamscc9203b2011-05-08 17:34:44 -0700125 * NORMALIZE_GET_POINTER() -
126 *
127 * This macro will normalize the completion queue get pointer so its value can
128 * be used as an index into an array
129 */
130#define NORMALIZE_GET_POINTER(x) \
131 ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
132
133/**
134 * NORMALIZE_GET_POINTER_CYCLE_BIT() -
135 *
136 * This macro will normalize the completion queue cycle pointer so it matches
137 * the completion queue cycle bit
138 */
139#define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
140 ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
141
142/**
143 * COMPLETION_QUEUE_CYCLE_BIT() -
144 *
145 * This macro will return the cycle bit of the completion queue entry
146 */
147#define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
148
Edmund Nadolski12ef6542011-06-02 00:10:50 +0000149/* Init the state machine and call the state entry function (if any) */
150void sci_init_sm(struct sci_base_state_machine *sm,
151 const struct sci_base_state *state_table, u32 initial_state)
152{
153 sci_state_transition_t handler;
154
155 sm->initial_state_id = initial_state;
156 sm->previous_state_id = initial_state;
157 sm->current_state_id = initial_state;
158 sm->state_table = state_table;
159
160 handler = sm->state_table[initial_state].enter_state;
161 if (handler)
162 handler(sm);
163}
164
165/* Call the state exit fn, update the current state, call the state entry fn */
166void sci_change_state(struct sci_base_state_machine *sm, u32 next_state)
167{
168 sci_state_transition_t handler;
169
170 handler = sm->state_table[sm->current_state_id].exit_state;
171 if (handler)
172 handler(sm);
173
174 sm->previous_state_id = sm->current_state_id;
175 sm->current_state_id = next_state;
176
177 handler = sm->state_table[sm->current_state_id].enter_state;
178 if (handler)
179 handler(sm);
180}
181
Dan Williams89a73012011-06-30 19:14:33 -0700182static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700183{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700184 u32 get_value = ihost->completion_queue_get;
Dan Williamscc9203b2011-05-08 17:34:44 -0700185 u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
186
187 if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700188 COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]))
Dan Williamscc9203b2011-05-08 17:34:44 -0700189 return true;
190
191 return false;
192}
193
Dan Williams89a73012011-06-30 19:14:33 -0700194static bool sci_controller_isr(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700195{
Dan Williams89a73012011-06-30 19:14:33 -0700196 if (sci_controller_completion_queue_has_entries(ihost)) {
Dan Williamscc9203b2011-05-08 17:34:44 -0700197 return true;
198 } else {
199 /*
200 * we have a spurious interrupt it could be that we have already
201 * emptied the completion queue from a previous interrupt */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700202 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
Dan Williamscc9203b2011-05-08 17:34:44 -0700203
204 /*
205 * There is a race in the hardware that could cause us not to be notified
206 * of an interrupt completion if we do not take this step. We will mask
207 * then unmask the interrupts so if there is another interrupt pending
208 * the clearing of the interrupt source we get the next interrupt message. */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700209 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
210 writel(0, &ihost->smu_registers->interrupt_mask);
Dan Williamscc9203b2011-05-08 17:34:44 -0700211 }
212
213 return false;
214}
215
Dan Williamsc7ef4032011-02-18 09:25:05 -0800216irqreturn_t isci_msix_isr(int vec, void *data)
Dan Williams6f231dd2011-07-02 22:56:22 -0700217{
Dan Williamsc7ef4032011-02-18 09:25:05 -0800218 struct isci_host *ihost = data;
Dan Williams6f231dd2011-07-02 22:56:22 -0700219
Dan Williams89a73012011-06-30 19:14:33 -0700220 if (sci_controller_isr(ihost))
Dan Williams0cf89d12011-02-18 09:25:07 -0800221 tasklet_schedule(&ihost->completion_tasklet);
Dan Williams6f231dd2011-07-02 22:56:22 -0700222
Dan Williamsc7ef4032011-02-18 09:25:05 -0800223 return IRQ_HANDLED;
Dan Williams6f231dd2011-07-02 22:56:22 -0700224}
225
Dan Williams89a73012011-06-30 19:14:33 -0700226static bool sci_controller_error_isr(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700227{
228 u32 interrupt_status;
229
230 interrupt_status =
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700231 readl(&ihost->smu_registers->interrupt_status);
Dan Williamscc9203b2011-05-08 17:34:44 -0700232 interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
233
234 if (interrupt_status != 0) {
235 /*
236 * There is an error interrupt pending so let it through and handle
237 * in the callback */
238 return true;
239 }
240
241 /*
242 * There is a race in the hardware that could cause us not to be notified
243 * of an interrupt completion if we do not take this step. We will mask
244 * then unmask the error interrupts so if there was another interrupt
245 * pending we will be notified.
246 * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700247 writel(0xff, &ihost->smu_registers->interrupt_mask);
248 writel(0, &ihost->smu_registers->interrupt_mask);
Dan Williamscc9203b2011-05-08 17:34:44 -0700249
250 return false;
251}
252
Dan Williams89a73012011-06-30 19:14:33 -0700253static void sci_controller_task_completion(struct isci_host *ihost, u32 ent)
Dan Williamscc9203b2011-05-08 17:34:44 -0700254{
Dan Williams89a73012011-06-30 19:14:33 -0700255 u32 index = SCU_GET_COMPLETION_INDEX(ent);
Dan Williamsdb056252011-06-17 14:18:39 -0700256 struct isci_request *ireq = ihost->reqs[index];
Dan Williamscc9203b2011-05-08 17:34:44 -0700257
258 /* Make sure that we really want to process this IO request */
Dan Williamsdb056252011-06-17 14:18:39 -0700259 if (test_bit(IREQ_ACTIVE, &ireq->flags) &&
Dan Williams5076a1a2011-06-27 14:57:03 -0700260 ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG &&
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700261 ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index])
Dan Williams89a73012011-06-30 19:14:33 -0700262 /* Yep this is a valid io request pass it along to the
263 * io request handler
264 */
265 sci_io_request_tc_completion(ireq, ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700266}
267
Dan Williams89a73012011-06-30 19:14:33 -0700268static void sci_controller_sdma_completion(struct isci_host *ihost, u32 ent)
Dan Williamscc9203b2011-05-08 17:34:44 -0700269{
270 u32 index;
Dan Williams5076a1a2011-06-27 14:57:03 -0700271 struct isci_request *ireq;
Dan Williams78a6f062011-06-30 16:31:37 -0700272 struct isci_remote_device *idev;
Dan Williamscc9203b2011-05-08 17:34:44 -0700273
Dan Williams89a73012011-06-30 19:14:33 -0700274 index = SCU_GET_COMPLETION_INDEX(ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700275
Dan Williams89a73012011-06-30 19:14:33 -0700276 switch (scu_get_command_request_type(ent)) {
Dan Williamscc9203b2011-05-08 17:34:44 -0700277 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
278 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700279 ireq = ihost->reqs[index];
280 dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n",
Dan Williams89a73012011-06-30 19:14:33 -0700281 __func__, ent, ireq);
Dan Williamscc9203b2011-05-08 17:34:44 -0700282 /* @todo For a post TC operation we need to fail the IO
283 * request
284 */
285 break;
Dan Williamscc9203b2011-05-08 17:34:44 -0700286 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
287 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
288 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700289 idev = ihost->device_table[index];
290 dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n",
Dan Williams89a73012011-06-30 19:14:33 -0700291 __func__, ent, idev);
Dan Williamscc9203b2011-05-08 17:34:44 -0700292 /* @todo For a port RNC operation we need to fail the
293 * device
294 */
295 break;
Dan Williamscc9203b2011-05-08 17:34:44 -0700296 default:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700297 dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n",
Dan Williams89a73012011-06-30 19:14:33 -0700298 __func__, ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700299 break;
Dan Williamscc9203b2011-05-08 17:34:44 -0700300 }
301}
302
Dan Williams89a73012011-06-30 19:14:33 -0700303static void sci_controller_unsolicited_frame(struct isci_host *ihost, u32 ent)
Dan Williamscc9203b2011-05-08 17:34:44 -0700304{
305 u32 index;
306 u32 frame_index;
307
Dan Williamscc9203b2011-05-08 17:34:44 -0700308 struct scu_unsolicited_frame_header *frame_header;
Dan Williams85280952011-06-28 15:05:53 -0700309 struct isci_phy *iphy;
Dan Williams78a6f062011-06-30 16:31:37 -0700310 struct isci_remote_device *idev;
Dan Williamscc9203b2011-05-08 17:34:44 -0700311
312 enum sci_status result = SCI_FAILURE;
313
Dan Williams89a73012011-06-30 19:14:33 -0700314 frame_index = SCU_GET_FRAME_INDEX(ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700315
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700316 frame_header = ihost->uf_control.buffers.array[frame_index].header;
317 ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
Dan Williamscc9203b2011-05-08 17:34:44 -0700318
Dan Williams89a73012011-06-30 19:14:33 -0700319 if (SCU_GET_FRAME_ERROR(ent)) {
Dan Williamscc9203b2011-05-08 17:34:44 -0700320 /*
321 * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
322 * / this cause a problem? We expect the phy initialization will
323 * / fail if there is an error in the frame. */
Dan Williams89a73012011-06-30 19:14:33 -0700324 sci_controller_release_frame(ihost, frame_index);
Dan Williamscc9203b2011-05-08 17:34:44 -0700325 return;
326 }
327
328 if (frame_header->is_address_frame) {
Dan Williams89a73012011-06-30 19:14:33 -0700329 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
Dan Williams85280952011-06-28 15:05:53 -0700330 iphy = &ihost->phys[index];
Dan Williams89a73012011-06-30 19:14:33 -0700331 result = sci_phy_frame_handler(iphy, frame_index);
Dan Williamscc9203b2011-05-08 17:34:44 -0700332 } else {
333
Dan Williams89a73012011-06-30 19:14:33 -0700334 index = SCU_GET_COMPLETION_INDEX(ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700335
336 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
337 /*
338 * This is a signature fis or a frame from a direct attached SATA
339 * device that has not yet been created. In either case forwared
340 * the frame to the PE and let it take care of the frame data. */
Dan Williams89a73012011-06-30 19:14:33 -0700341 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
Dan Williams85280952011-06-28 15:05:53 -0700342 iphy = &ihost->phys[index];
Dan Williams89a73012011-06-30 19:14:33 -0700343 result = sci_phy_frame_handler(iphy, frame_index);
Dan Williamscc9203b2011-05-08 17:34:44 -0700344 } else {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700345 if (index < ihost->remote_node_entries)
346 idev = ihost->device_table[index];
Dan Williamscc9203b2011-05-08 17:34:44 -0700347 else
Dan Williams78a6f062011-06-30 16:31:37 -0700348 idev = NULL;
Dan Williamscc9203b2011-05-08 17:34:44 -0700349
Dan Williams78a6f062011-06-30 16:31:37 -0700350 if (idev != NULL)
Dan Williams89a73012011-06-30 19:14:33 -0700351 result = sci_remote_device_frame_handler(idev, frame_index);
Dan Williamscc9203b2011-05-08 17:34:44 -0700352 else
Dan Williams89a73012011-06-30 19:14:33 -0700353 sci_controller_release_frame(ihost, frame_index);
Dan Williamscc9203b2011-05-08 17:34:44 -0700354 }
355 }
356
357 if (result != SCI_SUCCESS) {
358 /*
359 * / @todo Is there any reason to report some additional error message
360 * / when we get this failure notifiction? */
361 }
362}
363
Dan Williams89a73012011-06-30 19:14:33 -0700364static void sci_controller_event_completion(struct isci_host *ihost, u32 ent)
Dan Williamscc9203b2011-05-08 17:34:44 -0700365{
Dan Williams78a6f062011-06-30 16:31:37 -0700366 struct isci_remote_device *idev;
Dan Williams5076a1a2011-06-27 14:57:03 -0700367 struct isci_request *ireq;
Dan Williams85280952011-06-28 15:05:53 -0700368 struct isci_phy *iphy;
Dan Williamscc9203b2011-05-08 17:34:44 -0700369 u32 index;
370
Dan Williams89a73012011-06-30 19:14:33 -0700371 index = SCU_GET_COMPLETION_INDEX(ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700372
Dan Williams89a73012011-06-30 19:14:33 -0700373 switch (scu_get_event_type(ent)) {
Dan Williamscc9203b2011-05-08 17:34:44 -0700374 case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
375 /* / @todo The driver did something wrong and we need to fix the condtion. */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700376 dev_err(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -0700377 "%s: SCIC Controller 0x%p received SMU command error "
378 "0x%x\n",
379 __func__,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700380 ihost,
Dan Williams89a73012011-06-30 19:14:33 -0700381 ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700382 break;
383
384 case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
385 case SCU_EVENT_TYPE_SMU_ERROR:
386 case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
387 /*
388 * / @todo This is a hardware failure and its likely that we want to
389 * / reset the controller. */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700390 dev_err(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -0700391 "%s: SCIC Controller 0x%p received fatal controller "
392 "event 0x%x\n",
393 __func__,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700394 ihost,
Dan Williams89a73012011-06-30 19:14:33 -0700395 ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700396 break;
397
398 case SCU_EVENT_TYPE_TRANSPORT_ERROR:
Dan Williams5076a1a2011-06-27 14:57:03 -0700399 ireq = ihost->reqs[index];
Dan Williams89a73012011-06-30 19:14:33 -0700400 sci_io_request_event_handler(ireq, ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700401 break;
402
403 case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
Dan Williams89a73012011-06-30 19:14:33 -0700404 switch (scu_get_event_specifier(ent)) {
Dan Williamscc9203b2011-05-08 17:34:44 -0700405 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
406 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
Dan Williams5076a1a2011-06-27 14:57:03 -0700407 ireq = ihost->reqs[index];
408 if (ireq != NULL)
Dan Williams89a73012011-06-30 19:14:33 -0700409 sci_io_request_event_handler(ireq, ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700410 else
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700411 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -0700412 "%s: SCIC Controller 0x%p received "
413 "event 0x%x for io request object "
414 "that doesnt exist.\n",
415 __func__,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700416 ihost,
Dan Williams89a73012011-06-30 19:14:33 -0700417 ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700418
419 break;
420
421 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700422 idev = ihost->device_table[index];
Dan Williams78a6f062011-06-30 16:31:37 -0700423 if (idev != NULL)
Dan Williams89a73012011-06-30 19:14:33 -0700424 sci_remote_device_event_handler(idev, ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700425 else
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700426 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -0700427 "%s: SCIC Controller 0x%p received "
428 "event 0x%x for remote device object "
429 "that doesnt exist.\n",
430 __func__,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700431 ihost,
Dan Williams89a73012011-06-30 19:14:33 -0700432 ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700433
434 break;
435 }
436 break;
437
438 case SCU_EVENT_TYPE_BROADCAST_CHANGE:
439 /*
440 * direct the broadcast change event to the phy first and then let
441 * the phy redirect the broadcast change to the port object */
442 case SCU_EVENT_TYPE_ERR_CNT_EVENT:
443 /*
444 * direct error counter event to the phy object since that is where
445 * we get the event notification. This is a type 4 event. */
446 case SCU_EVENT_TYPE_OSSP_EVENT:
Dan Williams89a73012011-06-30 19:14:33 -0700447 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
Dan Williams85280952011-06-28 15:05:53 -0700448 iphy = &ihost->phys[index];
Dan Williams89a73012011-06-30 19:14:33 -0700449 sci_phy_event_handler(iphy, ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700450 break;
451
452 case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
453 case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
454 case SCU_EVENT_TYPE_RNC_OPS_MISC:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700455 if (index < ihost->remote_node_entries) {
456 idev = ihost->device_table[index];
Dan Williamscc9203b2011-05-08 17:34:44 -0700457
Dan Williams78a6f062011-06-30 16:31:37 -0700458 if (idev != NULL)
Dan Williams89a73012011-06-30 19:14:33 -0700459 sci_remote_device_event_handler(idev, ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700460 } else
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700461 dev_err(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -0700462 "%s: SCIC Controller 0x%p received event 0x%x "
463 "for remote device object 0x%0x that doesnt "
464 "exist.\n",
465 __func__,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700466 ihost,
Dan Williams89a73012011-06-30 19:14:33 -0700467 ent,
Dan Williamscc9203b2011-05-08 17:34:44 -0700468 index);
469
470 break;
471
472 default:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700473 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -0700474 "%s: SCIC Controller received unknown event code %x\n",
475 __func__,
Dan Williams89a73012011-06-30 19:14:33 -0700476 ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700477 break;
478 }
479}
480
Dan Williams89a73012011-06-30 19:14:33 -0700481static void sci_controller_process_completions(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700482{
483 u32 completion_count = 0;
Dan Williams89a73012011-06-30 19:14:33 -0700484 u32 ent;
Dan Williamscc9203b2011-05-08 17:34:44 -0700485 u32 get_index;
486 u32 get_cycle;
Dan Williams994a9302011-06-09 16:04:28 -0700487 u32 event_get;
Dan Williamscc9203b2011-05-08 17:34:44 -0700488 u32 event_cycle;
489
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700490 dev_dbg(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -0700491 "%s: completion queue begining get:0x%08x\n",
492 __func__,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700493 ihost->completion_queue_get);
Dan Williamscc9203b2011-05-08 17:34:44 -0700494
495 /* Get the component parts of the completion queue */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700496 get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get);
497 get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get;
Dan Williamscc9203b2011-05-08 17:34:44 -0700498
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700499 event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get);
500 event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get;
Dan Williamscc9203b2011-05-08 17:34:44 -0700501
502 while (
503 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700504 == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])
Dan Williamscc9203b2011-05-08 17:34:44 -0700505 ) {
506 completion_count++;
507
Dan Williams89a73012011-06-30 19:14:33 -0700508 ent = ihost->completion_queue[get_index];
Dan Williams994a9302011-06-09 16:04:28 -0700509
510 /* increment the get pointer and check for rollover to toggle the cycle bit */
511 get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) <<
512 (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT);
513 get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1);
Dan Williamscc9203b2011-05-08 17:34:44 -0700514
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700515 dev_dbg(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -0700516 "%s: completion queue entry:0x%08x\n",
517 __func__,
Dan Williams89a73012011-06-30 19:14:33 -0700518 ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700519
Dan Williams89a73012011-06-30 19:14:33 -0700520 switch (SCU_GET_COMPLETION_TYPE(ent)) {
Dan Williamscc9203b2011-05-08 17:34:44 -0700521 case SCU_COMPLETION_TYPE_TASK:
Dan Williams89a73012011-06-30 19:14:33 -0700522 sci_controller_task_completion(ihost, ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700523 break;
524
525 case SCU_COMPLETION_TYPE_SDMA:
Dan Williams89a73012011-06-30 19:14:33 -0700526 sci_controller_sdma_completion(ihost, ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700527 break;
528
529 case SCU_COMPLETION_TYPE_UFI:
Dan Williams89a73012011-06-30 19:14:33 -0700530 sci_controller_unsolicited_frame(ihost, ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700531 break;
532
533 case SCU_COMPLETION_TYPE_EVENT:
Dan Williams77cd72a2011-07-29 17:17:16 -0700534 sci_controller_event_completion(ihost, ent);
535 break;
536
Dan Williams994a9302011-06-09 16:04:28 -0700537 case SCU_COMPLETION_TYPE_NOTIFY: {
538 event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) <<
539 (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT);
540 event_get = (event_get+1) & (SCU_MAX_EVENTS-1);
541
Dan Williams89a73012011-06-30 19:14:33 -0700542 sci_controller_event_completion(ihost, ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700543 break;
Dan Williams994a9302011-06-09 16:04:28 -0700544 }
Dan Williamscc9203b2011-05-08 17:34:44 -0700545 default:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700546 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -0700547 "%s: SCIC Controller received unknown "
548 "completion type %x\n",
549 __func__,
Dan Williams89a73012011-06-30 19:14:33 -0700550 ent);
Dan Williamscc9203b2011-05-08 17:34:44 -0700551 break;
552 }
553 }
554
555 /* Update the get register if we completed one or more entries */
556 if (completion_count > 0) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700557 ihost->completion_queue_get =
Dan Williamscc9203b2011-05-08 17:34:44 -0700558 SMU_CQGR_GEN_BIT(ENABLE) |
559 SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
560 event_cycle |
Dan Williams994a9302011-06-09 16:04:28 -0700561 SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) |
Dan Williamscc9203b2011-05-08 17:34:44 -0700562 get_cycle |
563 SMU_CQGR_GEN_VAL(POINTER, get_index);
564
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700565 writel(ihost->completion_queue_get,
566 &ihost->smu_registers->completion_queue_get);
Dan Williamscc9203b2011-05-08 17:34:44 -0700567
568 }
569
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700570 dev_dbg(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -0700571 "%s: completion queue ending get:0x%08x\n",
572 __func__,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700573 ihost->completion_queue_get);
Dan Williamscc9203b2011-05-08 17:34:44 -0700574
575}
576
Dan Williams89a73012011-06-30 19:14:33 -0700577static void sci_controller_error_handler(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700578{
579 u32 interrupt_status;
580
581 interrupt_status =
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700582 readl(&ihost->smu_registers->interrupt_status);
Dan Williamscc9203b2011-05-08 17:34:44 -0700583
584 if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
Dan Williams89a73012011-06-30 19:14:33 -0700585 sci_controller_completion_queue_has_entries(ihost)) {
Dan Williamscc9203b2011-05-08 17:34:44 -0700586
Dan Williams89a73012011-06-30 19:14:33 -0700587 sci_controller_process_completions(ihost);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700588 writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status);
Dan Williamscc9203b2011-05-08 17:34:44 -0700589 } else {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700590 dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__,
Dan Williamscc9203b2011-05-08 17:34:44 -0700591 interrupt_status);
592
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700593 sci_change_state(&ihost->sm, SCIC_FAILED);
Dan Williamscc9203b2011-05-08 17:34:44 -0700594
595 return;
596 }
597
598 /* If we dont process any completions I am not sure that we want to do this.
599 * We are in the middle of a hardware fault and should probably be reset.
600 */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700601 writel(0, &ihost->smu_registers->interrupt_mask);
Dan Williamscc9203b2011-05-08 17:34:44 -0700602}
603
Dan Williamsc7ef4032011-02-18 09:25:05 -0800604irqreturn_t isci_intx_isr(int vec, void *data)
Dan Williams6f231dd2011-07-02 22:56:22 -0700605{
Dan Williams6f231dd2011-07-02 22:56:22 -0700606 irqreturn_t ret = IRQ_NONE;
Dan Williams31e824e2011-04-19 12:32:51 -0700607 struct isci_host *ihost = data;
Dan Williams6f231dd2011-07-02 22:56:22 -0700608
Dan Williams89a73012011-06-30 19:14:33 -0700609 if (sci_controller_isr(ihost)) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700610 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
Dan Williams31e824e2011-04-19 12:32:51 -0700611 tasklet_schedule(&ihost->completion_tasklet);
612 ret = IRQ_HANDLED;
Dan Williams89a73012011-06-30 19:14:33 -0700613 } else if (sci_controller_error_isr(ihost)) {
Dan Williams31e824e2011-04-19 12:32:51 -0700614 spin_lock(&ihost->scic_lock);
Dan Williams89a73012011-06-30 19:14:33 -0700615 sci_controller_error_handler(ihost);
Dan Williams31e824e2011-04-19 12:32:51 -0700616 spin_unlock(&ihost->scic_lock);
617 ret = IRQ_HANDLED;
Dan Williams6f231dd2011-07-02 22:56:22 -0700618 }
Dan Williams92f4f0f2011-02-18 09:25:11 -0800619
Dan Williams6f231dd2011-07-02 22:56:22 -0700620 return ret;
621}
622
Dan Williams92f4f0f2011-02-18 09:25:11 -0800623irqreturn_t isci_error_isr(int vec, void *data)
624{
625 struct isci_host *ihost = data;
Dan Williams92f4f0f2011-02-18 09:25:11 -0800626
Dan Williams89a73012011-06-30 19:14:33 -0700627 if (sci_controller_error_isr(ihost))
628 sci_controller_error_handler(ihost);
Dan Williams92f4f0f2011-02-18 09:25:11 -0800629
630 return IRQ_HANDLED;
631}
Dan Williams6f231dd2011-07-02 22:56:22 -0700632
633/**
634 * isci_host_start_complete() - This function is called by the core library,
635 * through the ISCI Module, to indicate controller start status.
636 * @isci_host: This parameter specifies the ISCI host object
637 * @completion_status: This parameter specifies the completion status from the
638 * core library.
639 *
640 */
Dan Williamscc9203b2011-05-08 17:34:44 -0700641static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
Dan Williams6f231dd2011-07-02 22:56:22 -0700642{
Dan Williams0cf89d12011-02-18 09:25:07 -0800643 if (completion_status != SCI_SUCCESS)
644 dev_info(&ihost->pdev->dev,
645 "controller start timed out, continuing...\n");
646 isci_host_change_state(ihost, isci_ready);
647 clear_bit(IHOST_START_PENDING, &ihost->flags);
648 wake_up(&ihost->eventq);
Dan Williams6f231dd2011-07-02 22:56:22 -0700649}
650
Dan Williamsc7ef4032011-02-18 09:25:05 -0800651int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
Dan Williams6f231dd2011-07-02 22:56:22 -0700652{
Dan Williams4393aa42011-03-31 13:10:44 -0700653 struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
Dan Williams6f231dd2011-07-02 22:56:22 -0700654
Edmund Nadolski77950f52011-02-18 09:25:09 -0800655 if (test_bit(IHOST_START_PENDING, &ihost->flags))
Dan Williams6f231dd2011-07-02 22:56:22 -0700656 return 0;
Dan Williams6f231dd2011-07-02 22:56:22 -0700657
Edmund Nadolski77950f52011-02-18 09:25:09 -0800658 /* todo: use sas_flush_discovery once it is upstream */
659 scsi_flush_work(shost);
660
661 scsi_flush_work(shost);
Dan Williams6f231dd2011-07-02 22:56:22 -0700662
Dan Williams0cf89d12011-02-18 09:25:07 -0800663 dev_dbg(&ihost->pdev->dev,
664 "%s: ihost->status = %d, time = %ld\n",
665 __func__, isci_host_get_state(ihost), time);
Dan Williams6f231dd2011-07-02 22:56:22 -0700666
Dan Williams6f231dd2011-07-02 22:56:22 -0700667 return 1;
668
669}
670
Dan Williamscc9203b2011-05-08 17:34:44 -0700671/**
Dan Williams89a73012011-06-30 19:14:33 -0700672 * sci_controller_get_suggested_start_timeout() - This method returns the
673 * suggested sci_controller_start() timeout amount. The user is free to
Dan Williamscc9203b2011-05-08 17:34:44 -0700674 * use any timeout value, but this method provides the suggested minimum
675 * start timeout value. The returned value is based upon empirical
676 * information determined as a result of interoperability testing.
677 * @controller: the handle to the controller object for which to return the
678 * suggested start timeout.
679 *
680 * This method returns the number of milliseconds for the suggested start
681 * operation timeout.
682 */
Dan Williams89a73012011-06-30 19:14:33 -0700683static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700684{
685 /* Validate the user supplied parameters. */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700686 if (!ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700687 return 0;
688
689 /*
690 * The suggested minimum timeout value for a controller start operation:
691 *
692 * Signature FIS Timeout
693 * + Phy Start Timeout
694 * + Number of Phy Spin Up Intervals
695 * ---------------------------------
696 * Number of milliseconds for the controller start operation.
697 *
698 * NOTE: The number of phy spin up intervals will be equivalent
699 * to the number of phys divided by the number phys allowed
700 * per interval - 1 (once OEM parameters are supported).
701 * Currently we assume only 1 phy per interval. */
702
703 return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
704 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
705 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
706}
707
Dan Williams89a73012011-06-30 19:14:33 -0700708static void sci_controller_enable_interrupts(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700709{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700710 BUG_ON(ihost->smu_registers == NULL);
711 writel(0, &ihost->smu_registers->interrupt_mask);
Dan Williamscc9203b2011-05-08 17:34:44 -0700712}
713
Dan Williams89a73012011-06-30 19:14:33 -0700714void sci_controller_disable_interrupts(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700715{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700716 BUG_ON(ihost->smu_registers == NULL);
717 writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
Dan Williamscc9203b2011-05-08 17:34:44 -0700718}
719
Dan Williams89a73012011-06-30 19:14:33 -0700720static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700721{
722 u32 port_task_scheduler_value;
723
724 port_task_scheduler_value =
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700725 readl(&ihost->scu_registers->peg0.ptsg.control);
Dan Williamscc9203b2011-05-08 17:34:44 -0700726 port_task_scheduler_value |=
727 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
728 SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
729 writel(port_task_scheduler_value,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700730 &ihost->scu_registers->peg0.ptsg.control);
Dan Williamscc9203b2011-05-08 17:34:44 -0700731}
732
Dan Williams89a73012011-06-30 19:14:33 -0700733static void sci_controller_assign_task_entries(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700734{
735 u32 task_assignment;
736
737 /*
738 * Assign all the TCs to function 0
739 * TODO: Do we actually need to read this register to write it back?
740 */
741
742 task_assignment =
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700743 readl(&ihost->smu_registers->task_context_assignment[0]);
Dan Williamscc9203b2011-05-08 17:34:44 -0700744
745 task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700746 (SMU_TCA_GEN_VAL(ENDING, ihost->task_context_entries - 1)) |
Dan Williamscc9203b2011-05-08 17:34:44 -0700747 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
748
749 writel(task_assignment,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700750 &ihost->smu_registers->task_context_assignment[0]);
Dan Williamscc9203b2011-05-08 17:34:44 -0700751
752}
753
Dan Williams89a73012011-06-30 19:14:33 -0700754static void sci_controller_initialize_completion_queue(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700755{
756 u32 index;
757 u32 completion_queue_control_value;
758 u32 completion_queue_get_value;
759 u32 completion_queue_put_value;
760
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700761 ihost->completion_queue_get = 0;
Dan Williamscc9203b2011-05-08 17:34:44 -0700762
Dan Williams7c78da32011-06-01 16:00:01 -0700763 completion_queue_control_value =
764 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) |
765 SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1));
Dan Williamscc9203b2011-05-08 17:34:44 -0700766
767 writel(completion_queue_control_value,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700768 &ihost->smu_registers->completion_queue_control);
Dan Williamscc9203b2011-05-08 17:34:44 -0700769
770
771 /* Set the completion queue get pointer and enable the queue */
772 completion_queue_get_value = (
773 (SMU_CQGR_GEN_VAL(POINTER, 0))
774 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
775 | (SMU_CQGR_GEN_BIT(ENABLE))
776 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
777 );
778
779 writel(completion_queue_get_value,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700780 &ihost->smu_registers->completion_queue_get);
Dan Williamscc9203b2011-05-08 17:34:44 -0700781
782 /* Set the completion queue put pointer */
783 completion_queue_put_value = (
784 (SMU_CQPR_GEN_VAL(POINTER, 0))
785 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
786 );
787
788 writel(completion_queue_put_value,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700789 &ihost->smu_registers->completion_queue_put);
Dan Williamscc9203b2011-05-08 17:34:44 -0700790
791 /* Initialize the cycle bit of the completion queue entries */
Dan Williams7c78da32011-06-01 16:00:01 -0700792 for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) {
Dan Williamscc9203b2011-05-08 17:34:44 -0700793 /*
794 * If get.cycle_bit != completion_queue.cycle_bit
795 * its not a valid completion queue entry
796 * so at system start all entries are invalid */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700797 ihost->completion_queue[index] = 0x80000000;
Dan Williamscc9203b2011-05-08 17:34:44 -0700798 }
799}
800
Dan Williams89a73012011-06-30 19:14:33 -0700801static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700802{
803 u32 frame_queue_control_value;
804 u32 frame_queue_get_value;
805 u32 frame_queue_put_value;
806
807 /* Write the queue size */
808 frame_queue_control_value =
Dan Williams7c78da32011-06-01 16:00:01 -0700809 SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
Dan Williamscc9203b2011-05-08 17:34:44 -0700810
811 writel(frame_queue_control_value,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700812 &ihost->scu_registers->sdma.unsolicited_frame_queue_control);
Dan Williamscc9203b2011-05-08 17:34:44 -0700813
814 /* Setup the get pointer for the unsolicited frame queue */
815 frame_queue_get_value = (
816 SCU_UFQGP_GEN_VAL(POINTER, 0)
817 | SCU_UFQGP_GEN_BIT(ENABLE_BIT)
818 );
819
820 writel(frame_queue_get_value,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700821 &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
Dan Williamscc9203b2011-05-08 17:34:44 -0700822 /* Setup the put pointer for the unsolicited frame queue */
823 frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
824 writel(frame_queue_put_value,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700825 &ihost->scu_registers->sdma.unsolicited_frame_put_pointer);
Dan Williamscc9203b2011-05-08 17:34:44 -0700826}
827
Dan Williams89a73012011-06-30 19:14:33 -0700828static void sci_controller_transition_to_ready(struct isci_host *ihost, enum sci_status status)
Dan Williamscc9203b2011-05-08 17:34:44 -0700829{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700830 if (ihost->sm.current_state_id == SCIC_STARTING) {
Dan Williamscc9203b2011-05-08 17:34:44 -0700831 /*
832 * We move into the ready state, because some of the phys/ports
833 * may be up and operational.
834 */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700835 sci_change_state(&ihost->sm, SCIC_READY);
Dan Williamscc9203b2011-05-08 17:34:44 -0700836
837 isci_host_start_complete(ihost, status);
838 }
839}
840
Dan Williams85280952011-06-28 15:05:53 -0700841static bool is_phy_starting(struct isci_phy *iphy)
Adam Gruchala4a33c522011-05-10 23:54:23 +0000842{
Dan Williams89a73012011-06-30 19:14:33 -0700843 enum sci_phy_states state;
Adam Gruchala4a33c522011-05-10 23:54:23 +0000844
Dan Williams85280952011-06-28 15:05:53 -0700845 state = iphy->sm.current_state_id;
Adam Gruchala4a33c522011-05-10 23:54:23 +0000846 switch (state) {
Edmund Nadolskie3013702011-06-02 00:10:43 +0000847 case SCI_PHY_STARTING:
848 case SCI_PHY_SUB_INITIAL:
849 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
850 case SCI_PHY_SUB_AWAIT_IAF_UF:
851 case SCI_PHY_SUB_AWAIT_SAS_POWER:
852 case SCI_PHY_SUB_AWAIT_SATA_POWER:
853 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
854 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
855 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
856 case SCI_PHY_SUB_FINAL:
Adam Gruchala4a33c522011-05-10 23:54:23 +0000857 return true;
858 default:
859 return false;
860 }
861}
862
Dan Williamscc9203b2011-05-08 17:34:44 -0700863/**
Dan Williams89a73012011-06-30 19:14:33 -0700864 * sci_controller_start_next_phy - start phy
Dan Williamscc9203b2011-05-08 17:34:44 -0700865 * @scic: controller
866 *
867 * If all the phys have been started, then attempt to transition the
868 * controller to the READY state and inform the user
Dan Williams89a73012011-06-30 19:14:33 -0700869 * (sci_cb_controller_start_complete()).
Dan Williamscc9203b2011-05-08 17:34:44 -0700870 */
Dan Williams89a73012011-06-30 19:14:33 -0700871static enum sci_status sci_controller_start_next_phy(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -0700872{
Dan Williams89a73012011-06-30 19:14:33 -0700873 struct sci_oem_params *oem = &ihost->oem_parameters;
Dan Williams85280952011-06-28 15:05:53 -0700874 struct isci_phy *iphy;
Dan Williamscc9203b2011-05-08 17:34:44 -0700875 enum sci_status status;
876
877 status = SCI_SUCCESS;
878
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700879 if (ihost->phy_startup_timer_pending)
Dan Williamscc9203b2011-05-08 17:34:44 -0700880 return status;
881
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700882 if (ihost->next_phy_to_start >= SCI_MAX_PHYS) {
Dan Williamscc9203b2011-05-08 17:34:44 -0700883 bool is_controller_start_complete = true;
884 u32 state;
885 u8 index;
886
887 for (index = 0; index < SCI_MAX_PHYS; index++) {
Dan Williams85280952011-06-28 15:05:53 -0700888 iphy = &ihost->phys[index];
889 state = iphy->sm.current_state_id;
Dan Williamscc9203b2011-05-08 17:34:44 -0700890
Dan Williams85280952011-06-28 15:05:53 -0700891 if (!phy_get_non_dummy_port(iphy))
Dan Williamscc9203b2011-05-08 17:34:44 -0700892 continue;
893
894 /* The controller start operation is complete iff:
895 * - all links have been given an opportunity to start
896 * - have no indication of a connected device
897 * - have an indication of a connected device and it has
898 * finished the link training process.
899 */
Dan Williams85280952011-06-28 15:05:53 -0700900 if ((iphy->is_in_link_training == false && state == SCI_PHY_INITIAL) ||
901 (iphy->is_in_link_training == false && state == SCI_PHY_STOPPED) ||
Marcin Tomczakbe778342012-01-04 01:33:31 -0800902 (iphy->is_in_link_training == true && is_phy_starting(iphy)) ||
903 (ihost->port_agent.phy_ready_mask != ihost->port_agent.phy_configured_mask)) {
Dan Williamscc9203b2011-05-08 17:34:44 -0700904 is_controller_start_complete = false;
905 break;
906 }
907 }
908
909 /*
910 * The controller has successfully finished the start process.
911 * Inform the SCI Core user and transition to the READY state. */
912 if (is_controller_start_complete == true) {
Dan Williams89a73012011-06-30 19:14:33 -0700913 sci_controller_transition_to_ready(ihost, SCI_SUCCESS);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700914 sci_del_timer(&ihost->phy_timer);
915 ihost->phy_startup_timer_pending = false;
Dan Williamscc9203b2011-05-08 17:34:44 -0700916 }
917 } else {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700918 iphy = &ihost->phys[ihost->next_phy_to_start];
Dan Williamscc9203b2011-05-08 17:34:44 -0700919
920 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
Dan Williams85280952011-06-28 15:05:53 -0700921 if (phy_get_non_dummy_port(iphy) == NULL) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700922 ihost->next_phy_to_start++;
Dan Williamscc9203b2011-05-08 17:34:44 -0700923
924 /* Caution recursion ahead be forwarned
925 *
926 * The PHY was never added to a PORT in MPC mode
927 * so start the next phy in sequence This phy
928 * will never go link up and will not draw power
929 * the OEM parameters either configured the phy
930 * incorrectly for the PORT or it was never
931 * assigned to a PORT
932 */
Dan Williams89a73012011-06-30 19:14:33 -0700933 return sci_controller_start_next_phy(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -0700934 }
935 }
936
Dan Williams89a73012011-06-30 19:14:33 -0700937 status = sci_phy_start(iphy);
Dan Williamscc9203b2011-05-08 17:34:44 -0700938
939 if (status == SCI_SUCCESS) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700940 sci_mod_timer(&ihost->phy_timer,
Edmund Nadolskibb3dbdf2011-05-19 20:26:02 -0700941 SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700942 ihost->phy_startup_timer_pending = true;
Dan Williamscc9203b2011-05-08 17:34:44 -0700943 } else {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700944 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -0700945 "%s: Controller stop operation failed "
946 "to stop phy %d because of status "
947 "%d.\n",
948 __func__,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700949 ihost->phys[ihost->next_phy_to_start].phy_index,
Dan Williamscc9203b2011-05-08 17:34:44 -0700950 status);
951 }
952
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700953 ihost->next_phy_to_start++;
Dan Williamscc9203b2011-05-08 17:34:44 -0700954 }
955
956 return status;
957}
958
Edmund Nadolskibb3dbdf2011-05-19 20:26:02 -0700959static void phy_startup_timeout(unsigned long data)
Dan Williamscc9203b2011-05-08 17:34:44 -0700960{
Edmund Nadolskibb3dbdf2011-05-19 20:26:02 -0700961 struct sci_timer *tmr = (struct sci_timer *)data;
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700962 struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer);
Edmund Nadolskibb3dbdf2011-05-19 20:26:02 -0700963 unsigned long flags;
Dan Williamscc9203b2011-05-08 17:34:44 -0700964 enum sci_status status;
965
Edmund Nadolskibb3dbdf2011-05-19 20:26:02 -0700966 spin_lock_irqsave(&ihost->scic_lock, flags);
967
968 if (tmr->cancel)
969 goto done;
970
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700971 ihost->phy_startup_timer_pending = false;
Edmund Nadolskibb3dbdf2011-05-19 20:26:02 -0700972
973 do {
Dan Williams89a73012011-06-30 19:14:33 -0700974 status = sci_controller_start_next_phy(ihost);
Edmund Nadolskibb3dbdf2011-05-19 20:26:02 -0700975 } while (status != SCI_SUCCESS);
976
977done:
978 spin_unlock_irqrestore(&ihost->scic_lock, flags);
Dan Williamscc9203b2011-05-08 17:34:44 -0700979}
980
Dan Williamsac668c62011-06-07 18:50:55 -0700981static u16 isci_tci_active(struct isci_host *ihost)
982{
983 return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
984}
985
Dan Williams89a73012011-06-30 19:14:33 -0700986static enum sci_status sci_controller_start(struct isci_host *ihost,
Dan Williamscc9203b2011-05-08 17:34:44 -0700987 u32 timeout)
988{
Dan Williamscc9203b2011-05-08 17:34:44 -0700989 enum sci_status result;
990 u16 index;
991
Dan Williamsd9dcb4b2011-06-30 17:38:32 -0700992 if (ihost->sm.current_state_id != SCIC_INITIALIZED) {
993 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -0700994 "SCIC Controller start operation requested in "
995 "invalid state\n");
996 return SCI_FAILURE_INVALID_STATE;
997 }
998
999 /* Build the TCi free pool */
Dan Williamsac668c62011-06-07 18:50:55 -07001000 BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8);
1001 ihost->tci_head = 0;
1002 ihost->tci_tail = 0;
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001003 for (index = 0; index < ihost->task_context_entries; index++)
Dan Williamsac668c62011-06-07 18:50:55 -07001004 isci_tci_free(ihost, index);
Dan Williamscc9203b2011-05-08 17:34:44 -07001005
1006 /* Build the RNi free pool */
Dan Williams89a73012011-06-30 19:14:33 -07001007 sci_remote_node_table_initialize(&ihost->available_remote_nodes,
1008 ihost->remote_node_entries);
Dan Williamscc9203b2011-05-08 17:34:44 -07001009
1010 /*
1011 * Before anything else lets make sure we will not be
1012 * interrupted by the hardware.
1013 */
Dan Williams89a73012011-06-30 19:14:33 -07001014 sci_controller_disable_interrupts(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07001015
1016 /* Enable the port task scheduler */
Dan Williams89a73012011-06-30 19:14:33 -07001017 sci_controller_enable_port_task_scheduler(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07001018
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001019 /* Assign all the task entries to ihost physical function */
Dan Williams89a73012011-06-30 19:14:33 -07001020 sci_controller_assign_task_entries(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07001021
1022 /* Now initialize the completion queue */
Dan Williams89a73012011-06-30 19:14:33 -07001023 sci_controller_initialize_completion_queue(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07001024
1025 /* Initialize the unsolicited frame queue for use */
Dan Williams89a73012011-06-30 19:14:33 -07001026 sci_controller_initialize_unsolicited_frame_queue(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07001027
1028 /* Start all of the ports on this controller */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001029 for (index = 0; index < ihost->logical_port_entries; index++) {
Dan Williamsffe191c2011-06-29 13:09:25 -07001030 struct isci_port *iport = &ihost->ports[index];
Dan Williamscc9203b2011-05-08 17:34:44 -07001031
Dan Williams89a73012011-06-30 19:14:33 -07001032 result = sci_port_start(iport);
Dan Williamscc9203b2011-05-08 17:34:44 -07001033 if (result)
1034 return result;
1035 }
1036
Dan Williams89a73012011-06-30 19:14:33 -07001037 sci_controller_start_next_phy(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07001038
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001039 sci_mod_timer(&ihost->timer, timeout);
Dan Williamscc9203b2011-05-08 17:34:44 -07001040
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001041 sci_change_state(&ihost->sm, SCIC_STARTING);
Dan Williamscc9203b2011-05-08 17:34:44 -07001042
1043 return SCI_SUCCESS;
1044}
1045
Dan Williams6f231dd2011-07-02 22:56:22 -07001046void isci_host_scan_start(struct Scsi_Host *shost)
1047{
Dan Williams4393aa42011-03-31 13:10:44 -07001048 struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
Dan Williams89a73012011-06-30 19:14:33 -07001049 unsigned long tmo = sci_controller_get_suggested_start_timeout(ihost);
Dan Williams6f231dd2011-07-02 22:56:22 -07001050
Dan Williams0cf89d12011-02-18 09:25:07 -08001051 set_bit(IHOST_START_PENDING, &ihost->flags);
Edmund Nadolski77950f52011-02-18 09:25:09 -08001052
1053 spin_lock_irq(&ihost->scic_lock);
Dan Williams89a73012011-06-30 19:14:33 -07001054 sci_controller_start(ihost, tmo);
1055 sci_controller_enable_interrupts(ihost);
Edmund Nadolski77950f52011-02-18 09:25:09 -08001056 spin_unlock_irq(&ihost->scic_lock);
Dan Williams6f231dd2011-07-02 22:56:22 -07001057}
1058
Dan Williamscc9203b2011-05-08 17:34:44 -07001059static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status)
Dan Williams6f231dd2011-07-02 22:56:22 -07001060{
Dan Williams0cf89d12011-02-18 09:25:07 -08001061 isci_host_change_state(ihost, isci_stopped);
Dan Williams89a73012011-06-30 19:14:33 -07001062 sci_controller_disable_interrupts(ihost);
Dan Williams0cf89d12011-02-18 09:25:07 -08001063 clear_bit(IHOST_STOP_PENDING, &ihost->flags);
1064 wake_up(&ihost->eventq);
Dan Williams6f231dd2011-07-02 22:56:22 -07001065}
1066
Dan Williams89a73012011-06-30 19:14:33 -07001067static void sci_controller_completion_handler(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07001068{
1069 /* Empty out the completion queue */
Dan Williams89a73012011-06-30 19:14:33 -07001070 if (sci_controller_completion_queue_has_entries(ihost))
1071 sci_controller_process_completions(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07001072
1073 /* Clear the interrupt and enable all interrupts again */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001074 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
Dan Williamscc9203b2011-05-08 17:34:44 -07001075 /* Could we write the value of SMU_ISR_COMPLETION? */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001076 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
1077 writel(0, &ihost->smu_registers->interrupt_mask);
Dan Williamscc9203b2011-05-08 17:34:44 -07001078}
1079
Dan Williams6f231dd2011-07-02 22:56:22 -07001080/**
1081 * isci_host_completion_routine() - This function is the delayed service
1082 * routine that calls the sci core library's completion handler. It's
1083 * scheduled as a tasklet from the interrupt service routine when interrupts
1084 * in use, or set as the timeout function in polled mode.
1085 * @data: This parameter specifies the ISCI host object
1086 *
1087 */
1088static void isci_host_completion_routine(unsigned long data)
1089{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001090 struct isci_host *ihost = (struct isci_host *)data;
Jeff Skirvin11b00c12011-03-04 14:06:40 -08001091 struct list_head completed_request_list;
1092 struct list_head errored_request_list;
1093 struct list_head *current_position;
1094 struct list_head *next_position;
Dan Williams6f231dd2011-07-02 22:56:22 -07001095 struct isci_request *request;
1096 struct isci_request *next_request;
Jeff Skirvin11b00c12011-03-04 14:06:40 -08001097 struct sas_task *task;
Dan Williams9b4be522011-07-29 17:17:10 -07001098 u16 active;
Dan Williams6f231dd2011-07-02 22:56:22 -07001099
1100 INIT_LIST_HEAD(&completed_request_list);
Jeff Skirvin11b00c12011-03-04 14:06:40 -08001101 INIT_LIST_HEAD(&errored_request_list);
Dan Williams6f231dd2011-07-02 22:56:22 -07001102
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001103 spin_lock_irq(&ihost->scic_lock);
Dan Williams6f231dd2011-07-02 22:56:22 -07001104
Dan Williams89a73012011-06-30 19:14:33 -07001105 sci_controller_completion_handler(ihost);
Dan Williamsc7ef4032011-02-18 09:25:05 -08001106
Dan Williams6f231dd2011-07-02 22:56:22 -07001107 /* Take the lists of completed I/Os from the host. */
Jeff Skirvin11b00c12011-03-04 14:06:40 -08001108
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001109 list_splice_init(&ihost->requests_to_complete,
Dan Williams6f231dd2011-07-02 22:56:22 -07001110 &completed_request_list);
1111
Jeff Skirvin11b00c12011-03-04 14:06:40 -08001112 /* Take the list of errored I/Os from the host. */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001113 list_splice_init(&ihost->requests_to_errorback,
Jeff Skirvin11b00c12011-03-04 14:06:40 -08001114 &errored_request_list);
Dan Williams6f231dd2011-07-02 22:56:22 -07001115
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001116 spin_unlock_irq(&ihost->scic_lock);
Dan Williams6f231dd2011-07-02 22:56:22 -07001117
1118 /* Process any completions in the lists. */
1119 list_for_each_safe(current_position, next_position,
1120 &completed_request_list) {
1121
1122 request = list_entry(current_position, struct isci_request,
1123 completed_node);
1124 task = isci_request_access_task(request);
1125
1126 /* Normal notification (task_done) */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001127 dev_dbg(&ihost->pdev->dev,
Dan Williams6f231dd2011-07-02 22:56:22 -07001128 "%s: Normal - request/task = %p/%p\n",
1129 __func__,
1130 request,
1131 task);
1132
Jeff Skirvin11b00c12011-03-04 14:06:40 -08001133 /* Return the task to libsas */
1134 if (task != NULL) {
Dan Williams6f231dd2011-07-02 22:56:22 -07001135
Jeff Skirvin11b00c12011-03-04 14:06:40 -08001136 task->lldd_task = NULL;
1137 if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1138
1139 /* If the task is already in the abort path,
1140 * the task_done callback cannot be called.
1141 */
1142 task->task_done(task);
1143 }
1144 }
Dan Williams312e0c22011-06-28 13:47:09 -07001145
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001146 spin_lock_irq(&ihost->scic_lock);
1147 isci_free_tag(ihost, request->io_tag);
1148 spin_unlock_irq(&ihost->scic_lock);
Dan Williams6f231dd2011-07-02 22:56:22 -07001149 }
Jeff Skirvin11b00c12011-03-04 14:06:40 -08001150 list_for_each_entry_safe(request, next_request, &errored_request_list,
Dan Williams6f231dd2011-07-02 22:56:22 -07001151 completed_node) {
1152
1153 task = isci_request_access_task(request);
1154
1155 /* Use sas_task_abort */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001156 dev_warn(&ihost->pdev->dev,
Dan Williams6f231dd2011-07-02 22:56:22 -07001157 "%s: Error - request/task = %p/%p\n",
1158 __func__,
1159 request,
1160 task);
1161
Jeff Skirvin11b00c12011-03-04 14:06:40 -08001162 if (task != NULL) {
1163
1164 /* Put the task into the abort path if it's not there
1165 * already.
1166 */
1167 if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED))
1168 sas_task_abort(task);
1169
1170 } else {
1171 /* This is a case where the request has completed with a
1172 * status such that it needed further target servicing,
1173 * but the sas_task reference has already been removed
1174 * from the request. Since it was errored, it was not
1175 * being aborted, so there is nothing to do except free
1176 * it.
1177 */
1178
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001179 spin_lock_irq(&ihost->scic_lock);
Jeff Skirvin11b00c12011-03-04 14:06:40 -08001180 /* Remove the request from the remote device's list
1181 * of pending requests.
1182 */
1183 list_del_init(&request->dev_node);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001184 isci_free_tag(ihost, request->io_tag);
1185 spin_unlock_irq(&ihost->scic_lock);
Jeff Skirvin11b00c12011-03-04 14:06:40 -08001186 }
Dan Williams6f231dd2011-07-02 22:56:22 -07001187 }
1188
Dan Williams9b4be522011-07-29 17:17:10 -07001189 /* the coalesence timeout doubles at each encoding step, so
1190 * update it based on the ilog2 value of the outstanding requests
1191 */
1192 active = isci_tci_active(ihost);
1193 writel(SMU_ICC_GEN_VAL(NUMBER, active) |
1194 SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)),
1195 &ihost->smu_registers->interrupt_coalesce_control);
Dan Williams6f231dd2011-07-02 22:56:22 -07001196}
1197
Dan Williamscc9203b2011-05-08 17:34:44 -07001198/**
Dan Williams89a73012011-06-30 19:14:33 -07001199 * sci_controller_stop() - This method will stop an individual controller
Dan Williamscc9203b2011-05-08 17:34:44 -07001200 * object.This method will invoke the associated user callback upon
1201 * completion. The completion callback is called when the following
1202 * conditions are met: -# the method return status is SCI_SUCCESS. -# the
1203 * controller has been quiesced. This method will ensure that all IO
1204 * requests are quiesced, phys are stopped, and all additional operation by
1205 * the hardware is halted.
1206 * @controller: the handle to the controller object to stop.
1207 * @timeout: This parameter specifies the number of milliseconds in which the
1208 * stop operation should complete.
1209 *
1210 * The controller must be in the STARTED or STOPPED state. Indicate if the
1211 * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
1212 * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
1213 * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1214 * controller is not either in the STARTED or STOPPED states.
1215 */
Dan Williams89a73012011-06-30 19:14:33 -07001216static enum sci_status sci_controller_stop(struct isci_host *ihost, u32 timeout)
Dan Williamscc9203b2011-05-08 17:34:44 -07001217{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001218 if (ihost->sm.current_state_id != SCIC_READY) {
1219 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -07001220 "SCIC Controller stop operation requested in "
1221 "invalid state\n");
1222 return SCI_FAILURE_INVALID_STATE;
1223 }
1224
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001225 sci_mod_timer(&ihost->timer, timeout);
1226 sci_change_state(&ihost->sm, SCIC_STOPPING);
Dan Williamscc9203b2011-05-08 17:34:44 -07001227 return SCI_SUCCESS;
1228}
1229
1230/**
Dan Williams89a73012011-06-30 19:14:33 -07001231 * sci_controller_reset() - This method will reset the supplied core
Dan Williamscc9203b2011-05-08 17:34:44 -07001232 * controller regardless of the state of said controller. This operation is
1233 * considered destructive. In other words, all current operations are wiped
1234 * out. No IO completions for outstanding devices occur. Outstanding IO
1235 * requests are not aborted or completed at the actual remote device.
1236 * @controller: the handle to the controller object to reset.
1237 *
1238 * Indicate if the controller reset method succeeded or failed in some way.
1239 * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1240 * the controller reset operation is unable to complete.
1241 */
Dan Williams89a73012011-06-30 19:14:33 -07001242static enum sci_status sci_controller_reset(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07001243{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001244 switch (ihost->sm.current_state_id) {
Edmund Nadolskie3013702011-06-02 00:10:43 +00001245 case SCIC_RESET:
1246 case SCIC_READY:
1247 case SCIC_STOPPED:
1248 case SCIC_FAILED:
Dan Williamscc9203b2011-05-08 17:34:44 -07001249 /*
1250 * The reset operation is not a graceful cleanup, just
1251 * perform the state transition.
1252 */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001253 sci_change_state(&ihost->sm, SCIC_RESETTING);
Dan Williamscc9203b2011-05-08 17:34:44 -07001254 return SCI_SUCCESS;
1255 default:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001256 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -07001257 "SCIC Controller reset operation requested in "
1258 "invalid state\n");
1259 return SCI_FAILURE_INVALID_STATE;
1260 }
1261}
1262
Dan Williams0cf89d12011-02-18 09:25:07 -08001263void isci_host_deinit(struct isci_host *ihost)
Dan Williams6f231dd2011-07-02 22:56:22 -07001264{
1265 int i;
1266
Dan Williamsad4f4c12011-09-01 21:18:31 -07001267 /* disable output data selects */
1268 for (i = 0; i < isci_gpio_count(ihost); i++)
1269 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
1270
Dan Williams0cf89d12011-02-18 09:25:07 -08001271 isci_host_change_state(ihost, isci_stopping);
Dan Williams6f231dd2011-07-02 22:56:22 -07001272 for (i = 0; i < SCI_MAX_PORTS; i++) {
Dan Williamse5313812011-05-07 10:11:43 -07001273 struct isci_port *iport = &ihost->ports[i];
Dan Williams0cf89d12011-02-18 09:25:07 -08001274 struct isci_remote_device *idev, *d;
1275
Dan Williamse5313812011-05-07 10:11:43 -07001276 list_for_each_entry_safe(idev, d, &iport->remote_dev_list, node) {
Dan Williams209fae12011-06-13 17:39:44 -07001277 if (test_bit(IDEV_ALLOCATED, &idev->flags))
1278 isci_remote_device_stop(ihost, idev);
Dan Williams6f231dd2011-07-02 22:56:22 -07001279 }
1280 }
1281
Dan Williams0cf89d12011-02-18 09:25:07 -08001282 set_bit(IHOST_STOP_PENDING, &ihost->flags);
Dan Williams7c40a802011-03-02 11:49:26 -08001283
1284 spin_lock_irq(&ihost->scic_lock);
Dan Williams89a73012011-06-30 19:14:33 -07001285 sci_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT);
Dan Williams7c40a802011-03-02 11:49:26 -08001286 spin_unlock_irq(&ihost->scic_lock);
1287
Dan Williams0cf89d12011-02-18 09:25:07 -08001288 wait_for_stop(ihost);
Dan Williamsad4f4c12011-09-01 21:18:31 -07001289
1290 /* disable sgpio: where the above wait should give time for the
1291 * enclosure to sample the gpios going inactive
1292 */
1293 writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
1294
Dan Williams89a73012011-06-30 19:14:33 -07001295 sci_controller_reset(ihost);
Edmund Nadolski5553ba22011-05-19 11:59:10 +00001296
1297 /* Cancel any/all outstanding port timers */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001298 for (i = 0; i < ihost->logical_port_entries; i++) {
Dan Williamsffe191c2011-06-29 13:09:25 -07001299 struct isci_port *iport = &ihost->ports[i];
1300 del_timer_sync(&iport->timer.timer);
Edmund Nadolski5553ba22011-05-19 11:59:10 +00001301 }
1302
Edmund Nadolskia628d472011-05-19 11:59:36 +00001303 /* Cancel any/all outstanding phy timers */
1304 for (i = 0; i < SCI_MAX_PHYS; i++) {
Dan Williams85280952011-06-28 15:05:53 -07001305 struct isci_phy *iphy = &ihost->phys[i];
1306 del_timer_sync(&iphy->sata_timer.timer);
Edmund Nadolskia628d472011-05-19 11:59:36 +00001307 }
1308
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001309 del_timer_sync(&ihost->port_agent.timer.timer);
Edmund Nadolskiac0eeb42011-05-19 20:00:51 -07001310
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001311 del_timer_sync(&ihost->power_control.timer.timer);
Edmund Nadolski04736612011-05-19 20:17:47 -07001312
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001313 del_timer_sync(&ihost->timer.timer);
Edmund Nadolski6cb58532011-05-19 11:59:56 +00001314
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001315 del_timer_sync(&ihost->phy_timer.timer);
Dan Williams6f231dd2011-07-02 22:56:22 -07001316}
1317
Dan Williams6f231dd2011-07-02 22:56:22 -07001318static void __iomem *scu_base(struct isci_host *isci_host)
1319{
1320 struct pci_dev *pdev = isci_host->pdev;
1321 int id = isci_host->id;
1322
1323 return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
1324}
1325
1326static void __iomem *smu_base(struct isci_host *isci_host)
1327{
1328 struct pci_dev *pdev = isci_host->pdev;
1329 int id = isci_host->id;
1330
1331 return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
1332}
1333
Dan Williams89a73012011-06-30 19:14:33 -07001334static void isci_user_parameters_get(struct sci_user_parameters *u)
Dave Jiangb5f18a22011-03-16 14:57:23 -07001335{
Dave Jiangb5f18a22011-03-16 14:57:23 -07001336 int i;
1337
1338 for (i = 0; i < SCI_MAX_PHYS; i++) {
1339 struct sci_phy_user_params *u_phy = &u->phys[i];
1340
1341 u_phy->max_speed_generation = phy_gen;
1342
1343 /* we are not exporting these for now */
1344 u_phy->align_insertion_frequency = 0x7f;
1345 u_phy->in_connection_align_insertion_frequency = 0xff;
1346 u_phy->notify_enable_spin_up_insertion_frequency = 0x33;
1347 }
1348
1349 u->stp_inactivity_timeout = stp_inactive_to;
1350 u->ssp_inactivity_timeout = ssp_inactive_to;
1351 u->stp_max_occupancy_timeout = stp_max_occ_to;
1352 u->ssp_max_occupancy_timeout = ssp_max_occ_to;
1353 u->no_outbound_task_timeout = no_outbound_task_to;
Andrzej Jakowski7000f7c2011-10-27 15:05:42 -07001354 u->max_concurr_spinup = max_concurr_spinup;
Dave Jiangb5f18a22011-03-16 14:57:23 -07001355}
1356
Dan Williams89a73012011-06-30 19:14:33 -07001357static void sci_controller_initial_state_enter(struct sci_base_state_machine *sm)
Dan Williamscc9203b2011-05-08 17:34:44 -07001358{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001359 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
Dan Williamscc9203b2011-05-08 17:34:44 -07001360
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001361 sci_change_state(&ihost->sm, SCIC_RESET);
Dan Williamscc9203b2011-05-08 17:34:44 -07001362}
1363
Dan Williams89a73012011-06-30 19:14:33 -07001364static inline void sci_controller_starting_state_exit(struct sci_base_state_machine *sm)
Dan Williamscc9203b2011-05-08 17:34:44 -07001365{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001366 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
Dan Williamscc9203b2011-05-08 17:34:44 -07001367
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001368 sci_del_timer(&ihost->timer);
Dan Williamscc9203b2011-05-08 17:34:44 -07001369}
1370
1371#define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
1372#define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
1373#define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000
1374#define INTERRUPT_COALESCE_NUMBER_MAX 256
1375#define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7
1376#define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28
1377
1378/**
Dan Williams89a73012011-06-30 19:14:33 -07001379 * sci_controller_set_interrupt_coalescence() - This method allows the user to
Dan Williamscc9203b2011-05-08 17:34:44 -07001380 * configure the interrupt coalescence.
1381 * @controller: This parameter represents the handle to the controller object
1382 * for which its interrupt coalesce register is overridden.
1383 * @coalesce_number: Used to control the number of entries in the Completion
1384 * Queue before an interrupt is generated. If the number of entries exceed
1385 * this number, an interrupt will be generated. The valid range of the input
1386 * is [0, 256]. A setting of 0 results in coalescing being disabled.
1387 * @coalesce_timeout: Timeout value in microseconds. The valid range of the
1388 * input is [0, 2700000] . A setting of 0 is allowed and results in no
1389 * interrupt coalescing timeout.
1390 *
1391 * Indicate if the user successfully set the interrupt coalesce parameters.
1392 * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1393 * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1394 */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001395static enum sci_status
Dan Williams89a73012011-06-30 19:14:33 -07001396sci_controller_set_interrupt_coalescence(struct isci_host *ihost,
1397 u32 coalesce_number,
1398 u32 coalesce_timeout)
Dan Williamscc9203b2011-05-08 17:34:44 -07001399{
1400 u8 timeout_encode = 0;
1401 u32 min = 0;
1402 u32 max = 0;
1403
1404 /* Check if the input parameters fall in the range. */
1405 if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
1406 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1407
1408 /*
1409 * Defined encoding for interrupt coalescing timeout:
1410 * Value Min Max Units
1411 * ----- --- --- -----
1412 * 0 - - Disabled
1413 * 1 13.3 20.0 ns
1414 * 2 26.7 40.0
1415 * 3 53.3 80.0
1416 * 4 106.7 160.0
1417 * 5 213.3 320.0
1418 * 6 426.7 640.0
1419 * 7 853.3 1280.0
1420 * 8 1.7 2.6 us
1421 * 9 3.4 5.1
1422 * 10 6.8 10.2
1423 * 11 13.7 20.5
1424 * 12 27.3 41.0
1425 * 13 54.6 81.9
1426 * 14 109.2 163.8
1427 * 15 218.5 327.7
1428 * 16 436.9 655.4
1429 * 17 873.8 1310.7
1430 * 18 1.7 2.6 ms
1431 * 19 3.5 5.2
1432 * 20 7.0 10.5
1433 * 21 14.0 21.0
1434 * 22 28.0 41.9
1435 * 23 55.9 83.9
1436 * 24 111.8 167.8
1437 * 25 223.7 335.5
1438 * 26 447.4 671.1
1439 * 27 894.8 1342.2
1440 * 28 1.8 2.7 s
1441 * Others Undefined */
1442
1443 /*
1444 * Use the table above to decide the encode of interrupt coalescing timeout
1445 * value for register writing. */
1446 if (coalesce_timeout == 0)
1447 timeout_encode = 0;
1448 else{
1449 /* make the timeout value in unit of (10 ns). */
1450 coalesce_timeout = coalesce_timeout * 100;
1451 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
1452 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
1453
1454 /* get the encode of timeout for register writing. */
1455 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
1456 timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
1457 timeout_encode++) {
1458 if (min <= coalesce_timeout && max > coalesce_timeout)
1459 break;
1460 else if (coalesce_timeout >= max && coalesce_timeout < min * 2
1461 && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
1462 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
1463 break;
1464 else{
1465 timeout_encode++;
1466 break;
1467 }
1468 } else {
1469 max = max * 2;
1470 min = min * 2;
1471 }
1472 }
1473
1474 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
1475 /* the value is out of range. */
1476 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1477 }
1478
1479 writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
1480 SMU_ICC_GEN_VAL(TIMER, timeout_encode),
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001481 &ihost->smu_registers->interrupt_coalesce_control);
Dan Williamscc9203b2011-05-08 17:34:44 -07001482
1483
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001484 ihost->interrupt_coalesce_number = (u16)coalesce_number;
1485 ihost->interrupt_coalesce_timeout = coalesce_timeout / 100;
Dan Williamscc9203b2011-05-08 17:34:44 -07001486
1487 return SCI_SUCCESS;
1488}
1489
1490
Dan Williams89a73012011-06-30 19:14:33 -07001491static void sci_controller_ready_state_enter(struct sci_base_state_machine *sm)
Dan Williamscc9203b2011-05-08 17:34:44 -07001492{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001493 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
Dan Williamscc9203b2011-05-08 17:34:44 -07001494
1495 /* set the default interrupt coalescence number and timeout value. */
Dan Williams9b4be522011-07-29 17:17:10 -07001496 sci_controller_set_interrupt_coalescence(ihost, 0, 0);
Dan Williamscc9203b2011-05-08 17:34:44 -07001497}
1498
Dan Williams89a73012011-06-30 19:14:33 -07001499static void sci_controller_ready_state_exit(struct sci_base_state_machine *sm)
Dan Williamscc9203b2011-05-08 17:34:44 -07001500{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001501 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
Dan Williamscc9203b2011-05-08 17:34:44 -07001502
1503 /* disable interrupt coalescence. */
Dan Williams89a73012011-06-30 19:14:33 -07001504 sci_controller_set_interrupt_coalescence(ihost, 0, 0);
Dan Williamscc9203b2011-05-08 17:34:44 -07001505}
1506
Dan Williams89a73012011-06-30 19:14:33 -07001507static enum sci_status sci_controller_stop_phys(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07001508{
1509 u32 index;
1510 enum sci_status status;
1511 enum sci_status phy_status;
Dan Williamscc9203b2011-05-08 17:34:44 -07001512
1513 status = SCI_SUCCESS;
1514
1515 for (index = 0; index < SCI_MAX_PHYS; index++) {
Dan Williams89a73012011-06-30 19:14:33 -07001516 phy_status = sci_phy_stop(&ihost->phys[index]);
Dan Williamscc9203b2011-05-08 17:34:44 -07001517
1518 if (phy_status != SCI_SUCCESS &&
1519 phy_status != SCI_FAILURE_INVALID_STATE) {
1520 status = SCI_FAILURE;
1521
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001522 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -07001523 "%s: Controller stop operation failed to stop "
1524 "phy %d because of status %d.\n",
1525 __func__,
Dan Williams85280952011-06-28 15:05:53 -07001526 ihost->phys[index].phy_index, phy_status);
Dan Williamscc9203b2011-05-08 17:34:44 -07001527 }
1528 }
1529
1530 return status;
1531}
1532
Dan Williams89a73012011-06-30 19:14:33 -07001533static enum sci_status sci_controller_stop_ports(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07001534{
1535 u32 index;
1536 enum sci_status port_status;
1537 enum sci_status status = SCI_SUCCESS;
Dan Williamscc9203b2011-05-08 17:34:44 -07001538
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001539 for (index = 0; index < ihost->logical_port_entries; index++) {
Dan Williamsffe191c2011-06-29 13:09:25 -07001540 struct isci_port *iport = &ihost->ports[index];
Dan Williamscc9203b2011-05-08 17:34:44 -07001541
Dan Williams89a73012011-06-30 19:14:33 -07001542 port_status = sci_port_stop(iport);
Dan Williamscc9203b2011-05-08 17:34:44 -07001543
1544 if ((port_status != SCI_SUCCESS) &&
1545 (port_status != SCI_FAILURE_INVALID_STATE)) {
1546 status = SCI_FAILURE;
1547
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001548 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -07001549 "%s: Controller stop operation failed to "
1550 "stop port %d because of status %d.\n",
1551 __func__,
Dan Williamsffe191c2011-06-29 13:09:25 -07001552 iport->logical_port_index,
Dan Williamscc9203b2011-05-08 17:34:44 -07001553 port_status);
1554 }
1555 }
1556
1557 return status;
1558}
1559
Dan Williams89a73012011-06-30 19:14:33 -07001560static enum sci_status sci_controller_stop_devices(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07001561{
1562 u32 index;
1563 enum sci_status status;
1564 enum sci_status device_status;
1565
1566 status = SCI_SUCCESS;
1567
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001568 for (index = 0; index < ihost->remote_node_entries; index++) {
1569 if (ihost->device_table[index] != NULL) {
Dan Williamscc9203b2011-05-08 17:34:44 -07001570 /* / @todo What timeout value do we want to provide to this request? */
Dan Williams89a73012011-06-30 19:14:33 -07001571 device_status = sci_remote_device_stop(ihost->device_table[index], 0);
Dan Williamscc9203b2011-05-08 17:34:44 -07001572
1573 if ((device_status != SCI_SUCCESS) &&
1574 (device_status != SCI_FAILURE_INVALID_STATE)) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001575 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -07001576 "%s: Controller stop operation failed "
1577 "to stop device 0x%p because of "
1578 "status %d.\n",
1579 __func__,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001580 ihost->device_table[index], device_status);
Dan Williamscc9203b2011-05-08 17:34:44 -07001581 }
1582 }
1583 }
1584
1585 return status;
1586}
1587
Dan Williams89a73012011-06-30 19:14:33 -07001588static void sci_controller_stopping_state_enter(struct sci_base_state_machine *sm)
Dan Williamscc9203b2011-05-08 17:34:44 -07001589{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001590 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
Dan Williamscc9203b2011-05-08 17:34:44 -07001591
1592 /* Stop all of the components for this controller */
Dan Williams89a73012011-06-30 19:14:33 -07001593 sci_controller_stop_phys(ihost);
1594 sci_controller_stop_ports(ihost);
1595 sci_controller_stop_devices(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07001596}
1597
Dan Williams89a73012011-06-30 19:14:33 -07001598static void sci_controller_stopping_state_exit(struct sci_base_state_machine *sm)
Dan Williamscc9203b2011-05-08 17:34:44 -07001599{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001600 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
Dan Williamscc9203b2011-05-08 17:34:44 -07001601
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001602 sci_del_timer(&ihost->timer);
Dan Williamscc9203b2011-05-08 17:34:44 -07001603}
1604
Dan Williams89a73012011-06-30 19:14:33 -07001605static void sci_controller_reset_hardware(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07001606{
1607 /* Disable interrupts so we dont take any spurious interrupts */
Dan Williams89a73012011-06-30 19:14:33 -07001608 sci_controller_disable_interrupts(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07001609
1610 /* Reset the SCU */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001611 writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control);
Dan Williamscc9203b2011-05-08 17:34:44 -07001612
1613 /* Delay for 1ms to before clearing the CQP and UFQPR. */
1614 udelay(1000);
1615
1616 /* The write to the CQGR clears the CQP */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001617 writel(0x00000000, &ihost->smu_registers->completion_queue_get);
Dan Williamscc9203b2011-05-08 17:34:44 -07001618
1619 /* The write to the UFQGP clears the UFQPR */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001620 writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
Dan Williamscc9203b2011-05-08 17:34:44 -07001621}
1622
Dan Williams89a73012011-06-30 19:14:33 -07001623static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm)
Dan Williamscc9203b2011-05-08 17:34:44 -07001624{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001625 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
Dan Williamscc9203b2011-05-08 17:34:44 -07001626
Dan Williams89a73012011-06-30 19:14:33 -07001627 sci_controller_reset_hardware(ihost);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001628 sci_change_state(&ihost->sm, SCIC_RESET);
Dan Williamscc9203b2011-05-08 17:34:44 -07001629}
1630
Dan Williams89a73012011-06-30 19:14:33 -07001631static const struct sci_base_state sci_controller_state_table[] = {
Edmund Nadolskie3013702011-06-02 00:10:43 +00001632 [SCIC_INITIAL] = {
Dan Williams89a73012011-06-30 19:14:33 -07001633 .enter_state = sci_controller_initial_state_enter,
Dan Williamscc9203b2011-05-08 17:34:44 -07001634 },
Edmund Nadolskie3013702011-06-02 00:10:43 +00001635 [SCIC_RESET] = {},
1636 [SCIC_INITIALIZING] = {},
1637 [SCIC_INITIALIZED] = {},
1638 [SCIC_STARTING] = {
Dan Williams89a73012011-06-30 19:14:33 -07001639 .exit_state = sci_controller_starting_state_exit,
Dan Williamscc9203b2011-05-08 17:34:44 -07001640 },
Edmund Nadolskie3013702011-06-02 00:10:43 +00001641 [SCIC_READY] = {
Dan Williams89a73012011-06-30 19:14:33 -07001642 .enter_state = sci_controller_ready_state_enter,
1643 .exit_state = sci_controller_ready_state_exit,
Dan Williamscc9203b2011-05-08 17:34:44 -07001644 },
Edmund Nadolskie3013702011-06-02 00:10:43 +00001645 [SCIC_RESETTING] = {
Dan Williams89a73012011-06-30 19:14:33 -07001646 .enter_state = sci_controller_resetting_state_enter,
Dan Williamscc9203b2011-05-08 17:34:44 -07001647 },
Edmund Nadolskie3013702011-06-02 00:10:43 +00001648 [SCIC_STOPPING] = {
Dan Williams89a73012011-06-30 19:14:33 -07001649 .enter_state = sci_controller_stopping_state_enter,
1650 .exit_state = sci_controller_stopping_state_exit,
Dan Williamscc9203b2011-05-08 17:34:44 -07001651 },
Edmund Nadolskie3013702011-06-02 00:10:43 +00001652 [SCIC_STOPPED] = {},
1653 [SCIC_FAILED] = {}
Dan Williamscc9203b2011-05-08 17:34:44 -07001654};
1655
Dan Williams89a73012011-06-30 19:14:33 -07001656static void sci_controller_set_default_config_parameters(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07001657{
1658 /* these defaults are overridden by the platform / firmware */
Dan Williamscc9203b2011-05-08 17:34:44 -07001659 u16 index;
1660
1661 /* Default to APC mode. */
Dan Williams89a73012011-06-30 19:14:33 -07001662 ihost->oem_parameters.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
Dan Williamscc9203b2011-05-08 17:34:44 -07001663
1664 /* Default to APC mode. */
Andrzej Jakowski7000f7c2011-10-27 15:05:42 -07001665 ihost->oem_parameters.controller.max_concurr_spin_up = 1;
Dan Williamscc9203b2011-05-08 17:34:44 -07001666
1667 /* Default to no SSC operation. */
Dan Williams89a73012011-06-30 19:14:33 -07001668 ihost->oem_parameters.controller.do_enable_ssc = false;
Dan Williamscc9203b2011-05-08 17:34:44 -07001669
Jeff Skirvin9fee6072012-01-04 01:32:49 -08001670 /* Default to short cables on all phys. */
1671 ihost->oem_parameters.controller.cable_selection_mask = 0;
1672
Dan Williamscc9203b2011-05-08 17:34:44 -07001673 /* Initialize all of the port parameter information to narrow ports. */
1674 for (index = 0; index < SCI_MAX_PORTS; index++) {
Dan Williams89a73012011-06-30 19:14:33 -07001675 ihost->oem_parameters.ports[index].phy_mask = 0;
Dan Williamscc9203b2011-05-08 17:34:44 -07001676 }
1677
1678 /* Initialize all of the phy parameter information. */
1679 for (index = 0; index < SCI_MAX_PHYS; index++) {
Jeff Skirvinbe168a32012-01-04 01:33:00 -08001680 /* Default to 3G (i.e. Gen 2). */
1681 ihost->user_parameters.phys[index].max_speed_generation =
1682 SCIC_SDS_PARM_GEN2_SPEED;
Dan Williamscc9203b2011-05-08 17:34:44 -07001683
1684 /* the frequencies cannot be 0 */
Dan Williams89a73012011-06-30 19:14:33 -07001685 ihost->user_parameters.phys[index].align_insertion_frequency = 0x7f;
1686 ihost->user_parameters.phys[index].in_connection_align_insertion_frequency = 0xff;
1687 ihost->user_parameters.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
Dan Williamscc9203b2011-05-08 17:34:44 -07001688
1689 /*
1690 * Previous Vitesse based expanders had a arbitration issue that
1691 * is worked around by having the upper 32-bits of SAS address
1692 * with a value greater then the Vitesse company identifier.
1693 * Hence, usage of 0x5FCFFFFF. */
Dan Williams89a73012011-06-30 19:14:33 -07001694 ihost->oem_parameters.phys[index].sas_address.low = 0x1 + ihost->id;
1695 ihost->oem_parameters.phys[index].sas_address.high = 0x5FCFFFFF;
Dan Williamscc9203b2011-05-08 17:34:44 -07001696 }
1697
Dan Williams89a73012011-06-30 19:14:33 -07001698 ihost->user_parameters.stp_inactivity_timeout = 5;
1699 ihost->user_parameters.ssp_inactivity_timeout = 5;
1700 ihost->user_parameters.stp_max_occupancy_timeout = 5;
1701 ihost->user_parameters.ssp_max_occupancy_timeout = 20;
Marcin Tomczak6024d382012-01-04 01:32:54 -08001702 ihost->user_parameters.no_outbound_task_timeout = 2;
Dan Williamscc9203b2011-05-08 17:34:44 -07001703}
1704
Edmund Nadolski6cb58532011-05-19 11:59:56 +00001705static void controller_timeout(unsigned long data)
1706{
1707 struct sci_timer *tmr = (struct sci_timer *)data;
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001708 struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer);
1709 struct sci_base_state_machine *sm = &ihost->sm;
Edmund Nadolski6cb58532011-05-19 11:59:56 +00001710 unsigned long flags;
Dan Williamscc9203b2011-05-08 17:34:44 -07001711
Edmund Nadolski6cb58532011-05-19 11:59:56 +00001712 spin_lock_irqsave(&ihost->scic_lock, flags);
1713
1714 if (tmr->cancel)
1715 goto done;
1716
Edmund Nadolskie3013702011-06-02 00:10:43 +00001717 if (sm->current_state_id == SCIC_STARTING)
Dan Williams89a73012011-06-30 19:14:33 -07001718 sci_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT);
Edmund Nadolskie3013702011-06-02 00:10:43 +00001719 else if (sm->current_state_id == SCIC_STOPPING) {
1720 sci_change_state(sm, SCIC_FAILED);
Edmund Nadolski6cb58532011-05-19 11:59:56 +00001721 isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT);
1722 } else /* / @todo Now what do we want to do in this case? */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001723 dev_err(&ihost->pdev->dev,
Edmund Nadolski6cb58532011-05-19 11:59:56 +00001724 "%s: Controller timer fired when controller was not "
1725 "in a state being timed.\n",
1726 __func__);
1727
1728done:
1729 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1730}
Dan Williamscc9203b2011-05-08 17:34:44 -07001731
Dan Williams89a73012011-06-30 19:14:33 -07001732static enum sci_status sci_controller_construct(struct isci_host *ihost,
1733 void __iomem *scu_base,
1734 void __iomem *smu_base)
Dan Williamscc9203b2011-05-08 17:34:44 -07001735{
Dan Williamscc9203b2011-05-08 17:34:44 -07001736 u8 i;
1737
Dan Williams89a73012011-06-30 19:14:33 -07001738 sci_init_sm(&ihost->sm, sci_controller_state_table, SCIC_INITIAL);
Dan Williamscc9203b2011-05-08 17:34:44 -07001739
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001740 ihost->scu_registers = scu_base;
1741 ihost->smu_registers = smu_base;
Dan Williamscc9203b2011-05-08 17:34:44 -07001742
Dan Williams89a73012011-06-30 19:14:33 -07001743 sci_port_configuration_agent_construct(&ihost->port_agent);
Dan Williamscc9203b2011-05-08 17:34:44 -07001744
1745 /* Construct the ports for this controller */
1746 for (i = 0; i < SCI_MAX_PORTS; i++)
Dan Williams89a73012011-06-30 19:14:33 -07001747 sci_port_construct(&ihost->ports[i], i, ihost);
1748 sci_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07001749
1750 /* Construct the phys for this controller */
1751 for (i = 0; i < SCI_MAX_PHYS; i++) {
1752 /* Add all the PHYs to the dummy port */
Dan Williams89a73012011-06-30 19:14:33 -07001753 sci_phy_construct(&ihost->phys[i],
1754 &ihost->ports[SCI_MAX_PORTS], i);
Dan Williamscc9203b2011-05-08 17:34:44 -07001755 }
1756
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001757 ihost->invalid_phy_mask = 0;
Dan Williamscc9203b2011-05-08 17:34:44 -07001758
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001759 sci_init_timer(&ihost->timer, controller_timeout);
Edmund Nadolski6cb58532011-05-19 11:59:56 +00001760
Dan Williamscc9203b2011-05-08 17:34:44 -07001761 /* Initialize the User and OEM parameters to default values. */
Dan Williams89a73012011-06-30 19:14:33 -07001762 sci_controller_set_default_config_parameters(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07001763
Dan Williams89a73012011-06-30 19:14:33 -07001764 return sci_controller_reset(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07001765}
1766
Dave Jiang594e5662012-01-04 01:32:44 -08001767int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version)
Dan Williamscc9203b2011-05-08 17:34:44 -07001768{
1769 int i;
1770
1771 for (i = 0; i < SCI_MAX_PORTS; i++)
1772 if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
1773 return -EINVAL;
1774
1775 for (i = 0; i < SCI_MAX_PHYS; i++)
1776 if (oem->phys[i].sas_address.high == 0 &&
1777 oem->phys[i].sas_address.low == 0)
1778 return -EINVAL;
1779
1780 if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
1781 for (i = 0; i < SCI_MAX_PHYS; i++)
1782 if (oem->ports[i].phy_mask != 0)
1783 return -EINVAL;
1784 } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
1785 u8 phy_mask = 0;
1786
1787 for (i = 0; i < SCI_MAX_PHYS; i++)
1788 phy_mask |= oem->ports[i].phy_mask;
1789
1790 if (phy_mask == 0)
1791 return -EINVAL;
1792 } else
1793 return -EINVAL;
1794
Andrzej Jakowski7000f7c2011-10-27 15:05:42 -07001795 if (oem->controller.max_concurr_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT ||
1796 oem->controller.max_concurr_spin_up < 1)
Dan Williamscc9203b2011-05-08 17:34:44 -07001797 return -EINVAL;
1798
Dave Jiang594e5662012-01-04 01:32:44 -08001799 if (oem->controller.do_enable_ssc) {
1800 if (version < ISCI_ROM_VER_1_1 && oem->controller.do_enable_ssc != 1)
1801 return -EINVAL;
1802
1803 if (version >= ISCI_ROM_VER_1_1) {
1804 u8 test = oem->controller.ssc_sata_tx_spread_level;
1805
1806 switch (test) {
1807 case 0:
1808 case 2:
1809 case 3:
1810 case 6:
1811 case 7:
1812 break;
1813 default:
1814 return -EINVAL;
1815 }
1816
1817 test = oem->controller.ssc_sas_tx_spread_level;
1818 if (oem->controller.ssc_sas_tx_type == 0) {
1819 switch (test) {
1820 case 0:
1821 case 2:
1822 case 3:
1823 break;
1824 default:
1825 return -EINVAL;
1826 }
1827 } else if (oem->controller.ssc_sas_tx_type == 1) {
1828 switch (test) {
1829 case 0:
1830 case 3:
1831 case 6:
1832 break;
1833 default:
1834 return -EINVAL;
1835 }
1836 }
1837 }
1838 }
1839
Dan Williamscc9203b2011-05-08 17:34:44 -07001840 return 0;
1841}
1842
Dan Williams89a73012011-06-30 19:14:33 -07001843static enum sci_status sci_oem_parameters_set(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07001844{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001845 u32 state = ihost->sm.current_state_id;
Dave Jiang594e5662012-01-04 01:32:44 -08001846 struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
Dan Williamscc9203b2011-05-08 17:34:44 -07001847
Edmund Nadolskie3013702011-06-02 00:10:43 +00001848 if (state == SCIC_RESET ||
1849 state == SCIC_INITIALIZING ||
1850 state == SCIC_INITIALIZED) {
Dan Williamscc9203b2011-05-08 17:34:44 -07001851
Dave Jiang594e5662012-01-04 01:32:44 -08001852 if (sci_oem_parameters_validate(&ihost->oem_parameters,
1853 pci_info->orom->hdr.version))
Dan Williamscc9203b2011-05-08 17:34:44 -07001854 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
Dan Williamscc9203b2011-05-08 17:34:44 -07001855
1856 return SCI_SUCCESS;
1857 }
1858
1859 return SCI_FAILURE_INVALID_STATE;
1860}
1861
Andrzej Jakowski7000f7c2011-10-27 15:05:42 -07001862static u8 max_spin_up(struct isci_host *ihost)
1863{
1864 if (ihost->user_parameters.max_concurr_spinup)
1865 return min_t(u8, ihost->user_parameters.max_concurr_spinup,
1866 MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1867 else
1868 return min_t(u8, ihost->oem_parameters.controller.max_concurr_spin_up,
1869 MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1870}
1871
Edmund Nadolski04736612011-05-19 20:17:47 -07001872static void power_control_timeout(unsigned long data)
Dan Williamscc9203b2011-05-08 17:34:44 -07001873{
Edmund Nadolski04736612011-05-19 20:17:47 -07001874 struct sci_timer *tmr = (struct sci_timer *)data;
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001875 struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer);
Dan Williams85280952011-06-28 15:05:53 -07001876 struct isci_phy *iphy;
Edmund Nadolski04736612011-05-19 20:17:47 -07001877 unsigned long flags;
1878 u8 i;
Dan Williamscc9203b2011-05-08 17:34:44 -07001879
Edmund Nadolski04736612011-05-19 20:17:47 -07001880 spin_lock_irqsave(&ihost->scic_lock, flags);
Dan Williamscc9203b2011-05-08 17:34:44 -07001881
Edmund Nadolski04736612011-05-19 20:17:47 -07001882 if (tmr->cancel)
1883 goto done;
Dan Williamscc9203b2011-05-08 17:34:44 -07001884
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001885 ihost->power_control.phys_granted_power = 0;
Dan Williamscc9203b2011-05-08 17:34:44 -07001886
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001887 if (ihost->power_control.phys_waiting == 0) {
1888 ihost->power_control.timer_started = false;
Edmund Nadolski04736612011-05-19 20:17:47 -07001889 goto done;
Dan Williamscc9203b2011-05-08 17:34:44 -07001890 }
Edmund Nadolski04736612011-05-19 20:17:47 -07001891
1892 for (i = 0; i < SCI_MAX_PHYS; i++) {
1893
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001894 if (ihost->power_control.phys_waiting == 0)
Edmund Nadolski04736612011-05-19 20:17:47 -07001895 break;
1896
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001897 iphy = ihost->power_control.requesters[i];
Dan Williams85280952011-06-28 15:05:53 -07001898 if (iphy == NULL)
Edmund Nadolski04736612011-05-19 20:17:47 -07001899 continue;
1900
Andrzej Jakowski7000f7c2011-10-27 15:05:42 -07001901 if (ihost->power_control.phys_granted_power >= max_spin_up(ihost))
Edmund Nadolski04736612011-05-19 20:17:47 -07001902 break;
1903
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001904 ihost->power_control.requesters[i] = NULL;
1905 ihost->power_control.phys_waiting--;
1906 ihost->power_control.phys_granted_power++;
Dan Williams89a73012011-06-30 19:14:33 -07001907 sci_phy_consume_power_handler(iphy);
Marcin Tomczakbe778342012-01-04 01:33:31 -08001908
1909 if (iphy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) {
1910 u8 j;
1911
1912 for (j = 0; j < SCI_MAX_PHYS; j++) {
1913 struct isci_phy *requester = ihost->power_control.requesters[j];
1914
1915 /*
1916 * Search the power_control queue to see if there are other phys
1917 * attached to the same remote device. If found, take all of
1918 * them out of await_sas_power state.
1919 */
1920 if (requester != NULL && requester != iphy) {
1921 u8 other = memcmp(requester->frame_rcvd.iaf.sas_addr,
1922 iphy->frame_rcvd.iaf.sas_addr,
1923 sizeof(requester->frame_rcvd.iaf.sas_addr));
1924
1925 if (other == 0) {
1926 ihost->power_control.requesters[j] = NULL;
1927 ihost->power_control.phys_waiting--;
1928 sci_phy_consume_power_handler(requester);
1929 }
1930 }
1931 }
1932 }
Edmund Nadolski04736612011-05-19 20:17:47 -07001933 }
1934
1935 /*
1936 * It doesn't matter if the power list is empty, we need to start the
1937 * timer in case another phy becomes ready.
1938 */
1939 sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001940 ihost->power_control.timer_started = true;
Edmund Nadolski04736612011-05-19 20:17:47 -07001941
1942done:
1943 spin_unlock_irqrestore(&ihost->scic_lock, flags);
Dan Williamscc9203b2011-05-08 17:34:44 -07001944}
1945
Dan Williams89a73012011-06-30 19:14:33 -07001946void sci_controller_power_control_queue_insert(struct isci_host *ihost,
1947 struct isci_phy *iphy)
Dan Williamscc9203b2011-05-08 17:34:44 -07001948{
Dan Williams85280952011-06-28 15:05:53 -07001949 BUG_ON(iphy == NULL);
Dan Williamscc9203b2011-05-08 17:34:44 -07001950
Andrzej Jakowski7000f7c2011-10-27 15:05:42 -07001951 if (ihost->power_control.phys_granted_power < max_spin_up(ihost)) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001952 ihost->power_control.phys_granted_power++;
Dan Williams89a73012011-06-30 19:14:33 -07001953 sci_phy_consume_power_handler(iphy);
Dan Williamscc9203b2011-05-08 17:34:44 -07001954
1955 /*
1956 * stop and start the power_control timer. When the timer fires, the
1957 * no_of_phys_granted_power will be set to 0
1958 */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001959 if (ihost->power_control.timer_started)
1960 sci_del_timer(&ihost->power_control.timer);
Edmund Nadolski04736612011-05-19 20:17:47 -07001961
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001962 sci_mod_timer(&ihost->power_control.timer,
Edmund Nadolski04736612011-05-19 20:17:47 -07001963 SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07001964 ihost->power_control.timer_started = true;
Edmund Nadolski04736612011-05-19 20:17:47 -07001965
Dan Williamscc9203b2011-05-08 17:34:44 -07001966 } else {
Marcin Tomczakbe778342012-01-04 01:33:31 -08001967 /*
1968 * There are phys, attached to the same sas address as this phy, are
1969 * already in READY state, this phy don't need wait.
1970 */
1971 u8 i;
1972 struct isci_phy *current_phy;
1973
1974 for (i = 0; i < SCI_MAX_PHYS; i++) {
1975 u8 other;
1976 current_phy = &ihost->phys[i];
1977
1978 other = memcmp(current_phy->frame_rcvd.iaf.sas_addr,
1979 iphy->frame_rcvd.iaf.sas_addr,
1980 sizeof(current_phy->frame_rcvd.iaf.sas_addr));
1981
1982 if (current_phy->sm.current_state_id == SCI_PHY_READY &&
1983 current_phy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS &&
1984 other == 0) {
1985 sci_phy_consume_power_handler(iphy);
1986 break;
1987 }
1988 }
1989
1990 if (i == SCI_MAX_PHYS) {
1991 /* Add the phy in the waiting list */
1992 ihost->power_control.requesters[iphy->phy_index] = iphy;
1993 ihost->power_control.phys_waiting++;
1994 }
Dan Williamscc9203b2011-05-08 17:34:44 -07001995 }
1996}
1997
Dan Williams89a73012011-06-30 19:14:33 -07001998void sci_controller_power_control_queue_remove(struct isci_host *ihost,
1999 struct isci_phy *iphy)
Dan Williamscc9203b2011-05-08 17:34:44 -07002000{
Dan Williams85280952011-06-28 15:05:53 -07002001 BUG_ON(iphy == NULL);
Dan Williamscc9203b2011-05-08 17:34:44 -07002002
Dan Williams89a73012011-06-30 19:14:33 -07002003 if (ihost->power_control.requesters[iphy->phy_index])
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002004 ihost->power_control.phys_waiting--;
Dan Williamscc9203b2011-05-08 17:34:44 -07002005
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002006 ihost->power_control.requesters[iphy->phy_index] = NULL;
Dan Williamscc9203b2011-05-08 17:34:44 -07002007}
2008
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002009static int is_long_cable(int phy, unsigned char selection_byte)
2010{
Jeff Skirvin9fee6072012-01-04 01:32:49 -08002011 return !!(selection_byte & (1 << phy));
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002012}
2013
2014static int is_medium_cable(int phy, unsigned char selection_byte)
2015{
Jeff Skirvin9fee6072012-01-04 01:32:49 -08002016 return !!(selection_byte & (1 << (phy + 4)));
2017}
2018
2019static enum cable_selections decode_selection_byte(
2020 int phy,
2021 unsigned char selection_byte)
2022{
2023 return ((selection_byte & (1 << phy)) ? 1 : 0)
2024 + (selection_byte & (1 << (phy + 4)) ? 2 : 0);
2025}
2026
2027static unsigned char *to_cable_select(struct isci_host *ihost)
2028{
2029 if (is_cable_select_overridden())
2030 return ((unsigned char *)&cable_selection_override)
2031 + ihost->id;
2032 else
2033 return &ihost->oem_parameters.controller.cable_selection_mask;
2034}
2035
2036enum cable_selections decode_cable_selection(struct isci_host *ihost, int phy)
2037{
2038 return decode_selection_byte(phy, *to_cable_select(ihost));
2039}
2040
2041char *lookup_cable_names(enum cable_selections selection)
2042{
2043 static char *cable_names[] = {
2044 [short_cable] = "short",
2045 [long_cable] = "long",
2046 [medium_cable] = "medium",
2047 [undefined_cable] = "<undefined, assumed long>" /* bit 0==1 */
2048 };
2049 return (selection <= undefined_cable) ? cable_names[selection]
2050 : cable_names[undefined_cable];
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002051}
2052
Dan Williamscc9203b2011-05-08 17:34:44 -07002053#define AFE_REGISTER_WRITE_DELAY 10
2054
Dan Williams89a73012011-06-30 19:14:33 -07002055static void sci_controller_afe_initialization(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07002056{
Dan Williams2e5da882012-01-04 01:32:34 -08002057 struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
Dan Williams89a73012011-06-30 19:14:33 -07002058 const struct sci_oem_params *oem = &ihost->oem_parameters;
Dan Williamsdc00c8b2011-07-01 11:41:21 -07002059 struct pci_dev *pdev = ihost->pdev;
Dan Williamscc9203b2011-05-08 17:34:44 -07002060 u32 afe_status;
2061 u32 phy_id;
Jeff Skirvin9fee6072012-01-04 01:32:49 -08002062 unsigned char cable_selection_mask = *to_cable_select(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07002063
2064 /* Clear DFX Status registers */
Dan Williams2e5da882012-01-04 01:32:34 -08002065 writel(0x0081000f, &afe->afe_dfx_master_control0);
Dan Williamscc9203b2011-05-08 17:34:44 -07002066 udelay(AFE_REGISTER_WRITE_DELAY);
2067
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002068 if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) {
Dan Williamscc9203b2011-05-08 17:34:44 -07002069 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
Dan Williams2e5da882012-01-04 01:32:34 -08002070 * Timer, PM Stagger Timer
2071 */
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002072 writel(0x0007FFFF, &afe->afe_pmsn_master_control2);
Dan Williamscc9203b2011-05-08 17:34:44 -07002073 udelay(AFE_REGISTER_WRITE_DELAY);
2074 }
2075
2076 /* Configure bias currents to normal */
Dan Williamsdc00c8b2011-07-01 11:41:21 -07002077 if (is_a2(pdev))
Dan Williams2e5da882012-01-04 01:32:34 -08002078 writel(0x00005A00, &afe->afe_bias_control);
Dan Williamsdc00c8b2011-07-01 11:41:21 -07002079 else if (is_b0(pdev) || is_c0(pdev))
Dan Williams2e5da882012-01-04 01:32:34 -08002080 writel(0x00005F00, &afe->afe_bias_control);
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002081 else if (is_c1(pdev))
2082 writel(0x00005500, &afe->afe_bias_control);
Dan Williamscc9203b2011-05-08 17:34:44 -07002083
2084 udelay(AFE_REGISTER_WRITE_DELAY);
2085
2086 /* Enable PLL */
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002087 if (is_a2(pdev))
Dan Williams2e5da882012-01-04 01:32:34 -08002088 writel(0x80040908, &afe->afe_pll_control0);
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002089 else if (is_b0(pdev) || is_c0(pdev))
2090 writel(0x80040A08, &afe->afe_pll_control0);
2091 else if (is_c1(pdev)) {
2092 writel(0x80000B08, &afe->afe_pll_control0);
2093 udelay(AFE_REGISTER_WRITE_DELAY);
2094 writel(0x00000B08, &afe->afe_pll_control0);
2095 udelay(AFE_REGISTER_WRITE_DELAY);
2096 writel(0x80000B08, &afe->afe_pll_control0);
2097 }
Dan Williamscc9203b2011-05-08 17:34:44 -07002098
2099 udelay(AFE_REGISTER_WRITE_DELAY);
2100
2101 /* Wait for the PLL to lock */
2102 do {
Dan Williams2e5da882012-01-04 01:32:34 -08002103 afe_status = readl(&afe->afe_common_block_status);
Dan Williamscc9203b2011-05-08 17:34:44 -07002104 udelay(AFE_REGISTER_WRITE_DELAY);
2105 } while ((afe_status & 0x00001000) == 0);
2106
Dan Williamsdc00c8b2011-07-01 11:41:21 -07002107 if (is_a2(pdev)) {
Dan Williams2e5da882012-01-04 01:32:34 -08002108 /* Shorten SAS SNW lock time (RxLock timer value from 76
2109 * us to 50 us)
2110 */
2111 writel(0x7bcc96ad, &afe->afe_pmsn_master_control0);
Dan Williamscc9203b2011-05-08 17:34:44 -07002112 udelay(AFE_REGISTER_WRITE_DELAY);
2113 }
2114
2115 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
Dan Williams2e5da882012-01-04 01:32:34 -08002116 struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_id];
Dan Williamscc9203b2011-05-08 17:34:44 -07002117 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002118 int cable_length_long =
2119 is_long_cable(phy_id, cable_selection_mask);
2120 int cable_length_medium =
2121 is_medium_cable(phy_id, cable_selection_mask);
Dan Williamscc9203b2011-05-08 17:34:44 -07002122
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002123 if (is_a2(pdev)) {
Dan Williams2e5da882012-01-04 01:32:34 -08002124 /* All defaults, except the Receive Word
2125 * Alignament/Comma Detect Enable....(0xe800)
2126 */
2127 writel(0x00004512, &xcvr->afe_xcvr_control0);
Dan Williamscc9203b2011-05-08 17:34:44 -07002128 udelay(AFE_REGISTER_WRITE_DELAY);
2129
Dan Williams2e5da882012-01-04 01:32:34 -08002130 writel(0x0050100F, &xcvr->afe_xcvr_control1);
Dan Williamscc9203b2011-05-08 17:34:44 -07002131 udelay(AFE_REGISTER_WRITE_DELAY);
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002132 } else if (is_b0(pdev)) {
2133 /* Configure transmitter SSC parameters */
2134 writel(0x00030000, &xcvr->afe_tx_ssc_control);
2135 udelay(AFE_REGISTER_WRITE_DELAY);
2136 } else if (is_c0(pdev)) {
2137 /* Configure transmitter SSC parameters */
2138 writel(0x00010202, &xcvr->afe_tx_ssc_control);
2139 udelay(AFE_REGISTER_WRITE_DELAY);
2140
2141 /* All defaults, except the Receive Word
2142 * Alignament/Comma Detect Enable....(0xe800)
2143 */
2144 writel(0x00014500, &xcvr->afe_xcvr_control0);
2145 udelay(AFE_REGISTER_WRITE_DELAY);
2146 } else if (is_c1(pdev)) {
2147 /* Configure transmitter SSC parameters */
2148 writel(0x00010202, &xcvr->afe_tx_ssc_control);
2149 udelay(AFE_REGISTER_WRITE_DELAY);
2150
2151 /* All defaults, except the Receive Word
2152 * Alignament/Comma Detect Enable....(0xe800)
2153 */
2154 writel(0x0001C500, &xcvr->afe_xcvr_control0);
2155 udelay(AFE_REGISTER_WRITE_DELAY);
Dan Williamscc9203b2011-05-08 17:34:44 -07002156 }
2157
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002158 /* Power up TX and RX out from power down (PWRDNTX and
2159 * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c)
Dan Williams2e5da882012-01-04 01:32:34 -08002160 */
Dan Williamsdc00c8b2011-07-01 11:41:21 -07002161 if (is_a2(pdev))
Dan Williams2e5da882012-01-04 01:32:34 -08002162 writel(0x000003F0, &xcvr->afe_channel_control);
Dan Williamsdc00c8b2011-07-01 11:41:21 -07002163 else if (is_b0(pdev)) {
Dan Williams2e5da882012-01-04 01:32:34 -08002164 writel(0x000003D7, &xcvr->afe_channel_control);
Dan Williamscc9203b2011-05-08 17:34:44 -07002165 udelay(AFE_REGISTER_WRITE_DELAY);
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002166
Dan Williams2e5da882012-01-04 01:32:34 -08002167 writel(0x000003D4, &xcvr->afe_channel_control);
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002168 } else if (is_c0(pdev)) {
Dan Williams2e5da882012-01-04 01:32:34 -08002169 writel(0x000001E7, &xcvr->afe_channel_control);
Adam Gruchaladbb07432011-06-01 22:31:03 +00002170 udelay(AFE_REGISTER_WRITE_DELAY);
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002171
Dan Williams2e5da882012-01-04 01:32:34 -08002172 writel(0x000001E4, &xcvr->afe_channel_control);
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002173 } else if (is_c1(pdev)) {
2174 writel(cable_length_long ? 0x000002F7 : 0x000001F7,
2175 &xcvr->afe_channel_control);
2176 udelay(AFE_REGISTER_WRITE_DELAY);
2177
2178 writel(cable_length_long ? 0x000002F4 : 0x000001F4,
2179 &xcvr->afe_channel_control);
Dan Williamscc9203b2011-05-08 17:34:44 -07002180 }
2181 udelay(AFE_REGISTER_WRITE_DELAY);
2182
Dan Williamsdc00c8b2011-07-01 11:41:21 -07002183 if (is_a2(pdev)) {
Dan Williamscc9203b2011-05-08 17:34:44 -07002184 /* Enable TX equalization (0xe824) */
Dan Williams2e5da882012-01-04 01:32:34 -08002185 writel(0x00040000, &xcvr->afe_tx_control);
Dan Williamscc9203b2011-05-08 17:34:44 -07002186 udelay(AFE_REGISTER_WRITE_DELAY);
2187 }
2188
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002189 if (is_a2(pdev) || is_b0(pdev))
2190 /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0,
2191 * TPD=0x0(TX Power On), RDD=0x0(RX Detect
2192 * Enabled) ....(0xe800)
2193 */
2194 writel(0x00004100, &xcvr->afe_xcvr_control0);
2195 else if (is_c0(pdev))
2196 writel(0x00014100, &xcvr->afe_xcvr_control0);
2197 else if (is_c1(pdev))
2198 writel(0x0001C100, &xcvr->afe_xcvr_control0);
Dan Williamscc9203b2011-05-08 17:34:44 -07002199 udelay(AFE_REGISTER_WRITE_DELAY);
2200
2201 /* Leave DFE/FFE on */
Dan Williamsdc00c8b2011-07-01 11:41:21 -07002202 if (is_a2(pdev))
Dan Williams2e5da882012-01-04 01:32:34 -08002203 writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
Dan Williamsdc00c8b2011-07-01 11:41:21 -07002204 else if (is_b0(pdev)) {
Dan Williams2e5da882012-01-04 01:32:34 -08002205 writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
Dan Williamscc9203b2011-05-08 17:34:44 -07002206 udelay(AFE_REGISTER_WRITE_DELAY);
2207 /* Enable TX equalization (0xe824) */
Dan Williams2e5da882012-01-04 01:32:34 -08002208 writel(0x00040000, &xcvr->afe_tx_control);
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002209 } else if (is_c0(pdev)) {
2210 writel(0x01400C0F, &xcvr->afe_rx_ssc_control1);
Adam Gruchaladbb07432011-06-01 22:31:03 +00002211 udelay(AFE_REGISTER_WRITE_DELAY);
2212
Dan Williams2e5da882012-01-04 01:32:34 -08002213 writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0);
Adam Gruchaladbb07432011-06-01 22:31:03 +00002214 udelay(AFE_REGISTER_WRITE_DELAY);
2215
2216 /* Enable TX equalization (0xe824) */
Dan Williams2e5da882012-01-04 01:32:34 -08002217 writel(0x00040000, &xcvr->afe_tx_control);
Jeff Skirvinafd13a12012-01-04 01:32:39 -08002218 } else if (is_c1(pdev)) {
2219 writel(cable_length_long ? 0x01500C0C :
2220 cable_length_medium ? 0x01400C0D : 0x02400C0D,
2221 &xcvr->afe_xcvr_control1);
2222 udelay(AFE_REGISTER_WRITE_DELAY);
2223
2224 writel(0x000003E0, &xcvr->afe_dfx_rx_control1);
2225 udelay(AFE_REGISTER_WRITE_DELAY);
2226
2227 writel(cable_length_long ? 0x33091C1F :
2228 cable_length_medium ? 0x3315181F : 0x2B17161F,
2229 &xcvr->afe_rx_ssc_control0);
2230 udelay(AFE_REGISTER_WRITE_DELAY);
2231
2232 /* Enable TX equalization (0xe824) */
2233 writel(0x00040000, &xcvr->afe_tx_control);
Dan Williamscc9203b2011-05-08 17:34:44 -07002234 }
Adam Gruchaladbb07432011-06-01 22:31:03 +00002235
Dan Williamscc9203b2011-05-08 17:34:44 -07002236 udelay(AFE_REGISTER_WRITE_DELAY);
2237
Dan Williams2e5da882012-01-04 01:32:34 -08002238 writel(oem_phy->afe_tx_amp_control0, &xcvr->afe_tx_amp_control0);
Dan Williamscc9203b2011-05-08 17:34:44 -07002239 udelay(AFE_REGISTER_WRITE_DELAY);
2240
Dan Williams2e5da882012-01-04 01:32:34 -08002241 writel(oem_phy->afe_tx_amp_control1, &xcvr->afe_tx_amp_control1);
Dan Williamscc9203b2011-05-08 17:34:44 -07002242 udelay(AFE_REGISTER_WRITE_DELAY);
2243
Dan Williams2e5da882012-01-04 01:32:34 -08002244 writel(oem_phy->afe_tx_amp_control2, &xcvr->afe_tx_amp_control2);
Dan Williamscc9203b2011-05-08 17:34:44 -07002245 udelay(AFE_REGISTER_WRITE_DELAY);
2246
Dan Williams2e5da882012-01-04 01:32:34 -08002247 writel(oem_phy->afe_tx_amp_control3, &xcvr->afe_tx_amp_control3);
Dan Williamscc9203b2011-05-08 17:34:44 -07002248 udelay(AFE_REGISTER_WRITE_DELAY);
2249 }
2250
2251 /* Transfer control to the PEs */
Dan Williams2e5da882012-01-04 01:32:34 -08002252 writel(0x00010f00, &afe->afe_dfx_master_control0);
Dan Williamscc9203b2011-05-08 17:34:44 -07002253 udelay(AFE_REGISTER_WRITE_DELAY);
2254}
2255
Dan Williams89a73012011-06-30 19:14:33 -07002256static void sci_controller_initialize_power_control(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07002257{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002258 sci_init_timer(&ihost->power_control.timer, power_control_timeout);
Dan Williamscc9203b2011-05-08 17:34:44 -07002259
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002260 memset(ihost->power_control.requesters, 0,
2261 sizeof(ihost->power_control.requesters));
Dan Williamscc9203b2011-05-08 17:34:44 -07002262
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002263 ihost->power_control.phys_waiting = 0;
2264 ihost->power_control.phys_granted_power = 0;
Dan Williamscc9203b2011-05-08 17:34:44 -07002265}
2266
Dan Williams89a73012011-06-30 19:14:33 -07002267static enum sci_status sci_controller_initialize(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07002268{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002269 struct sci_base_state_machine *sm = &ihost->sm;
Dan Williams7c78da32011-06-01 16:00:01 -07002270 enum sci_status result = SCI_FAILURE;
2271 unsigned long i, state, val;
Dan Williamscc9203b2011-05-08 17:34:44 -07002272
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002273 if (ihost->sm.current_state_id != SCIC_RESET) {
2274 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -07002275 "SCIC Controller initialize operation requested "
2276 "in invalid state\n");
2277 return SCI_FAILURE_INVALID_STATE;
2278 }
2279
Edmund Nadolskie3013702011-06-02 00:10:43 +00002280 sci_change_state(sm, SCIC_INITIALIZING);
Dan Williamscc9203b2011-05-08 17:34:44 -07002281
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002282 sci_init_timer(&ihost->phy_timer, phy_startup_timeout);
Edmund Nadolskibb3dbdf2011-05-19 20:26:02 -07002283
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002284 ihost->next_phy_to_start = 0;
2285 ihost->phy_startup_timer_pending = false;
Dan Williamscc9203b2011-05-08 17:34:44 -07002286
Dan Williams89a73012011-06-30 19:14:33 -07002287 sci_controller_initialize_power_control(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07002288
2289 /*
2290 * There is nothing to do here for B0 since we do not have to
2291 * program the AFE registers.
2292 * / @todo The AFE settings are supposed to be correct for the B0 but
2293 * / presently they seem to be wrong. */
Dan Williams89a73012011-06-30 19:14:33 -07002294 sci_controller_afe_initialization(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07002295
Dan Williams7c78da32011-06-01 16:00:01 -07002296
2297 /* Take the hardware out of reset */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002298 writel(0, &ihost->smu_registers->soft_reset_control);
Dan Williams7c78da32011-06-01 16:00:01 -07002299
2300 /*
2301 * / @todo Provide meaningfull error code for hardware failure
2302 * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2303 for (i = 100; i >= 1; i--) {
Dan Williamscc9203b2011-05-08 17:34:44 -07002304 u32 status;
Dan Williamscc9203b2011-05-08 17:34:44 -07002305
Dan Williams7c78da32011-06-01 16:00:01 -07002306 /* Loop until the hardware reports success */
2307 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002308 status = readl(&ihost->smu_registers->control_status);
Dan Williamscc9203b2011-05-08 17:34:44 -07002309
Dan Williams7c78da32011-06-01 16:00:01 -07002310 if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
2311 break;
Dan Williamscc9203b2011-05-08 17:34:44 -07002312 }
Dan Williams7c78da32011-06-01 16:00:01 -07002313 if (i == 0)
2314 goto out;
Dan Williamscc9203b2011-05-08 17:34:44 -07002315
Dan Williams7c78da32011-06-01 16:00:01 -07002316 /*
2317 * Determine what are the actaul device capacities that the
2318 * hardware will support */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002319 val = readl(&ihost->smu_registers->device_context_capacity);
Dan Williamscc9203b2011-05-08 17:34:44 -07002320
Dan Williams7c78da32011-06-01 16:00:01 -07002321 /* Record the smaller of the two capacity values */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002322 ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS);
2323 ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS);
2324 ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES);
Dan Williamscc9203b2011-05-08 17:34:44 -07002325
Dan Williams7c78da32011-06-01 16:00:01 -07002326 /*
2327 * Make all PEs that are unassigned match up with the
2328 * logical ports
2329 */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002330 for (i = 0; i < ihost->logical_port_entries; i++) {
Dan Williams7c78da32011-06-01 16:00:01 -07002331 struct scu_port_task_scheduler_group_registers __iomem
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002332 *ptsg = &ihost->scu_registers->peg0.ptsg;
Dan Williamscc9203b2011-05-08 17:34:44 -07002333
Dan Williams7c78da32011-06-01 16:00:01 -07002334 writel(i, &ptsg->protocol_engine[i]);
Dan Williamscc9203b2011-05-08 17:34:44 -07002335 }
2336
2337 /* Initialize hardware PCI Relaxed ordering in DMA engines */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002338 val = readl(&ihost->scu_registers->sdma.pdma_configuration);
Dan Williams7c78da32011-06-01 16:00:01 -07002339 val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002340 writel(val, &ihost->scu_registers->sdma.pdma_configuration);
Dan Williamscc9203b2011-05-08 17:34:44 -07002341
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002342 val = readl(&ihost->scu_registers->sdma.cdma_configuration);
Dan Williams7c78da32011-06-01 16:00:01 -07002343 val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002344 writel(val, &ihost->scu_registers->sdma.cdma_configuration);
Dan Williamscc9203b2011-05-08 17:34:44 -07002345
2346 /*
2347 * Initialize the PHYs before the PORTs because the PHY registers
2348 * are accessed during the port initialization.
2349 */
Dan Williams7c78da32011-06-01 16:00:01 -07002350 for (i = 0; i < SCI_MAX_PHYS; i++) {
Dan Williams89a73012011-06-30 19:14:33 -07002351 result = sci_phy_initialize(&ihost->phys[i],
2352 &ihost->scu_registers->peg0.pe[i].tl,
2353 &ihost->scu_registers->peg0.pe[i].ll);
Dan Williams7c78da32011-06-01 16:00:01 -07002354 if (result != SCI_SUCCESS)
2355 goto out;
Dan Williamscc9203b2011-05-08 17:34:44 -07002356 }
2357
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002358 for (i = 0; i < ihost->logical_port_entries; i++) {
Dan Williams89a73012011-06-30 19:14:33 -07002359 struct isci_port *iport = &ihost->ports[i];
Dan Williams7c78da32011-06-01 16:00:01 -07002360
Dan Williams89a73012011-06-30 19:14:33 -07002361 iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i];
2362 iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0];
2363 iport->viit_registers = &ihost->scu_registers->peg0.viit[i];
Dan Williamscc9203b2011-05-08 17:34:44 -07002364 }
2365
Dan Williams89a73012011-06-30 19:14:33 -07002366 result = sci_port_configuration_agent_initialize(ihost, &ihost->port_agent);
Dan Williamscc9203b2011-05-08 17:34:44 -07002367
Dan Williams7c78da32011-06-01 16:00:01 -07002368 out:
Dan Williamscc9203b2011-05-08 17:34:44 -07002369 /* Advance the controller state machine */
2370 if (result == SCI_SUCCESS)
Edmund Nadolskie3013702011-06-02 00:10:43 +00002371 state = SCIC_INITIALIZED;
Dan Williamscc9203b2011-05-08 17:34:44 -07002372 else
Edmund Nadolskie3013702011-06-02 00:10:43 +00002373 state = SCIC_FAILED;
2374 sci_change_state(sm, state);
Dan Williamscc9203b2011-05-08 17:34:44 -07002375
2376 return result;
2377}
2378
Dan Williams89a73012011-06-30 19:14:33 -07002379static enum sci_status sci_user_parameters_set(struct isci_host *ihost,
2380 struct sci_user_parameters *sci_parms)
Dan Williamscc9203b2011-05-08 17:34:44 -07002381{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002382 u32 state = ihost->sm.current_state_id;
Dan Williamscc9203b2011-05-08 17:34:44 -07002383
Edmund Nadolskie3013702011-06-02 00:10:43 +00002384 if (state == SCIC_RESET ||
2385 state == SCIC_INITIALIZING ||
2386 state == SCIC_INITIALIZED) {
Dan Williamscc9203b2011-05-08 17:34:44 -07002387 u16 index;
2388
2389 /*
2390 * Validate the user parameters. If they are not legal, then
2391 * return a failure.
2392 */
2393 for (index = 0; index < SCI_MAX_PHYS; index++) {
2394 struct sci_phy_user_params *user_phy;
2395
Dan Williams89a73012011-06-30 19:14:33 -07002396 user_phy = &sci_parms->phys[index];
Dan Williamscc9203b2011-05-08 17:34:44 -07002397
2398 if (!((user_phy->max_speed_generation <=
2399 SCIC_SDS_PARM_MAX_SPEED) &&
2400 (user_phy->max_speed_generation >
2401 SCIC_SDS_PARM_NO_SPEED)))
2402 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2403
2404 if (user_phy->in_connection_align_insertion_frequency <
2405 3)
2406 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2407
2408 if ((user_phy->in_connection_align_insertion_frequency <
2409 3) ||
2410 (user_phy->align_insertion_frequency == 0) ||
2411 (user_phy->
2412 notify_enable_spin_up_insertion_frequency ==
2413 0))
2414 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2415 }
2416
Dan Williams89a73012011-06-30 19:14:33 -07002417 if ((sci_parms->stp_inactivity_timeout == 0) ||
2418 (sci_parms->ssp_inactivity_timeout == 0) ||
2419 (sci_parms->stp_max_occupancy_timeout == 0) ||
2420 (sci_parms->ssp_max_occupancy_timeout == 0) ||
2421 (sci_parms->no_outbound_task_timeout == 0))
Dan Williamscc9203b2011-05-08 17:34:44 -07002422 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2423
Dan Williams89a73012011-06-30 19:14:33 -07002424 memcpy(&ihost->user_parameters, sci_parms, sizeof(*sci_parms));
Dan Williamscc9203b2011-05-08 17:34:44 -07002425
2426 return SCI_SUCCESS;
2427 }
2428
2429 return SCI_FAILURE_INVALID_STATE;
2430}
2431
Dan Williams89a73012011-06-30 19:14:33 -07002432static int sci_controller_mem_init(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07002433{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002434 struct device *dev = &ihost->pdev->dev;
Dan Williams7c78da32011-06-01 16:00:01 -07002435 dma_addr_t dma;
2436 size_t size;
2437 int err;
Dan Williamscc9203b2011-05-08 17:34:44 -07002438
Dan Williams7c78da32011-06-01 16:00:01 -07002439 size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002440 ihost->completion_queue = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2441 if (!ihost->completion_queue)
Dan Williamscc9203b2011-05-08 17:34:44 -07002442 return -ENOMEM;
2443
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002444 writel(lower_32_bits(dma), &ihost->smu_registers->completion_queue_lower);
2445 writel(upper_32_bits(dma), &ihost->smu_registers->completion_queue_upper);
Dan Williamscc9203b2011-05-08 17:34:44 -07002446
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002447 size = ihost->remote_node_entries * sizeof(union scu_remote_node_context);
2448 ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &dma,
Dan Williams89a73012011-06-30 19:14:33 -07002449 GFP_KERNEL);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002450 if (!ihost->remote_node_context_table)
Dan Williamscc9203b2011-05-08 17:34:44 -07002451 return -ENOMEM;
2452
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002453 writel(lower_32_bits(dma), &ihost->smu_registers->remote_node_context_lower);
2454 writel(upper_32_bits(dma), &ihost->smu_registers->remote_node_context_upper);
Dan Williamscc9203b2011-05-08 17:34:44 -07002455
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002456 size = ihost->task_context_entries * sizeof(struct scu_task_context),
2457 ihost->task_context_table = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2458 if (!ihost->task_context_table)
Dan Williamscc9203b2011-05-08 17:34:44 -07002459 return -ENOMEM;
2460
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002461 ihost->task_context_dma = dma;
2462 writel(lower_32_bits(dma), &ihost->smu_registers->host_task_table_lower);
2463 writel(upper_32_bits(dma), &ihost->smu_registers->host_task_table_upper);
Dan Williamscc9203b2011-05-08 17:34:44 -07002464
Dan Williams89a73012011-06-30 19:14:33 -07002465 err = sci_unsolicited_frame_control_construct(ihost);
Dan Williams7c78da32011-06-01 16:00:01 -07002466 if (err)
2467 return err;
Dan Williamscc9203b2011-05-08 17:34:44 -07002468
2469 /*
2470 * Inform the silicon as to the location of the UF headers and
2471 * address table.
2472 */
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002473 writel(lower_32_bits(ihost->uf_control.headers.physical_address),
2474 &ihost->scu_registers->sdma.uf_header_base_address_lower);
2475 writel(upper_32_bits(ihost->uf_control.headers.physical_address),
2476 &ihost->scu_registers->sdma.uf_header_base_address_upper);
Dan Williamscc9203b2011-05-08 17:34:44 -07002477
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002478 writel(lower_32_bits(ihost->uf_control.address_table.physical_address),
2479 &ihost->scu_registers->sdma.uf_address_table_lower);
2480 writel(upper_32_bits(ihost->uf_control.address_table.physical_address),
2481 &ihost->scu_registers->sdma.uf_address_table_upper);
Dan Williamscc9203b2011-05-08 17:34:44 -07002482
2483 return 0;
2484}
2485
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002486int isci_host_init(struct isci_host *ihost)
Dan Williams6f231dd2011-07-02 22:56:22 -07002487{
Dan Williamsd9c37392011-03-03 17:59:32 -08002488 int err = 0, i;
Dan Williams6f231dd2011-07-02 22:56:22 -07002489 enum sci_status status;
Dan Williams89a73012011-06-30 19:14:33 -07002490 struct sci_user_parameters sci_user_params;
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002491 struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
Dan Williams6f231dd2011-07-02 22:56:22 -07002492
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002493 spin_lock_init(&ihost->state_lock);
2494 spin_lock_init(&ihost->scic_lock);
2495 init_waitqueue_head(&ihost->eventq);
Dan Williams6f231dd2011-07-02 22:56:22 -07002496
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002497 isci_host_change_state(ihost, isci_starting);
Dan Williams6f231dd2011-07-02 22:56:22 -07002498
Dan Williams89a73012011-06-30 19:14:33 -07002499 status = sci_controller_construct(ihost, scu_base(ihost),
2500 smu_base(ihost));
Dan Williams6f231dd2011-07-02 22:56:22 -07002501
2502 if (status != SCI_SUCCESS) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002503 dev_err(&ihost->pdev->dev,
Dan Williams89a73012011-06-30 19:14:33 -07002504 "%s: sci_controller_construct failed - status = %x\n",
Dan Williams6f231dd2011-07-02 22:56:22 -07002505 __func__,
2506 status);
Dave Jiang858d4aa2011-02-22 01:27:03 -08002507 return -ENODEV;
Dan Williams6f231dd2011-07-02 22:56:22 -07002508 }
2509
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002510 ihost->sas_ha.dev = &ihost->pdev->dev;
2511 ihost->sas_ha.lldd_ha = ihost;
Dan Williams6f231dd2011-07-02 22:56:22 -07002512
Dan Williamsd044af12011-03-08 09:52:49 -08002513 /*
2514 * grab initial values stored in the controller object for OEM and USER
2515 * parameters
2516 */
Dan Williams89a73012011-06-30 19:14:33 -07002517 isci_user_parameters_get(&sci_user_params);
2518 status = sci_user_parameters_set(ihost, &sci_user_params);
Dan Williamsd044af12011-03-08 09:52:49 -08002519 if (status != SCI_SUCCESS) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002520 dev_warn(&ihost->pdev->dev,
Dan Williams89a73012011-06-30 19:14:33 -07002521 "%s: sci_user_parameters_set failed\n",
Dan Williamsd044af12011-03-08 09:52:49 -08002522 __func__);
2523 return -ENODEV;
2524 }
Dan Williams6f231dd2011-07-02 22:56:22 -07002525
Dan Williamsd044af12011-03-08 09:52:49 -08002526 /* grab any OEM parameters specified in orom */
2527 if (pci_info->orom) {
Dan Williams89a73012011-06-30 19:14:33 -07002528 status = isci_parse_oem_parameters(&ihost->oem_parameters,
Dan Williamsd044af12011-03-08 09:52:49 -08002529 pci_info->orom,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002530 ihost->id);
Dan Williams6f231dd2011-07-02 22:56:22 -07002531 if (status != SCI_SUCCESS) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002532 dev_warn(&ihost->pdev->dev,
Dan Williams6f231dd2011-07-02 22:56:22 -07002533 "parsing firmware oem parameters failed\n");
Dave Jiang858d4aa2011-02-22 01:27:03 -08002534 return -EINVAL;
Dan Williams6f231dd2011-07-02 22:56:22 -07002535 }
Dan Williams4711ba12011-03-11 10:43:57 -08002536 }
2537
Dan Williams89a73012011-06-30 19:14:33 -07002538 status = sci_oem_parameters_set(ihost);
Dan Williams4711ba12011-03-11 10:43:57 -08002539 if (status != SCI_SUCCESS) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002540 dev_warn(&ihost->pdev->dev,
Dan Williams89a73012011-06-30 19:14:33 -07002541 "%s: sci_oem_parameters_set failed\n",
Dan Williams4711ba12011-03-11 10:43:57 -08002542 __func__);
2543 return -ENODEV;
Dan Williams6f231dd2011-07-02 22:56:22 -07002544 }
2545
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002546 tasklet_init(&ihost->completion_tasklet,
2547 isci_host_completion_routine, (unsigned long)ihost);
Dan Williams6f231dd2011-07-02 22:56:22 -07002548
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002549 INIT_LIST_HEAD(&ihost->requests_to_complete);
2550 INIT_LIST_HEAD(&ihost->requests_to_errorback);
Dan Williams6f231dd2011-07-02 22:56:22 -07002551
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002552 spin_lock_irq(&ihost->scic_lock);
Dan Williams89a73012011-06-30 19:14:33 -07002553 status = sci_controller_initialize(ihost);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002554 spin_unlock_irq(&ihost->scic_lock);
Dan Williams7c40a802011-03-02 11:49:26 -08002555 if (status != SCI_SUCCESS) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002556 dev_warn(&ihost->pdev->dev,
Dan Williams89a73012011-06-30 19:14:33 -07002557 "%s: sci_controller_initialize failed -"
Dan Williams7c40a802011-03-02 11:49:26 -08002558 " status = 0x%x\n",
2559 __func__, status);
2560 return -ENODEV;
2561 }
2562
Dan Williams89a73012011-06-30 19:14:33 -07002563 err = sci_controller_mem_init(ihost);
Dan Williams6f231dd2011-07-02 22:56:22 -07002564 if (err)
Dave Jiang858d4aa2011-02-22 01:27:03 -08002565 return err;
Dan Williams6f231dd2011-07-02 22:56:22 -07002566
Dan Williamsd9c37392011-03-03 17:59:32 -08002567 for (i = 0; i < SCI_MAX_PORTS; i++)
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002568 isci_port_init(&ihost->ports[i], ihost, i);
Dan Williams6f231dd2011-07-02 22:56:22 -07002569
Dan Williamsd9c37392011-03-03 17:59:32 -08002570 for (i = 0; i < SCI_MAX_PHYS; i++)
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002571 isci_phy_init(&ihost->phys[i], ihost, i);
Dan Williamsd9c37392011-03-03 17:59:32 -08002572
Dan Williamsad4f4c12011-09-01 21:18:31 -07002573 /* enable sgpio */
2574 writel(1, &ihost->scu_registers->peg0.sgpio.interface_control);
2575 for (i = 0; i < isci_gpio_count(ihost); i++)
2576 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
2577 writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code);
2578
Dan Williamsd9c37392011-03-03 17:59:32 -08002579 for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002580 struct isci_remote_device *idev = &ihost->devices[i];
Dan Williamsd9c37392011-03-03 17:59:32 -08002581
2582 INIT_LIST_HEAD(&idev->reqs_in_process);
2583 INIT_LIST_HEAD(&idev->node);
Dan Williamsd9c37392011-03-03 17:59:32 -08002584 }
Dan Williams6f231dd2011-07-02 22:56:22 -07002585
Dan Williamsdb056252011-06-17 14:18:39 -07002586 for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) {
2587 struct isci_request *ireq;
2588 dma_addr_t dma;
2589
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002590 ireq = dmam_alloc_coherent(&ihost->pdev->dev,
Dan Williamsdb056252011-06-17 14:18:39 -07002591 sizeof(struct isci_request), &dma,
2592 GFP_KERNEL);
2593 if (!ireq)
2594 return -ENOMEM;
2595
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002596 ireq->tc = &ihost->task_context_table[i];
2597 ireq->owning_controller = ihost;
Dan Williamsdb056252011-06-17 14:18:39 -07002598 spin_lock_init(&ireq->state_lock);
2599 ireq->request_daddr = dma;
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002600 ireq->isci_host = ihost;
2601 ihost->reqs[i] = ireq;
Dan Williamsdb056252011-06-17 14:18:39 -07002602 }
2603
Dave Jiang858d4aa2011-02-22 01:27:03 -08002604 return 0;
Dan Williams6f231dd2011-07-02 22:56:22 -07002605}
Dan Williamscc9203b2011-05-08 17:34:44 -07002606
Dan Williams89a73012011-06-30 19:14:33 -07002607void sci_controller_link_up(struct isci_host *ihost, struct isci_port *iport,
2608 struct isci_phy *iphy)
Dan Williamscc9203b2011-05-08 17:34:44 -07002609{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002610 switch (ihost->sm.current_state_id) {
Edmund Nadolskie3013702011-06-02 00:10:43 +00002611 case SCIC_STARTING:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002612 sci_del_timer(&ihost->phy_timer);
2613 ihost->phy_startup_timer_pending = false;
2614 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
Dan Williams89a73012011-06-30 19:14:33 -07002615 iport, iphy);
2616 sci_controller_start_next_phy(ihost);
Dan Williamscc9203b2011-05-08 17:34:44 -07002617 break;
Edmund Nadolskie3013702011-06-02 00:10:43 +00002618 case SCIC_READY:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002619 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
Dan Williams89a73012011-06-30 19:14:33 -07002620 iport, iphy);
Dan Williamscc9203b2011-05-08 17:34:44 -07002621 break;
2622 default:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002623 dev_dbg(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -07002624 "%s: SCIC Controller linkup event from phy %d in "
Dan Williams85280952011-06-28 15:05:53 -07002625 "unexpected state %d\n", __func__, iphy->phy_index,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002626 ihost->sm.current_state_id);
Dan Williamscc9203b2011-05-08 17:34:44 -07002627 }
2628}
2629
Dan Williams89a73012011-06-30 19:14:33 -07002630void sci_controller_link_down(struct isci_host *ihost, struct isci_port *iport,
2631 struct isci_phy *iphy)
Dan Williamscc9203b2011-05-08 17:34:44 -07002632{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002633 switch (ihost->sm.current_state_id) {
Edmund Nadolskie3013702011-06-02 00:10:43 +00002634 case SCIC_STARTING:
2635 case SCIC_READY:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002636 ihost->port_agent.link_down_handler(ihost, &ihost->port_agent,
Dan Williamsffe191c2011-06-29 13:09:25 -07002637 iport, iphy);
Dan Williamscc9203b2011-05-08 17:34:44 -07002638 break;
2639 default:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002640 dev_dbg(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -07002641 "%s: SCIC Controller linkdown event from phy %d in "
2642 "unexpected state %d\n",
2643 __func__,
Dan Williams85280952011-06-28 15:05:53 -07002644 iphy->phy_index,
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002645 ihost->sm.current_state_id);
Dan Williamscc9203b2011-05-08 17:34:44 -07002646 }
2647}
2648
Dan Williams89a73012011-06-30 19:14:33 -07002649static bool sci_controller_has_remote_devices_stopping(struct isci_host *ihost)
Dan Williamscc9203b2011-05-08 17:34:44 -07002650{
2651 u32 index;
2652
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002653 for (index = 0; index < ihost->remote_node_entries; index++) {
2654 if ((ihost->device_table[index] != NULL) &&
2655 (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING))
Dan Williamscc9203b2011-05-08 17:34:44 -07002656 return true;
2657 }
2658
2659 return false;
2660}
2661
Dan Williams89a73012011-06-30 19:14:33 -07002662void sci_controller_remote_device_stopped(struct isci_host *ihost,
2663 struct isci_remote_device *idev)
Dan Williamscc9203b2011-05-08 17:34:44 -07002664{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002665 if (ihost->sm.current_state_id != SCIC_STOPPING) {
2666 dev_dbg(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -07002667 "SCIC Controller 0x%p remote device stopped event "
2668 "from device 0x%p in unexpected state %d\n",
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002669 ihost, idev,
2670 ihost->sm.current_state_id);
Dan Williamscc9203b2011-05-08 17:34:44 -07002671 return;
2672 }
2673
Dan Williams89a73012011-06-30 19:14:33 -07002674 if (!sci_controller_has_remote_devices_stopping(ihost))
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002675 sci_change_state(&ihost->sm, SCIC_STOPPED);
Dan Williamscc9203b2011-05-08 17:34:44 -07002676}
2677
Dan Williams89a73012011-06-30 19:14:33 -07002678void sci_controller_post_request(struct isci_host *ihost, u32 request)
Dan Williamscc9203b2011-05-08 17:34:44 -07002679{
Dan Williams89a73012011-06-30 19:14:33 -07002680 dev_dbg(&ihost->pdev->dev, "%s[%d]: %#x\n",
2681 __func__, ihost->id, request);
Dan Williamscc9203b2011-05-08 17:34:44 -07002682
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002683 writel(request, &ihost->smu_registers->post_context_port);
Dan Williamscc9203b2011-05-08 17:34:44 -07002684}
2685
Dan Williams89a73012011-06-30 19:14:33 -07002686struct isci_request *sci_request_by_tag(struct isci_host *ihost, u16 io_tag)
Dan Williamscc9203b2011-05-08 17:34:44 -07002687{
2688 u16 task_index;
2689 u16 task_sequence;
2690
Dan Williamsdd047c82011-06-09 11:06:58 -07002691 task_index = ISCI_TAG_TCI(io_tag);
Dan Williamscc9203b2011-05-08 17:34:44 -07002692
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002693 if (task_index < ihost->task_context_entries) {
2694 struct isci_request *ireq = ihost->reqs[task_index];
Dan Williamsdb056252011-06-17 14:18:39 -07002695
2696 if (test_bit(IREQ_ACTIVE, &ireq->flags)) {
Dan Williamsdd047c82011-06-09 11:06:58 -07002697 task_sequence = ISCI_TAG_SEQ(io_tag);
Dan Williamscc9203b2011-05-08 17:34:44 -07002698
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002699 if (task_sequence == ihost->io_request_sequence[task_index])
Dan Williams5076a1a2011-06-27 14:57:03 -07002700 return ireq;
Dan Williamscc9203b2011-05-08 17:34:44 -07002701 }
2702 }
2703
2704 return NULL;
2705}
2706
2707/**
2708 * This method allocates remote node index and the reserves the remote node
2709 * context space for use. This method can fail if there are no more remote
2710 * node index available.
2711 * @scic: This is the controller object which contains the set of
2712 * free remote node ids
2713 * @sci_dev: This is the device object which is requesting the a remote node
2714 * id
2715 * @node_id: This is the remote node id that is assinged to the device if one
2716 * is available
2717 *
2718 * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
2719 * node index available.
2720 */
Dan Williams89a73012011-06-30 19:14:33 -07002721enum sci_status sci_controller_allocate_remote_node_context(struct isci_host *ihost,
2722 struct isci_remote_device *idev,
2723 u16 *node_id)
Dan Williamscc9203b2011-05-08 17:34:44 -07002724{
2725 u16 node_index;
Dan Williams89a73012011-06-30 19:14:33 -07002726 u32 remote_node_count = sci_remote_device_node_count(idev);
Dan Williamscc9203b2011-05-08 17:34:44 -07002727
Dan Williams89a73012011-06-30 19:14:33 -07002728 node_index = sci_remote_node_table_allocate_remote_node(
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002729 &ihost->available_remote_nodes, remote_node_count
Dan Williamscc9203b2011-05-08 17:34:44 -07002730 );
2731
2732 if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002733 ihost->device_table[node_index] = idev;
Dan Williamscc9203b2011-05-08 17:34:44 -07002734
2735 *node_id = node_index;
2736
2737 return SCI_SUCCESS;
2738 }
2739
2740 return SCI_FAILURE_INSUFFICIENT_RESOURCES;
2741}
2742
Dan Williams89a73012011-06-30 19:14:33 -07002743void sci_controller_free_remote_node_context(struct isci_host *ihost,
2744 struct isci_remote_device *idev,
2745 u16 node_id)
Dan Williamscc9203b2011-05-08 17:34:44 -07002746{
Dan Williams89a73012011-06-30 19:14:33 -07002747 u32 remote_node_count = sci_remote_device_node_count(idev);
Dan Williamscc9203b2011-05-08 17:34:44 -07002748
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002749 if (ihost->device_table[node_id] == idev) {
2750 ihost->device_table[node_id] = NULL;
Dan Williamscc9203b2011-05-08 17:34:44 -07002751
Dan Williams89a73012011-06-30 19:14:33 -07002752 sci_remote_node_table_release_remote_node_index(
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002753 &ihost->available_remote_nodes, remote_node_count, node_id
Dan Williamscc9203b2011-05-08 17:34:44 -07002754 );
2755 }
2756}
2757
Dan Williams89a73012011-06-30 19:14:33 -07002758void sci_controller_copy_sata_response(void *response_buffer,
2759 void *frame_header,
2760 void *frame_buffer)
Dan Williamscc9203b2011-05-08 17:34:44 -07002761{
Dan Williams89a73012011-06-30 19:14:33 -07002762 /* XXX type safety? */
Dan Williamscc9203b2011-05-08 17:34:44 -07002763 memcpy(response_buffer, frame_header, sizeof(u32));
2764
2765 memcpy(response_buffer + sizeof(u32),
2766 frame_buffer,
2767 sizeof(struct dev_to_host_fis) - sizeof(u32));
2768}
2769
Dan Williams89a73012011-06-30 19:14:33 -07002770void sci_controller_release_frame(struct isci_host *ihost, u32 frame_index)
Dan Williamscc9203b2011-05-08 17:34:44 -07002771{
Dan Williams89a73012011-06-30 19:14:33 -07002772 if (sci_unsolicited_frame_control_release_frame(&ihost->uf_control, frame_index))
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002773 writel(ihost->uf_control.get,
2774 &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
Dan Williamscc9203b2011-05-08 17:34:44 -07002775}
2776
Dan Williams312e0c22011-06-28 13:47:09 -07002777void isci_tci_free(struct isci_host *ihost, u16 tci)
2778{
2779 u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1);
2780
2781 ihost->tci_pool[tail] = tci;
2782 ihost->tci_tail = tail + 1;
2783}
2784
2785static u16 isci_tci_alloc(struct isci_host *ihost)
2786{
2787 u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1);
2788 u16 tci = ihost->tci_pool[head];
2789
2790 ihost->tci_head = head + 1;
2791 return tci;
2792}
2793
2794static u16 isci_tci_space(struct isci_host *ihost)
2795{
2796 return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
2797}
2798
2799u16 isci_alloc_tag(struct isci_host *ihost)
2800{
2801 if (isci_tci_space(ihost)) {
2802 u16 tci = isci_tci_alloc(ihost);
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002803 u8 seq = ihost->io_request_sequence[tci];
Dan Williams312e0c22011-06-28 13:47:09 -07002804
2805 return ISCI_TAG(seq, tci);
2806 }
2807
2808 return SCI_CONTROLLER_INVALID_IO_TAG;
2809}
2810
2811enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
2812{
Dan Williams312e0c22011-06-28 13:47:09 -07002813 u16 tci = ISCI_TAG_TCI(io_tag);
2814 u16 seq = ISCI_TAG_SEQ(io_tag);
2815
2816 /* prevent tail from passing head */
2817 if (isci_tci_active(ihost) == 0)
2818 return SCI_FAILURE_INVALID_IO_TAG;
2819
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002820 if (seq == ihost->io_request_sequence[tci]) {
2821 ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1);
Dan Williams312e0c22011-06-28 13:47:09 -07002822
2823 isci_tci_free(ihost, tci);
2824
2825 return SCI_SUCCESS;
2826 }
2827 return SCI_FAILURE_INVALID_IO_TAG;
2828}
2829
Dan Williams89a73012011-06-30 19:14:33 -07002830enum sci_status sci_controller_start_io(struct isci_host *ihost,
2831 struct isci_remote_device *idev,
2832 struct isci_request *ireq)
Dan Williamscc9203b2011-05-08 17:34:44 -07002833{
2834 enum sci_status status;
2835
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002836 if (ihost->sm.current_state_id != SCIC_READY) {
2837 dev_warn(&ihost->pdev->dev, "invalid state to start I/O");
Dan Williamscc9203b2011-05-08 17:34:44 -07002838 return SCI_FAILURE_INVALID_STATE;
2839 }
2840
Dan Williams89a73012011-06-30 19:14:33 -07002841 status = sci_remote_device_start_io(ihost, idev, ireq);
Dan Williamscc9203b2011-05-08 17:34:44 -07002842 if (status != SCI_SUCCESS)
2843 return status;
2844
Dan Williams5076a1a2011-06-27 14:57:03 -07002845 set_bit(IREQ_ACTIVE, &ireq->flags);
Dan Williams34a99152011-07-01 02:25:15 -07002846 sci_controller_post_request(ihost, ireq->post_context);
Dan Williamscc9203b2011-05-08 17:34:44 -07002847 return SCI_SUCCESS;
2848}
2849
Dan Williams89a73012011-06-30 19:14:33 -07002850enum sci_status sci_controller_terminate_request(struct isci_host *ihost,
2851 struct isci_remote_device *idev,
2852 struct isci_request *ireq)
Dan Williamscc9203b2011-05-08 17:34:44 -07002853{
Dan Williams89a73012011-06-30 19:14:33 -07002854 /* terminate an ongoing (i.e. started) core IO request. This does not
2855 * abort the IO request at the target, but rather removes the IO
2856 * request from the host controller.
2857 */
Dan Williamscc9203b2011-05-08 17:34:44 -07002858 enum sci_status status;
2859
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002860 if (ihost->sm.current_state_id != SCIC_READY) {
2861 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -07002862 "invalid state to terminate request\n");
2863 return SCI_FAILURE_INVALID_STATE;
2864 }
2865
Dan Williams89a73012011-06-30 19:14:33 -07002866 status = sci_io_request_terminate(ireq);
Dan Williamscc9203b2011-05-08 17:34:44 -07002867 if (status != SCI_SUCCESS)
2868 return status;
2869
2870 /*
2871 * Utilize the original post context command and or in the POST_TC_ABORT
2872 * request sub-type.
2873 */
Dan Williams89a73012011-06-30 19:14:33 -07002874 sci_controller_post_request(ihost,
2875 ireq->post_context | SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
Dan Williamscc9203b2011-05-08 17:34:44 -07002876 return SCI_SUCCESS;
2877}
2878
2879/**
Dan Williams89a73012011-06-30 19:14:33 -07002880 * sci_controller_complete_io() - This method will perform core specific
Dan Williamscc9203b2011-05-08 17:34:44 -07002881 * completion operations for an IO request. After this method is invoked,
2882 * the user should consider the IO request as invalid until it is properly
2883 * reused (i.e. re-constructed).
Dan Williams89a73012011-06-30 19:14:33 -07002884 * @ihost: The handle to the controller object for which to complete the
Dan Williamscc9203b2011-05-08 17:34:44 -07002885 * IO request.
Dan Williams89a73012011-06-30 19:14:33 -07002886 * @idev: The handle to the remote device object for which to complete
Dan Williamscc9203b2011-05-08 17:34:44 -07002887 * the IO request.
Dan Williams89a73012011-06-30 19:14:33 -07002888 * @ireq: the handle to the io request object to complete.
Dan Williamscc9203b2011-05-08 17:34:44 -07002889 */
Dan Williams89a73012011-06-30 19:14:33 -07002890enum sci_status sci_controller_complete_io(struct isci_host *ihost,
2891 struct isci_remote_device *idev,
2892 struct isci_request *ireq)
Dan Williamscc9203b2011-05-08 17:34:44 -07002893{
2894 enum sci_status status;
2895 u16 index;
2896
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002897 switch (ihost->sm.current_state_id) {
Edmund Nadolskie3013702011-06-02 00:10:43 +00002898 case SCIC_STOPPING:
Dan Williamscc9203b2011-05-08 17:34:44 -07002899 /* XXX: Implement this function */
2900 return SCI_FAILURE;
Edmund Nadolskie3013702011-06-02 00:10:43 +00002901 case SCIC_READY:
Dan Williams89a73012011-06-30 19:14:33 -07002902 status = sci_remote_device_complete_io(ihost, idev, ireq);
Dan Williamscc9203b2011-05-08 17:34:44 -07002903 if (status != SCI_SUCCESS)
2904 return status;
2905
Dan Williams5076a1a2011-06-27 14:57:03 -07002906 index = ISCI_TAG_TCI(ireq->io_tag);
2907 clear_bit(IREQ_ACTIVE, &ireq->flags);
Dan Williamscc9203b2011-05-08 17:34:44 -07002908 return SCI_SUCCESS;
2909 default:
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002910 dev_warn(&ihost->pdev->dev, "invalid state to complete I/O");
Dan Williamscc9203b2011-05-08 17:34:44 -07002911 return SCI_FAILURE_INVALID_STATE;
2912 }
2913
2914}
2915
Dan Williams89a73012011-06-30 19:14:33 -07002916enum sci_status sci_controller_continue_io(struct isci_request *ireq)
Dan Williamscc9203b2011-05-08 17:34:44 -07002917{
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002918 struct isci_host *ihost = ireq->owning_controller;
Dan Williamscc9203b2011-05-08 17:34:44 -07002919
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002920 if (ihost->sm.current_state_id != SCIC_READY) {
2921 dev_warn(&ihost->pdev->dev, "invalid state to continue I/O");
Dan Williamscc9203b2011-05-08 17:34:44 -07002922 return SCI_FAILURE_INVALID_STATE;
2923 }
2924
Dan Williams5076a1a2011-06-27 14:57:03 -07002925 set_bit(IREQ_ACTIVE, &ireq->flags);
Dan Williams34a99152011-07-01 02:25:15 -07002926 sci_controller_post_request(ihost, ireq->post_context);
Dan Williamscc9203b2011-05-08 17:34:44 -07002927 return SCI_SUCCESS;
2928}
2929
2930/**
Dan Williams89a73012011-06-30 19:14:33 -07002931 * sci_controller_start_task() - This method is called by the SCIC user to
Dan Williamscc9203b2011-05-08 17:34:44 -07002932 * send/start a framework task management request.
2933 * @controller: the handle to the controller object for which to start the task
2934 * management request.
2935 * @remote_device: the handle to the remote device object for which to start
2936 * the task management request.
2937 * @task_request: the handle to the task request object to start.
Dan Williamscc9203b2011-05-08 17:34:44 -07002938 */
Dan Williams89a73012011-06-30 19:14:33 -07002939enum sci_task_status sci_controller_start_task(struct isci_host *ihost,
2940 struct isci_remote_device *idev,
2941 struct isci_request *ireq)
Dan Williamscc9203b2011-05-08 17:34:44 -07002942{
2943 enum sci_status status;
2944
Dan Williamsd9dcb4b2011-06-30 17:38:32 -07002945 if (ihost->sm.current_state_id != SCIC_READY) {
2946 dev_warn(&ihost->pdev->dev,
Dan Williamscc9203b2011-05-08 17:34:44 -07002947 "%s: SCIC Controller starting task from invalid "
2948 "state\n",
2949 __func__);
2950 return SCI_TASK_FAILURE_INVALID_STATE;
2951 }
2952
Dan Williams89a73012011-06-30 19:14:33 -07002953 status = sci_remote_device_start_task(ihost, idev, ireq);
Dan Williamscc9203b2011-05-08 17:34:44 -07002954 switch (status) {
2955 case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
Dan Williamsdb056252011-06-17 14:18:39 -07002956 set_bit(IREQ_ACTIVE, &ireq->flags);
Dan Williamscc9203b2011-05-08 17:34:44 -07002957
2958 /*
2959 * We will let framework know this task request started successfully,
2960 * although core is still woring on starting the request (to post tc when
2961 * RNC is resumed.)
2962 */
2963 return SCI_SUCCESS;
2964 case SCI_SUCCESS:
Dan Williamsdb056252011-06-17 14:18:39 -07002965 set_bit(IREQ_ACTIVE, &ireq->flags);
Dan Williams34a99152011-07-01 02:25:15 -07002966 sci_controller_post_request(ihost, ireq->post_context);
Dan Williamscc9203b2011-05-08 17:34:44 -07002967 break;
2968 default:
2969 break;
2970 }
2971
2972 return status;
2973}
Dan Williamsad4f4c12011-09-01 21:18:31 -07002974
2975static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data)
2976{
2977 int d;
2978
2979 /* no support for TX_GP_CFG */
2980 if (reg_index == 0)
2981 return -EINVAL;
2982
2983 for (d = 0; d < isci_gpio_count(ihost); d++) {
2984 u32 val = 0x444; /* all ODx.n clear */
2985 int i;
2986
2987 for (i = 0; i < 3; i++) {
2988 int bit = (i << 2) + 2;
2989
2990 bit = try_test_sas_gpio_gp_bit(to_sas_gpio_od(d, i),
2991 write_data, reg_index,
2992 reg_count);
2993 if (bit < 0)
2994 break;
2995
2996 /* if od is set, clear the 'invert' bit */
2997 val &= ~(bit << ((i << 2) + 2));
2998 }
2999
3000 if (i < 3)
3001 break;
3002 writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]);
3003 }
3004
3005 /* unless reg_index is > 1, we should always be able to write at
3006 * least one register
3007 */
3008 return d > 0;
3009}
3010
3011int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index,
3012 u8 reg_count, u8 *write_data)
3013{
3014 struct isci_host *ihost = sas_ha->lldd_ha;
3015 int written;
3016
3017 switch (reg_type) {
3018 case SAS_GPIO_REG_TX_GP:
3019 written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data);
3020 break;
3021 default:
3022 written = -EINVAL;
3023 }
3024
3025 return written;
3026}