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review.evervolv.com / android_kernel_oneplus_msm8996 / bb6e2fa3f511060c1d22e97b8df1de27e39cfdb3 / . / arch / arm / boot / dts / imx53.dtsi
blob: 1e8a9782371cb03fb43178356f1779dcdea965f8 [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]14#include "imx53-pinfunc.h"
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]15
16/ {
17 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]23 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
27 gpio4 = &gpio5;
28 gpio5 = &gpio6;
29 gpio6 = &gpio7;
Philipp Zabelc60dc1d2013-04-09 19:18:47 +0200[diff] [blame]30 i2c0 = &i2c1;
31 i2c1 = &i2c2;
32 i2c2 = &i2c3;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]33 };
34
35 tzic: tz-interrupt-controller@0fffc000 {
36 compatible = "fsl,imx53-tzic", "fsl,tzic";
37 interrupt-controller;
38 #interrupt-cells = <1>;
39 reg = <0x0fffc000 0x4000>;
40 };
41
42 clocks {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 ckil {
47 compatible = "fsl,imx-ckil", "fixed-clock";
48 clock-frequency = <32768>;
49 };
50
51 ckih1 {
52 compatible = "fsl,imx-ckih1", "fixed-clock";
53 clock-frequency = <22579200>;
54 };
55
56 ckih2 {
57 compatible = "fsl,imx-ckih2", "fixed-clock";
58 clock-frequency = <0>;
59 };
60
61 osc {
62 compatible = "fsl,imx-osc", "fixed-clock";
63 clock-frequency = <24000000>;
64 };
65 };
66
67 soc {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 interrupt-parent = <&tzic>;
72 ranges;
73
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]74 ipu: ipu@18000000 {
75 #crtc-cells = <1>;
76 compatible = "fsl,imx53-ipu";
77 reg = <0x18000000 0x080000000>;
78 interrupts = <11 10>;
Philipp Zabel4438a6a2013-03-27 18:30:36 +0100[diff] [blame]79 clocks = <&clks 59>, <&clks 110>, <&clks 61>;
80 clock-names = "bus", "di0", "di1";
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]81 resets = <&src 2>;
Sascha Hauerabed9a62012-06-05 13:52:10 +0200[diff] [blame]82 };
83
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]84 aips@50000000 { /* AIPS1 */
85 compatible = "fsl,aips-bus", "simple-bus";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 reg = <0x50000000 0x10000000>;
89 ranges;
90
91 spba@50000000 {
92 compatible = "fsl,spba-bus", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 reg = <0x50000000 0x40000>;
96 ranges;
97
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]98 esdhc1: esdhc@50004000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]99 compatible = "fsl,imx53-esdhc";
100 reg = <0x50004000 0x4000>;
101 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]102 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
103 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]104 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]105 status = "disabled";
106 };
107
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]108 esdhc2: esdhc@50008000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]109 compatible = "fsl,imx53-esdhc";
110 reg = <0x50008000 0x4000>;
111 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]112 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
113 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]114 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]115 status = "disabled";
116 };
117
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]118 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]119 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
120 reg = <0x5000c000 0x4000>;
121 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]122 clocks = <&clks 32>, <&clks 33>;
123 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]124 status = "disabled";
125 };
126
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]127 ecspi1: ecspi@50010000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]128 #address-cells = <1>;
129 #size-cells = <0>;
130 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
131 reg = <0x50010000 0x4000>;
132 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]133 clocks = <&clks 51>, <&clks 52>;
134 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]135 status = "disabled";
136 };
137
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]138 ssi2: ssi@50014000 {
139 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
140 reg = <0x50014000 0x4000>;
141 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]142 clocks = <&clks 49>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]143 fsl,fifo-depth = <15>;
144 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
145 status = "disabled";
146 };
147
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]148 esdhc3: esdhc@50020000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]149 compatible = "fsl,imx53-esdhc";
150 reg = <0x50020000 0x4000>;
151 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]152 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
153 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]154 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]155 status = "disabled";
156 };
157
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]158 esdhc4: esdhc@50024000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]159 compatible = "fsl,imx53-esdhc";
160 reg = <0x50024000 0x4000>;
161 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]162 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
163 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]164 bus-width = <4>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]165 status = "disabled";
166 };
167 };
168
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]169 usbphy0: usbphy@0 {
170 compatible = "usb-nop-xceiv";
171 clocks = <&clks 124>;
172 clock-names = "main_clk";
173 status = "okay";
174 };
175
176 usbphy1: usbphy@1 {
177 compatible = "usb-nop-xceiv";
178 clocks = <&clks 125>;
179 clock-names = "main_clk";
180 status = "okay";
181 };
182
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]183 usbotg: usb@53f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]184 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
185 reg = <0x53f80000 0x0200>;
186 interrupts = <18>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]187 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]188 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]189 fsl,usbphy = <&usbphy0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]190 status = "disabled";
191 };
192
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]193 usbh1: usb@53f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]194 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
195 reg = <0x53f80200 0x0200>;
196 interrupts = <14>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]197 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]198 fsl,usbmisc = <&usbmisc 1>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200[diff] [blame]199 fsl,usbphy = <&usbphy1>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]200 status = "disabled";
201 };
202
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]203 usbh2: usb@53f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]204 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
205 reg = <0x53f80400 0x0200>;
206 interrupts = <16>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]207 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]208 fsl,usbmisc = <&usbmisc 2>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]209 status = "disabled";
210 };
211
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]212 usbh3: usb@53f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]213 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
214 reg = <0x53f80600 0x0200>;
215 interrupts = <17>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]216 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]217 fsl,usbmisc = <&usbmisc 3>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]218 status = "disabled";
219 };
220
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]221 usbmisc: usbmisc@53f80800 {
222 #index-cells = <1>;
223 compatible = "fsl,imx53-usbmisc";
224 reg = <0x53f80800 0x200>;
Michael Grzeschik8e388902013-04-11 12:13:15 +0200[diff] [blame]225 clocks = <&clks 108>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200[diff] [blame]226 };
227
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]228 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]229 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]230 reg = <0x53f84000 0x4000>;
231 interrupts = <50 51>;
232 gpio-controller;
233 #gpio-cells = <2>;
234 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]235 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]236 };
237
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]238 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]239 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]240 reg = <0x53f88000 0x4000>;
241 interrupts = <52 53>;
242 gpio-controller;
243 #gpio-cells = <2>;
244 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]245 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]246 };
247
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]248 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]249 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]250 reg = <0x53f8c000 0x4000>;
251 interrupts = <54 55>;
252 gpio-controller;
253 #gpio-cells = <2>;
254 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]255 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]256 };
257
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]258 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]259 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]260 reg = <0x53f90000 0x4000>;
261 interrupts = <56 57>;
262 gpio-controller;
263 #gpio-cells = <2>;
264 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]265 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]266 };
267
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]268 wdog1: wdog@53f98000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]269 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
270 reg = <0x53f98000 0x4000>;
271 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]272 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]273 };
274
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]275 wdog2: wdog@53f9c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]276 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
277 reg = <0x53f9c000 0x4000>;
278 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]279 clocks = <&clks 0>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]280 status = "disabled";
281 };
282
Sascha Hauercc8aae92013-03-14 13:09:00 +0100[diff] [blame]283 gpt: timer@53fa0000 {
284 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
285 reg = <0x53fa0000 0x4000>;
286 interrupts = <39>;
287 clocks = <&clks 36>, <&clks 41>;
288 clock-names = "ipg", "per";
289 };
290
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]291 iomuxc: iomuxc@53fa8000 {
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]292 compatible = "fsl,imx53-iomuxc";
293 reg = <0x53fa8000 0x4000>;
294
295 audmux {
296 pinctrl_audmux_1: audmuxgrp-1 {
297 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]298 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
299 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
300 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
301 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]302 >;
303 };
Marek Vasutdd04c172013-04-21 23:30:01 +0200[diff] [blame]304
305 pinctrl_audmux_2: audmuxgrp-2 {
306 fsl,pins = <
307 MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
308 MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
309 MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
310 MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
311 >;
312 };
Steffen Trumtrarbb6e2fa2013-04-24 11:41:20 +0200[diff] [blame^]313
314 pinctrl_audmux_3: audmuxgrp-3 {
315 fsl,pins = <
316 MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
317 MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
318 MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
319 MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
320 >;
321 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]322 };
323
324 fec {
325 pinctrl_fec_1: fecgrp-1 {
326 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]327 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
328 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
329 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
330 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
331 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
332 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
333 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
334 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
335 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
336 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]337 >;
338 };
339 };
340
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]341 csi {
342 pinctrl_csi_1: csigrp-1 {
343 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]344 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5
345 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
346 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
347 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
348 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
349 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
350 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
351 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
352 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
353 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
354 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
355 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
356 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5
357 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5
358 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5
359 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5
360 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5
361 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5
362 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5
363 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5
364 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]365 >;
366 };
367 };
368
369 cspi {
370 pinctrl_cspi_1: cspigrp-1 {
371 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]372 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5
373 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5
374 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]375 >;
376 };
377 };
378
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]379 ecspi1 {
380 pinctrl_ecspi1_1: ecspi1grp-1 {
381 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]382 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
383 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
384 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]385 >;
386 };
387 };
388
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]389 esdhc1 {
390 pinctrl_esdhc1_1: esdhc1grp-1 {
391 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]392 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
393 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
394 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
395 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
396 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
397 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]398 >;
399 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]400
401 pinctrl_esdhc1_2: esdhc1grp-2 {
402 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]403 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
404 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
405 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
406 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
407 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5
408 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5
409 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5
410 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5
411 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
412 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]413 >;
414 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]415 };
416
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]417 esdhc2 {
418 pinctrl_esdhc2_1: esdhc2grp-1 {
419 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]420 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5
421 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5
422 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5
423 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5
424 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5
425 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]426 >;
427 };
428 };
429
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]430 esdhc3 {
431 pinctrl_esdhc3_1: esdhc3grp-1 {
432 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]433 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
434 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
435 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
436 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
437 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
438 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
439 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
440 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
441 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
442 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]443 >;
444 };
445 };
446
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]447 can1 {
448 pinctrl_can1_1: can1grp-1 {
449 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]450 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000
451 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]452 >;
453 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]454
455 pinctrl_can1_2: can1grp-2 {
456 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]457 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000
458 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]459 >;
460 };
Marek Vasut0f14ac42013-04-21 23:30:02 +0200[diff] [blame]461
462 pinctrl_can1_3: can1grp-3 {
463 fsl,pins = <
464 MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
465 MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
466 >;
467 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]468 };
469
470 can2 {
471 pinctrl_can2_1: can2grp-1 {
472 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]473 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000
474 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]475 >;
476 };
477 };
478
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]479 i2c1 {
480 pinctrl_i2c1_1: i2c1grp-1 {
481 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]482 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000
483 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]484 >;
485 };
Marek Vasutd7974712013-04-21 23:30:03 +0200[diff] [blame]486
487 pinctrl_i2c1_2: i2c1grp-2 {
488 fsl,pins = <
489 MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
490 MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
491 >;
492 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]493 };
494
495 i2c2 {
496 pinctrl_i2c2_1: i2c2grp-1 {
497 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]498 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
499 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]500 >;
501 };
Marek Vasuted5be462013-04-21 23:30:04 +0200[diff] [blame]502
503 pinctrl_i2c2_2: i2c2grp-2 {
504 fsl,pins = <
505 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
506 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
507 >;
508 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]509 };
510
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]511 i2c3 {
512 pinctrl_i2c3_1: i2c3grp-1 {
513 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]514 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
515 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]516 >;
517 };
518 };
519
Marek Vasut9f7fbb12013-04-21 23:30:06 +0200[diff] [blame]520 ipu_disp1 {
521 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
522 fsl,pins = <
523 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
524 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
525 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
526 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
527 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
528 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
529 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
530 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
531 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
532 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
533 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
534 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
535 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
536 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
537 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
538 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
539 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
540 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
541 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
542 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
543 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
544 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
545 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
546 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
547 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
548 MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
549 MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
550 MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
551 MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
552 MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
553 MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
554 MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
555 >;
556 };
557 };
558
559 ipu_disp2 {
560 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
561 fsl,pins = <
562 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
563 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
564 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
565 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
566 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
567 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
568 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
569 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
570 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
571 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
572 >;
573 };
574 };
575
Marek Vasutefee5e12013-04-21 23:30:05 +0200[diff] [blame]576 nand {
577 pinctrl_nand_1: nandgrp-1 {
578 fsl,pins = <
579 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
580 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
581 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
582 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
583 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
584 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
585 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
586 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
587 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
588 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
589 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
590 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
591 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
592 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
593 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
594 >;
595 };
596 };
597
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]598 owire {
599 pinctrl_owire_1: owiregrp-1 {
600 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]601 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]602 >;
603 };
604 };
605
Marek Vasut95050492013-04-21 23:30:07 +0200[diff] [blame]606 pwm1 {
607 pinctrl_pwm1_1: pwm1grp-1 {
608 fsl,pins = <
609 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
610 >;
611 };
612 };
613
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]614 uart1 {
615 pinctrl_uart1_1: uart1grp-1 {
616 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]617 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5
618 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]619 >;
620 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]621
622 pinctrl_uart1_2: uart1grp-2 {
623 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]624 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5
625 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]626 >;
627 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]628 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]629
630 uart2 {
631 pinctrl_uart2_1: uart2grp-1 {
632 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]633 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
634 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]635 >;
636 };
637 };
638
639 uart3 {
640 pinctrl_uart3_1: uart3grp-1 {
641 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]642 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
643 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
644 MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5
645 MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]646 >;
647 };
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]648
649 pinctrl_uart3_2: uart3grp-2 {
650 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]651 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5
652 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5
Steffen Trumtrar11ab21e2013-01-09 14:44:23 +0100[diff] [blame]653 >;
654 };
655
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]656 };
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]657
658 uart4 {
659 pinctrl_uart4_1: uart4grp-1 {
660 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]661 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5
662 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]663 >;
664 };
665 };
666
667 uart5 {
668 pinctrl_uart5_1: uart5grp-1 {
669 fsl,pins = <
Shawn Guoe1641532013-02-20 10:32:52 +0800[diff] [blame]670 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5
671 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5
Roland Stiggea1fff232012-10-25 13:26:39 +0200[diff] [blame]672 >;
673 };
674 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]675 };
676
Philipp Zabel5af9f142013-03-27 18:30:43 +0100[diff] [blame]677 gpr: iomuxc-gpr@53fa8000 {
678 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
679 reg = <0x53fa8000 0xc>;
680 };
681
Philipp Zabel420714a2013-03-27 18:30:44 +0100[diff] [blame]682 ldb: ldb@53fa8008 {
683 #address-cells = <1>;
684 #size-cells = <0>;
685 compatible = "fsl,imx53-ldb";
686 reg = <0x53fa8008 0x4>;
687 gpr = <&gpr>;
688 clocks = <&clks 122>, <&clks 120>,
689 <&clks 115>, <&clks 116>,
690 <&clks 123>, <&clks 85>;
691 clock-names = "di0_pll", "di1_pll",
692 "di0_sel", "di1_sel",
693 "di0", "di1";
694 status = "disabled";
695
696 lvds-channel@0 {
697 reg = <0>;
698 crtcs = <&ipu 0>;
699 status = "disabled";
700 };
701
702 lvds-channel@1 {
703 reg = <1>;
704 crtcs = <&ipu 1>;
705 status = "disabled";
706 };
707 };
708
Sascha Hauer9ae90af2012-07-04 12:30:37 +0200[diff] [blame]709 pwm1: pwm@53fb4000 {
710 #pwm-cells = <2>;
711 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
712 reg = <0x53fb4000 0x4000>;
713 clocks = <&clks 37>, <&clks 38>;
714 clock-names = "ipg", "per";
715 interrupts = <61>;
716 };
717
718 pwm2: pwm@53fb8000 {
719 #pwm-cells = <2>;
720 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
721 reg = <0x53fb8000 0x4000>;
722 clocks = <&clks 39>, <&clks 40>;
723 clock-names = "ipg", "per";
724 interrupts = <94>;
725 };
726
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]727 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]728 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
729 reg = <0x53fbc000 0x4000>;
730 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]731 clocks = <&clks 28>, <&clks 29>;
732 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]733 status = "disabled";
734 };
735
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]736 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]737 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
738 reg = <0x53fc0000 0x4000>;
739 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]740 clocks = <&clks 30>, <&clks 31>;
741 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]742 status = "disabled";
743 };
744
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]745 can1: can@53fc8000 {
746 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
747 reg = <0x53fc8000 0x4000>;
748 interrupts = <82>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]749 clocks = <&clks 158>, <&clks 157>;
750 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]751 status = "disabled";
752 };
753
754 can2: can@53fcc000 {
755 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
756 reg = <0x53fcc000 0x4000>;
757 interrupts = <83>;
Marek Vasute37f0d52013-01-07 15:27:00 +0100[diff] [blame]758 clocks = <&clks 87>, <&clks 86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]759 clock-names = "ipg", "per";
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]760 status = "disabled";
761 };
762
Philipp Zabel8d84c372013-03-28 17:35:23 +0100[diff] [blame]763 src: src@53fd0000 {
764 compatible = "fsl,imx53-src", "fsl,imx51-src";
765 reg = <0x53fd0000 0x4000>;
766 #reset-cells = <1>;
767 };
768
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]769 clks: ccm@53fd4000{
770 compatible = "fsl,imx53-ccm";
771 reg = <0x53fd4000 0x4000>;
772 interrupts = <0 71 0x04 0 72 0x04>;
773 #clock-cells = <1>;
774 };
775
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]776 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]777 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]778 reg = <0x53fdc000 0x4000>;
779 interrupts = <103 104>;
780 gpio-controller;
781 #gpio-cells = <2>;
782 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]783 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]784 };
785
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]786 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]787 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]788 reg = <0x53fe0000 0x4000>;
789 interrupts = <105 106>;
790 gpio-controller;
791 #gpio-cells = <2>;
792 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]793 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]794 };
795
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]796 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]797 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]798 reg = <0x53fe4000 0x4000>;
799 interrupts = <107 108>;
800 gpio-controller;
801 #gpio-cells = <2>;
802 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]803 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]804 };
805
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]806 i2c3: i2c@53fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]807 #address-cells = <1>;
808 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]809 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]810 reg = <0x53fec000 0x4000>;
811 interrupts = <64>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]812 clocks = <&clks 88>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]813 status = "disabled";
814 };
815
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]816 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]817 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
818 reg = <0x53ff0000 0x4000>;
819 interrupts = <13>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]820 clocks = <&clks 65>, <&clks 66>;
821 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]822 status = "disabled";
823 };
824 };
825
826 aips@60000000 { /* AIPS2 */
827 compatible = "fsl,aips-bus", "simple-bus";
828 #address-cells = <1>;
829 #size-cells = <1>;
830 reg = <0x60000000 0x10000000>;
831 ranges;
832
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]833 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]834 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
835 reg = <0x63f90000 0x4000>;
836 interrupts = <86>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]837 clocks = <&clks 67>, <&clks 68>;
838 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]839 status = "disabled";
840 };
841
Martin Fuzzeya82b7b92013-01-29 16:46:19 +0100[diff] [blame]842 owire: owire@63fa4000 {
843 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
844 reg = <0x63fa4000 0x4000>;
845 clocks = <&clks 159>;
846 status = "disabled";
847 };
848
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]849 ecspi2: ecspi@63fac000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]850 #address-cells = <1>;
851 #size-cells = <0>;
852 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
853 reg = <0x63fac000 0x4000>;
854 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]855 clocks = <&clks 53>, <&clks 54>;
856 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]857 status = "disabled";
858 };
859
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]860 sdma: sdma@63fb0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]861 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
862 reg = <0x63fb0000 0x4000>;
863 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]864 clocks = <&clks 56>, <&clks 56>;
865 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]866 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]867 };
868
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]869 cspi: cspi@63fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]870 #address-cells = <1>;
871 #size-cells = <0>;
872 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
873 reg = <0x63fc0000 0x4000>;
874 interrupts = <38>;
Jonas Andersson37523dc2013-05-23 13:38:05 +0200[diff] [blame]875 clocks = <&clks 55>, <&clks 55>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]876 clock-names = "ipg", "per";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]877 status = "disabled";
878 };
879
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]880 i2c2: i2c@63fc4000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]881 #address-cells = <1>;
882 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]883 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]884 reg = <0x63fc4000 0x4000>;
885 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]886 clocks = <&clks 35>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]887 status = "disabled";
888 };
889
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]890 i2c1: i2c@63fc8000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]891 #address-cells = <1>;
892 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]893 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]894 reg = <0x63fc8000 0x4000>;
895 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]896 clocks = <&clks 34>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]897 status = "disabled";
898 };
899
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]900 ssi1: ssi@63fcc000 {
901 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
902 reg = <0x63fcc000 0x4000>;
903 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]904 clocks = <&clks 48>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]905 fsl,fifo-depth = <15>;
906 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
907 status = "disabled";
908 };
909
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]910 audmux: audmux@63fd0000 {
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]911 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
912 reg = <0x63fd0000 0x4000>;
913 status = "disabled";
914 };
915
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]916 nfc: nand@63fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]917 compatible = "fsl,imx53-nand";
918 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
919 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]920 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]921 status = "disabled";
922 };
923
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]924 ssi3: ssi@63fe8000 {
925 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
926 reg = <0x63fe8000 0x4000>;
927 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]928 clocks = <&clks 50>;
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]929 fsl,fifo-depth = <15>;
930 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
931 status = "disabled";
932 };
933
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]934 fec: ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]935 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
936 reg = <0x63fec000 0x4000>;
937 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]938 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
939 clock-names = "ipg", "ahb", "ptp";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]940 status = "disabled";
941 };
942 };
943 };
944};