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Catalin Marinas8ad68bb2005-10-31 14:25:02 +00001/*
2 * linux/include/asm-arm/arch-realview/platform.h
3 *
4 * Copyright (c) ARM Limited 2003. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
Catalin Marinas356cb472008-02-04 17:34:58 +010021#ifndef __ASM_ARCH_PLATFORM_H
22#define __ASM_ARCH_PLATFORM_H
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000023
24/*
25 * Memory definitions
26 */
27#define REALVIEW_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/
28#define REALVIEW_BOOT_ROM_HI 0x30000000
29#define REALVIEW_BOOT_ROM_BASE REALVIEW_BOOT_ROM_HI /* Normal position */
30#define REALVIEW_BOOT_ROM_SIZE SZ_64M
31
32#define REALVIEW_SSRAM_BASE /* REALVIEW_SSMC_BASE ? */
33#define REALVIEW_SSRAM_SIZE SZ_2M
34
35#define REALVIEW_FLASH_BASE 0x40000000
36#define REALVIEW_FLASH_SIZE SZ_64M
37
38/*
39 * SDRAM
40 */
41#define REALVIEW_SDRAM_BASE 0x00000000
42
43/*
44 * Logic expansion modules
45 *
46 */
47
48
49/* ------------------------------------------------------------------------
50 * RealView Registers
51 * ------------------------------------------------------------------------
52 *
53 */
54#define REALVIEW_SYS_ID_OFFSET 0x00
55#define REALVIEW_SYS_SW_OFFSET 0x04
56#define REALVIEW_SYS_LED_OFFSET 0x08
57#define REALVIEW_SYS_OSC0_OFFSET 0x0C
58
59#define REALVIEW_SYS_OSC1_OFFSET 0x10
60#define REALVIEW_SYS_OSC2_OFFSET 0x14
61#define REALVIEW_SYS_OSC3_OFFSET 0x18
62#define REALVIEW_SYS_OSC4_OFFSET 0x1C /* OSC1 for RealView/AB */
63
64#define REALVIEW_SYS_LOCK_OFFSET 0x20
65#define REALVIEW_SYS_100HZ_OFFSET 0x24
66#define REALVIEW_SYS_CFGDATA1_OFFSET 0x28
67#define REALVIEW_SYS_CFGDATA2_OFFSET 0x2C
68#define REALVIEW_SYS_FLAGS_OFFSET 0x30
69#define REALVIEW_SYS_FLAGSSET_OFFSET 0x30
70#define REALVIEW_SYS_FLAGSCLR_OFFSET 0x34
71#define REALVIEW_SYS_NVFLAGS_OFFSET 0x38
72#define REALVIEW_SYS_NVFLAGSSET_OFFSET 0x38
73#define REALVIEW_SYS_NVFLAGSCLR_OFFSET 0x3C
74#define REALVIEW_SYS_RESETCTL_OFFSET 0x40
75#define REALVIEW_SYS_PCICTL_OFFSET 0x44
76#define REALVIEW_SYS_MCI_OFFSET 0x48
77#define REALVIEW_SYS_FLASH_OFFSET 0x4C
78#define REALVIEW_SYS_CLCD_OFFSET 0x50
79#define REALVIEW_SYS_CLCDSER_OFFSET 0x54
80#define REALVIEW_SYS_BOOTCS_OFFSET 0x58
81#define REALVIEW_SYS_24MHz_OFFSET 0x5C
82#define REALVIEW_SYS_MISC_OFFSET 0x60
83#define REALVIEW_SYS_IOSEL_OFFSET 0x70
Catalin Marinas356cb472008-02-04 17:34:58 +010084#define REALVIEW_SYS_PROCID_OFFSET 0x84
85#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
86#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
87#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
88#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
89#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
Catalin Marinas8ad68bb2005-10-31 14:25:02 +000090
91#define REALVIEW_SYS_BASE 0x10000000
92#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
93#define REALVIEW_SYS_SW (REALVIEW_SYS_BASE + REALVIEW_SYS_SW_OFFSET)
94#define REALVIEW_SYS_LED (REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET)
95#define REALVIEW_SYS_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC0_OFFSET)
96#define REALVIEW_SYS_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_OSC1_OFFSET)
97
98#define REALVIEW_SYS_LOCK (REALVIEW_SYS_BASE + REALVIEW_SYS_LOCK_OFFSET)
99#define REALVIEW_SYS_100HZ (REALVIEW_SYS_BASE + REALVIEW_SYS_100HZ_OFFSET)
100#define REALVIEW_SYS_CFGDATA1 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA1_OFFSET)
101#define REALVIEW_SYS_CFGDATA2 (REALVIEW_SYS_BASE + REALVIEW_SYS_CFGDATA2_OFFSET)
102#define REALVIEW_SYS_FLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGS_OFFSET)
103#define REALVIEW_SYS_FLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSSET_OFFSET)
104#define REALVIEW_SYS_FLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_FLAGSCLR_OFFSET)
105#define REALVIEW_SYS_NVFLAGS (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGS_OFFSET)
106#define REALVIEW_SYS_NVFLAGSSET (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSSET_OFFSET)
107#define REALVIEW_SYS_NVFLAGSCLR (REALVIEW_SYS_BASE + REALVIEW_SYS_NVFLAGSCLR_OFFSET)
108#define REALVIEW_SYS_RESETCTL (REALVIEW_SYS_BASE + REALVIEW_SYS_RESETCTL_OFFSET)
109#define REALVIEW_SYS_PCICTL (REALVIEW_SYS_BASE + REALVIEW_SYS_PCICTL_OFFSET)
110#define REALVIEW_SYS_MCI (REALVIEW_SYS_BASE + REALVIEW_SYS_MCI_OFFSET)
111#define REALVIEW_SYS_FLASH (REALVIEW_SYS_BASE + REALVIEW_SYS_FLASH_OFFSET)
112#define REALVIEW_SYS_CLCD (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCD_OFFSET)
113#define REALVIEW_SYS_CLCDSER (REALVIEW_SYS_BASE + REALVIEW_SYS_CLCDSER_OFFSET)
114#define REALVIEW_SYS_BOOTCS (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
115#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
116#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
117#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
Catalin Marinas356cb472008-02-04 17:34:58 +0100118#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000119#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
120#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
121#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
122#define REALVIEW_SYS_TEST_OSC3 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC3_OFFSET)
123#define REALVIEW_SYS_TEST_OSC4 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC4_OFFSET)
124
125/*
126 * Values for REALVIEW_SYS_RESET_CTRL
127 */
128#define REALVIEW_SYS_CTRL_RESET_CONFIGCLR 0x01
129#define REALVIEW_SYS_CTRL_RESET_CONFIGINIT 0x02
130#define REALVIEW_SYS_CTRL_RESET_DLLRESET 0x03
131#define REALVIEW_SYS_CTRL_RESET_PLLRESET 0x04
132#define REALVIEW_SYS_CTRL_RESET_POR 0x05
133#define REALVIEW_SYS_CTRL_RESET_DoC 0x06
134
135#define REALVIEW_SYS_CTRL_LED (1 << 0)
136
137
138/* ------------------------------------------------------------------------
139 * RealView control registers
140 * ------------------------------------------------------------------------
141 */
142
143/*
144 * REALVIEW_IDFIELD
145 *
146 * 31:24 = manufacturer (0x41 = ARM)
147 * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
148 * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
149 * 11:4 = build value
150 * 3:0 = revision number (0x1 = rev B (AHB))
151 */
152
153/*
154 * REALVIEW_SYS_LOCK
155 * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL,
156 * SYS_CLD, SYS_BOOTCS
157 */
158#define REALVIEW_SYS_LOCK_LOCKED (1 << 16)
159#define REALVIEW_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */
160
161/*
162 * REALVIEW_SYS_FLASH
163 */
164#define REALVIEW_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */
165
166/*
167 * REALVIEW_INTREG
168 * - used to acknowledge and control MMCI and UART interrupts
169 */
170#define REALVIEW_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */
171#define REALVIEW_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */
172#define REALVIEW_INTREG_CARDIN 0x08 /* MMCI card in detect */
173 /* write 1 to acknowledge and clear */
174#define REALVIEW_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */
175#define REALVIEW_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */
176
177/*
178 * REALVIEW peripheral addresses
179 */
180#define REALVIEW_SCTL_BASE 0x10001000 /* System controller */
181#define REALVIEW_I2C_BASE 0x10002000 /* I2C control */
182 /* Reserved 0x10003000 */
183#define REALVIEW_AACI_BASE 0x10004000 /* Audio */
184#define REALVIEW_MMCI0_BASE 0x10005000 /* MMC interface */
185#define REALVIEW_KMI0_BASE 0x10006000 /* KMI interface */
186#define REALVIEW_KMI1_BASE 0x10007000 /* KMI 2nd interface */
187#define REALVIEW_CHAR_LCD_BASE 0x10008000 /* Character LCD */
188#define REALVIEW_UART0_BASE 0x10009000 /* UART 0 */
189#define REALVIEW_UART1_BASE 0x1000A000 /* UART 1 */
190#define REALVIEW_UART2_BASE 0x1000B000 /* UART 2 */
191#define REALVIEW_UART3_BASE 0x1000C000 /* UART 3 */
192#define REALVIEW_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
193#define REALVIEW_SCI_BASE 0x1000E000 /* Smart card controller */
194 /* Reserved 0x1000F000 */
195#define REALVIEW_WATCHDOG_BASE 0x10010000 /* watchdog interface */
196#define REALVIEW_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
197#define REALVIEW_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
198#define REALVIEW_GPIO0_BASE 0x10013000 /* GPIO port 0 */
199#define REALVIEW_GPIO1_BASE 0x10014000 /* GPIO port 1 */
200#define REALVIEW_GPIO2_BASE 0x10015000 /* GPIO port 2 */
201 /* Reserved 0x10016000 */
202#define REALVIEW_RTC_BASE 0x10017000 /* Real Time Clock */
203#define REALVIEW_DMC_BASE 0x10018000 /* DMC configuration */
204#define REALVIEW_PCI_CORE_BASE 0x10019000 /* PCI configuration */
205 /* Reserved 0x1001A000 - 0x1001FFFF */
206#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
207#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
208#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
209#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
210#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
211 /* Reserved 0x10090000 - 0x100EFFFF */
212
213#define REALVIEW_ETH_BASE 0x4E000000 /* Ethernet */
214
215/* PCI space */
216#define REALVIEW_PCI_BASE 0x41000000 /* PCI Interface */
217#define REALVIEW_PCI_CFG_BASE 0x42000000
218#define REALVIEW_PCI_MEM_BASE0 0x44000000
219#define REALVIEW_PCI_MEM_BASE1 0x50000000
220#define REALVIEW_PCI_MEM_BASE2 0x60000000
221/* Sizes of above maps */
222#define REALVIEW_PCI_BASE_SIZE 0x01000000
223#define REALVIEW_PCI_CFG_BASE_SIZE 0x02000000
224#define REALVIEW_PCI_MEM_BASE0_SIZE 0x0c000000 /* 32Mb */
225#define REALVIEW_PCI_MEM_BASE1_SIZE 0x10000000 /* 256Mb */
226#define REALVIEW_PCI_MEM_BASE2_SIZE 0x10000000 /* 256Mb */
227
228#define REALVIEW_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */
229#define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */
230
231/*
232 * Disk on Chip
233 */
234#define REALVIEW_DOC_BASE 0x2C000000
235#define REALVIEW_DOC_SIZE (16 << 20)
236#define REALVIEW_DOC_PAGE_SIZE 512
237#define REALVIEW_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE)
238
239#define ERASE_UNIT_PAGES 32
240#define START_PAGE 0x80
241
242/*
243 * LED settings, bits [7:0]
244 */
245#define REALVIEW_SYS_LED0 (1 << 0)
246#define REALVIEW_SYS_LED1 (1 << 1)
247#define REALVIEW_SYS_LED2 (1 << 2)
248#define REALVIEW_SYS_LED3 (1 << 3)
249#define REALVIEW_SYS_LED4 (1 << 4)
250#define REALVIEW_SYS_LED5 (1 << 5)
251#define REALVIEW_SYS_LED6 (1 << 6)
252#define REALVIEW_SYS_LED7 (1 << 7)
253
254#define ALL_LEDS 0xFF
255
256#define LED_BANK REALVIEW_SYS_LED
257
258/*
259 * Control registers
260 */
261#define REALVIEW_IDFIELD_OFFSET 0x0 /* RealView build information */
262#define REALVIEW_FLASHPROG_OFFSET 0x4 /* Flash devices */
263#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
264#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
265
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000266/*
267 * Application Flash
268 *
269 */
270#define FLASH_BASE REALVIEW_FLASH_BASE
271#define FLASH_SIZE REALVIEW_FLASH_SIZE
272#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
273#define FLASH_BLOCK_SIZE SZ_128K
274
275/*
276 * Boot Flash
277 *
278 */
279#define EPROM_BASE REALVIEW_BOOT_ROM_HI
280#define EPROM_SIZE REALVIEW_BOOT_ROM_SIZE
281#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
282
283/*
284 * Clean base - dummy
285 *
286 */
287#define CLEAN_BASE EPROM_BASE
288
289/*
290 * System controller bit assignment
291 */
292#define REALVIEW_REFCLK 0
293#define REALVIEW_TIMCLK 1
294
295#define REALVIEW_TIMER1_EnSel 15
296#define REALVIEW_TIMER2_EnSel 17
297#define REALVIEW_TIMER3_EnSel 19
298#define REALVIEW_TIMER4_EnSel 21
299
300
301#define MAX_TIMER 2
302#define MAX_PERIOD 699050
303#define TICKS_PER_uSEC 1
304
305/*
306 * These are useconds NOT ticks.
307 *
308 */
309#define mSEC_1 1000
310#define mSEC_5 (mSEC_1 * 5)
311#define mSEC_10 (mSEC_1 * 10)
312#define mSEC_25 (mSEC_1 * 25)
313#define SEC_1 (mSEC_1 * 1000)
314
315#define REALVIEW_CSR_BASE 0x10000000
316#define REALVIEW_CSR_SIZE 0x10000000
317
Catalin Marinas356cb472008-02-04 17:34:58 +0100318#endif /* __ASM_ARCH_PLATFORM_H */