| Stephen Warren | be944d4 | 2012-04-10 16:31:59 -0600 | [diff] [blame] | 1 | NVIDIA Tegra30 AHUB (Audio Hub) |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible : "nvidia,tegra30-ahub" |
| 5 | - reg : Should contain the register physical address and length for each of |
| 6 | the AHUB's APBIF registers and the AHUB's own registers. |
| 7 | - interrupts : Should contain AHUB interrupt |
| 8 | - nvidia,dma-request-selector : The Tegra DMA controller's phandle and |
| 9 | request selector for the first APBIF channel. |
| 10 | - ranges : The bus address mapping for the configlink register bus. |
| 11 | Can be empty since the mapping is 1:1. |
| 12 | - #address-cells : For the configlink bus. Should be <1>; |
| 13 | - #size-cells : For the configlink bus. Should be <1>. |
| 14 | |
| 15 | AHUB client modules need to specify the IDs of their CIFs (Client InterFaces). |
| 16 | For RX CIFs, the numbers indicate the register number within AHUB routing |
| 17 | register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1). |
| 18 | For TX CIFs, the numbers indicate the bit position within the AHUB routing |
| 19 | registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1). |
| 20 | |
| 21 | Example: |
| 22 | |
| 23 | ahub@70080000 { |
| 24 | compatible = "nvidia,tegra30-ahub"; |
| 25 | reg = <0x70080000 0x200 0x70080200 0x100>; |
| 26 | interrupts = < 0 103 0x04 >; |
| 27 | nvidia,dma-request-selector = <&apbdma 1>; |
| 28 | |
| 29 | ranges; |
| 30 | #address-cells = <1>; |
| 31 | #size-cells = <1>; |
| 32 | }; |