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Bastian Hecht33419a62013-01-09 19:41:51 +00001/*
2 * SMP support for SoC sh73a0
3 *
4 * Copyright (C) 2012 Bastian Hecht
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#include <linux/linkage.h>
23#include <linux/init.h>
24#include <asm/memory.h>
25
26 __CPUINIT
27/*
28 * Reset vector for secondary CPUs.
29 *
30 * First we turn on L1 cache coherency for our CPU. Then we jump to
31 * shmobile_invalidate_start that invalidates the cache and hands over control
32 * to the common ARM startup code.
33 * This function will be mapped to address 0 by the SBAR register.
34 * A normal branch is out of range here so we need a long jump. We jump to
35 * the physical address as the MMU is still turned off.
36 */
37 .align 12
38ENTRY(sh73a0_secondary_vector)
39 mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
40 and r0, r0, #3 @ mask out cpu ID
41 lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
42 mov r1, #0xf0000000 @ SCU base address
43 ldr r2, [r1, #8] @ SCU Power Status Register
44 mov r3, #3
45 bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
46 str r2, [r1, #8] @ write back
47
48 ldr pc, 1f
491: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
50ENDPROC(sh73a0_secondary_vector)