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review.evervolv.com / android_kernel_oneplus_msm8996 / c04abb3a07b56db4756b6f970609e65a8624b0a3 / . / arch / arm / boot / dts / tegra20.dtsi
blob: 0e371f92d1d260624411ee4518504a11a1833202 [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
4 compatible = "nvidia,tegra20";
5 interrupt-parent = <&intc>;
6
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]7 intc: interrupt-controller {
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]8 compatible = "arm,cortex-a9-gic";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]9 interrupt-controller;
pdeschrijver@nvidia.com0d4f7472011-11-29 18:29:19 -0700[diff] [blame]10 #interrupt-cells = <3>;
Stephen Warren5ff48882012-05-11 16:26:03 -0600[diff] [blame]11 reg = <0x50041000 0x1000
12 0x50040100 0x0100>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]13 };
14
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]15 apbdma: dma {
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]16 compatible = "nvidia,tegra20-apbdma";
17 reg = <0x6000a000 0x1200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]18 interrupts = <0 104 0x04
19 0 105 0x04
20 0 106 0x04
21 0 107 0x04
22 0 108 0x04
23 0 109 0x04
24 0 110 0x04
25 0 111 0x04
26 0 112 0x04
27 0 113 0x04
28 0 114 0x04
29 0 115 0x04
30 0 116 0x04
31 0 117 0x04
32 0 118 0x04
33 0 119 0x04>;
Stephen Warren8051b752012-01-11 16:09:54 -0700[diff] [blame]34 };
35
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame^]36 ahb {
37 compatible = "nvidia,tegra20-ahb";
38 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]39 };
40
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]41 gpio: gpio {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]42 compatible = "nvidia,tegra20-gpio";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]43 reg = <0x6000d000 0x1000>;
44 interrupts = <0 32 0x04
45 0 33 0x04
46 0 34 0x04
47 0 35 0x04
48 0 55 0x04
49 0 87 0x04
50 0 89 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]51 #gpio-cells = <2>;
52 gpio-controller;
Stephen Warren6f74dc92012-01-04 08:39:37 +0000[diff] [blame]53 #interrupt-cells = <2>;
54 interrupt-controller;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]55 };
56
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]57 pinmux: pinmux {
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]58 compatible = "nvidia,tegra20-pinmux";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]59 reg = <0x70000014 0x10 /* Tri-state registers */
60 0x70000080 0x20 /* Mux registers */
61 0x700000a0 0x14 /* Pull-up/down registers */
62 0x70000868 0xa8>; /* Pad control registers */
Stephen Warrenf62f5482011-10-11 16:16:13 -0600[diff] [blame]63 };
64
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame^]65 das {
66 compatible = "nvidia,tegra20-das";
67 reg = <0x70000c00 0x80>;
68 };
69
70 tegra_i2s1: i2s@70002800 {
71 compatible = "nvidia,tegra20-i2s";
72 reg = <0x70002800 0x200>;
73 interrupts = <0 13 0x04>;
74 nvidia,dma-request-selector = <&apbdma 2>;
75 };
76
77 tegra_i2s2: i2s@70002a00 {
78 compatible = "nvidia,tegra20-i2s";
79 reg = <0x70002a00 0x200>;
80 interrupts = <0 3 0x04>;
81 nvidia,dma-request-selector = <&apbdma 1>;
82 };
83
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]84 serial@70006000 {
85 compatible = "nvidia,tegra20-uart";
86 reg = <0x70006000 0x40>;
87 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]88 interrupts = <0 36 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]89 };
90
91 serial@70006040 {
92 compatible = "nvidia,tegra20-uart";
93 reg = <0x70006040 0x40>;
94 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]95 interrupts = <0 37 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]96 };
97
98 serial@70006200 {
99 compatible = "nvidia,tegra20-uart";
100 reg = <0x70006200 0x100>;
101 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]102 interrupts = <0 46 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]103 };
104
105 serial@70006300 {
106 compatible = "nvidia,tegra20-uart";
107 reg = <0x70006300 0x100>;
108 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]109 interrupts = <0 90 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]110 };
111
112 serial@70006400 {
113 compatible = "nvidia,tegra20-uart";
114 reg = <0x70006400 0x100>;
115 reg-shift = <2>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]116 interrupts = <0 91 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]117 };
118
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame^]119 i2c@7000c000 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 compatible = "nvidia,tegra20-i2c";
123 reg = <0x7000c000 0x100>;
124 interrupts = <0 38 0x04>;
125 };
126
127 i2c@7000c400 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 compatible = "nvidia,tegra20-i2c";
131 reg = <0x7000c400 0x100>;
132 interrupts = <0 84 0x04>;
133 };
134
135 i2c@7000c500 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 compatible = "nvidia,tegra20-i2c";
139 reg = <0x7000c500 0x100>;
140 interrupts = <0 92 0x04>;
141 };
142
143 i2c@7000d000 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 compatible = "nvidia,tegra20-i2c-dvc";
147 reg = <0x7000d000 0x200>;
148 interrupts = <0 53 0x04>;
149 };
150
151 pmc {
152 compatible = "nvidia,tegra20-pmc";
153 reg = <0x7000e400 0x400>;
154 };
155
156 mc {
157 compatible = "nvidia,tegra20-mc";
158 reg = <0x7000f000 0x024
159 0x7000f03c 0x3c4>;
160 interrupts = <0 77 0x04>;
161 };
162
163 gart {
164 compatible = "nvidia,tegra20-gart";
165 reg = <0x7000f024 0x00000018 /* controller registers */
166 0x58000000 0x02000000>; /* GART aperture */
167 };
168
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]169 emc {
Olof Johansson0c6700a2011-10-13 02:14:55 -0700[diff] [blame]170 #address-cells = <1>;
171 #size-cells = <0>;
172 compatible = "nvidia,tegra20-emc";
173 reg = <0x7000f400 0x200>;
174 };
175
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame^]176 usb@c5000000 {
177 compatible = "nvidia,tegra20-ehci", "usb-ehci";
178 reg = <0xc5000000 0x4000>;
179 interrupts = <0 20 0x04>;
180 phy_type = "utmi";
181 nvidia,has-legacy-mode;
182 };
183
184 usb@c5004000 {
185 compatible = "nvidia,tegra20-ehci", "usb-ehci";
186 reg = <0xc5004000 0x4000>;
187 interrupts = <0 21 0x04>;
188 phy_type = "ulpi";
189 };
190
191 usb@c5008000 {
192 compatible = "nvidia,tegra20-ehci", "usb-ehci";
193 reg = <0xc5008000 0x4000>;
194 interrupts = <0 97 0x04>;
195 phy_type = "utmi";
196 };
197
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]198 sdhci@c8000000 {
199 compatible = "nvidia,tegra20-sdhci";
200 reg = <0xc8000000 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]201 interrupts = <0 14 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]202 };
203
204 sdhci@c8000200 {
205 compatible = "nvidia,tegra20-sdhci";
206 reg = <0xc8000200 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]207 interrupts = <0 15 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]208 };
209
210 sdhci@c8000400 {
211 compatible = "nvidia,tegra20-sdhci";
212 reg = <0xc8000400 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]213 interrupts = <0 19 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]214 };
215
216 sdhci@c8000600 {
217 compatible = "nvidia,tegra20-sdhci";
218 reg = <0xc8000600 0x200>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]219 interrupts = <0 31 0x04>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]220 };
Olof Johanssonc27317c2011-11-04 09:12:39 +0000[diff] [blame]221
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame^]222 pmu {
223 compatible = "arm,cortex-a9-pmu";
224 interrupts = <0 56 0x04
225 0 57 0x04>;
hdoyu@nvidia.com6a943e02012-05-09 21:45:33 +0000[diff] [blame]226 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]227};