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review.evervolv.com / android_kernel_oneplus_msm8996 / c0b6cc499c1a214b51bac45d2c74ba66953efedc / . / arch / arm / boot / dts / am33xx.dtsi
blob: c2f14e875eb6274b18fc159e8e773395aca6df87 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]15 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]16
17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
23 serial5 = &uart6;
24 };
25
26 cpus {
27 cpu@0 {
28 compatible = "arm,cortex-a8";
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]29
30 /*
31 * To consider voltage drop between PMIC and SoC,
32 * tolerance value is reduced to 2% from 4% and
33 * voltage value is increased as a precaution.
34 */
35 operating-points = <
36 /* kHz uV */
37 720000 1285000
38 600000 1225000
39 500000 1125000
40 275000 1125000
41 >;
42 voltage-tolerance = <2>; /* 2 percentage */
43 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]44 };
45 };
46
47 /*
48 * The soc node represents the soc top level view. It is uses for IPs
49 * that are not memory mapped in the MPU view or for the MPU itself.
50 */
51 soc {
52 compatible = "ti,omap-infra";
53 mpu {
54 compatible = "ti,omap3-mpu";
55 ti,hwmods = "mpu";
56 };
57 };
58
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]59 am33xx_pinmux: pinmux@44e10800 {
60 compatible = "pinctrl-single";
61 reg = <0x44e10800 0x0238>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64 pinctrl-single,register-width = <32>;
65 pinctrl-single,function-mask = <0x7f>;
66 };
67
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]68 /*
69 * XXX: Use a flat representation of the AM33XX interconnect.
70 * The real AM33XX interconnect network is quite complex.Since
71 * that will not bring real advantage to represent that in DT
72 * for the moment, just use a fake OCP bus entry to represent
73 * the whole bus hierarchy.
74 */
75 ocp {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80 ti,hwmods = "l3_main";
81
82 intc: interrupt-controller@48200000 {
83 compatible = "ti,omap2-intc";
84 interrupt-controller;
85 #interrupt-cells = <1>;
86 ti,intc-size = <128>;
87 reg = <0x48200000 0x1000>;
88 };
89
90 gpio1: gpio@44e07000 {
91 compatible = "ti,omap4-gpio";
92 ti,hwmods = "gpio1";
93 gpio-controller;
94 #gpio-cells = <2>;
95 interrupt-controller;
96 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]97 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]98 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]99 };
100
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]101 gpio2: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]102 compatible = "ti,omap4-gpio";
103 ti,hwmods = "gpio2";
104 gpio-controller;
105 #gpio-cells = <2>;
106 interrupt-controller;
107 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]108 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]109 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]110 };
111
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]112 gpio3: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]113 compatible = "ti,omap4-gpio";
114 ti,hwmods = "gpio3";
115 gpio-controller;
116 #gpio-cells = <2>;
117 interrupt-controller;
118 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]119 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]120 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]121 };
122
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]123 gpio4: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]124 compatible = "ti,omap4-gpio";
125 ti,hwmods = "gpio4";
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]130 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]131 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]132 };
133
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]134 uart1: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]135 compatible = "ti,omap3-uart";
136 ti,hwmods = "uart1";
137 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]138 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]139 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]140 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]141 };
142
143 uart2: serial@48022000 {
144 compatible = "ti,omap3-uart";
145 ti,hwmods = "uart2";
146 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]147 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]148 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]149 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]150 };
151
152 uart3: serial@48024000 {
153 compatible = "ti,omap3-uart";
154 ti,hwmods = "uart3";
155 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]156 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]157 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]158 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]159 };
160
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]161 uart4: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]162 compatible = "ti,omap3-uart";
163 ti,hwmods = "uart4";
164 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]165 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]166 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]167 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]168 };
169
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]170 uart5: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]171 compatible = "ti,omap3-uart";
172 ti,hwmods = "uart5";
173 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]174 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]175 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]176 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]177 };
178
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]179 uart6: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]180 compatible = "ti,omap3-uart";
181 ti,hwmods = "uart6";
182 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]183 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]184 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]185 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]186 };
187
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]188 i2c1: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]189 compatible = "ti,omap4-i2c";
190 #address-cells = <1>;
191 #size-cells = <0>;
192 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]193 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]194 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]195 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]196 };
197
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]198 i2c2: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]199 compatible = "ti,omap4-i2c";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]203 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]204 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]205 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]206 };
207
Vaibhav Hiremath5d83cb82012-08-27 16:59:08 +0530[diff] [blame]208 i2c3: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]209 compatible = "ti,omap4-i2c";
210 #address-cells = <1>;
211 #size-cells = <0>;
212 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]213 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]214 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]215 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]216 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]217
218 wdt2: wdt@44e35000 {
219 compatible = "ti,omap3-wdt";
220 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]221 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]222 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]223 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]224
225 dcan0: d_can@481cc000 {
226 compatible = "bosch,d_can";
227 ti,hwmods = "d_can0";
228 reg = <0x481cc000 0x2000>;
229 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]230 status = "disabled";
231 };
232
233 dcan1: d_can@481d0000 {
234 compatible = "bosch,d_can";
235 ti,hwmods = "d_can1";
236 reg = <0x481d0000 0x2000>;
237 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]238 status = "disabled";
239 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]240
241 timer1: timer@44e31000 {
242 compatible = "ti,omap2-timer";
243 reg = <0x44e31000 0x400>;
244 interrupts = <67>;
245 ti,hwmods = "timer1";
246 ti,timer-alwon;
247 };
248
249 timer2: timer@48040000 {
250 compatible = "ti,omap2-timer";
251 reg = <0x48040000 0x400>;
252 interrupts = <68>;
253 ti,hwmods = "timer2";
254 };
255
256 timer3: timer@48042000 {
257 compatible = "ti,omap2-timer";
258 reg = <0x48042000 0x400>;
259 interrupts = <69>;
260 ti,hwmods = "timer3";
261 };
262
263 timer4: timer@48044000 {
264 compatible = "ti,omap2-timer";
265 reg = <0x48044000 0x400>;
266 interrupts = <92>;
267 ti,hwmods = "timer4";
268 ti,timer-pwm;
269 };
270
271 timer5: timer@48046000 {
272 compatible = "ti,omap2-timer";
273 reg = <0x48046000 0x400>;
274 interrupts = <93>;
275 ti,hwmods = "timer5";
276 ti,timer-pwm;
277 };
278
279 timer6: timer@48048000 {
280 compatible = "ti,omap2-timer";
281 reg = <0x48048000 0x400>;
282 interrupts = <94>;
283 ti,hwmods = "timer6";
284 ti,timer-pwm;
285 };
286
287 timer7: timer@4804a000 {
288 compatible = "ti,omap2-timer";
289 reg = <0x4804a000 0x400>;
290 interrupts = <95>;
291 ti,hwmods = "timer7";
292 ti,timer-pwm;
293 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]294
295 rtc@44e3e000 {
296 compatible = "ti,da830-rtc";
297 reg = <0x44e3e000 0x1000>;
298 interrupts = <75
299 76>;
300 ti,hwmods = "rtc";
301 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]302
303 spi0: spi@48030000 {
304 compatible = "ti,omap4-mcspi";
305 #address-cells = <1>;
306 #size-cells = <0>;
307 reg = <0x48030000 0x400>;
308 interrupt = <65>;
309 ti,spi-num-cs = <2>;
310 ti,hwmods = "spi0";
311 status = "disabled";
312 };
313
314 spi1: spi@481a0000 {
315 compatible = "ti,omap4-mcspi";
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <0x481a0000 0x400>;
319 interrupt = <125>;
320 ti,spi-num-cs = <2>;
321 ti,hwmods = "spi1";
322 status = "disabled";
323 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]324
325 usb@47400000 {
326 compatible = "ti,musb-am33xx";
327 reg = <0x47400000 0x1000 /* usbss */
328 0x47401000 0x800 /* musb instance 0 */
329 0x47401800 0x800>; /* musb instance 1 */
330 interrupts = <17 /* usbss */
331 18 /* musb instance 0 */
332 19>; /* musb instance 1 */
333 multipoint = <1>;
334 num-eps = <16>;
335 ram-bits = <12>;
336 port0-mode = <3>;
337 port1-mode = <3>;
338 power = <250>;
339 ti,hwmods = "usb_otg_hs";
340 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]341
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]342 mac: ethernet@4a100000 {
343 compatible = "ti,cpsw";
344 ti,hwmods = "cpgmac0";
345 cpdma_channels = <8>;
346 ale_entries = <1024>;
347 bd_ram_size = <0x2000>;
348 no_bd_ram = <0>;
349 rx_descs = <64>;
350 mac_control = <0x20>;
351 slaves = <2>;
352 cpts_active_slave = <0>;
353 cpts_clock_mult = <0x80000000>;
354 cpts_clock_shift = <29>;
355 reg = <0x4a100000 0x800
356 0x4a101200 0x100>;
357 #address-cells = <1>;
358 #size-cells = <1>;
359 interrupt-parent = <&intc>;
360 /*
361 * c0_rx_thresh_pend
362 * c0_rx_pend
363 * c0_tx_pend
364 * c0_misc_pend
365 */
366 interrupts = <40 41 42 43>;
367 ranges;
368
369 davinci_mdio: mdio@4a101000 {
370 compatible = "ti,davinci_mdio";
371 #address-cells = <1>;
372 #size-cells = <0>;
373 ti,hwmods = "davinci_mdio";
374 bus_freq = <1000000>;
375 reg = <0x4a101000 0x100>;
376 };
377
378 cpsw_emac0: slave@4a100200 {
379 /* Filled in by U-Boot */
380 mac-address = [ 00 00 00 00 00 00 ];
381 };
382
383 cpsw_emac1: slave@4a100300 {
384 /* Filled in by U-Boot */
385 mac-address = [ 00 00 00 00 00 00 ];
386 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]387 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]388 };
389};