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review.evervolv.com / android_kernel_oneplus_msm8996 / c0b6cc499c1a214b51bac45d2c74ba66953efedc / . / arch / arm / boot / dts / armada-xp.dtsi
blob: 367aa3f94912ac9d78a35d22321c64667af406cf [file] [log] [blame]
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
Thomas Petazzoni10b683c2012-08-02 17:13:47 +0200[diff] [blame]15 * Contains definitions specific to the Armada XP SoC that are not
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]16 * common to all Armada SoCs.
17 */
18
19/include/ "armada-370-xp.dtsi"
20
21/ {
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
Gregory CLEMENT2f96fbb2012-09-26 18:02:49 +0200[diff] [blame]25 L2: l2-cache {
26 compatible = "marvell,aurora-system-cache";
27 reg = <0xd0008000 0x1000>;
28 cache-id-part = <0x100>;
29 wt-override;
30 };
31
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]32 mpic: interrupt-controller@d0020000 {
33 reg = <0xd0020a00 0x1d0>,
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300[diff] [blame]34 <0xd0021070 0x58>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]35 };
36
Gregory CLEMENT7444dad2012-08-02 11:17:51 +0300[diff] [blame]37 armada-370-xp-pmsu@d0022000 {
38 compatible = "marvell,armada-370-xp-pmsu";
39 reg = <0xd0022100 0x430>,
40 <0xd0020800 0x20>;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]41 };
42
43 soc {
44 serial@d0012200 {
45 compatible = "ns16550";
46 reg = <0xd0012200 0x100>;
47 reg-shift = <2>;
48 interrupts = <43>;
49 status = "disabled";
50 };
51 serial@d0012300 {
52 compatible = "ns16550";
53 reg = <0xd0012300 0x100>;
54 reg-shift = <2>;
55 interrupts = <44>;
56 status = "disabled";
57 };
58
59 timer@d0020300 {
60 marvell,timer-25Mhz;
61 };
62
Gregory CLEMENT9d202782012-11-17 15:22:24 +0100[diff] [blame]63 coreclk: mvebu-sar@d0018230 {
64 compatible = "marvell,armada-xp-core-clock";
65 reg = <0xd0018230 0x08>;
66 #clock-cells = <1>;
67 };
68
69 cpuclk: clock-complex@d0018700 {
70 #clock-cells = <1>;
71 compatible = "marvell,armada-xp-cpu-clock";
72 reg = <0xd0018700 0xA0>;
73 clocks = <&coreclk 1>;
74 };
75
76 gateclk: clock-gating-control@d0018220 {
77 compatible = "marvell,armada-xp-gating-clock";
78 reg = <0xd0018220 0x4>;
79 clocks = <&coreclk 0>;
80 #clock-cells = <1>;
81 };
82
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]83 system-controller@d0018200 {
84 compatible = "marvell,armada-370-xp-system-controller";
85 reg = <0xd0018200 0x500>;
86 };
Thomas Petazzoni323c1012012-09-04 15:06:43 +0200[diff] [blame]87
88 ethernet@d0030000 {
89 compatible = "marvell,armada-370-neta";
90 reg = <0xd0030000 0x2500>;
91 interrupts = <12>;
Thomas Petazzoni4aa935a2012-11-19 14:18:09 +0100[diff] [blame]92 clocks = <&gateclk 2>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +0200[diff] [blame]93 status = "disabled";
94 };
95
96 ethernet@d0034000 {
97 compatible = "marvell,armada-370-neta";
98 reg = <0xd0034000 0x2500>;
99 interrupts = <14>;
Thomas Petazzoni4aa935a2012-11-19 14:18:09 +0100[diff] [blame]100 clocks = <&gateclk 1>;
Thomas Petazzoni323c1012012-09-04 15:06:43 +0200[diff] [blame]101 status = "disabled";
102 };
Jason Cooper98d8df62012-11-21 19:57:23 +0000[diff] [blame]103
Thomas Petazzonia1d53da2012-11-20 16:03:19 +0100[diff] [blame]104 xor@d0060900 {
105 compatible = "marvell,orion-xor";
106 reg = <0xd0060900 0x100
107 0xd0060b00 0x100>;
108 clocks = <&gateclk 22>;
109 status = "okay";
110
111 xor10 {
112 interrupts = <51>;
113 dmacap,memcpy;
114 dmacap,xor;
115 };
116 xor11 {
117 interrupts = <52>;
118 dmacap,memcpy;
119 dmacap,xor;
120 dmacap,memset;
121 };
122 };
123
124 xor@d00f0900 {
125 compatible = "marvell,orion-xor";
126 reg = <0xd00F0900 0x100
127 0xd00F0B00 0x100>;
128 clocks = <&gateclk 28>;
129 status = "okay";
130
131 xor00 {
132 interrupts = <94>;
133 dmacap,memcpy;
134 dmacap,xor;
135 };
136 xor01 {
137 interrupts = <95>;
138 dmacap,memcpy;
139 dmacap,xor;
140 dmacap,memset;
141 };
142 };
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200[diff] [blame]143 };
144};