blob: d0c7a8b1c8859acdb8c37133e88a07ba8b774072 [file] [log] [blame]
Joseph Loc2be5bf2012-08-16 17:31:50 +08001/*
2 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __MACH_TEGRA_SLEEP_H
18#define __MACH_TEGRA_SLEEP_H
19
20#include <mach/iomap.h>
21
22#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
23 + IO_PPSB_VIRT)
24
25#ifdef __ASSEMBLY__
26/* returns the offset of the flow controller halt register for a cpu */
27.macro cpu_to_halt_reg rd, rcpu
28 cmp \rcpu, #0
29 subne \rd, \rcpu, #1
30 movne \rd, \rd, lsl #3
31 addne \rd, \rd, #0x14
32 moveq \rd, #0
33.endm
34
35/* returns the offset of the flow controller csr register for a cpu */
36.macro cpu_to_csr_reg rd, rcpu
37 cmp \rcpu, #0
38 subne \rd, \rcpu, #1
39 movne \rd, \rd, lsl #3
40 addne \rd, \rd, #0x18
41 moveq \rd, #8
42.endm
43
44/* returns the ID of the current processor */
45.macro cpu_id, rd
46 mrc p15, 0, \rd, c0, c0, 5
47 and \rd, \rd, #0xF
48.endm
49
50/* loads a 32-bit value into a register without a data access */
51.macro mov32, reg, val
52 movw \reg, #:lower16:\val
53 movt \reg, #:upper16:\val
54.endm
55#endif
56#endif