| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This program is free software; you can redistribute it and/or modify it |
| 3 | * under the terms of the GNU General Public License as published by the |
| 4 | * Free Software Foundation; either version 2 of the License, or (at your |
| 5 | * option) any later version. |
| 6 | * |
| 7 | * Galileo Technology chip interrupt handler |
| 8 | */ |
| 9 | #include <linux/interrupt.h> |
| 10 | #include <linux/kernel.h> |
| 11 | #include <linux/config.h> |
| 12 | #include <linux/sched.h> |
| 13 | #include <linux/kernel_stat.h> |
| 14 | #include <asm/ptrace.h> |
| 15 | #include <asm/gt64120.h> |
| 16 | |
| 17 | /* |
| 18 | * These are interrupt handlers for the GT on-chip interrupts. They all come |
| 19 | * in to the MIPS on a single interrupt line, and have to be handled and ack'ed |
| 20 | * differently than other MIPS interrupts. |
| 21 | */ |
| 22 | |
| 23 | static void gt64120_irq(int irq, void *dev_id, struct pt_regs *regs) |
| 24 | { |
| 25 | unsigned int irq_src, int_high_src, irq_src_mask, int_high_src_mask; |
| 26 | int handled = 0; |
| 27 | |
| 28 | irq_src = GT_READ(GT_INTRCAUSE_OFS); |
| 29 | irq_src_mask = GT_READ(GT_INTRMASK_OFS); |
| 30 | int_high_src = GT_READ(GT_HINTRCAUSE_OFS); |
| 31 | int_high_src_mask = GT_READ(GT_HINTRMASK_OFS); |
| 32 | irq_src = irq_src & irq_src_mask; |
| 33 | int_high_src = int_high_src & int_high_src_mask; |
| 34 | |
| 35 | if (irq_src & 0x00000800) { /* Check for timer interrupt */ |
| 36 | handled = 1; |
| 37 | irq_src &= ~0x00000800; |
| 38 | do_timer(regs); |
| 39 | #ifndef CONFIG_SMP |
| 40 | update_process_times(user_mode(regs)); |
| 41 | #endif |
| 42 | } |
| 43 | |
| 44 | GT_WRITE(GT_INTRCAUSE_OFS, 0); |
| 45 | GT_WRITE(GT_HINTRCAUSE_OFS, 0); |
| 46 | } |
| 47 | |
| 48 | /* |
| 49 | * Initializes timer using galileo's built in timer. |
| 50 | */ |
| 51 | #ifdef CONFIG_SYSCLK_100 |
| 52 | #define Sys_clock (100 * 1000000) // 100 MHz |
| 53 | #endif |
| 54 | #ifdef CONFIG_SYSCLK_83 |
| 55 | #define Sys_clock (83.333 * 1000000) // 83.333 MHz |
| 56 | #endif |
| 57 | #ifdef CONFIG_SYSCLK_75 |
| 58 | #define Sys_clock (75 * 1000000) // 75 MHz |
| 59 | #endif |
| 60 | |
| 61 | /* |
| 62 | * This will ignore the standard MIPS timer interrupt handler that is passed in |
| 63 | * as *irq (=irq0 in ../kernel/time.c). We will do our own timer interrupt |
| 64 | * handling. |
| 65 | */ |
| 66 | void gt64120_time_init(void) |
| 67 | { |
| 68 | static struct irqaction timer; |
| 69 | |
| 70 | /* Disable timer first */ |
| 71 | GT_WRITE(GT_TC_CONTROL_OFS, 0); |
| 72 | /* Load timer value for 100 Hz */ |
| 73 | GT_WRITE(GT_TC3_OFS, Sys_clock / 100); |
| 74 | |
| 75 | /* |
| 76 | * Create the IRQ structure entry for the timer. Since we're too early |
| 77 | * in the boot process to use the "request_irq()" call, we'll hard-code |
| 78 | * the values to the correct interrupt line. |
| 79 | */ |
| 80 | timer.handler = gt64120_irq; |
| 81 | timer.flags = SA_SHIRQ | SA_INTERRUPT; |
| 82 | timer.name = "timer"; |
| 83 | timer.dev_id = NULL; |
| 84 | timer.next = NULL; |
| 85 | timer.mask = CPU_MASK_NONE; |
| 86 | irq_desc[GT_TIMER].action = &timer; |
| 87 | |
| 88 | enable_irq(GT_TIMER); |
| 89 | |
| 90 | /* Enable timer ints */ |
| 91 | GT_WRITE(GT_TC_CONTROL_OFS, 0xc0); |
| 92 | /* clear Cause register first */ |
| 93 | GT_WRITE(GT_INTRCAUSE_OFS, 0x0); |
| 94 | /* Unmask timer int */ |
| 95 | GT_WRITE(GT_INTRMASK_OFS, 0x800); |
| 96 | /* Clear High int register */ |
| 97 | GT_WRITE(GT_HINTRCAUSE_OFS, 0x0); |
| 98 | /* Mask All interrupts at High cause interrupt */ |
| 99 | GT_WRITE(GT_HINTRMASK_OFS, 0x0); |
| 100 | } |