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review.evervolv.com / android_kernel_oneplus_msm8996 / c4b51a431561f0bacc1740aa27f080bf95c4d6c7 / . / arch / arm / boot / dts / am33xx.dtsi
blob: 38b446ba1ce104b42fce6b2737ba2c8755fda4a1 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef62013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
25 serial4 = &uart4;
26 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]27 d_can0 = &dcan0;
28 d_can1 = &dcan1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]29 };
30
31 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]32 #address-cells = <1>;
33 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]34 cpu@0 {
35 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]36 device_type = "cpu";
37 reg = <0>;
AnilKumar Chefeedcf2012-08-31 15:07:20 +0530[diff] [blame]38
39 /*
40 * To consider voltage drop between PMIC and SoC,
41 * tolerance value is reduced to 2% from 4% and
42 * voltage value is increased as a precaution.
43 */
44 operating-points = <
45 /* kHz uV */
46 720000 1285000
47 600000 1225000
48 500000 1125000
49 275000 1125000
50 >;
51 voltage-tolerance = <2>; /* 2 percentage */
52 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]53 };
54 };
55
56 /*
57 * The soc node represents the soc top level view. It is uses for IPs
58 * that are not memory mapped in the MPU view or for the MPU itself.
59 */
60 soc {
61 compatible = "ti,omap-infra";
62 mpu {
63 compatible = "ti,omap3-mpu";
64 ti,hwmods = "mpu";
65 };
66 };
67
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]68 am33xx_pinmux: pinmux@44e10800 {
69 compatible = "pinctrl-single";
70 reg = <0x44e10800 0x0238>;
71 #address-cells = <1>;
72 #size-cells = <0>;
73 pinctrl-single,register-width = <32>;
74 pinctrl-single,function-mask = <0x7f>;
75 };
76
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]77 /*
78 * XXX: Use a flat representation of the AM33XX interconnect.
79 * The real AM33XX interconnect network is quite complex.Since
80 * that will not bring real advantage to represent that in DT
81 * for the moment, just use a fake OCP bus entry to represent
82 * the whole bus hierarchy.
83 */
84 ocp {
85 compatible = "simple-bus";
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges;
89 ti,hwmods = "l3_main";
90
91 intc: interrupt-controller@48200000 {
92 compatible = "ti,omap2-intc";
93 interrupt-controller;
94 #interrupt-cells = <1>;
95 ti,intc-size = <128>;
96 reg = <0x48200000 0x1000>;
97 };
98
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]99 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]100 compatible = "ti,omap4-gpio";
101 ti,hwmods = "gpio1";
102 gpio-controller;
103 #gpio-cells = <2>;
104 interrupt-controller;
105 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]106 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]107 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]108 };
109
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]110 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]111 compatible = "ti,omap4-gpio";
112 ti,hwmods = "gpio2";
113 gpio-controller;
114 #gpio-cells = <2>;
115 interrupt-controller;
116 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]117 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]118 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]119 };
120
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]121 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]122 compatible = "ti,omap4-gpio";
123 ti,hwmods = "gpio3";
124 gpio-controller;
125 #gpio-cells = <2>;
126 interrupt-controller;
127 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]128 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]129 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]130 };
131
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]132 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]133 compatible = "ti,omap4-gpio";
134 ti,hwmods = "gpio4";
135 gpio-controller;
136 #gpio-cells = <2>;
137 interrupt-controller;
138 #interrupt-cells = <1>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]139 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]140 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]141 };
142
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]143 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]144 compatible = "ti,omap3-uart";
145 ti,hwmods = "uart1";
146 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]147 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]148 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]149 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]150 };
151
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]152 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]153 compatible = "ti,omap3-uart";
154 ti,hwmods = "uart2";
155 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]156 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]157 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]158 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]159 };
160
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]161 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]162 compatible = "ti,omap3-uart";
163 ti,hwmods = "uart3";
164 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]165 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]166 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]167 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]168 };
169
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]170 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]171 compatible = "ti,omap3-uart";
172 ti,hwmods = "uart4";
173 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]174 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]175 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]176 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]177 };
178
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]179 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]180 compatible = "ti,omap3-uart";
181 ti,hwmods = "uart5";
182 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]183 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]184 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]185 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]186 };
187
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]188 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]189 compatible = "ti,omap3-uart";
190 ti,hwmods = "uart6";
191 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]192 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]193 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]194 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]195 };
196
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]197 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]198 compatible = "ti,omap4-i2c";
199 #address-cells = <1>;
200 #size-cells = <0>;
201 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]202 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]203 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]204 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]205 };
206
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]207 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]208 compatible = "ti,omap4-i2c";
209 #address-cells = <1>;
210 #size-cells = <0>;
211 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]212 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]213 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]214 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]215 };
216
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]217 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]218 compatible = "ti,omap4-i2c";
219 #address-cells = <1>;
220 #size-cells = <0>;
221 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]222 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]223 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]224 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]225 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]226
227 wdt2: wdt@44e35000 {
228 compatible = "ti,omap3-wdt";
229 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]230 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]231 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]232 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]233
234 dcan0: d_can@481cc000 {
235 compatible = "bosch,d_can";
236 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]237 reg = <0x481cc000 0x2000
238 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]239 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]240 status = "disabled";
241 };
242
243 dcan1: d_can@481d0000 {
244 compatible = "bosch,d_can";
245 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]246 reg = <0x481d0000 0x2000
247 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]248 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]249 status = "disabled";
250 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]251
252 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]253 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]254 reg = <0x44e31000 0x400>;
255 interrupts = <67>;
256 ti,hwmods = "timer1";
257 ti,timer-alwon;
258 };
259
260 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]261 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]262 reg = <0x48040000 0x400>;
263 interrupts = <68>;
264 ti,hwmods = "timer2";
265 };
266
267 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]268 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]269 reg = <0x48042000 0x400>;
270 interrupts = <69>;
271 ti,hwmods = "timer3";
272 };
273
274 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]275 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]276 reg = <0x48044000 0x400>;
277 interrupts = <92>;
278 ti,hwmods = "timer4";
279 ti,timer-pwm;
280 };
281
282 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]283 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]284 reg = <0x48046000 0x400>;
285 interrupts = <93>;
286 ti,hwmods = "timer5";
287 ti,timer-pwm;
288 };
289
290 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]291 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]292 reg = <0x48048000 0x400>;
293 interrupts = <94>;
294 ti,hwmods = "timer6";
295 ti,timer-pwm;
296 };
297
298 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]299 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]300 reg = <0x4804a000 0x400>;
301 interrupts = <95>;
302 ti,hwmods = "timer7";
303 ti,timer-pwm;
304 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]305
306 rtc@44e3e000 {
307 compatible = "ti,da830-rtc";
308 reg = <0x44e3e000 0x1000>;
309 interrupts = <75
310 76>;
311 ti,hwmods = "rtc";
312 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]313
314 spi0: spi@48030000 {
315 compatible = "ti,omap4-mcspi";
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]319 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]320 ti,spi-num-cs = <2>;
321 ti,hwmods = "spi0";
322 status = "disabled";
323 };
324
325 spi1: spi@481a0000 {
326 compatible = "ti,omap4-mcspi";
327 #address-cells = <1>;
328 #size-cells = <0>;
329 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]330 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]331 ti,spi-num-cs = <2>;
332 ti,hwmods = "spi1";
333 status = "disabled";
334 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]335
336 usb@47400000 {
337 compatible = "ti,musb-am33xx";
338 reg = <0x47400000 0x1000 /* usbss */
339 0x47401000 0x800 /* musb instance 0 */
340 0x47401800 0x800>; /* musb instance 1 */
341 interrupts = <17 /* usbss */
342 18 /* musb instance 0 */
343 19>; /* musb instance 1 */
344 multipoint = <1>;
345 num-eps = <16>;
346 ram-bits = <12>;
347 port0-mode = <3>;
348 port1-mode = <3>;
349 power = <250>;
350 ti,hwmods = "usb_otg_hs";
351 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]352
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]353 epwmss0: epwmss@48300000 {
354 compatible = "ti,am33xx-pwmss";
355 reg = <0x48300000 0x10>;
356 ti,hwmods = "epwmss0";
357 #address-cells = <1>;
358 #size-cells = <1>;
359 status = "disabled";
360 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
361 0x48300180 0x48300180 0x80 /* EQEP */
362 0x48300200 0x48300200 0x80>; /* EHRPWM */
363
364 ecap0: ecap@48300100 {
365 compatible = "ti,am33xx-ecap";
366 #pwm-cells = <3>;
367 reg = <0x48300100 0x80>;
368 ti,hwmods = "ecap0";
369 status = "disabled";
370 };
371
372 ehrpwm0: ehrpwm@48300200 {
373 compatible = "ti,am33xx-ehrpwm";
374 #pwm-cells = <3>;
375 reg = <0x48300200 0x80>;
376 ti,hwmods = "ehrpwm0";
377 status = "disabled";
378 };
379 };
380
381 epwmss1: epwmss@48302000 {
382 compatible = "ti,am33xx-pwmss";
383 reg = <0x48302000 0x10>;
384 ti,hwmods = "epwmss1";
385 #address-cells = <1>;
386 #size-cells = <1>;
387 status = "disabled";
388 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
389 0x48302180 0x48302180 0x80 /* EQEP */
390 0x48302200 0x48302200 0x80>; /* EHRPWM */
391
392 ecap1: ecap@48302100 {
393 compatible = "ti,am33xx-ecap";
394 #pwm-cells = <3>;
395 reg = <0x48302100 0x80>;
396 ti,hwmods = "ecap1";
397 status = "disabled";
398 };
399
400 ehrpwm1: ehrpwm@48302200 {
401 compatible = "ti,am33xx-ehrpwm";
402 #pwm-cells = <3>;
403 reg = <0x48302200 0x80>;
404 ti,hwmods = "ehrpwm1";
405 status = "disabled";
406 };
407 };
408
409 epwmss2: epwmss@48304000 {
410 compatible = "ti,am33xx-pwmss";
411 reg = <0x48304000 0x10>;
412 ti,hwmods = "epwmss2";
413 #address-cells = <1>;
414 #size-cells = <1>;
415 status = "disabled";
416 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
417 0x48304180 0x48304180 0x80 /* EQEP */
418 0x48304200 0x48304200 0x80>; /* EHRPWM */
419
420 ecap2: ecap@48304100 {
421 compatible = "ti,am33xx-ecap";
422 #pwm-cells = <3>;
423 reg = <0x48304100 0x80>;
424 ti,hwmods = "ecap2";
425 status = "disabled";
426 };
427
428 ehrpwm2: ehrpwm@48304200 {
429 compatible = "ti,am33xx-ehrpwm";
430 #pwm-cells = <3>;
431 reg = <0x48304200 0x80>;
432 ti,hwmods = "ehrpwm2";
433 status = "disabled";
434 };
435 };
436
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]437 mac: ethernet@4a100000 {
438 compatible = "ti,cpsw";
439 ti,hwmods = "cpgmac0";
440 cpdma_channels = <8>;
441 ale_entries = <1024>;
442 bd_ram_size = <0x2000>;
443 no_bd_ram = <0>;
444 rx_descs = <64>;
445 mac_control = <0x20>;
446 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]447 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]448 cpts_clock_mult = <0x80000000>;
449 cpts_clock_shift = <29>;
450 reg = <0x4a100000 0x800
451 0x4a101200 0x100>;
452 #address-cells = <1>;
453 #size-cells = <1>;
454 interrupt-parent = <&intc>;
455 /*
456 * c0_rx_thresh_pend
457 * c0_rx_pend
458 * c0_tx_pend
459 * c0_misc_pend
460 */
461 interrupts = <40 41 42 43>;
462 ranges;
463
464 davinci_mdio: mdio@4a101000 {
465 compatible = "ti,davinci_mdio";
466 #address-cells = <1>;
467 #size-cells = <0>;
468 ti,hwmods = "davinci_mdio";
469 bus_freq = <1000000>;
470 reg = <0x4a101000 0x100>;
471 };
472
473 cpsw_emac0: slave@4a100200 {
474 /* Filled in by U-Boot */
475 mac-address = [ 00 00 00 00 00 00 ];
476 };
477
478 cpsw_emac1: slave@4a100300 {
479 /* Filled in by U-Boot */
480 mac-address = [ 00 00 00 00 00 00 ];
481 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]482 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]483
484 ocmcram: ocmcram@40300000 {
485 compatible = "ti,am3352-ocmcram";
486 reg = <0x40300000 0x10000>;
487 ti,hwmods = "ocmcram";
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]488 };
489
490 wkup_m3: wkup_m3@44d00000 {
491 compatible = "ti,am3353-wkup-m3";
492 reg = <0x44d00000 0x4000 /* M3 UMEM */
493 0x44d80000 0x2000>; /* M3 DMEM */
494 ti,hwmods = "wkup_m3";
495 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]496
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]497 elm: elm@48080000 {
498 compatible = "ti,am3352-elm";
499 reg = <0x48080000 0x2000>;
500 interrupts = <4>;
501 ti,hwmods = "elm";
502 status = "disabled";
503 };
504
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]505 tscadc: tscadc@44e0d000 {
506 compatible = "ti,am3359-tscadc";
507 reg = <0x44e0d000 0x1000>;
508 interrupt-parent = <&intc>;
509 interrupts = <16>;
510 ti,hwmods = "adc_tsc";
511 status = "disabled";
512
513 tsc {
514 compatible = "ti,am3359-tsc";
515 };
516 am335x_adc: adc {
517 #io-channel-cells = <1>;
518 compatible = "ti,am3359-adc";
519 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]520 };
521
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]522 gpmc: gpmc@50000000 {
523 compatible = "ti,am3352-gpmc";
524 ti,hwmods = "gpmc";
525 reg = <0x50000000 0x2000>;
526 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]527 gpmc,num-cs = <7>;
528 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]529 #address-cells = <2>;
530 #size-cells = <1>;
531 status = "disabled";
532 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]533 };
534};