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review.evervolv.com / android_kernel_oneplus_msm8996 / c4b51a431561f0bacc1740aa27f080bf95c4d6c7 / . / arch / arm / boot / dts / kirkwood.dtsi
blob: 9809fc1f105ccf683ede2fc11afee659a483a5dc [file] [log] [blame]
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]4 compatible = "marvell,kirkwood";
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]5 interrupt-parent = <&intc>;
6
Adam Baker33a66752013-06-02 22:59:50 +0100[diff] [blame]7 cpus {
8 #address-cells = <1>;
9 #size-cells = <0>;
10
11 cpu@0 {
12 device_type = "cpu";
13 compatible = "marvell,feroceon";
14 clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
15 clock-names = "cpu_clk", "ddrclk", "powersave";
16 };
17 };
18
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]19 aliases {
20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 };
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]23 intc: interrupt-controller {
24 compatible = "marvell,orion-intc", "marvell,intc";
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 reg = <0xf1020204 0x04>,
28 <0xf1020214 0x04>;
29 };
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]30
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]31 ocp@f1000000 {
32 compatible = "simple-bus";
Ezequiel Garcia01db5272013-06-18 12:31:19 -0300[diff] [blame]33 ranges = <0x00000000 0xf1000000 0x0100000
Thomas Petazzoni670ee032013-05-15 15:36:56 +0200[diff] [blame]34 0xe0000000 0xe0000000 0x8100000 /* PCIE */
Ezequiel Garcia01db5272013-06-18 12:31:19 -0300[diff] [blame]35 0xf4000000 0xf4000000 0x0000400
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]36 0xf5000000 0xf5000000 0x0000400>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]37 #address-cells = <1>;
38 #size-cells = <1>;
39
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]40 core_clk: core-clocks@10030 {
41 compatible = "marvell,kirkwood-core-clock";
42 reg = <0x10030 0x4>;
43 #clock-cells = <1>;
44 };
45
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]46 gpio0: gpio@10100 {
47 compatible = "marvell,orion-gpio";
48 #gpio-cells = <2>;
49 gpio-controller;
50 reg = <0x10100 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]51 ngpios = <32>;
52 interrupt-controller;
Sebastian Hesselbarth09d75bc2013-01-22 20:46:33 +0100[diff] [blame]53 #interrupt-cells = <2>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]54 interrupts = <35>, <36>, <37>, <38>;
Andrew Lunnde887472013-02-03 11:34:26 +0100[diff] [blame]55 clocks = <&gate_clk 7>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]56 };
57
58 gpio1: gpio@10140 {
59 compatible = "marvell,orion-gpio";
60 #gpio-cells = <2>;
61 gpio-controller;
62 reg = <0x10140 0x40>;
Andrew Lunnf9e75922012-11-17 17:00:44 +0100[diff] [blame]63 ngpios = <18>;
64 interrupt-controller;
Sebastian Hesselbarth09d75bc2013-01-22 20:46:33 +0100[diff] [blame]65 #interrupt-cells = <2>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]66 interrupts = <39>, <40>, <41>;
Andrew Lunnde887472013-02-03 11:34:26 +0100[diff] [blame]67 clocks = <&gate_clk 7>;
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]68 };
69
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]70 serial@12000 {
71 compatible = "ns16550a";
72 reg = <0x12000 0x100>;
73 reg-shift = <2>;
74 interrupts = <33>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]75 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]76 status = "disabled";
77 };
78
79 serial@12100 {
80 compatible = "ns16550a";
81 reg = <0x12100 0x100>;
82 reg-shift = <2>;
83 interrupts = <34>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]84 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]85 status = "disabled";
86 };
Jason Coopere871b872012-03-06 23:55:04 +0000[diff] [blame]87
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]88 spi@10600 {
89 compatible = "marvell,orion-spi";
90 #address-cells = <1>;
91 #size-cells = <0>;
92 cell-index = <0>;
93 interrupts = <23>;
94 reg = <0x10600 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]95 clocks = <&gate_clk 7>;
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]96 status = "disabled";
97 };
98
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]99 gate_clk: clock-gating-control@2011c {
100 compatible = "marvell,kirkwood-gating-clock";
101 reg = <0x2011c 0x4>;
102 clocks = <&core_clk 0>;
103 #clock-cells = <1>;
104 };
105
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]106 wdt@20300 {
107 compatible = "marvell,orion-wdt";
108 reg = <0x20300 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]109 clocks = <&gate_clk 7>;
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]110 status = "okay";
111 };
112
Andrew Lunnc896ed02012-11-18 11:44:57 +0100[diff] [blame]113 xor@60800 {
114 compatible = "marvell,orion-xor";
115 reg = <0x60800 0x100
116 0x60A00 0x100>;
117 status = "okay";
118 clocks = <&gate_clk 8>;
119
120 xor00 {
121 interrupts = <5>;
122 dmacap,memcpy;
123 dmacap,xor;
124 };
125 xor01 {
126 interrupts = <6>;
127 dmacap,memcpy;
128 dmacap,xor;
129 dmacap,memset;
130 };
131 };
132
133 xor@60900 {
134 compatible = "marvell,orion-xor";
135 reg = <0x60900 0x100
136 0xd0B00 0x100>;
137 status = "okay";
138 clocks = <&gate_clk 16>;
139
140 xor00 {
141 interrupts = <7>;
142 dmacap,memcpy;
143 dmacap,xor;
144 };
145 xor01 {
146 interrupts = <8>;
147 dmacap,memcpy;
148 dmacap,xor;
149 dmacap,memset;
150 };
151 };
152
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200[diff] [blame]153 ehci@50000 {
154 compatible = "marvell,orion-ehci";
155 reg = <0x50000 0x1000>;
156 interrupts = <19>;
Andrew Lunn53dfa8e2013-01-06 11:10:34 +0100[diff] [blame]157 clocks = <&gate_clk 3>;
Andrew Lunnb6cf8072012-10-20 13:10:01 +0200[diff] [blame]158 status = "okay";
159 };
160
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]161 nand@3000000 {
162 #address-cells = <1>;
163 #size-cells = <1>;
164 cle = <0>;
165 ale = <1>;
166 bank-width = <1>;
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]167 compatible = "marvell,orion-nand";
Ezequiel Garcia01db5272013-06-18 12:31:19 -0300[diff] [blame]168 reg = <0xf4000000 0x400>;
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]169 chip-delay = <25>;
170 /* set partition map and/or chip-delay in board dts */
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]171 clocks = <&gate_clk 7>;
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]172 status = "disabled";
173 };
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]174
175 i2c@11000 {
176 compatible = "marvell,mv64xxx-i2c";
177 reg = <0x11000 0x20>;
178 #address-cells = <1>;
179 #size-cells = <0>;
180 interrupts = <29>;
181 clock-frequency = <100000>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]182 clocks = <&gate_clk 7>;
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]183 status = "disabled";
184 };
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]185
186 crypto@30000 {
187 compatible = "marvell,orion-crypto";
188 reg = <0x30000 0x10000>,
189 <0xf5000000 0x800>;
190 reg-names = "regs", "sram";
191 interrupts = <22>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]192 clocks = <&gate_clk 17>;
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]193 status = "okay";
194 };
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]195 };
196};