blob: f3755ac81148761866df71104a0e356c2be72ed6 [file] [log] [blame]
Arnd Bergmann48be9ac2013-02-28 18:19:16 +01001/*
2 * arch/arm/mach-dove/board-dt.c
3 *
4 * Marvell Dove 88AP510 System On Chip FDT Board
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/init.h>
12#include <linux/clk-provider.h>
Arnd Bergmann48be9ac2013-02-28 18:19:16 +010013#include <linux/of.h>
14#include <linux/of_platform.h>
15#include <linux/platform_data/usb-ehci-orion.h>
16#include <asm/hardware/cache-tauros2.h>
17#include <asm/mach/arch.h>
18#include <mach/pm.h>
19#include <plat/common.h>
20#include <plat/irq.h>
21#include "common.h"
22
23/*
24 * There are still devices that doesn't even know about DT,
25 * get clock gates here and add a clock lookup.
26 */
27static void __init dove_legacy_clk_init(void)
28{
29 struct device_node *np = of_find_compatible_node(NULL, NULL,
30 "marvell,dove-gating-clock");
31 struct of_phandle_args clkspec;
32
33 clkspec.np = np;
34 clkspec.args_count = 1;
35
Arnd Bergmann48be9ac2013-02-28 18:19:16 +010036 clkspec.args[0] = CLOCK_GATING_BIT_GBE;
37 orion_clkdev_add(NULL, "mv643xx_eth_port.0",
38 of_clk_get_from_provider(&clkspec));
39
40 clkspec.args[0] = CLOCK_GATING_BIT_PCIE0;
41 orion_clkdev_add("0", "pcie",
42 of_clk_get_from_provider(&clkspec));
43
44 clkspec.args[0] = CLOCK_GATING_BIT_PCIE1;
45 orion_clkdev_add("1", "pcie",
46 of_clk_get_from_provider(&clkspec));
47}
48
49static void __init dove_of_clk_init(void)
50{
Sebastian Hesselbarth367dc182013-05-11 03:08:07 +020051 of_clk_init(NULL);
Arnd Bergmann48be9ac2013-02-28 18:19:16 +010052 dove_legacy_clk_init();
53}
54
55static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
56 .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
57};
58
59static void __init dove_dt_init(void)
60{
61 pr_info("Dove 88AP510 SoC\n");
62
63#ifdef CONFIG_CACHE_TAUROS2
64 tauros2_init(0);
65#endif
Thomas Petazzoni7d554902013-03-21 17:59:17 +010066 dove_setup_cpu_wins();
Arnd Bergmann48be9ac2013-02-28 18:19:16 +010067
68 /* Setup root of clk tree */
69 dove_of_clk_init();
70
71 /* Internal devices not ported to DT yet */
72 dove_ge00_init(&dove_dt_ge00_data);
Arnd Bergmann48be9ac2013-02-28 18:19:16 +010073 dove_pcie_init(1, 1);
74
75 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
76}
77
78static const char * const dove_dt_board_compat[] = {
79 "marvell,dove",
80 NULL
81};
82
83DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
84 .map_io = dove_map_io,
85 .init_early = dove_init_early,
86 .init_irq = orion_dt_init_irq,
87 .init_time = dove_timer_init,
88 .init_machine = dove_dt_init,
89 .restart = dove_restart,
90 .dt_compat = dove_dt_board_compat,
91MACHINE_END