| Benoit Cousson | 42e872a | 2013-05-29 12:38:02 -0400 | [diff] [blame] | 1 | /* |
| 2 | * OMAP54xx Power Management register bits |
| 3 | * |
| 4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com |
| 5 | * |
| 6 | * Paul Walmsley (paul@pwsan.com) |
| 7 | * Rajendra Nayak (rnayak@ti.com) |
| 8 | * Benoit Cousson (b-cousson@ti.com) |
| 9 | * |
| 10 | * This file is automatically generated from the OMAP hardware databases. |
| 11 | * We respectfully ask that any modifications to this file be coordinated |
| 12 | * with the public linux-omap@vger.kernel.org mailing list and the |
| 13 | * authors above to ensure that the autogeneration scripts are kept |
| 14 | * up-to-date with the file contents. |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License version 2 as |
| 18 | * published by the Free Software Foundation. |
| 19 | */ |
| 20 | |
| 21 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H |
| 22 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H |
| 23 | |
| 24 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ |
| 25 | #define OMAP54XX_ABBOFF_ACT_SHIFT 1 |
| 26 | #define OMAP54XX_ABBOFF_ACT_WIDTH 0x1 |
| 27 | #define OMAP54XX_ABBOFF_ACT_MASK (1 << 1) |
| 28 | |
| 29 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ |
| 30 | #define OMAP54XX_ABBOFF_SLEEP_SHIFT 2 |
| 31 | #define OMAP54XX_ABBOFF_SLEEP_WIDTH 0x1 |
| 32 | #define OMAP54XX_ABBOFF_SLEEP_MASK (1 << 2) |
| 33 | |
| 34 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 35 | #define OMAP54XX_ABB_MM_DONE_EN_SHIFT 31 |
| 36 | #define OMAP54XX_ABB_MM_DONE_EN_WIDTH 0x1 |
| 37 | #define OMAP54XX_ABB_MM_DONE_EN_MASK (1 << 31) |
| 38 | |
| 39 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 40 | #define OMAP54XX_ABB_MM_DONE_ST_SHIFT 31 |
| 41 | #define OMAP54XX_ABB_MM_DONE_ST_WIDTH 0x1 |
| 42 | #define OMAP54XX_ABB_MM_DONE_ST_MASK (1 << 31) |
| 43 | |
| 44 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 45 | #define OMAP54XX_ABB_MPU_DONE_EN_SHIFT 7 |
| 46 | #define OMAP54XX_ABB_MPU_DONE_EN_WIDTH 0x1 |
| 47 | #define OMAP54XX_ABB_MPU_DONE_EN_MASK (1 << 7) |
| 48 | |
| 49 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 50 | #define OMAP54XX_ABB_MPU_DONE_ST_SHIFT 7 |
| 51 | #define OMAP54XX_ABB_MPU_DONE_ST_WIDTH 0x1 |
| 52 | #define OMAP54XX_ABB_MPU_DONE_ST_MASK (1 << 7) |
| 53 | |
| 54 | /* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ |
| 55 | #define OMAP54XX_ACTIVE_FBB_SEL_SHIFT 2 |
| 56 | #define OMAP54XX_ACTIVE_FBB_SEL_WIDTH 0x1 |
| 57 | #define OMAP54XX_ACTIVE_FBB_SEL_MASK (1 << 2) |
| 58 | |
| 59 | /* Used by PM_ABE_PWRSTCTRL */ |
| 60 | #define OMAP54XX_AESSMEM_ONSTATE_SHIFT 16 |
| 61 | #define OMAP54XX_AESSMEM_ONSTATE_WIDTH 0x2 |
| 62 | #define OMAP54XX_AESSMEM_ONSTATE_MASK (0x3 << 16) |
| 63 | |
| 64 | /* Used by PM_ABE_PWRSTCTRL */ |
| 65 | #define OMAP54XX_AESSMEM_RETSTATE_SHIFT 8 |
| 66 | #define OMAP54XX_AESSMEM_RETSTATE_WIDTH 0x1 |
| 67 | #define OMAP54XX_AESSMEM_RETSTATE_MASK (1 << 8) |
| 68 | |
| 69 | /* Used by PM_ABE_PWRSTST */ |
| 70 | #define OMAP54XX_AESSMEM_STATEST_SHIFT 4 |
| 71 | #define OMAP54XX_AESSMEM_STATEST_WIDTH 0x2 |
| 72 | #define OMAP54XX_AESSMEM_STATEST_MASK (0x3 << 4) |
| 73 | |
| 74 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ |
| 75 | #define OMAP54XX_AIPOFF_SHIFT 8 |
| 76 | #define OMAP54XX_AIPOFF_WIDTH 0x1 |
| 77 | #define OMAP54XX_AIPOFF_MASK (1 << 8) |
| 78 | |
| 79 | /* Used by PRM_VOLTCTRL */ |
| 80 | #define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT 0 |
| 81 | #define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH 0x2 |
| 82 | #define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) |
| 83 | |
| 84 | /* Used by PRM_VOLTCTRL */ |
| 85 | #define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT 4 |
| 86 | #define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH 0x2 |
| 87 | #define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK (0x3 << 4) |
| 88 | |
| 89 | /* Used by PRM_VOLTCTRL */ |
| 90 | #define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT 2 |
| 91 | #define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH 0x2 |
| 92 | #define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) |
| 93 | |
| 94 | /* Used by PRM_VC_BYPASS_ERRST */ |
| 95 | #define OMAP54XX_BYPS_RA_ERR_SHIFT 1 |
| 96 | #define OMAP54XX_BYPS_RA_ERR_WIDTH 0x1 |
| 97 | #define OMAP54XX_BYPS_RA_ERR_MASK (1 << 1) |
| 98 | |
| 99 | /* Used by PRM_VC_BYPASS_ERRST */ |
| 100 | #define OMAP54XX_BYPS_SA_ERR_SHIFT 0 |
| 101 | #define OMAP54XX_BYPS_SA_ERR_WIDTH 0x1 |
| 102 | #define OMAP54XX_BYPS_SA_ERR_MASK (1 << 0) |
| 103 | |
| 104 | /* Used by PRM_VC_BYPASS_ERRST */ |
| 105 | #define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT 2 |
| 106 | #define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH 0x1 |
| 107 | #define OMAP54XX_BYPS_TIMEOUT_ERR_MASK (1 << 2) |
| 108 | |
| 109 | /* Used by PRM_RSTST */ |
| 110 | #define OMAP54XX_C2C_RST_SHIFT 10 |
| 111 | #define OMAP54XX_C2C_RST_WIDTH 0x1 |
| 112 | #define OMAP54XX_C2C_RST_MASK (1 << 10) |
| 113 | |
| 114 | /* Used by PM_CAM_PWRSTCTRL */ |
| 115 | #define OMAP54XX_CAM_MEM_ONSTATE_SHIFT 16 |
| 116 | #define OMAP54XX_CAM_MEM_ONSTATE_WIDTH 0x2 |
| 117 | #define OMAP54XX_CAM_MEM_ONSTATE_MASK (0x3 << 16) |
| 118 | |
| 119 | /* Used by PM_CAM_PWRSTST */ |
| 120 | #define OMAP54XX_CAM_MEM_STATEST_SHIFT 4 |
| 121 | #define OMAP54XX_CAM_MEM_STATEST_WIDTH 0x2 |
| 122 | #define OMAP54XX_CAM_MEM_STATEST_MASK (0x3 << 4) |
| 123 | |
| 124 | /* Used by PRM_CLKREQCTRL */ |
| 125 | #define OMAP54XX_CLKREQ_COND_SHIFT 0 |
| 126 | #define OMAP54XX_CLKREQ_COND_WIDTH 0x3 |
| 127 | #define OMAP54XX_CLKREQ_COND_MASK (0x7 << 0) |
| 128 | |
| 129 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ |
| 130 | #define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT 16 |
| 131 | #define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH 0x8 |
| 132 | #define OMAP54XX_CMDRA_VDD_CORE_L_MASK (0xff << 16) |
| 133 | |
| 134 | /* Used by PRM_VC_SMPS_MM_CONFIG */ |
| 135 | #define OMAP54XX_CMDRA_VDD_MM_L_SHIFT 16 |
| 136 | #define OMAP54XX_CMDRA_VDD_MM_L_WIDTH 0x8 |
| 137 | #define OMAP54XX_CMDRA_VDD_MM_L_MASK (0xff << 16) |
| 138 | |
| 139 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ |
| 140 | #define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT 16 |
| 141 | #define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH 0x8 |
| 142 | #define OMAP54XX_CMDRA_VDD_MPU_L_MASK (0xff << 16) |
| 143 | |
| 144 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ |
| 145 | #define OMAP54XX_CMD_VDD_CORE_L_SHIFT 28 |
| 146 | #define OMAP54XX_CMD_VDD_CORE_L_WIDTH 0x1 |
| 147 | #define OMAP54XX_CMD_VDD_CORE_L_MASK (1 << 28) |
| 148 | |
| 149 | /* Used by PRM_VC_SMPS_MM_CONFIG */ |
| 150 | #define OMAP54XX_CMD_VDD_MM_L_SHIFT 28 |
| 151 | #define OMAP54XX_CMD_VDD_MM_L_WIDTH 0x1 |
| 152 | #define OMAP54XX_CMD_VDD_MM_L_MASK (1 << 28) |
| 153 | |
| 154 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ |
| 155 | #define OMAP54XX_CMD_VDD_MPU_L_SHIFT 28 |
| 156 | #define OMAP54XX_CMD_VDD_MPU_L_WIDTH 0x1 |
| 157 | #define OMAP54XX_CMD_VDD_MPU_L_MASK (1 << 28) |
| 158 | |
| 159 | /* Used by PM_CORE_PWRSTCTRL */ |
| 160 | #define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT 18 |
| 161 | #define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH 0x2 |
| 162 | #define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) |
| 163 | |
| 164 | /* Used by PM_CORE_PWRSTCTRL */ |
| 165 | #define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT 9 |
| 166 | #define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH 0x1 |
| 167 | #define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK (1 << 9) |
| 168 | |
| 169 | /* Used by PM_CORE_PWRSTST */ |
| 170 | #define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT 6 |
| 171 | #define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH 0x2 |
| 172 | #define OMAP54XX_CORE_OCMRAM_STATEST_MASK (0x3 << 6) |
| 173 | |
| 174 | /* Used by PM_CORE_PWRSTCTRL */ |
| 175 | #define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT 16 |
| 176 | #define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH 0x2 |
| 177 | #define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) |
| 178 | |
| 179 | /* Used by PM_CORE_PWRSTCTRL */ |
| 180 | #define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT 8 |
| 181 | #define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH 0x1 |
| 182 | #define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) |
| 183 | |
| 184 | /* Used by PM_CORE_PWRSTST */ |
| 185 | #define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT 4 |
| 186 | #define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH 0x2 |
| 187 | #define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) |
| 188 | |
| 189 | /* Used by REVISION_PRM */ |
| 190 | #define OMAP54XX_CUSTOM_SHIFT 6 |
| 191 | #define OMAP54XX_CUSTOM_WIDTH 0x2 |
| 192 | #define OMAP54XX_CUSTOM_MASK (0x3 << 6) |
| 193 | |
| 194 | /* Used by PRM_VC_VAL_BYPASS */ |
| 195 | #define OMAP54XX_DATA_SHIFT 16 |
| 196 | #define OMAP54XX_DATA_WIDTH 0x8 |
| 197 | #define OMAP54XX_DATA_MASK (0xff << 16) |
| 198 | |
| 199 | /* Used by PRM_DEBUG_CORE_RET_TRANS */ |
| 200 | #define OMAP54XX_PRM_DEBUG_OUT_SHIFT 0 |
| 201 | #define OMAP54XX_PRM_DEBUG_OUT_WIDTH 0x1c |
| 202 | #define OMAP54XX_PRM_DEBUG_OUT_MASK (0xfffffff << 0) |
| 203 | |
| 204 | /* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */ |
| 205 | #define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 |
| 206 | #define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa |
| 207 | #define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) |
| 208 | |
| 209 | /* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */ |
| 210 | #define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 |
| 211 | #define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 |
| 212 | #define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) |
| 213 | |
| 214 | /* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */ |
| 215 | #define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 |
| 216 | #define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 |
| 217 | #define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) |
| 218 | |
| 219 | /* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */ |
| 220 | #define OMAP54XX_DEBUG_OUT_0_11_SHIFT 0 |
| 221 | #define OMAP54XX_DEBUG_OUT_0_11_WIDTH 0xc |
| 222 | #define OMAP54XX_DEBUG_OUT_0_11_MASK (0xfff << 0) |
| 223 | |
| 224 | /* Used by PRM_DEVICE_OFF_CTRL */ |
| 225 | #define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT 0 |
| 226 | #define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH 0x1 |
| 227 | #define OMAP54XX_DEVICE_OFF_ENABLE_MASK (1 << 0) |
| 228 | |
| 229 | /* Used by PRM_VC_CFG_I2C_MODE */ |
| 230 | #define OMAP54XX_DFILTEREN_SHIFT 6 |
| 231 | #define OMAP54XX_DFILTEREN_WIDTH 0x1 |
| 232 | #define OMAP54XX_DFILTEREN_MASK (1 << 6) |
| 233 | |
| 234 | /* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 235 | #define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT 4 |
| 236 | #define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH 0x1 |
| 237 | #define OMAP54XX_DPLL_ABE_RECAL_EN_MASK (1 << 4) |
| 238 | |
| 239 | /* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 240 | #define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT 4 |
| 241 | #define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH 0x1 |
| 242 | #define OMAP54XX_DPLL_ABE_RECAL_ST_MASK (1 << 4) |
| 243 | |
| 244 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 245 | #define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT 0 |
| 246 | #define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH 0x1 |
| 247 | #define OMAP54XX_DPLL_CORE_RECAL_EN_MASK (1 << 0) |
| 248 | |
| 249 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 250 | #define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT 0 |
| 251 | #define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH 0x1 |
| 252 | #define OMAP54XX_DPLL_CORE_RECAL_ST_MASK (1 << 0) |
| 253 | |
| 254 | /* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 255 | #define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT 2 |
| 256 | #define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH 0x1 |
| 257 | #define OMAP54XX_DPLL_IVA_RECAL_EN_MASK (1 << 2) |
| 258 | |
| 259 | /* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 260 | #define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT 2 |
| 261 | #define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH 0x1 |
| 262 | #define OMAP54XX_DPLL_IVA_RECAL_ST_MASK (1 << 2) |
| 263 | |
| 264 | /* Used by PRM_IRQENABLE_MPU */ |
| 265 | #define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT 1 |
| 266 | #define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH 0x1 |
| 267 | #define OMAP54XX_DPLL_MPU_RECAL_EN_MASK (1 << 1) |
| 268 | |
| 269 | /* Used by PRM_IRQSTATUS_MPU */ |
| 270 | #define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT 1 |
| 271 | #define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH 0x1 |
| 272 | #define OMAP54XX_DPLL_MPU_RECAL_ST_MASK (1 << 1) |
| 273 | |
| 274 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 275 | #define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT 3 |
| 276 | #define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH 0x1 |
| 277 | #define OMAP54XX_DPLL_PER_RECAL_EN_MASK (1 << 3) |
| 278 | |
| 279 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 280 | #define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT 3 |
| 281 | #define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH 0x1 |
| 282 | #define OMAP54XX_DPLL_PER_RECAL_ST_MASK (1 << 3) |
| 283 | |
| 284 | /* Used by PM_DSP_PWRSTCTRL */ |
| 285 | #define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT 20 |
| 286 | #define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH 0x2 |
| 287 | #define OMAP54XX_DSP_EDMA_ONSTATE_MASK (0x3 << 20) |
| 288 | |
| 289 | /* Used by PM_DSP_PWRSTCTRL */ |
| 290 | #define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT 10 |
| 291 | #define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH 0x1 |
| 292 | #define OMAP54XX_DSP_EDMA_RETSTATE_MASK (1 << 10) |
| 293 | |
| 294 | /* Used by PM_DSP_PWRSTST */ |
| 295 | #define OMAP54XX_DSP_EDMA_STATEST_SHIFT 8 |
| 296 | #define OMAP54XX_DSP_EDMA_STATEST_WIDTH 0x2 |
| 297 | #define OMAP54XX_DSP_EDMA_STATEST_MASK (0x3 << 8) |
| 298 | |
| 299 | /* Used by PM_DSP_PWRSTCTRL */ |
| 300 | #define OMAP54XX_DSP_L1_ONSTATE_SHIFT 16 |
| 301 | #define OMAP54XX_DSP_L1_ONSTATE_WIDTH 0x2 |
| 302 | #define OMAP54XX_DSP_L1_ONSTATE_MASK (0x3 << 16) |
| 303 | |
| 304 | /* Used by PM_DSP_PWRSTCTRL */ |
| 305 | #define OMAP54XX_DSP_L1_RETSTATE_SHIFT 8 |
| 306 | #define OMAP54XX_DSP_L1_RETSTATE_WIDTH 0x1 |
| 307 | #define OMAP54XX_DSP_L1_RETSTATE_MASK (1 << 8) |
| 308 | |
| 309 | /* Used by PM_DSP_PWRSTST */ |
| 310 | #define OMAP54XX_DSP_L1_STATEST_SHIFT 4 |
| 311 | #define OMAP54XX_DSP_L1_STATEST_WIDTH 0x2 |
| 312 | #define OMAP54XX_DSP_L1_STATEST_MASK (0x3 << 4) |
| 313 | |
| 314 | /* Used by PM_DSP_PWRSTCTRL */ |
| 315 | #define OMAP54XX_DSP_L2_ONSTATE_SHIFT 18 |
| 316 | #define OMAP54XX_DSP_L2_ONSTATE_WIDTH 0x2 |
| 317 | #define OMAP54XX_DSP_L2_ONSTATE_MASK (0x3 << 18) |
| 318 | |
| 319 | /* Used by PM_DSP_PWRSTCTRL */ |
| 320 | #define OMAP54XX_DSP_L2_RETSTATE_SHIFT 9 |
| 321 | #define OMAP54XX_DSP_L2_RETSTATE_WIDTH 0x1 |
| 322 | #define OMAP54XX_DSP_L2_RETSTATE_MASK (1 << 9) |
| 323 | |
| 324 | /* Used by PM_DSP_PWRSTST */ |
| 325 | #define OMAP54XX_DSP_L2_STATEST_SHIFT 6 |
| 326 | #define OMAP54XX_DSP_L2_STATEST_WIDTH 0x2 |
| 327 | #define OMAP54XX_DSP_L2_STATEST_MASK (0x3 << 6) |
| 328 | |
| 329 | /* Used by PM_DSS_PWRSTCTRL */ |
| 330 | #define OMAP54XX_DSS_MEM_ONSTATE_SHIFT 16 |
| 331 | #define OMAP54XX_DSS_MEM_ONSTATE_WIDTH 0x2 |
| 332 | #define OMAP54XX_DSS_MEM_ONSTATE_MASK (0x3 << 16) |
| 333 | |
| 334 | /* Used by PM_DSS_PWRSTCTRL */ |
| 335 | #define OMAP54XX_DSS_MEM_RETSTATE_SHIFT 8 |
| 336 | #define OMAP54XX_DSS_MEM_RETSTATE_WIDTH 0x1 |
| 337 | #define OMAP54XX_DSS_MEM_RETSTATE_MASK (1 << 8) |
| 338 | |
| 339 | /* Used by PM_DSS_PWRSTST */ |
| 340 | #define OMAP54XX_DSS_MEM_STATEST_SHIFT 4 |
| 341 | #define OMAP54XX_DSS_MEM_STATEST_WIDTH 0x2 |
| 342 | #define OMAP54XX_DSS_MEM_STATEST_MASK (0x3 << 4) |
| 343 | |
| 344 | /* Used by PRM_DEVICE_OFF_CTRL */ |
| 345 | #define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT 8 |
| 346 | #define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH 0x1 |
| 347 | #define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8) |
| 348 | |
| 349 | /* Used by PRM_DEVICE_OFF_CTRL */ |
| 350 | #define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT 9 |
| 351 | #define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH 0x1 |
| 352 | #define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9) |
| 353 | |
| 354 | /* Used by PM_EMU_PWRSTCTRL */ |
| 355 | #define OMAP54XX_EMU_BANK_ONSTATE_SHIFT 16 |
| 356 | #define OMAP54XX_EMU_BANK_ONSTATE_WIDTH 0x2 |
| 357 | #define OMAP54XX_EMU_BANK_ONSTATE_MASK (0x3 << 16) |
| 358 | |
| 359 | /* Used by PM_EMU_PWRSTST */ |
| 360 | #define OMAP54XX_EMU_BANK_STATEST_SHIFT 4 |
| 361 | #define OMAP54XX_EMU_BANK_STATEST_WIDTH 0x2 |
| 362 | #define OMAP54XX_EMU_BANK_STATEST_MASK (0x3 << 4) |
| 363 | |
| 364 | /* |
| 365 | * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP, |
| 366 | * PRM_SRAM_WKUP_SETUP |
| 367 | */ |
| 368 | #define OMAP54XX_ENABLE_RTA_SHIFT 0 |
| 369 | #define OMAP54XX_ENABLE_RTA_WIDTH 0x1 |
| 370 | #define OMAP54XX_ENABLE_RTA_MASK (1 << 0) |
| 371 | |
| 372 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ |
| 373 | #define OMAP54XX_ENFUNC1_SHIFT 3 |
| 374 | #define OMAP54XX_ENFUNC1_WIDTH 0x1 |
| 375 | #define OMAP54XX_ENFUNC1_MASK (1 << 3) |
| 376 | |
| 377 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ |
| 378 | #define OMAP54XX_ENFUNC2_SHIFT 4 |
| 379 | #define OMAP54XX_ENFUNC2_WIDTH 0x1 |
| 380 | #define OMAP54XX_ENFUNC2_MASK (1 << 4) |
| 381 | |
| 382 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ |
| 383 | #define OMAP54XX_ENFUNC3_SHIFT 5 |
| 384 | #define OMAP54XX_ENFUNC3_WIDTH 0x1 |
| 385 | #define OMAP54XX_ENFUNC3_MASK (1 << 5) |
| 386 | |
| 387 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ |
| 388 | #define OMAP54XX_ENFUNC4_SHIFT 6 |
| 389 | #define OMAP54XX_ENFUNC4_WIDTH 0x1 |
| 390 | #define OMAP54XX_ENFUNC4_MASK (1 << 6) |
| 391 | |
| 392 | /* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ |
| 393 | #define OMAP54XX_ENFUNC5_SHIFT 7 |
| 394 | #define OMAP54XX_ENFUNC5_WIDTH 0x1 |
| 395 | #define OMAP54XX_ENFUNC5_MASK (1 << 7) |
| 396 | |
| 397 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ |
| 398 | #define OMAP54XX_ERRORGAIN_SHIFT 16 |
| 399 | #define OMAP54XX_ERRORGAIN_WIDTH 0x8 |
| 400 | #define OMAP54XX_ERRORGAIN_MASK (0xff << 16) |
| 401 | |
| 402 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ |
| 403 | #define OMAP54XX_ERROROFFSET_SHIFT 24 |
| 404 | #define OMAP54XX_ERROROFFSET_WIDTH 0x8 |
| 405 | #define OMAP54XX_ERROROFFSET_MASK (0xff << 24) |
| 406 | |
| 407 | /* Used by PRM_RSTST */ |
| 408 | #define OMAP54XX_EXTERNAL_WARM_RST_SHIFT 5 |
| 409 | #define OMAP54XX_EXTERNAL_WARM_RST_WIDTH 0x1 |
| 410 | #define OMAP54XX_EXTERNAL_WARM_RST_MASK (1 << 5) |
| 411 | |
| 412 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ |
| 413 | #define OMAP54XX_FORCEUPDATE_SHIFT 1 |
| 414 | #define OMAP54XX_FORCEUPDATE_WIDTH 0x1 |
| 415 | #define OMAP54XX_FORCEUPDATE_MASK (1 << 1) |
| 416 | |
| 417 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ |
| 418 | #define OMAP54XX_FORCEUPDATEWAIT_SHIFT 8 |
| 419 | #define OMAP54XX_FORCEUPDATEWAIT_WIDTH 0x18 |
| 420 | #define OMAP54XX_FORCEUPDATEWAIT_MASK (0xffffff << 8) |
| 421 | |
| 422 | /* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */ |
| 423 | #define OMAP54XX_FORCEWKUP_EN_SHIFT 10 |
| 424 | #define OMAP54XX_FORCEWKUP_EN_WIDTH 0x1 |
| 425 | #define OMAP54XX_FORCEWKUP_EN_MASK (1 << 10) |
| 426 | |
| 427 | /* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */ |
| 428 | #define OMAP54XX_FORCEWKUP_ST_SHIFT 10 |
| 429 | #define OMAP54XX_FORCEWKUP_ST_WIDTH 0x1 |
| 430 | #define OMAP54XX_FORCEWKUP_ST_MASK (1 << 10) |
| 431 | |
| 432 | /* Used by REVISION_PRM */ |
| 433 | #define OMAP54XX_FUNC_SHIFT 16 |
| 434 | #define OMAP54XX_FUNC_WIDTH 0xc |
| 435 | #define OMAP54XX_FUNC_MASK (0xfff << 16) |
| 436 | |
| 437 | /* Used by PRM_RSTST */ |
| 438 | #define OMAP54XX_GLOBAL_COLD_RST_SHIFT 0 |
| 439 | #define OMAP54XX_GLOBAL_COLD_RST_WIDTH 0x1 |
| 440 | #define OMAP54XX_GLOBAL_COLD_RST_MASK (1 << 0) |
| 441 | |
| 442 | /* Used by PRM_RSTST */ |
| 443 | #define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT 1 |
| 444 | #define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH 0x1 |
| 445 | #define OMAP54XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) |
| 446 | |
| 447 | /* Used by PRM_IO_PMCTRL */ |
| 448 | #define OMAP54XX_GLOBAL_WUEN_SHIFT 16 |
| 449 | #define OMAP54XX_GLOBAL_WUEN_WIDTH 0x1 |
| 450 | #define OMAP54XX_GLOBAL_WUEN_MASK (1 << 16) |
| 451 | |
| 452 | /* Used by PM_GPU_PWRSTCTRL */ |
| 453 | #define OMAP54XX_GPU_MEM_ONSTATE_SHIFT 16 |
| 454 | #define OMAP54XX_GPU_MEM_ONSTATE_WIDTH 0x2 |
| 455 | #define OMAP54XX_GPU_MEM_ONSTATE_MASK (0x3 << 16) |
| 456 | |
| 457 | /* Used by PM_GPU_PWRSTST */ |
| 458 | #define OMAP54XX_GPU_MEM_STATEST_SHIFT 4 |
| 459 | #define OMAP54XX_GPU_MEM_STATEST_WIDTH 0x2 |
| 460 | #define OMAP54XX_GPU_MEM_STATEST_MASK (0x3 << 4) |
| 461 | |
| 462 | /* Used by PRM_VC_CFG_I2C_MODE */ |
| 463 | #define OMAP54XX_HSMCODE_SHIFT 0 |
| 464 | #define OMAP54XX_HSMCODE_WIDTH 0x3 |
| 465 | #define OMAP54XX_HSMCODE_MASK (0x7 << 0) |
| 466 | |
| 467 | /* Used by PRM_VC_CFG_I2C_MODE */ |
| 468 | #define OMAP54XX_HSMODEEN_SHIFT 3 |
| 469 | #define OMAP54XX_HSMODEEN_WIDTH 0x1 |
| 470 | #define OMAP54XX_HSMODEEN_MASK (1 << 3) |
| 471 | |
| 472 | /* Used by PRM_VC_CFG_I2C_CLK */ |
| 473 | #define OMAP54XX_HSSCLH_SHIFT 16 |
| 474 | #define OMAP54XX_HSSCLH_WIDTH 0x8 |
| 475 | #define OMAP54XX_HSSCLH_MASK (0xff << 16) |
| 476 | |
| 477 | /* Used by PRM_VC_CFG_I2C_CLK */ |
| 478 | #define OMAP54XX_HSSCLL_SHIFT 24 |
| 479 | #define OMAP54XX_HSSCLL_WIDTH 0x8 |
| 480 | #define OMAP54XX_HSSCLL_MASK (0xff << 24) |
| 481 | |
| 482 | /* Used by PM_IVA_PWRSTCTRL */ |
| 483 | #define OMAP54XX_HWA_MEM_ONSTATE_SHIFT 16 |
| 484 | #define OMAP54XX_HWA_MEM_ONSTATE_WIDTH 0x2 |
| 485 | #define OMAP54XX_HWA_MEM_ONSTATE_MASK (0x3 << 16) |
| 486 | |
| 487 | /* Used by PM_IVA_PWRSTCTRL */ |
| 488 | #define OMAP54XX_HWA_MEM_RETSTATE_SHIFT 8 |
| 489 | #define OMAP54XX_HWA_MEM_RETSTATE_WIDTH 0x1 |
| 490 | #define OMAP54XX_HWA_MEM_RETSTATE_MASK (1 << 8) |
| 491 | |
| 492 | /* Used by PM_IVA_PWRSTST */ |
| 493 | #define OMAP54XX_HWA_MEM_STATEST_SHIFT 4 |
| 494 | #define OMAP54XX_HWA_MEM_STATEST_WIDTH 0x2 |
| 495 | #define OMAP54XX_HWA_MEM_STATEST_MASK (0x3 << 4) |
| 496 | |
| 497 | /* Used by PRM_RSTST */ |
| 498 | #define OMAP54XX_ICEPICK_RST_SHIFT 9 |
| 499 | #define OMAP54XX_ICEPICK_RST_WIDTH 0x1 |
| 500 | #define OMAP54XX_ICEPICK_RST_MASK (1 << 9) |
| 501 | |
| 502 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ |
| 503 | #define OMAP54XX_INITVDD_SHIFT 2 |
| 504 | #define OMAP54XX_INITVDD_WIDTH 0x1 |
| 505 | #define OMAP54XX_INITVDD_MASK (1 << 2) |
| 506 | |
| 507 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ |
| 508 | #define OMAP54XX_INITVOLTAGE_SHIFT 8 |
| 509 | #define OMAP54XX_INITVOLTAGE_WIDTH 0x8 |
| 510 | #define OMAP54XX_INITVOLTAGE_MASK (0xff << 8) |
| 511 | |
| 512 | /* |
| 513 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, |
| 514 | * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, |
| 515 | * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST, |
| 516 | * PRM_VOLTST_MM, PRM_VOLTST_MPU |
| 517 | */ |
| 518 | #define OMAP54XX_INTRANSITION_SHIFT 20 |
| 519 | #define OMAP54XX_INTRANSITION_WIDTH 0x1 |
| 520 | #define OMAP54XX_INTRANSITION_MASK (1 << 20) |
| 521 | |
| 522 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 523 | #define OMAP54XX_IO_EN_SHIFT 9 |
| 524 | #define OMAP54XX_IO_EN_WIDTH 0x1 |
| 525 | #define OMAP54XX_IO_EN_MASK (1 << 9) |
| 526 | |
| 527 | /* Used by PRM_IO_PMCTRL */ |
| 528 | #define OMAP54XX_IO_ON_STATUS_SHIFT 5 |
| 529 | #define OMAP54XX_IO_ON_STATUS_WIDTH 0x1 |
| 530 | #define OMAP54XX_IO_ON_STATUS_MASK (1 << 5) |
| 531 | |
| 532 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 533 | #define OMAP54XX_IO_ST_SHIFT 9 |
| 534 | #define OMAP54XX_IO_ST_WIDTH 0x1 |
| 535 | #define OMAP54XX_IO_ST_MASK (1 << 9) |
| 536 | |
| 537 | /* Used by PM_CORE_PWRSTCTRL */ |
| 538 | #define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT 20 |
| 539 | #define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH 0x2 |
| 540 | #define OMAP54XX_IPU_L2RAM_ONSTATE_MASK (0x3 << 20) |
| 541 | |
| 542 | /* Used by PM_CORE_PWRSTCTRL */ |
| 543 | #define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT 10 |
| 544 | #define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH 0x1 |
| 545 | #define OMAP54XX_IPU_L2RAM_RETSTATE_MASK (1 << 10) |
| 546 | |
| 547 | /* Used by PM_CORE_PWRSTST */ |
| 548 | #define OMAP54XX_IPU_L2RAM_STATEST_SHIFT 8 |
| 549 | #define OMAP54XX_IPU_L2RAM_STATEST_WIDTH 0x2 |
| 550 | #define OMAP54XX_IPU_L2RAM_STATEST_MASK (0x3 << 8) |
| 551 | |
| 552 | /* Used by PM_CORE_PWRSTCTRL */ |
| 553 | #define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT 22 |
| 554 | #define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH 0x2 |
| 555 | #define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK (0x3 << 22) |
| 556 | |
| 557 | /* Used by PM_CORE_PWRSTCTRL */ |
| 558 | #define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT 11 |
| 559 | #define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH 0x1 |
| 560 | #define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK (1 << 11) |
| 561 | |
| 562 | /* Used by PM_CORE_PWRSTST */ |
| 563 | #define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT 10 |
| 564 | #define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH 0x2 |
| 565 | #define OMAP54XX_IPU_UNICACHE_STATEST_MASK (0x3 << 10) |
| 566 | |
| 567 | /* Used by PRM_IO_PMCTRL */ |
| 568 | #define OMAP54XX_ISOCLK_OVERRIDE_SHIFT 0 |
| 569 | #define OMAP54XX_ISOCLK_OVERRIDE_WIDTH 0x1 |
| 570 | #define OMAP54XX_ISOCLK_OVERRIDE_MASK (1 << 0) |
| 571 | |
| 572 | /* Used by PRM_IO_PMCTRL */ |
| 573 | #define OMAP54XX_ISOCLK_STATUS_SHIFT 1 |
| 574 | #define OMAP54XX_ISOCLK_STATUS_WIDTH 0x1 |
| 575 | #define OMAP54XX_ISOCLK_STATUS_MASK (1 << 1) |
| 576 | |
| 577 | /* Used by PRM_IO_PMCTRL */ |
| 578 | #define OMAP54XX_ISOOVR_EXTEND_SHIFT 4 |
| 579 | #define OMAP54XX_ISOOVR_EXTEND_WIDTH 0x1 |
| 580 | #define OMAP54XX_ISOOVR_EXTEND_MASK (1 << 4) |
| 581 | |
| 582 | /* Used by PRM_IO_COUNT */ |
| 583 | #define OMAP54XX_ISO_2_ON_TIME_SHIFT 0 |
| 584 | #define OMAP54XX_ISO_2_ON_TIME_WIDTH 0x8 |
| 585 | #define OMAP54XX_ISO_2_ON_TIME_MASK (0xff << 0) |
| 586 | |
| 587 | /* Used by PM_L3INIT_PWRSTCTRL */ |
| 588 | #define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT 16 |
| 589 | #define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH 0x2 |
| 590 | #define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) |
| 591 | |
| 592 | /* Used by PM_L3INIT_PWRSTCTRL */ |
| 593 | #define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT 8 |
| 594 | #define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH 0x1 |
| 595 | #define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK (1 << 8) |
| 596 | |
| 597 | /* Used by PM_L3INIT_PWRSTST */ |
| 598 | #define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT 4 |
| 599 | #define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH 0x2 |
| 600 | #define OMAP54XX_L3INIT_BANK1_STATEST_MASK (0x3 << 4) |
| 601 | |
| 602 | /* Used by PM_L3INIT_PWRSTCTRL */ |
| 603 | #define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT 18 |
| 604 | #define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH 0x2 |
| 605 | #define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK (0x3 << 18) |
| 606 | |
| 607 | /* Used by PM_L3INIT_PWRSTCTRL */ |
| 608 | #define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT 9 |
| 609 | #define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH 0x1 |
| 610 | #define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK (1 << 9) |
| 611 | |
| 612 | /* Used by PM_L3INIT_PWRSTST */ |
| 613 | #define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT 6 |
| 614 | #define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH 0x2 |
| 615 | #define OMAP54XX_L3INIT_BANK2_STATEST_MASK (0x3 << 6) |
| 616 | |
| 617 | /* |
| 618 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, |
| 619 | * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, |
| 620 | * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST |
| 621 | */ |
| 622 | #define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT 24 |
| 623 | #define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH 0x2 |
| 624 | #define OMAP54XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) |
| 625 | |
| 626 | /* Used by PRM_RSTST */ |
| 627 | #define OMAP54XX_LLI_RST_SHIFT 14 |
| 628 | #define OMAP54XX_LLI_RST_WIDTH 0x1 |
| 629 | #define OMAP54XX_LLI_RST_MASK (1 << 14) |
| 630 | |
| 631 | /* |
| 632 | * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL, |
| 633 | * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL |
| 634 | */ |
| 635 | #define OMAP54XX_LOGICRETSTATE_SHIFT 2 |
| 636 | #define OMAP54XX_LOGICRETSTATE_WIDTH 0x1 |
| 637 | #define OMAP54XX_LOGICRETSTATE_MASK (1 << 2) |
| 638 | |
| 639 | /* |
| 640 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, |
| 641 | * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, |
| 642 | * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST |
| 643 | */ |
| 644 | #define OMAP54XX_LOGICSTATEST_SHIFT 2 |
| 645 | #define OMAP54XX_LOGICSTATEST_WIDTH 0x1 |
| 646 | #define OMAP54XX_LOGICSTATEST_MASK (1 << 2) |
| 647 | |
| 648 | /* |
| 649 | * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, |
| 650 | * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, |
| 651 | * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT, |
| 652 | * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, |
| 653 | * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, |
| 654 | * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, |
| 655 | * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT, |
| 656 | * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT, |
| 657 | * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT, |
| 658 | * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT, |
| 659 | * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, |
| 660 | * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT, |
| 661 | * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT, |
| 662 | * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT, |
| 663 | * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, |
| 664 | * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, |
| 665 | * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, |
| 666 | * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT, |
| 667 | * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT, |
| 668 | * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, |
| 669 | * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, |
| 670 | * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, |
| 671 | * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, |
| 672 | * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, |
| 673 | * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT, |
| 674 | * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT, |
| 675 | * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, |
| 676 | * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT, |
| 677 | * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT, |
| 678 | * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT, |
| 679 | * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT, |
| 680 | * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT, |
| 681 | * RM_WKUPAON_WD_TIMER2_CONTEXT |
| 682 | */ |
| 683 | #define OMAP54XX_LOSTCONTEXT_DFF_SHIFT 0 |
| 684 | #define OMAP54XX_LOSTCONTEXT_DFF_WIDTH 0x1 |
| 685 | #define OMAP54XX_LOSTCONTEXT_DFF_MASK (1 << 0) |
| 686 | |
| 687 | /* |
| 688 | * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, |
| 689 | * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT, |
| 690 | * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, |
| 691 | * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT, |
| 692 | * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, |
| 693 | * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT, |
| 694 | * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, |
| 695 | * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, |
| 696 | * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT, |
| 697 | * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT, |
| 698 | * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, |
| 699 | * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, |
| 700 | * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT, |
| 701 | * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, |
| 702 | * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, |
| 703 | * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, |
| 704 | * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT, |
| 705 | * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, |
| 706 | * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT |
| 707 | */ |
| 708 | #define OMAP54XX_LOSTCONTEXT_RFF_SHIFT 1 |
| 709 | #define OMAP54XX_LOSTCONTEXT_RFF_WIDTH 0x1 |
| 710 | #define OMAP54XX_LOSTCONTEXT_RFF_MASK (1 << 1) |
| 711 | |
| 712 | /* Used by RM_ABE_AESS_CONTEXT */ |
| 713 | #define OMAP54XX_LOSTMEM_AESSMEM_SHIFT 8 |
| 714 | #define OMAP54XX_LOSTMEM_AESSMEM_WIDTH 0x1 |
| 715 | #define OMAP54XX_LOSTMEM_AESSMEM_MASK (1 << 8) |
| 716 | |
| 717 | /* Used by RM_CAM_CAL_CONTEXT */ |
| 718 | #define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT 8 |
| 719 | #define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH 0x1 |
| 720 | #define OMAP54XX_LOSTMEM_CAL_MEM_MASK (1 << 8) |
| 721 | |
| 722 | /* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ |
| 723 | #define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT 8 |
| 724 | #define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH 0x1 |
| 725 | #define OMAP54XX_LOSTMEM_CAM_MEM_MASK (1 << 8) |
| 726 | |
| 727 | /* Used by RM_EMIF_DMM_CONTEXT */ |
| 728 | #define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT 9 |
| 729 | #define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH 0x1 |
| 730 | #define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK (1 << 9) |
| 731 | |
| 732 | /* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */ |
| 733 | #define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT 8 |
| 734 | #define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH 0x1 |
| 735 | #define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK (1 << 8) |
| 736 | |
| 737 | /* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */ |
| 738 | #define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT 8 |
| 739 | #define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH 0x1 |
| 740 | #define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) |
| 741 | |
| 742 | /* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */ |
| 743 | #define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 |
| 744 | #define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH 0x1 |
| 745 | #define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) |
| 746 | |
| 747 | /* Used by RM_DSP_DSP_CONTEXT */ |
| 748 | #define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT 10 |
| 749 | #define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH 0x1 |
| 750 | #define OMAP54XX_LOSTMEM_DSP_EDMA_MASK (1 << 10) |
| 751 | |
| 752 | /* Used by RM_DSP_DSP_CONTEXT */ |
| 753 | #define OMAP54XX_LOSTMEM_DSP_L1_SHIFT 8 |
| 754 | #define OMAP54XX_LOSTMEM_DSP_L1_WIDTH 0x1 |
| 755 | #define OMAP54XX_LOSTMEM_DSP_L1_MASK (1 << 8) |
| 756 | |
| 757 | /* Used by RM_DSP_DSP_CONTEXT */ |
| 758 | #define OMAP54XX_LOSTMEM_DSP_L2_SHIFT 9 |
| 759 | #define OMAP54XX_LOSTMEM_DSP_L2_WIDTH 0x1 |
| 760 | #define OMAP54XX_LOSTMEM_DSP_L2_MASK (1 << 9) |
| 761 | |
| 762 | /* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */ |
| 763 | #define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT 8 |
| 764 | #define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH 0x1 |
| 765 | #define OMAP54XX_LOSTMEM_DSS_MEM_MASK (1 << 8) |
| 766 | |
| 767 | /* Used by RM_EMU_DEBUGSS_CONTEXT */ |
| 768 | #define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT 8 |
| 769 | #define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH 0x1 |
| 770 | #define OMAP54XX_LOSTMEM_EMU_BANK_MASK (1 << 8) |
| 771 | |
| 772 | /* Used by RM_GPU_GPU_CONTEXT */ |
| 773 | #define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT 8 |
| 774 | #define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH 0x1 |
| 775 | #define OMAP54XX_LOSTMEM_GPU_MEM_MASK (1 << 8) |
| 776 | |
| 777 | /* Used by RM_IVA_IVA_CONTEXT */ |
| 778 | #define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT 10 |
| 779 | #define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH 0x1 |
| 780 | #define OMAP54XX_LOSTMEM_HWA_MEM_MASK (1 << 10) |
| 781 | |
| 782 | /* Used by RM_IPU_IPU_CONTEXT */ |
| 783 | #define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT 9 |
| 784 | #define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH 0x1 |
| 785 | #define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK (1 << 9) |
| 786 | |
| 787 | /* Used by RM_IPU_IPU_CONTEXT */ |
| 788 | #define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT 8 |
| 789 | #define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH 0x1 |
| 790 | #define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK (1 << 8) |
| 791 | |
| 792 | /* |
| 793 | * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, |
| 794 | * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, |
| 795 | * RM_L3INIT_USB_OTG_SS_CONTEXT |
| 796 | */ |
| 797 | #define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT 8 |
| 798 | #define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH 0x1 |
| 799 | #define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) |
| 800 | |
| 801 | /* Used by RM_MPU_MPU_CONTEXT */ |
| 802 | #define OMAP54XX_LOSTMEM_MPU_L2_SHIFT 9 |
| 803 | #define OMAP54XX_LOSTMEM_MPU_L2_WIDTH 0x1 |
| 804 | #define OMAP54XX_LOSTMEM_MPU_L2_MASK (1 << 9) |
| 805 | |
| 806 | /* Used by RM_MPU_MPU_CONTEXT */ |
| 807 | #define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT 10 |
| 808 | #define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH 0x1 |
| 809 | #define OMAP54XX_LOSTMEM_MPU_RAM_MASK (1 << 10) |
| 810 | |
| 811 | /* |
| 812 | * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, |
| 813 | * RM_L4SEC_FPKA_CONTEXT |
| 814 | */ |
| 815 | #define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT 8 |
| 816 | #define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH 0x1 |
| 817 | #define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) |
| 818 | |
| 819 | /* |
| 820 | * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, |
| 821 | * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT |
| 822 | */ |
| 823 | #define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT 8 |
| 824 | #define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH 0x1 |
| 825 | #define OMAP54XX_LOSTMEM_PERIHPMEM_MASK (1 << 8) |
| 826 | |
| 827 | /* |
| 828 | * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, |
| 829 | * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, |
| 830 | * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT |
| 831 | */ |
| 832 | #define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT 8 |
| 833 | #define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH 0x1 |
| 834 | #define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK (1 << 8) |
| 835 | |
| 836 | /* Used by RM_IVA_SL2_CONTEXT */ |
| 837 | #define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT 8 |
| 838 | #define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH 0x1 |
| 839 | #define OMAP54XX_LOSTMEM_SL2_MEM_MASK (1 << 8) |
| 840 | |
| 841 | /* Used by RM_IVA_IVA_CONTEXT */ |
| 842 | #define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT 8 |
| 843 | #define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH 0x1 |
| 844 | #define OMAP54XX_LOSTMEM_TCM1_MEM_MASK (1 << 8) |
| 845 | |
| 846 | /* Used by RM_IVA_IVA_CONTEXT */ |
| 847 | #define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT 9 |
| 848 | #define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH 0x1 |
| 849 | #define OMAP54XX_LOSTMEM_TCM2_MEM_MASK (1 << 9) |
| 850 | |
| 851 | /* Used by RM_WKUPAON_SAR_RAM_CONTEXT */ |
| 852 | #define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT 8 |
| 853 | #define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH 0x1 |
| 854 | #define OMAP54XX_LOSTMEM_WKUP_BANK_MASK (1 << 8) |
| 855 | |
| 856 | /* |
| 857 | * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, |
| 858 | * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, |
| 859 | * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL |
| 860 | */ |
| 861 | #define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT 4 |
| 862 | #define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH 0x1 |
| 863 | #define OMAP54XX_LOWPOWERSTATECHANGE_MASK (1 << 4) |
| 864 | |
| 865 | /* Used by PRM_DEBUG_TRANS_CFG */ |
| 866 | #define OMAP54XX_MODE_SHIFT 0 |
| 867 | #define OMAP54XX_MODE_WIDTH 0x2 |
| 868 | #define OMAP54XX_MODE_MASK (0x3 << 0) |
| 869 | |
| 870 | /* Used by PRM_MODEM_IF_CTRL */ |
| 871 | #define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT 9 |
| 872 | #define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH 0x1 |
| 873 | #define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) |
| 874 | |
| 875 | /* Used by PRM_MODEM_IF_CTRL */ |
| 876 | #define OMAP54XX_MODEM_WAKE_IRQ_SHIFT 8 |
| 877 | #define OMAP54XX_MODEM_WAKE_IRQ_WIDTH 0x1 |
| 878 | #define OMAP54XX_MODEM_WAKE_IRQ_MASK (1 << 8) |
| 879 | |
| 880 | /* Used by PM_MPU_PWRSTCTRL */ |
| 881 | #define OMAP54XX_MPU_L2_ONSTATE_SHIFT 18 |
| 882 | #define OMAP54XX_MPU_L2_ONSTATE_WIDTH 0x2 |
| 883 | #define OMAP54XX_MPU_L2_ONSTATE_MASK (0x3 << 18) |
| 884 | |
| 885 | /* Used by PM_MPU_PWRSTCTRL */ |
| 886 | #define OMAP54XX_MPU_L2_RETSTATE_SHIFT 9 |
| 887 | #define OMAP54XX_MPU_L2_RETSTATE_WIDTH 0x1 |
| 888 | #define OMAP54XX_MPU_L2_RETSTATE_MASK (1 << 9) |
| 889 | |
| 890 | /* Used by PM_MPU_PWRSTST */ |
| 891 | #define OMAP54XX_MPU_L2_STATEST_SHIFT 6 |
| 892 | #define OMAP54XX_MPU_L2_STATEST_WIDTH 0x2 |
| 893 | #define OMAP54XX_MPU_L2_STATEST_MASK (0x3 << 6) |
| 894 | |
| 895 | /* Used by PM_MPU_PWRSTCTRL */ |
| 896 | #define OMAP54XX_MPU_RAM_ONSTATE_SHIFT 20 |
| 897 | #define OMAP54XX_MPU_RAM_ONSTATE_WIDTH 0x2 |
| 898 | #define OMAP54XX_MPU_RAM_ONSTATE_MASK (0x3 << 20) |
| 899 | |
| 900 | /* Used by PM_MPU_PWRSTCTRL */ |
| 901 | #define OMAP54XX_MPU_RAM_RETSTATE_SHIFT 10 |
| 902 | #define OMAP54XX_MPU_RAM_RETSTATE_WIDTH 0x1 |
| 903 | #define OMAP54XX_MPU_RAM_RETSTATE_MASK (1 << 10) |
| 904 | |
| 905 | /* Used by PM_MPU_PWRSTST */ |
| 906 | #define OMAP54XX_MPU_RAM_STATEST_SHIFT 8 |
| 907 | #define OMAP54XX_MPU_RAM_STATEST_WIDTH 0x2 |
| 908 | #define OMAP54XX_MPU_RAM_STATEST_MASK (0x3 << 8) |
| 909 | |
| 910 | /* Used by PRM_RSTST */ |
| 911 | #define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT 2 |
| 912 | #define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH 0x1 |
| 913 | #define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) |
| 914 | |
| 915 | /* Used by PRM_RSTST */ |
| 916 | #define OMAP54XX_MPU_WDT_RST_SHIFT 3 |
| 917 | #define OMAP54XX_MPU_WDT_RST_WIDTH 0x1 |
| 918 | #define OMAP54XX_MPU_WDT_RST_MASK (1 << 3) |
| 919 | |
| 920 | /* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ |
| 921 | #define OMAP54XX_NOCAP_SHIFT 4 |
| 922 | #define OMAP54XX_NOCAP_WIDTH 0x1 |
| 923 | #define OMAP54XX_NOCAP_MASK (1 << 4) |
| 924 | |
| 925 | /* Used by PM_CORE_PWRSTCTRL */ |
| 926 | #define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT 24 |
| 927 | #define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH 0x2 |
| 928 | #define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) |
| 929 | |
| 930 | /* Used by PM_CORE_PWRSTCTRL */ |
| 931 | #define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT 12 |
| 932 | #define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH 0x1 |
| 933 | #define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) |
| 934 | |
| 935 | /* Used by PM_CORE_PWRSTST */ |
| 936 | #define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT 12 |
| 937 | #define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH 0x2 |
| 938 | #define OMAP54XX_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) |
| 939 | |
| 940 | /* |
| 941 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, |
| 942 | * PRM_VC_VAL_CMD_VDD_MPU_L |
| 943 | */ |
| 944 | #define OMAP54XX_OFF_SHIFT 0 |
| 945 | #define OMAP54XX_OFF_WIDTH 0x8 |
| 946 | #define OMAP54XX_OFF_MASK (0xff << 0) |
| 947 | |
| 948 | /* |
| 949 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, |
| 950 | * PRM_VC_VAL_CMD_VDD_MPU_L |
| 951 | */ |
| 952 | #define OMAP54XX_ON_SHIFT 24 |
| 953 | #define OMAP54XX_ON_WIDTH 0x8 |
| 954 | #define OMAP54XX_ON_MASK (0xff << 24) |
| 955 | |
| 956 | /* |
| 957 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, |
| 958 | * PRM_VC_VAL_CMD_VDD_MPU_L |
| 959 | */ |
| 960 | #define OMAP54XX_ONLP_SHIFT 16 |
| 961 | #define OMAP54XX_ONLP_WIDTH 0x8 |
| 962 | #define OMAP54XX_ONLP_MASK (0xff << 16) |
| 963 | |
| 964 | /* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ |
| 965 | #define OMAP54XX_OPP_CHANGE_SHIFT 2 |
| 966 | #define OMAP54XX_OPP_CHANGE_WIDTH 0x1 |
| 967 | #define OMAP54XX_OPP_CHANGE_MASK (1 << 2) |
| 968 | |
| 969 | /* Used by PRM_VC_VAL_BYPASS */ |
| 970 | #define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT 25 |
| 971 | #define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH 0x1 |
| 972 | #define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK (1 << 25) |
| 973 | |
| 974 | /* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ |
| 975 | #define OMAP54XX_OPP_SEL_SHIFT 0 |
| 976 | #define OMAP54XX_OPP_SEL_WIDTH 0x2 |
| 977 | #define OMAP54XX_OPP_SEL_MASK (0x3 << 0) |
| 978 | |
| 979 | /* Used by PRM_DEBUG_OUT */ |
| 980 | #define OMAP54XX_OUTPUT_SHIFT 0 |
| 981 | #define OMAP54XX_OUTPUT_WIDTH 0x20 |
| 982 | #define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) |
| 983 | |
| 984 | /* Used by PRM_SRAM_COUNT */ |
| 985 | #define OMAP54XX_PCHARGECNT_VALUE_SHIFT 0 |
| 986 | #define OMAP54XX_PCHARGECNT_VALUE_WIDTH 0x6 |
| 987 | #define OMAP54XX_PCHARGECNT_VALUE_MASK (0x3f << 0) |
| 988 | |
| 989 | /* Used by PRM_PSCON_COUNT */ |
| 990 | #define OMAP54XX_PCHARGE_TIME_SHIFT 0 |
| 991 | #define OMAP54XX_PCHARGE_TIME_WIDTH 0x8 |
| 992 | #define OMAP54XX_PCHARGE_TIME_MASK (0xff << 0) |
| 993 | |
| 994 | /* Used by PM_ABE_PWRSTCTRL */ |
| 995 | #define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT 20 |
| 996 | #define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH 0x2 |
| 997 | #define OMAP54XX_PERIPHMEM_ONSTATE_MASK (0x3 << 20) |
| 998 | |
| 999 | /* Used by PM_ABE_PWRSTCTRL */ |
| 1000 | #define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT 10 |
| 1001 | #define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH 0x1 |
| 1002 | #define OMAP54XX_PERIPHMEM_RETSTATE_MASK (1 << 10) |
| 1003 | |
| 1004 | /* Used by PM_ABE_PWRSTST */ |
| 1005 | #define OMAP54XX_PERIPHMEM_STATEST_SHIFT 8 |
| 1006 | #define OMAP54XX_PERIPHMEM_STATEST_WIDTH 0x2 |
| 1007 | #define OMAP54XX_PERIPHMEM_STATEST_MASK (0x3 << 8) |
| 1008 | |
| 1009 | /* Used by PRM_PHASE1_CNDP */ |
| 1010 | #define OMAP54XX_PHASE1_CNDP_SHIFT 0 |
| 1011 | #define OMAP54XX_PHASE1_CNDP_WIDTH 0x20 |
| 1012 | #define OMAP54XX_PHASE1_CNDP_MASK (0xffffffff << 0) |
| 1013 | |
| 1014 | /* Used by PRM_PHASE2A_CNDP */ |
| 1015 | #define OMAP54XX_PHASE2A_CNDP_SHIFT 0 |
| 1016 | #define OMAP54XX_PHASE2A_CNDP_WIDTH 0x20 |
| 1017 | #define OMAP54XX_PHASE2A_CNDP_MASK (0xffffffff << 0) |
| 1018 | |
| 1019 | /* Used by PRM_PHASE2B_CNDP */ |
| 1020 | #define OMAP54XX_PHASE2B_CNDP_SHIFT 0 |
| 1021 | #define OMAP54XX_PHASE2B_CNDP_WIDTH 0x20 |
| 1022 | #define OMAP54XX_PHASE2B_CNDP_MASK (0xffffffff << 0) |
| 1023 | |
| 1024 | /* Used by PRM_PSCON_COUNT */ |
| 1025 | #define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT 8 |
| 1026 | #define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH 0x8 |
| 1027 | #define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) |
| 1028 | |
| 1029 | /* |
| 1030 | * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, |
| 1031 | * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, |
| 1032 | * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, |
| 1033 | * PM_MPU_PWRSTCTRL |
| 1034 | */ |
| 1035 | #define OMAP54XX_POWERSTATE_SHIFT 0 |
| 1036 | #define OMAP54XX_POWERSTATE_WIDTH 0x2 |
| 1037 | #define OMAP54XX_POWERSTATE_MASK (0x3 << 0) |
| 1038 | |
| 1039 | /* |
| 1040 | * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, |
| 1041 | * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, |
| 1042 | * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST |
| 1043 | */ |
| 1044 | #define OMAP54XX_POWERSTATEST_SHIFT 0 |
| 1045 | #define OMAP54XX_POWERSTATEST_WIDTH 0x2 |
| 1046 | #define OMAP54XX_POWERSTATEST_MASK (0x3 << 0) |
| 1047 | |
| 1048 | /* Used by PRM_PWRREQCTRL */ |
| 1049 | #define OMAP54XX_PWRREQ_COND_SHIFT 0 |
| 1050 | #define OMAP54XX_PWRREQ_COND_WIDTH 0x2 |
| 1051 | #define OMAP54XX_PWRREQ_COND_MASK (0x3 << 0) |
| 1052 | |
| 1053 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ |
| 1054 | #define OMAP54XX_RACEN_VDD_CORE_L_SHIFT 27 |
| 1055 | #define OMAP54XX_RACEN_VDD_CORE_L_WIDTH 0x1 |
| 1056 | #define OMAP54XX_RACEN_VDD_CORE_L_MASK (1 << 27) |
| 1057 | |
| 1058 | /* Used by PRM_VC_SMPS_MM_CONFIG */ |
| 1059 | #define OMAP54XX_RACEN_VDD_MM_L_SHIFT 27 |
| 1060 | #define OMAP54XX_RACEN_VDD_MM_L_WIDTH 0x1 |
| 1061 | #define OMAP54XX_RACEN_VDD_MM_L_MASK (1 << 27) |
| 1062 | |
| 1063 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ |
| 1064 | #define OMAP54XX_RACEN_VDD_MPU_L_SHIFT 27 |
| 1065 | #define OMAP54XX_RACEN_VDD_MPU_L_WIDTH 0x1 |
| 1066 | #define OMAP54XX_RACEN_VDD_MPU_L_MASK (1 << 27) |
| 1067 | |
| 1068 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ |
| 1069 | #define OMAP54XX_RAC_VDD_CORE_L_SHIFT 26 |
| 1070 | #define OMAP54XX_RAC_VDD_CORE_L_WIDTH 0x1 |
| 1071 | #define OMAP54XX_RAC_VDD_CORE_L_MASK (1 << 26) |
| 1072 | |
| 1073 | /* Used by PRM_VC_SMPS_MM_CONFIG */ |
| 1074 | #define OMAP54XX_RAC_VDD_MM_L_SHIFT 26 |
| 1075 | #define OMAP54XX_RAC_VDD_MM_L_WIDTH 0x1 |
| 1076 | #define OMAP54XX_RAC_VDD_MM_L_MASK (1 << 26) |
| 1077 | |
| 1078 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ |
| 1079 | #define OMAP54XX_RAC_VDD_MPU_L_SHIFT 26 |
| 1080 | #define OMAP54XX_RAC_VDD_MPU_L_WIDTH 0x1 |
| 1081 | #define OMAP54XX_RAC_VDD_MPU_L_MASK (1 << 26) |
| 1082 | |
| 1083 | /* |
| 1084 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, |
| 1085 | * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, |
| 1086 | * PRM_VOLTSETUP_MPU_RET_SLEEP |
| 1087 | */ |
| 1088 | #define OMAP54XX_RAMP_DOWN_COUNT_SHIFT 16 |
| 1089 | #define OMAP54XX_RAMP_DOWN_COUNT_WIDTH 0x6 |
| 1090 | #define OMAP54XX_RAMP_DOWN_COUNT_MASK (0x3f << 16) |
| 1091 | |
| 1092 | /* |
| 1093 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, |
| 1094 | * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, |
| 1095 | * PRM_VOLTSETUP_MPU_RET_SLEEP |
| 1096 | */ |
| 1097 | #define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT 24 |
| 1098 | #define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH 0x2 |
| 1099 | #define OMAP54XX_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) |
| 1100 | |
| 1101 | /* |
| 1102 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, |
| 1103 | * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, |
| 1104 | * PRM_VOLTSETUP_MPU_RET_SLEEP |
| 1105 | */ |
| 1106 | #define OMAP54XX_RAMP_UP_COUNT_SHIFT 0 |
| 1107 | #define OMAP54XX_RAMP_UP_COUNT_WIDTH 0x6 |
| 1108 | #define OMAP54XX_RAMP_UP_COUNT_MASK (0x3f << 0) |
| 1109 | |
| 1110 | /* |
| 1111 | * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, |
| 1112 | * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, |
| 1113 | * PRM_VOLTSETUP_MPU_RET_SLEEP |
| 1114 | */ |
| 1115 | #define OMAP54XX_RAMP_UP_PRESCAL_SHIFT 8 |
| 1116 | #define OMAP54XX_RAMP_UP_PRESCAL_WIDTH 0x2 |
| 1117 | #define OMAP54XX_RAMP_UP_PRESCAL_MASK (0x3 << 8) |
| 1118 | |
| 1119 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ |
| 1120 | #define OMAP54XX_RAV_VDD_CORE_L_SHIFT 25 |
| 1121 | #define OMAP54XX_RAV_VDD_CORE_L_WIDTH 0x1 |
| 1122 | #define OMAP54XX_RAV_VDD_CORE_L_MASK (1 << 25) |
| 1123 | |
| 1124 | /* Used by PRM_VC_SMPS_MM_CONFIG */ |
| 1125 | #define OMAP54XX_RAV_VDD_MM_L_SHIFT 25 |
| 1126 | #define OMAP54XX_RAV_VDD_MM_L_WIDTH 0x1 |
| 1127 | #define OMAP54XX_RAV_VDD_MM_L_MASK (1 << 25) |
| 1128 | |
| 1129 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ |
| 1130 | #define OMAP54XX_RAV_VDD_MPU_L_SHIFT 25 |
| 1131 | #define OMAP54XX_RAV_VDD_MPU_L_WIDTH 0x1 |
| 1132 | #define OMAP54XX_RAV_VDD_MPU_L_MASK (1 << 25) |
| 1133 | |
| 1134 | /* Used by PRM_VC_VAL_BYPASS */ |
| 1135 | #define OMAP54XX_REGADDR_SHIFT 8 |
| 1136 | #define OMAP54XX_REGADDR_WIDTH 0x8 |
| 1137 | #define OMAP54XX_REGADDR_MASK (0xff << 8) |
| 1138 | |
| 1139 | /* |
| 1140 | * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, |
| 1141 | * PRM_VC_VAL_CMD_VDD_MPU_L |
| 1142 | */ |
| 1143 | #define OMAP54XX_RET_SHIFT 8 |
| 1144 | #define OMAP54XX_RET_WIDTH 0x8 |
| 1145 | #define OMAP54XX_RET_MASK (0xff << 8) |
| 1146 | |
| 1147 | /* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ |
| 1148 | #define OMAP54XX_RETMODE_ENABLE_SHIFT 0 |
| 1149 | #define OMAP54XX_RETMODE_ENABLE_WIDTH 0x1 |
| 1150 | #define OMAP54XX_RETMODE_ENABLE_MASK (1 << 0) |
| 1151 | |
| 1152 | /* Used by PRM_RSTTIME */ |
| 1153 | #define OMAP54XX_RSTTIME1_SHIFT 0 |
| 1154 | #define OMAP54XX_RSTTIME1_WIDTH 0xa |
| 1155 | #define OMAP54XX_RSTTIME1_MASK (0x3ff << 0) |
| 1156 | |
| 1157 | /* Used by PRM_RSTTIME */ |
| 1158 | #define OMAP54XX_RSTTIME2_SHIFT 10 |
| 1159 | #define OMAP54XX_RSTTIME2_WIDTH 0x5 |
| 1160 | #define OMAP54XX_RSTTIME2_MASK (0x1f << 10) |
| 1161 | |
| 1162 | /* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ |
| 1163 | #define OMAP54XX_RST_CPU0_SHIFT 0 |
| 1164 | #define OMAP54XX_RST_CPU0_WIDTH 0x1 |
| 1165 | #define OMAP54XX_RST_CPU0_MASK (1 << 0) |
| 1166 | |
| 1167 | /* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ |
| 1168 | #define OMAP54XX_RST_CPU1_SHIFT 1 |
| 1169 | #define OMAP54XX_RST_CPU1_WIDTH 0x1 |
| 1170 | #define OMAP54XX_RST_CPU1_MASK (1 << 1) |
| 1171 | |
| 1172 | /* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ |
| 1173 | #define OMAP54XX_RST_DSP_SHIFT 0 |
| 1174 | #define OMAP54XX_RST_DSP_WIDTH 0x1 |
| 1175 | #define OMAP54XX_RST_DSP_MASK (1 << 0) |
| 1176 | |
| 1177 | /* Used by RM_DSP_RSTST */ |
| 1178 | #define OMAP54XX_RST_DSP_EMU_SHIFT 2 |
| 1179 | #define OMAP54XX_RST_DSP_EMU_WIDTH 0x1 |
| 1180 | #define OMAP54XX_RST_DSP_EMU_MASK (1 << 2) |
| 1181 | |
| 1182 | /* Used by RM_DSP_RSTST */ |
| 1183 | #define OMAP54XX_RST_DSP_EMU_REQ_SHIFT 3 |
| 1184 | #define OMAP54XX_RST_DSP_EMU_REQ_WIDTH 0x1 |
| 1185 | #define OMAP54XX_RST_DSP_EMU_REQ_MASK (1 << 3) |
| 1186 | |
| 1187 | /* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ |
| 1188 | #define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT 1 |
| 1189 | #define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH 0x1 |
| 1190 | #define OMAP54XX_RST_DSP_MMU_CACHE_MASK (1 << 1) |
| 1191 | |
| 1192 | /* Used by RM_IPU_RSTST */ |
| 1193 | #define OMAP54XX_RST_EMULATION_CPU0_SHIFT 3 |
| 1194 | #define OMAP54XX_RST_EMULATION_CPU0_WIDTH 0x1 |
| 1195 | #define OMAP54XX_RST_EMULATION_CPU0_MASK (1 << 3) |
| 1196 | |
| 1197 | /* Used by RM_IPU_RSTST */ |
| 1198 | #define OMAP54XX_RST_EMULATION_CPU1_SHIFT 4 |
| 1199 | #define OMAP54XX_RST_EMULATION_CPU1_WIDTH 0x1 |
| 1200 | #define OMAP54XX_RST_EMULATION_CPU1_MASK (1 << 4) |
| 1201 | |
| 1202 | /* Used by RM_IVA_RSTST */ |
| 1203 | #define OMAP54XX_RST_EMULATION_SEQ1_SHIFT 3 |
| 1204 | #define OMAP54XX_RST_EMULATION_SEQ1_WIDTH 0x1 |
| 1205 | #define OMAP54XX_RST_EMULATION_SEQ1_MASK (1 << 3) |
| 1206 | |
| 1207 | /* Used by RM_IVA_RSTST */ |
| 1208 | #define OMAP54XX_RST_EMULATION_SEQ2_SHIFT 4 |
| 1209 | #define OMAP54XX_RST_EMULATION_SEQ2_WIDTH 0x1 |
| 1210 | #define OMAP54XX_RST_EMULATION_SEQ2_MASK (1 << 4) |
| 1211 | |
| 1212 | /* Used by PRM_RSTCTRL */ |
| 1213 | #define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT 1 |
| 1214 | #define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH 0x1 |
| 1215 | #define OMAP54XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) |
| 1216 | |
| 1217 | /* Used by PRM_RSTCTRL */ |
| 1218 | #define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT 0 |
| 1219 | #define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH 0x1 |
| 1220 | #define OMAP54XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) |
| 1221 | |
| 1222 | /* Used by RM_IPU_RSTST */ |
| 1223 | #define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT 5 |
| 1224 | #define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH 0x1 |
| 1225 | #define OMAP54XX_RST_ICECRUSHER_CPU0_MASK (1 << 5) |
| 1226 | |
| 1227 | /* Used by RM_IPU_RSTST */ |
| 1228 | #define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT 6 |
| 1229 | #define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH 0x1 |
| 1230 | #define OMAP54XX_RST_ICECRUSHER_CPU1_MASK (1 << 6) |
| 1231 | |
| 1232 | /* Used by RM_IVA_RSTST */ |
| 1233 | #define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT 5 |
| 1234 | #define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH 0x1 |
| 1235 | #define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK (1 << 5) |
| 1236 | |
| 1237 | /* Used by RM_IVA_RSTST */ |
| 1238 | #define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT 6 |
| 1239 | #define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH 0x1 |
| 1240 | #define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK (1 << 6) |
| 1241 | |
| 1242 | /* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ |
| 1243 | #define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT 2 |
| 1244 | #define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH 0x1 |
| 1245 | #define OMAP54XX_RST_IPU_MMU_CACHE_MASK (1 << 2) |
| 1246 | |
| 1247 | /* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ |
| 1248 | #define OMAP54XX_RST_LOGIC_SHIFT 2 |
| 1249 | #define OMAP54XX_RST_LOGIC_WIDTH 0x1 |
| 1250 | #define OMAP54XX_RST_LOGIC_MASK (1 << 2) |
| 1251 | |
| 1252 | /* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ |
| 1253 | #define OMAP54XX_RST_SEQ1_SHIFT 0 |
| 1254 | #define OMAP54XX_RST_SEQ1_WIDTH 0x1 |
| 1255 | #define OMAP54XX_RST_SEQ1_MASK (1 << 0) |
| 1256 | |
| 1257 | /* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ |
| 1258 | #define OMAP54XX_RST_SEQ2_SHIFT 1 |
| 1259 | #define OMAP54XX_RST_SEQ2_WIDTH 0x1 |
| 1260 | #define OMAP54XX_RST_SEQ2_MASK (1 << 1) |
| 1261 | |
| 1262 | /* Used by REVISION_PRM */ |
| 1263 | #define OMAP54XX_R_RTL_SHIFT 11 |
| 1264 | #define OMAP54XX_R_RTL_WIDTH 0x5 |
| 1265 | #define OMAP54XX_R_RTL_MASK (0x1f << 11) |
| 1266 | |
| 1267 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ |
| 1268 | #define OMAP54XX_SA_VDD_CORE_L_SHIFT 0 |
| 1269 | #define OMAP54XX_SA_VDD_CORE_L_WIDTH 0x7 |
| 1270 | #define OMAP54XX_SA_VDD_CORE_L_MASK (0x7f << 0) |
| 1271 | |
| 1272 | /* Used by PRM_VC_SMPS_MM_CONFIG */ |
| 1273 | #define OMAP54XX_SA_VDD_MM_L_SHIFT 0 |
| 1274 | #define OMAP54XX_SA_VDD_MM_L_WIDTH 0x7 |
| 1275 | #define OMAP54XX_SA_VDD_MM_L_MASK (0x7f << 0) |
| 1276 | |
| 1277 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ |
| 1278 | #define OMAP54XX_SA_VDD_MPU_L_SHIFT 0 |
| 1279 | #define OMAP54XX_SA_VDD_MPU_L_WIDTH 0x7 |
| 1280 | #define OMAP54XX_SA_VDD_MPU_L_MASK (0x7f << 0) |
| 1281 | |
| 1282 | /* Used by REVISION_PRM */ |
| 1283 | #define OMAP54XX_SCHEME_SHIFT 30 |
| 1284 | #define OMAP54XX_SCHEME_WIDTH 0x2 |
| 1285 | #define OMAP54XX_SCHEME_MASK (0x3 << 30) |
| 1286 | |
| 1287 | /* Used by PRM_VC_CFG_I2C_CLK */ |
| 1288 | #define OMAP54XX_SCLH_SHIFT 0 |
| 1289 | #define OMAP54XX_SCLH_WIDTH 0x8 |
| 1290 | #define OMAP54XX_SCLH_MASK (0xff << 0) |
| 1291 | |
| 1292 | /* Used by PRM_VC_CFG_I2C_CLK */ |
| 1293 | #define OMAP54XX_SCLL_SHIFT 8 |
| 1294 | #define OMAP54XX_SCLL_WIDTH 0x8 |
| 1295 | #define OMAP54XX_SCLL_MASK (0xff << 8) |
| 1296 | |
| 1297 | /* Used by PRM_RSTST */ |
| 1298 | #define OMAP54XX_SECURE_WDT_RST_SHIFT 4 |
| 1299 | #define OMAP54XX_SECURE_WDT_RST_WIDTH 0x1 |
| 1300 | #define OMAP54XX_SECURE_WDT_RST_MASK (1 << 4) |
| 1301 | |
| 1302 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ |
| 1303 | #define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT 24 |
| 1304 | #define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH 0x1 |
| 1305 | #define OMAP54XX_SEL_SA_VDD_CORE_L_MASK (1 << 24) |
| 1306 | |
| 1307 | /* Used by PRM_VC_SMPS_MM_CONFIG */ |
| 1308 | #define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT 24 |
| 1309 | #define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH 0x1 |
| 1310 | #define OMAP54XX_SEL_SA_VDD_MM_L_MASK (1 << 24) |
| 1311 | |
| 1312 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ |
| 1313 | #define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT 24 |
| 1314 | #define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH 0x1 |
| 1315 | #define OMAP54XX_SEL_SA_VDD_MPU_L_MASK (1 << 24) |
| 1316 | |
| 1317 | /* Used by PM_IVA_PWRSTCTRL */ |
| 1318 | #define OMAP54XX_SL2_MEM_ONSTATE_SHIFT 18 |
| 1319 | #define OMAP54XX_SL2_MEM_ONSTATE_WIDTH 0x2 |
| 1320 | #define OMAP54XX_SL2_MEM_ONSTATE_MASK (0x3 << 18) |
| 1321 | |
| 1322 | /* Used by PM_IVA_PWRSTCTRL */ |
| 1323 | #define OMAP54XX_SL2_MEM_RETSTATE_SHIFT 9 |
| 1324 | #define OMAP54XX_SL2_MEM_RETSTATE_WIDTH 0x1 |
| 1325 | #define OMAP54XX_SL2_MEM_RETSTATE_MASK (1 << 9) |
| 1326 | |
| 1327 | /* Used by PM_IVA_PWRSTST */ |
| 1328 | #define OMAP54XX_SL2_MEM_STATEST_SHIFT 6 |
| 1329 | #define OMAP54XX_SL2_MEM_STATEST_WIDTH 0x2 |
| 1330 | #define OMAP54XX_SL2_MEM_STATEST_MASK (0x3 << 6) |
| 1331 | |
| 1332 | /* Used by PRM_VC_VAL_BYPASS */ |
| 1333 | #define OMAP54XX_SLAVEADDR_SHIFT 0 |
| 1334 | #define OMAP54XX_SLAVEADDR_WIDTH 0x7 |
| 1335 | #define OMAP54XX_SLAVEADDR_MASK (0x7f << 0) |
| 1336 | |
| 1337 | /* Used by PRM_SRAM_COUNT */ |
| 1338 | #define OMAP54XX_SLPCNT_VALUE_SHIFT 16 |
| 1339 | #define OMAP54XX_SLPCNT_VALUE_WIDTH 0x8 |
| 1340 | #define OMAP54XX_SLPCNT_VALUE_MASK (0xff << 16) |
| 1341 | |
| 1342 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ |
| 1343 | #define OMAP54XX_SMPSWAITTIMEMAX_SHIFT 8 |
| 1344 | #define OMAP54XX_SMPSWAITTIMEMAX_WIDTH 0x10 |
| 1345 | #define OMAP54XX_SMPSWAITTIMEMAX_MASK (0xffff << 8) |
| 1346 | |
| 1347 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ |
| 1348 | #define OMAP54XX_SMPSWAITTIMEMIN_SHIFT 8 |
| 1349 | #define OMAP54XX_SMPSWAITTIMEMIN_WIDTH 0x10 |
| 1350 | #define OMAP54XX_SMPSWAITTIMEMIN_MASK (0xffff << 8) |
| 1351 | |
| 1352 | /* Used by PRM_VC_CORE_ERRST */ |
| 1353 | #define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT 1 |
| 1354 | #define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH 0x1 |
| 1355 | #define OMAP54XX_SMPS_RA_ERR_CORE_MASK (1 << 1) |
| 1356 | |
| 1357 | /* Used by PRM_VC_MM_ERRST */ |
| 1358 | #define OMAP54XX_SMPS_RA_ERR_MM_SHIFT 1 |
| 1359 | #define OMAP54XX_SMPS_RA_ERR_MM_WIDTH 0x1 |
| 1360 | #define OMAP54XX_SMPS_RA_ERR_MM_MASK (1 << 1) |
| 1361 | |
| 1362 | /* Used by PRM_VC_MPU_ERRST */ |
| 1363 | #define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT 1 |
| 1364 | #define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH 0x1 |
| 1365 | #define OMAP54XX_SMPS_RA_ERR_MPU_MASK (1 << 1) |
| 1366 | |
| 1367 | /* Used by PRM_VC_CORE_ERRST */ |
| 1368 | #define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT 0 |
| 1369 | #define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH 0x1 |
| 1370 | #define OMAP54XX_SMPS_SA_ERR_CORE_MASK (1 << 0) |
| 1371 | |
| 1372 | /* Used by PRM_VC_MM_ERRST */ |
| 1373 | #define OMAP54XX_SMPS_SA_ERR_MM_SHIFT 0 |
| 1374 | #define OMAP54XX_SMPS_SA_ERR_MM_WIDTH 0x1 |
| 1375 | #define OMAP54XX_SMPS_SA_ERR_MM_MASK (1 << 0) |
| 1376 | |
| 1377 | /* Used by PRM_VC_MPU_ERRST */ |
| 1378 | #define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT 0 |
| 1379 | #define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH 0x1 |
| 1380 | #define OMAP54XX_SMPS_SA_ERR_MPU_MASK (1 << 0) |
| 1381 | |
| 1382 | /* Used by PRM_VC_CORE_ERRST */ |
| 1383 | #define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 |
| 1384 | #define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH 0x1 |
| 1385 | #define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) |
| 1386 | |
| 1387 | /* Used by PRM_VC_MM_ERRST */ |
| 1388 | #define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT 2 |
| 1389 | #define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH 0x1 |
| 1390 | #define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK (1 << 2) |
| 1391 | |
| 1392 | /* Used by PRM_VC_MPU_ERRST */ |
| 1393 | #define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT 2 |
| 1394 | #define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH 0x1 |
| 1395 | #define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 2) |
| 1396 | |
| 1397 | /* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ |
| 1398 | #define OMAP54XX_SR2EN_SHIFT 0 |
| 1399 | #define OMAP54XX_SR2EN_WIDTH 0x1 |
| 1400 | #define OMAP54XX_SR2EN_MASK (1 << 0) |
| 1401 | |
| 1402 | /* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ |
| 1403 | #define OMAP54XX_SR2_IN_TRANSITION_SHIFT 6 |
| 1404 | #define OMAP54XX_SR2_IN_TRANSITION_WIDTH 0x1 |
| 1405 | #define OMAP54XX_SR2_IN_TRANSITION_MASK (1 << 6) |
| 1406 | |
| 1407 | /* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ |
| 1408 | #define OMAP54XX_SR2_STATUS_SHIFT 3 |
| 1409 | #define OMAP54XX_SR2_STATUS_WIDTH 0x2 |
| 1410 | #define OMAP54XX_SR2_STATUS_MASK (0x3 << 3) |
| 1411 | |
| 1412 | /* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ |
| 1413 | #define OMAP54XX_SR2_WTCNT_VALUE_SHIFT 8 |
| 1414 | #define OMAP54XX_SR2_WTCNT_VALUE_WIDTH 0x8 |
| 1415 | #define OMAP54XX_SR2_WTCNT_VALUE_MASK (0xff << 8) |
| 1416 | |
| 1417 | /* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ |
| 1418 | #define OMAP54XX_SRAMLDO_STATUS_SHIFT 8 |
| 1419 | #define OMAP54XX_SRAMLDO_STATUS_WIDTH 0x1 |
| 1420 | #define OMAP54XX_SRAMLDO_STATUS_MASK (1 << 8) |
| 1421 | |
| 1422 | /* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ |
| 1423 | #define OMAP54XX_SRAM_IN_TRANSITION_SHIFT 9 |
| 1424 | #define OMAP54XX_SRAM_IN_TRANSITION_WIDTH 0x1 |
| 1425 | #define OMAP54XX_SRAM_IN_TRANSITION_MASK (1 << 9) |
| 1426 | |
| 1427 | /* Used by PRM_VC_CFG_I2C_MODE */ |
| 1428 | #define OMAP54XX_SRMODEEN_SHIFT 4 |
| 1429 | #define OMAP54XX_SRMODEEN_WIDTH 0x1 |
| 1430 | #define OMAP54XX_SRMODEEN_MASK (1 << 4) |
| 1431 | |
| 1432 | /* Used by PRM_VOLTSETUP_WARMRESET */ |
| 1433 | #define OMAP54XX_STABLE_COUNT_SHIFT 0 |
| 1434 | #define OMAP54XX_STABLE_COUNT_WIDTH 0x6 |
| 1435 | #define OMAP54XX_STABLE_COUNT_MASK (0x3f << 0) |
| 1436 | |
| 1437 | /* Used by PRM_VOLTSETUP_WARMRESET */ |
| 1438 | #define OMAP54XX_STABLE_PRESCAL_SHIFT 8 |
| 1439 | #define OMAP54XX_STABLE_PRESCAL_WIDTH 0x2 |
| 1440 | #define OMAP54XX_STABLE_PRESCAL_MASK (0x3 << 8) |
| 1441 | |
| 1442 | /* Used by PRM_BANDGAP_SETUP */ |
| 1443 | #define OMAP54XX_STARTUP_COUNT_SHIFT 0 |
| 1444 | #define OMAP54XX_STARTUP_COUNT_WIDTH 0x8 |
| 1445 | #define OMAP54XX_STARTUP_COUNT_MASK (0xff << 0) |
| 1446 | |
| 1447 | /* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ |
| 1448 | #define OMAP54XX_STARTUP_COUNT_24_31_SHIFT 24 |
| 1449 | #define OMAP54XX_STARTUP_COUNT_24_31_WIDTH 0x8 |
| 1450 | #define OMAP54XX_STARTUP_COUNT_24_31_MASK (0xff << 24) |
| 1451 | |
| 1452 | /* Used by PM_IVA_PWRSTCTRL */ |
| 1453 | #define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT 20 |
| 1454 | #define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH 0x2 |
| 1455 | #define OMAP54XX_TCM1_MEM_ONSTATE_MASK (0x3 << 20) |
| 1456 | |
| 1457 | /* Used by PM_IVA_PWRSTCTRL */ |
| 1458 | #define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT 10 |
| 1459 | #define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH 0x1 |
| 1460 | #define OMAP54XX_TCM1_MEM_RETSTATE_MASK (1 << 10) |
| 1461 | |
| 1462 | /* Used by PM_IVA_PWRSTST */ |
| 1463 | #define OMAP54XX_TCM1_MEM_STATEST_SHIFT 8 |
| 1464 | #define OMAP54XX_TCM1_MEM_STATEST_WIDTH 0x2 |
| 1465 | #define OMAP54XX_TCM1_MEM_STATEST_MASK (0x3 << 8) |
| 1466 | |
| 1467 | /* Used by PM_IVA_PWRSTCTRL */ |
| 1468 | #define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT 22 |
| 1469 | #define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH 0x2 |
| 1470 | #define OMAP54XX_TCM2_MEM_ONSTATE_MASK (0x3 << 22) |
| 1471 | |
| 1472 | /* Used by PM_IVA_PWRSTCTRL */ |
| 1473 | #define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT 11 |
| 1474 | #define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH 0x1 |
| 1475 | #define OMAP54XX_TCM2_MEM_RETSTATE_MASK (1 << 11) |
| 1476 | |
| 1477 | /* Used by PM_IVA_PWRSTST */ |
| 1478 | #define OMAP54XX_TCM2_MEM_STATEST_SHIFT 10 |
| 1479 | #define OMAP54XX_TCM2_MEM_STATEST_WIDTH 0x2 |
| 1480 | #define OMAP54XX_TCM2_MEM_STATEST_MASK (0x3 << 10) |
| 1481 | |
| 1482 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ |
| 1483 | #define OMAP54XX_TIMEOUT_SHIFT 0 |
| 1484 | #define OMAP54XX_TIMEOUT_WIDTH 0x10 |
| 1485 | #define OMAP54XX_TIMEOUT_MASK (0xffff << 0) |
| 1486 | |
| 1487 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ |
| 1488 | #define OMAP54XX_TIMEOUTEN_SHIFT 3 |
| 1489 | #define OMAP54XX_TIMEOUTEN_WIDTH 0x1 |
| 1490 | #define OMAP54XX_TIMEOUTEN_MASK (1 << 3) |
| 1491 | |
| 1492 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1493 | #define OMAP54XX_TRANSITION_EN_SHIFT 8 |
| 1494 | #define OMAP54XX_TRANSITION_EN_WIDTH 0x1 |
| 1495 | #define OMAP54XX_TRANSITION_EN_MASK (1 << 8) |
| 1496 | |
| 1497 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1498 | #define OMAP54XX_TRANSITION_ST_SHIFT 8 |
| 1499 | #define OMAP54XX_TRANSITION_ST_WIDTH 0x1 |
| 1500 | #define OMAP54XX_TRANSITION_ST_MASK (1 << 8) |
| 1501 | |
| 1502 | /* Used by PRM_DEBUG_TRANS_CFG */ |
| 1503 | #define OMAP54XX_TRIGGER_CLEAR_SHIFT 2 |
| 1504 | #define OMAP54XX_TRIGGER_CLEAR_WIDTH 0x1 |
| 1505 | #define OMAP54XX_TRIGGER_CLEAR_MASK (1 << 2) |
| 1506 | |
| 1507 | /* Used by PRM_RSTST */ |
| 1508 | #define OMAP54XX_TSHUT_CORE_RST_SHIFT 13 |
| 1509 | #define OMAP54XX_TSHUT_CORE_RST_WIDTH 0x1 |
| 1510 | #define OMAP54XX_TSHUT_CORE_RST_MASK (1 << 13) |
| 1511 | |
| 1512 | /* Used by PRM_RSTST */ |
| 1513 | #define OMAP54XX_TSHUT_MM_RST_SHIFT 12 |
| 1514 | #define OMAP54XX_TSHUT_MM_RST_WIDTH 0x1 |
| 1515 | #define OMAP54XX_TSHUT_MM_RST_MASK (1 << 12) |
| 1516 | |
| 1517 | /* Used by PRM_RSTST */ |
| 1518 | #define OMAP54XX_TSHUT_MPU_RST_SHIFT 11 |
| 1519 | #define OMAP54XX_TSHUT_MPU_RST_WIDTH 0x1 |
| 1520 | #define OMAP54XX_TSHUT_MPU_RST_MASK (1 << 11) |
| 1521 | |
| 1522 | /* Used by PRM_VC_VAL_BYPASS */ |
| 1523 | #define OMAP54XX_VALID_SHIFT 24 |
| 1524 | #define OMAP54XX_VALID_WIDTH 0x1 |
| 1525 | #define OMAP54XX_VALID_MASK (1 << 24) |
| 1526 | |
| 1527 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1528 | #define OMAP54XX_VC_BYPASSACK_EN_SHIFT 14 |
| 1529 | #define OMAP54XX_VC_BYPASSACK_EN_WIDTH 0x1 |
| 1530 | #define OMAP54XX_VC_BYPASSACK_EN_MASK (1 << 14) |
| 1531 | |
| 1532 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1533 | #define OMAP54XX_VC_BYPASSACK_ST_SHIFT 14 |
| 1534 | #define OMAP54XX_VC_BYPASSACK_ST_WIDTH 0x1 |
| 1535 | #define OMAP54XX_VC_BYPASSACK_ST_MASK (1 << 14) |
| 1536 | |
| 1537 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1538 | #define OMAP54XX_VC_CORE_VPACK_EN_SHIFT 22 |
| 1539 | #define OMAP54XX_VC_CORE_VPACK_EN_WIDTH 0x1 |
| 1540 | #define OMAP54XX_VC_CORE_VPACK_EN_MASK (1 << 22) |
| 1541 | |
| 1542 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1543 | #define OMAP54XX_VC_CORE_VPACK_ST_SHIFT 22 |
| 1544 | #define OMAP54XX_VC_CORE_VPACK_ST_WIDTH 0x1 |
| 1545 | #define OMAP54XX_VC_CORE_VPACK_ST_MASK (1 << 22) |
| 1546 | |
| 1547 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1548 | #define OMAP54XX_VC_MM_VPACK_EN_SHIFT 30 |
| 1549 | #define OMAP54XX_VC_MM_VPACK_EN_WIDTH 0x1 |
| 1550 | #define OMAP54XX_VC_MM_VPACK_EN_MASK (1 << 30) |
| 1551 | |
| 1552 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1553 | #define OMAP54XX_VC_MM_VPACK_ST_SHIFT 30 |
| 1554 | #define OMAP54XX_VC_MM_VPACK_ST_WIDTH 0x1 |
| 1555 | #define OMAP54XX_VC_MM_VPACK_ST_MASK (1 << 30) |
| 1556 | |
| 1557 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1558 | #define OMAP54XX_VC_MPU_VPACK_EN_SHIFT 6 |
| 1559 | #define OMAP54XX_VC_MPU_VPACK_EN_WIDTH 0x1 |
| 1560 | #define OMAP54XX_VC_MPU_VPACK_EN_MASK (1 << 6) |
| 1561 | |
| 1562 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1563 | #define OMAP54XX_VC_MPU_VPACK_ST_SHIFT 6 |
| 1564 | #define OMAP54XX_VC_MPU_VPACK_ST_WIDTH 0x1 |
| 1565 | #define OMAP54XX_VC_MPU_VPACK_ST_MASK (1 << 6) |
| 1566 | |
| 1567 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1568 | #define OMAP54XX_VC_RAERR_EN_SHIFT 12 |
| 1569 | #define OMAP54XX_VC_RAERR_EN_WIDTH 0x1 |
| 1570 | #define OMAP54XX_VC_RAERR_EN_MASK (1 << 12) |
| 1571 | |
| 1572 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1573 | #define OMAP54XX_VC_RAERR_ST_SHIFT 12 |
| 1574 | #define OMAP54XX_VC_RAERR_ST_WIDTH 0x1 |
| 1575 | #define OMAP54XX_VC_RAERR_ST_MASK (1 << 12) |
| 1576 | |
| 1577 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1578 | #define OMAP54XX_VC_SAERR_EN_SHIFT 11 |
| 1579 | #define OMAP54XX_VC_SAERR_EN_WIDTH 0x1 |
| 1580 | #define OMAP54XX_VC_SAERR_EN_MASK (1 << 11) |
| 1581 | |
| 1582 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1583 | #define OMAP54XX_VC_SAERR_ST_SHIFT 11 |
| 1584 | #define OMAP54XX_VC_SAERR_ST_WIDTH 0x1 |
| 1585 | #define OMAP54XX_VC_SAERR_ST_MASK (1 << 11) |
| 1586 | |
| 1587 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1588 | #define OMAP54XX_VC_TOERR_EN_SHIFT 13 |
| 1589 | #define OMAP54XX_VC_TOERR_EN_WIDTH 0x1 |
| 1590 | #define OMAP54XX_VC_TOERR_EN_MASK (1 << 13) |
| 1591 | |
| 1592 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1593 | #define OMAP54XX_VC_TOERR_ST_SHIFT 13 |
| 1594 | #define OMAP54XX_VC_TOERR_ST_WIDTH 0x1 |
| 1595 | #define OMAP54XX_VC_TOERR_ST_MASK (1 << 13) |
| 1596 | |
| 1597 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ |
| 1598 | #define OMAP54XX_VDDMAX_SHIFT 24 |
| 1599 | #define OMAP54XX_VDDMAX_WIDTH 0x8 |
| 1600 | #define OMAP54XX_VDDMAX_MASK (0xff << 24) |
| 1601 | |
| 1602 | /* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ |
| 1603 | #define OMAP54XX_VDDMIN_SHIFT 16 |
| 1604 | #define OMAP54XX_VDDMIN_WIDTH 0x8 |
| 1605 | #define OMAP54XX_VDDMIN_MASK (0xff << 16) |
| 1606 | |
| 1607 | /* Used by PRM_VOLTCTRL */ |
| 1608 | #define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT 12 |
| 1609 | #define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH 0x1 |
| 1610 | #define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK (1 << 12) |
| 1611 | |
| 1612 | /* Used by PRM_RSTST */ |
| 1613 | #define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT 8 |
| 1614 | #define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH 0x1 |
| 1615 | #define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) |
| 1616 | |
| 1617 | /* Used by PRM_VOLTCTRL */ |
| 1618 | #define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT 14 |
| 1619 | #define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH 0x1 |
| 1620 | #define OMAP54XX_VDD_MM_I2C_DISABLE_MASK (1 << 14) |
| 1621 | |
| 1622 | /* Used by PRM_VOLTCTRL */ |
| 1623 | #define OMAP54XX_VDD_MM_PRESENCE_SHIFT 9 |
| 1624 | #define OMAP54XX_VDD_MM_PRESENCE_WIDTH 0x1 |
| 1625 | #define OMAP54XX_VDD_MM_PRESENCE_MASK (1 << 9) |
| 1626 | |
| 1627 | /* Used by PRM_RSTST */ |
| 1628 | #define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT 7 |
| 1629 | #define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH 0x1 |
| 1630 | #define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK (1 << 7) |
| 1631 | |
| 1632 | /* Used by PRM_VOLTCTRL */ |
| 1633 | #define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT 13 |
| 1634 | #define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH 0x1 |
| 1635 | #define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK (1 << 13) |
| 1636 | |
| 1637 | /* Used by PRM_VOLTCTRL */ |
| 1638 | #define OMAP54XX_VDD_MPU_PRESENCE_SHIFT 8 |
| 1639 | #define OMAP54XX_VDD_MPU_PRESENCE_WIDTH 0x1 |
| 1640 | #define OMAP54XX_VDD_MPU_PRESENCE_MASK (1 << 8) |
| 1641 | |
| 1642 | /* Used by PRM_RSTST */ |
| 1643 | #define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT 6 |
| 1644 | #define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH 0x1 |
| 1645 | #define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) |
| 1646 | |
| 1647 | /* Used by PRM_VC_CORE_ERRST */ |
| 1648 | #define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT 4 |
| 1649 | #define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH 0x1 |
| 1650 | #define OMAP54XX_VFSM_RA_ERR_CORE_MASK (1 << 4) |
| 1651 | |
| 1652 | /* Used by PRM_VC_MM_ERRST */ |
| 1653 | #define OMAP54XX_VFSM_RA_ERR_MM_SHIFT 4 |
| 1654 | #define OMAP54XX_VFSM_RA_ERR_MM_WIDTH 0x1 |
| 1655 | #define OMAP54XX_VFSM_RA_ERR_MM_MASK (1 << 4) |
| 1656 | |
| 1657 | /* Used by PRM_VC_MPU_ERRST */ |
| 1658 | #define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT 4 |
| 1659 | #define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH 0x1 |
| 1660 | #define OMAP54XX_VFSM_RA_ERR_MPU_MASK (1 << 4) |
| 1661 | |
| 1662 | /* Used by PRM_VC_CORE_ERRST */ |
| 1663 | #define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT 3 |
| 1664 | #define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH 0x1 |
| 1665 | #define OMAP54XX_VFSM_SA_ERR_CORE_MASK (1 << 3) |
| 1666 | |
| 1667 | /* Used by PRM_VC_MM_ERRST */ |
| 1668 | #define OMAP54XX_VFSM_SA_ERR_MM_SHIFT 3 |
| 1669 | #define OMAP54XX_VFSM_SA_ERR_MM_WIDTH 0x1 |
| 1670 | #define OMAP54XX_VFSM_SA_ERR_MM_MASK (1 << 3) |
| 1671 | |
| 1672 | /* Used by PRM_VC_MPU_ERRST */ |
| 1673 | #define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT 3 |
| 1674 | #define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH 0x1 |
| 1675 | #define OMAP54XX_VFSM_SA_ERR_MPU_MASK (1 << 3) |
| 1676 | |
| 1677 | /* Used by PRM_VC_CORE_ERRST */ |
| 1678 | #define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 |
| 1679 | #define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH 0x1 |
| 1680 | #define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) |
| 1681 | |
| 1682 | /* Used by PRM_VC_MM_ERRST */ |
| 1683 | #define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT 5 |
| 1684 | #define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH 0x1 |
| 1685 | #define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK (1 << 5) |
| 1686 | |
| 1687 | /* Used by PRM_VC_MPU_ERRST */ |
| 1688 | #define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT 5 |
| 1689 | #define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH 0x1 |
| 1690 | #define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 5) |
| 1691 | |
| 1692 | /* Used by PRM_VC_SMPS_CORE_CONFIG */ |
| 1693 | #define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT 8 |
| 1694 | #define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH 0x8 |
| 1695 | #define OMAP54XX_VOLRA_VDD_CORE_L_MASK (0xff << 8) |
| 1696 | |
| 1697 | /* Used by PRM_VC_SMPS_MM_CONFIG */ |
| 1698 | #define OMAP54XX_VOLRA_VDD_MM_L_SHIFT 8 |
| 1699 | #define OMAP54XX_VOLRA_VDD_MM_L_WIDTH 0x8 |
| 1700 | #define OMAP54XX_VOLRA_VDD_MM_L_MASK (0xff << 8) |
| 1701 | |
| 1702 | /* Used by PRM_VC_SMPS_MPU_CONFIG */ |
| 1703 | #define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT 8 |
| 1704 | #define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH 0x8 |
| 1705 | #define OMAP54XX_VOLRA_VDD_MPU_L_MASK (0xff << 8) |
| 1706 | |
| 1707 | /* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */ |
| 1708 | #define OMAP54XX_VOLTSTATEST_SHIFT 0 |
| 1709 | #define OMAP54XX_VOLTSTATEST_WIDTH 0x2 |
| 1710 | #define OMAP54XX_VOLTSTATEST_MASK (0x3 << 0) |
| 1711 | |
| 1712 | /* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ |
| 1713 | #define OMAP54XX_VPENABLE_SHIFT 0 |
| 1714 | #define OMAP54XX_VPENABLE_WIDTH 0x1 |
| 1715 | #define OMAP54XX_VPENABLE_MASK (1 << 0) |
| 1716 | |
| 1717 | /* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */ |
| 1718 | #define OMAP54XX_VPINIDLE_SHIFT 0 |
| 1719 | #define OMAP54XX_VPINIDLE_WIDTH 0x1 |
| 1720 | #define OMAP54XX_VPINIDLE_MASK (1 << 0) |
| 1721 | |
| 1722 | /* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ |
| 1723 | #define OMAP54XX_VPVOLTAGE_SHIFT 0 |
| 1724 | #define OMAP54XX_VPVOLTAGE_WIDTH 0x8 |
| 1725 | #define OMAP54XX_VPVOLTAGE_MASK (0xff << 0) |
| 1726 | |
| 1727 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1728 | #define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT 20 |
| 1729 | #define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH 0x1 |
| 1730 | #define OMAP54XX_VP_CORE_EQVALUE_EN_MASK (1 << 20) |
| 1731 | |
| 1732 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1733 | #define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT 20 |
| 1734 | #define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH 0x1 |
| 1735 | #define OMAP54XX_VP_CORE_EQVALUE_ST_MASK (1 << 20) |
| 1736 | |
| 1737 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1738 | #define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT 18 |
| 1739 | #define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH 0x1 |
| 1740 | #define OMAP54XX_VP_CORE_MAXVDD_EN_MASK (1 << 18) |
| 1741 | |
| 1742 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1743 | #define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT 18 |
| 1744 | #define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH 0x1 |
| 1745 | #define OMAP54XX_VP_CORE_MAXVDD_ST_MASK (1 << 18) |
| 1746 | |
| 1747 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1748 | #define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT 17 |
| 1749 | #define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH 0x1 |
| 1750 | #define OMAP54XX_VP_CORE_MINVDD_EN_MASK (1 << 17) |
| 1751 | |
| 1752 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1753 | #define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT 17 |
| 1754 | #define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH 0x1 |
| 1755 | #define OMAP54XX_VP_CORE_MINVDD_ST_MASK (1 << 17) |
| 1756 | |
| 1757 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1758 | #define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT 19 |
| 1759 | #define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH 0x1 |
| 1760 | #define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) |
| 1761 | |
| 1762 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1763 | #define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT 19 |
| 1764 | #define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH 0x1 |
| 1765 | #define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) |
| 1766 | |
| 1767 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1768 | #define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 |
| 1769 | #define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH 0x1 |
| 1770 | #define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) |
| 1771 | |
| 1772 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1773 | #define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 |
| 1774 | #define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH 0x1 |
| 1775 | #define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) |
| 1776 | |
| 1777 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1778 | #define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT 21 |
| 1779 | #define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH 0x1 |
| 1780 | #define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK (1 << 21) |
| 1781 | |
| 1782 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1783 | #define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT 21 |
| 1784 | #define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH 0x1 |
| 1785 | #define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK (1 << 21) |
| 1786 | |
| 1787 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1788 | #define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT 28 |
| 1789 | #define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH 0x1 |
| 1790 | #define OMAP54XX_VP_MM_EQVALUE_EN_MASK (1 << 28) |
| 1791 | |
| 1792 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1793 | #define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT 28 |
| 1794 | #define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH 0x1 |
| 1795 | #define OMAP54XX_VP_MM_EQVALUE_ST_MASK (1 << 28) |
| 1796 | |
| 1797 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1798 | #define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT 26 |
| 1799 | #define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH 0x1 |
| 1800 | #define OMAP54XX_VP_MM_MAXVDD_EN_MASK (1 << 26) |
| 1801 | |
| 1802 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1803 | #define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT 26 |
| 1804 | #define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH 0x1 |
| 1805 | #define OMAP54XX_VP_MM_MAXVDD_ST_MASK (1 << 26) |
| 1806 | |
| 1807 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1808 | #define OMAP54XX_VP_MM_MINVDD_EN_SHIFT 25 |
| 1809 | #define OMAP54XX_VP_MM_MINVDD_EN_WIDTH 0x1 |
| 1810 | #define OMAP54XX_VP_MM_MINVDD_EN_MASK (1 << 25) |
| 1811 | |
| 1812 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1813 | #define OMAP54XX_VP_MM_MINVDD_ST_SHIFT 25 |
| 1814 | #define OMAP54XX_VP_MM_MINVDD_ST_WIDTH 0x1 |
| 1815 | #define OMAP54XX_VP_MM_MINVDD_ST_MASK (1 << 25) |
| 1816 | |
| 1817 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1818 | #define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT 27 |
| 1819 | #define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH 0x1 |
| 1820 | #define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK (1 << 27) |
| 1821 | |
| 1822 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1823 | #define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT 27 |
| 1824 | #define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH 0x1 |
| 1825 | #define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK (1 << 27) |
| 1826 | |
| 1827 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1828 | #define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT 24 |
| 1829 | #define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH 0x1 |
| 1830 | #define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK (1 << 24) |
| 1831 | |
| 1832 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1833 | #define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT 24 |
| 1834 | #define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH 0x1 |
| 1835 | #define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK (1 << 24) |
| 1836 | |
| 1837 | /* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ |
| 1838 | #define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT 29 |
| 1839 | #define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH 0x1 |
| 1840 | #define OMAP54XX_VP_MM_TRANXDONE_EN_MASK (1 << 29) |
| 1841 | |
| 1842 | /* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ |
| 1843 | #define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT 29 |
| 1844 | #define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH 0x1 |
| 1845 | #define OMAP54XX_VP_MM_TRANXDONE_ST_MASK (1 << 29) |
| 1846 | |
| 1847 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1848 | #define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT 4 |
| 1849 | #define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH 0x1 |
| 1850 | #define OMAP54XX_VP_MPU_EQVALUE_EN_MASK (1 << 4) |
| 1851 | |
| 1852 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1853 | #define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT 4 |
| 1854 | #define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH 0x1 |
| 1855 | #define OMAP54XX_VP_MPU_EQVALUE_ST_MASK (1 << 4) |
| 1856 | |
| 1857 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1858 | #define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT 2 |
| 1859 | #define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH 0x1 |
| 1860 | #define OMAP54XX_VP_MPU_MAXVDD_EN_MASK (1 << 2) |
| 1861 | |
| 1862 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1863 | #define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT 2 |
| 1864 | #define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH 0x1 |
| 1865 | #define OMAP54XX_VP_MPU_MAXVDD_ST_MASK (1 << 2) |
| 1866 | |
| 1867 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1868 | #define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT 1 |
| 1869 | #define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH 0x1 |
| 1870 | #define OMAP54XX_VP_MPU_MINVDD_EN_MASK (1 << 1) |
| 1871 | |
| 1872 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1873 | #define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT 1 |
| 1874 | #define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH 0x1 |
| 1875 | #define OMAP54XX_VP_MPU_MINVDD_ST_MASK (1 << 1) |
| 1876 | |
| 1877 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1878 | #define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT 3 |
| 1879 | #define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH 0x1 |
| 1880 | #define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) |
| 1881 | |
| 1882 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1883 | #define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT 3 |
| 1884 | #define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH 0x1 |
| 1885 | #define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) |
| 1886 | |
| 1887 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1888 | #define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 |
| 1889 | #define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH 0x1 |
| 1890 | #define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) |
| 1891 | |
| 1892 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1893 | #define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 |
| 1894 | #define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH 0x1 |
| 1895 | #define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) |
| 1896 | |
| 1897 | /* Used by PRM_IRQENABLE_MPU_2 */ |
| 1898 | #define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT 5 |
| 1899 | #define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH 0x1 |
| 1900 | #define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK (1 << 5) |
| 1901 | |
| 1902 | /* Used by PRM_IRQSTATUS_MPU_2 */ |
| 1903 | #define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT 5 |
| 1904 | #define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH 0x1 |
| 1905 | #define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK (1 << 5) |
| 1906 | |
| 1907 | /* Used by PRM_SRAM_COUNT */ |
| 1908 | #define OMAP54XX_VSETUPCNT_VALUE_SHIFT 8 |
| 1909 | #define OMAP54XX_VSETUPCNT_VALUE_WIDTH 0x8 |
| 1910 | #define OMAP54XX_VSETUPCNT_VALUE_MASK (0xff << 8) |
| 1911 | |
| 1912 | /* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ |
| 1913 | #define OMAP54XX_VSTEPMAX_SHIFT 0 |
| 1914 | #define OMAP54XX_VSTEPMAX_WIDTH 0x8 |
| 1915 | #define OMAP54XX_VSTEPMAX_MASK (0xff << 0) |
| 1916 | |
| 1917 | /* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ |
| 1918 | #define OMAP54XX_VSTEPMIN_SHIFT 0 |
| 1919 | #define OMAP54XX_VSTEPMIN_WIDTH 0x8 |
| 1920 | #define OMAP54XX_VSTEPMIN_MASK (0xff << 0) |
| 1921 | |
| 1922 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1923 | #define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT 2 |
| 1924 | #define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH 0x1 |
| 1925 | #define OMAP54XX_WKUPDEP_DISPC_DSP_MASK (1 << 2) |
| 1926 | |
| 1927 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1928 | #define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT 1 |
| 1929 | #define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH 0x1 |
| 1930 | #define OMAP54XX_WKUPDEP_DISPC_IPU_MASK (1 << 1) |
| 1931 | |
| 1932 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1933 | #define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT 0 |
| 1934 | #define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH 0x1 |
| 1935 | #define OMAP54XX_WKUPDEP_DISPC_MPU_MASK (1 << 0) |
| 1936 | |
| 1937 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1938 | #define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT 3 |
| 1939 | #define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH 0x1 |
| 1940 | #define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK (1 << 3) |
| 1941 | |
| 1942 | /* Used by PM_ABE_DMIC_WKDEP */ |
| 1943 | #define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT 6 |
| 1944 | #define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH 0x1 |
| 1945 | #define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK (1 << 6) |
| 1946 | |
| 1947 | /* Used by PM_ABE_DMIC_WKDEP */ |
| 1948 | #define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 |
| 1949 | #define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH 0x1 |
| 1950 | #define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) |
| 1951 | |
| 1952 | /* Used by PM_ABE_DMIC_WKDEP */ |
| 1953 | #define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT 2 |
| 1954 | #define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH 0x1 |
| 1955 | #define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK (1 << 2) |
| 1956 | |
| 1957 | /* Used by PM_ABE_DMIC_WKDEP */ |
| 1958 | #define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 |
| 1959 | #define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH 0x1 |
| 1960 | #define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) |
| 1961 | |
| 1962 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1963 | #define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT 6 |
| 1964 | #define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH 0x1 |
| 1965 | #define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK (1 << 6) |
| 1966 | |
| 1967 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1968 | #define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT 5 |
| 1969 | #define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH 0x1 |
| 1970 | #define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK (1 << 5) |
| 1971 | |
| 1972 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1973 | #define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT 4 |
| 1974 | #define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH 0x1 |
| 1975 | #define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK (1 << 4) |
| 1976 | |
| 1977 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1978 | #define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT 7 |
| 1979 | #define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH 0x1 |
| 1980 | #define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK (1 << 7) |
| 1981 | |
| 1982 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1983 | #define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT 10 |
| 1984 | #define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH 0x1 |
| 1985 | #define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK (1 << 10) |
| 1986 | |
| 1987 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1988 | #define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT 9 |
| 1989 | #define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH 0x1 |
| 1990 | #define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK (1 << 9) |
| 1991 | |
| 1992 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1993 | #define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT 8 |
| 1994 | #define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH 0x1 |
| 1995 | #define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK (1 << 8) |
| 1996 | |
| 1997 | /* Used by PM_DSS_DSS_WKDEP */ |
| 1998 | #define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT 11 |
| 1999 | #define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH 0x1 |
| 2000 | #define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK (1 << 11) |
| 2001 | |
| 2002 | /* Used by PM_DSS_DSS_WKDEP */ |
| 2003 | #define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT 17 |
| 2004 | #define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH 0x1 |
| 2005 | #define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK (1 << 17) |
| 2006 | |
| 2007 | /* Used by PM_DSS_DSS_WKDEP */ |
| 2008 | #define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT 16 |
| 2009 | #define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH 0x1 |
| 2010 | #define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK (1 << 16) |
| 2011 | |
| 2012 | /* Used by PM_DSS_DSS_WKDEP */ |
| 2013 | #define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT 15 |
| 2014 | #define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH 0x1 |
| 2015 | #define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK (1 << 15) |
| 2016 | |
| 2017 | /* Used by PM_DSS_DSS_WKDEP */ |
| 2018 | #define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT 18 |
| 2019 | #define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH 0x1 |
| 2020 | #define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK (1 << 18) |
| 2021 | |
| 2022 | /* Used by PM_WKUPAON_GPIO1_WKDEP */ |
| 2023 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT 1 |
| 2024 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH 0x1 |
| 2025 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK (1 << 1) |
| 2026 | |
| 2027 | /* Used by PM_WKUPAON_GPIO1_WKDEP */ |
| 2028 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 |
| 2029 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH 0x1 |
| 2030 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) |
| 2031 | |
| 2032 | /* Used by PM_WKUPAON_GPIO1_WKDEP */ |
| 2033 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT 6 |
| 2034 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH 0x1 |
| 2035 | #define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK (1 << 6) |
| 2036 | |
| 2037 | /* Used by PM_L4PER_GPIO2_WKDEP */ |
| 2038 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT 1 |
| 2039 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH 0x1 |
| 2040 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK (1 << 1) |
| 2041 | |
| 2042 | /* Used by PM_L4PER_GPIO2_WKDEP */ |
| 2043 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 |
| 2044 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH 0x1 |
| 2045 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) |
| 2046 | |
| 2047 | /* Used by PM_L4PER_GPIO2_WKDEP */ |
| 2048 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT 6 |
| 2049 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH 0x1 |
| 2050 | #define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK (1 << 6) |
| 2051 | |
| 2052 | /* Used by PM_L4PER_GPIO3_WKDEP */ |
| 2053 | #define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 |
| 2054 | #define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH 0x1 |
| 2055 | #define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) |
| 2056 | |
| 2057 | /* Used by PM_L4PER_GPIO3_WKDEP */ |
| 2058 | #define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT 6 |
| 2059 | #define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH 0x1 |
| 2060 | #define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK (1 << 6) |
| 2061 | |
| 2062 | /* Used by PM_L4PER_GPIO4_WKDEP */ |
| 2063 | #define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 |
| 2064 | #define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH 0x1 |
| 2065 | #define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) |
| 2066 | |
| 2067 | /* Used by PM_L4PER_GPIO4_WKDEP */ |
| 2068 | #define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT 6 |
| 2069 | #define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH 0x1 |
| 2070 | #define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK (1 << 6) |
| 2071 | |
| 2072 | /* Used by PM_L4PER_GPIO5_WKDEP */ |
| 2073 | #define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 |
| 2074 | #define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH 0x1 |
| 2075 | #define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) |
| 2076 | |
| 2077 | /* Used by PM_L4PER_GPIO5_WKDEP */ |
| 2078 | #define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT 6 |
| 2079 | #define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH 0x1 |
| 2080 | #define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK (1 << 6) |
| 2081 | |
| 2082 | /* Used by PM_L4PER_GPIO6_WKDEP */ |
| 2083 | #define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 |
| 2084 | #define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH 0x1 |
| 2085 | #define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) |
| 2086 | |
| 2087 | /* Used by PM_L4PER_GPIO6_WKDEP */ |
| 2088 | #define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT 6 |
| 2089 | #define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH 0x1 |
| 2090 | #define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK (1 << 6) |
| 2091 | |
| 2092 | /* Used by PM_L4PER_GPIO7_WKDEP */ |
| 2093 | #define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT 0 |
| 2094 | #define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH 0x1 |
| 2095 | #define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK (1 << 0) |
| 2096 | |
| 2097 | /* Used by PM_L4PER_GPIO8_WKDEP */ |
| 2098 | #define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT 0 |
| 2099 | #define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH 0x1 |
| 2100 | #define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK (1 << 0) |
| 2101 | |
| 2102 | /* Used by PM_DSS_DSS_WKDEP */ |
| 2103 | #define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 |
| 2104 | #define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH 0x1 |
| 2105 | #define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) |
| 2106 | |
| 2107 | /* Used by PM_DSS_DSS_WKDEP */ |
| 2108 | #define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT 14 |
| 2109 | #define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH 0x1 |
| 2110 | #define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK (1 << 14) |
| 2111 | |
| 2112 | /* Used by PM_DSS_DSS_WKDEP */ |
| 2113 | #define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT 13 |
| 2114 | #define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH 0x1 |
| 2115 | #define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK (1 << 13) |
| 2116 | |
| 2117 | /* Used by PM_DSS_DSS_WKDEP */ |
| 2118 | #define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 |
| 2119 | #define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH 0x1 |
| 2120 | #define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) |
| 2121 | |
| 2122 | /* Used by PM_L3INIT_HSI_WKDEP */ |
| 2123 | #define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT 6 |
| 2124 | #define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH 0x1 |
| 2125 | #define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK (1 << 6) |
| 2126 | |
| 2127 | /* Used by PM_L3INIT_HSI_WKDEP */ |
| 2128 | #define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT 1 |
| 2129 | #define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH 0x1 |
| 2130 | #define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK (1 << 1) |
| 2131 | |
| 2132 | /* Used by PM_L3INIT_HSI_WKDEP */ |
| 2133 | #define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT 0 |
| 2134 | #define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH 0x1 |
| 2135 | #define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) |
| 2136 | |
| 2137 | /* Used by PM_L4PER_I2C1_WKDEP */ |
| 2138 | #define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 |
| 2139 | #define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH 0x1 |
| 2140 | #define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) |
| 2141 | |
| 2142 | /* Used by PM_L4PER_I2C1_WKDEP */ |
| 2143 | #define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT 1 |
| 2144 | #define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH 0x1 |
| 2145 | #define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK (1 << 1) |
| 2146 | |
| 2147 | /* Used by PM_L4PER_I2C1_WKDEP */ |
| 2148 | #define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 |
| 2149 | #define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH 0x1 |
| 2150 | #define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) |
| 2151 | |
| 2152 | /* Used by PM_L4PER_I2C2_WKDEP */ |
| 2153 | #define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 |
| 2154 | #define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH 0x1 |
| 2155 | #define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) |
| 2156 | |
| 2157 | /* Used by PM_L4PER_I2C2_WKDEP */ |
| 2158 | #define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT 1 |
| 2159 | #define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH 0x1 |
| 2160 | #define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK (1 << 1) |
| 2161 | |
| 2162 | /* Used by PM_L4PER_I2C2_WKDEP */ |
| 2163 | #define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 |
| 2164 | #define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH 0x1 |
| 2165 | #define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) |
| 2166 | |
| 2167 | /* Used by PM_L4PER_I2C3_WKDEP */ |
| 2168 | #define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 |
| 2169 | #define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH 0x1 |
| 2170 | #define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) |
| 2171 | |
| 2172 | /* Used by PM_L4PER_I2C3_WKDEP */ |
| 2173 | #define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT 1 |
| 2174 | #define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH 0x1 |
| 2175 | #define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK (1 << 1) |
| 2176 | |
| 2177 | /* Used by PM_L4PER_I2C3_WKDEP */ |
| 2178 | #define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 |
| 2179 | #define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH 0x1 |
| 2180 | #define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) |
| 2181 | |
| 2182 | /* Used by PM_L4PER_I2C4_WKDEP */ |
| 2183 | #define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 |
| 2184 | #define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH 0x1 |
| 2185 | #define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) |
| 2186 | |
| 2187 | /* Used by PM_L4PER_I2C4_WKDEP */ |
| 2188 | #define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT 1 |
| 2189 | #define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH 0x1 |
| 2190 | #define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK (1 << 1) |
| 2191 | |
| 2192 | /* Used by PM_L4PER_I2C4_WKDEP */ |
| 2193 | #define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 |
| 2194 | #define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH 0x1 |
| 2195 | #define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) |
| 2196 | |
| 2197 | /* Used by PM_L4PER_I2C5_WKDEP */ |
| 2198 | #define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 |
| 2199 | #define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH 0x1 |
| 2200 | #define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) |
| 2201 | |
| 2202 | /* Used by PM_WKUPAON_KBD_WKDEP */ |
| 2203 | #define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT 0 |
| 2204 | #define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH 0x1 |
| 2205 | #define OMAP54XX_WKUPDEP_KBD_MPU_MASK (1 << 0) |
| 2206 | |
| 2207 | /* Used by PM_ABE_MCASP_WKDEP */ |
| 2208 | #define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT 6 |
| 2209 | #define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH 0x1 |
| 2210 | #define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK (1 << 6) |
| 2211 | |
| 2212 | /* Used by PM_ABE_MCASP_WKDEP */ |
| 2213 | #define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT 7 |
| 2214 | #define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH 0x1 |
| 2215 | #define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK (1 << 7) |
| 2216 | |
| 2217 | /* Used by PM_ABE_MCASP_WKDEP */ |
| 2218 | #define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT 2 |
| 2219 | #define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH 0x1 |
| 2220 | #define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK (1 << 2) |
| 2221 | |
| 2222 | /* Used by PM_ABE_MCASP_WKDEP */ |
| 2223 | #define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT 0 |
| 2224 | #define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH 0x1 |
| 2225 | #define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK (1 << 0) |
| 2226 | |
| 2227 | /* Used by PM_ABE_MCBSP1_WKDEP */ |
| 2228 | #define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT 2 |
| 2229 | #define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH 0x1 |
| 2230 | #define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK (1 << 2) |
| 2231 | |
| 2232 | /* Used by PM_ABE_MCBSP1_WKDEP */ |
| 2233 | #define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT 0 |
| 2234 | #define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH 0x1 |
| 2235 | #define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) |
| 2236 | |
| 2237 | /* Used by PM_ABE_MCBSP1_WKDEP */ |
| 2238 | #define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT 3 |
| 2239 | #define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH 0x1 |
| 2240 | #define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) |
| 2241 | |
| 2242 | /* Used by PM_ABE_MCBSP2_WKDEP */ |
| 2243 | #define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT 2 |
| 2244 | #define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH 0x1 |
| 2245 | #define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK (1 << 2) |
| 2246 | |
| 2247 | /* Used by PM_ABE_MCBSP2_WKDEP */ |
| 2248 | #define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT 0 |
| 2249 | #define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH 0x1 |
| 2250 | #define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) |
| 2251 | |
| 2252 | /* Used by PM_ABE_MCBSP2_WKDEP */ |
| 2253 | #define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT 3 |
| 2254 | #define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH 0x1 |
| 2255 | #define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) |
| 2256 | |
| 2257 | /* Used by PM_ABE_MCBSP3_WKDEP */ |
| 2258 | #define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT 2 |
| 2259 | #define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH 0x1 |
| 2260 | #define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK (1 << 2) |
| 2261 | |
| 2262 | /* Used by PM_ABE_MCBSP3_WKDEP */ |
| 2263 | #define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT 0 |
| 2264 | #define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH 0x1 |
| 2265 | #define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) |
| 2266 | |
| 2267 | /* Used by PM_ABE_MCBSP3_WKDEP */ |
| 2268 | #define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT 3 |
| 2269 | #define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH 0x1 |
| 2270 | #define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) |
| 2271 | |
| 2272 | /* Used by PM_ABE_MCPDM_WKDEP */ |
| 2273 | #define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT 6 |
| 2274 | #define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH 0x1 |
| 2275 | #define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK (1 << 6) |
| 2276 | |
| 2277 | /* Used by PM_ABE_MCPDM_WKDEP */ |
| 2278 | #define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT 7 |
| 2279 | #define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH 0x1 |
| 2280 | #define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK (1 << 7) |
| 2281 | |
| 2282 | /* Used by PM_ABE_MCPDM_WKDEP */ |
| 2283 | #define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT 2 |
| 2284 | #define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH 0x1 |
| 2285 | #define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK (1 << 2) |
| 2286 | |
| 2287 | /* Used by PM_ABE_MCPDM_WKDEP */ |
| 2288 | #define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT 0 |
| 2289 | #define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH 0x1 |
| 2290 | #define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK (1 << 0) |
| 2291 | |
| 2292 | /* Used by PM_L4PER_MCSPI1_WKDEP */ |
| 2293 | #define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT 2 |
| 2294 | #define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH 0x1 |
| 2295 | #define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK (1 << 2) |
| 2296 | |
| 2297 | /* Used by PM_L4PER_MCSPI1_WKDEP */ |
| 2298 | #define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT 1 |
| 2299 | #define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH 0x1 |
| 2300 | #define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK (1 << 1) |
| 2301 | |
| 2302 | /* Used by PM_L4PER_MCSPI1_WKDEP */ |
| 2303 | #define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT 0 |
| 2304 | #define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH 0x1 |
| 2305 | #define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) |
| 2306 | |
| 2307 | /* Used by PM_L4PER_MCSPI1_WKDEP */ |
| 2308 | #define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT 3 |
| 2309 | #define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH 0x1 |
| 2310 | #define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) |
| 2311 | |
| 2312 | /* Used by PM_L4PER_MCSPI2_WKDEP */ |
| 2313 | #define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT 1 |
| 2314 | #define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH 0x1 |
| 2315 | #define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK (1 << 1) |
| 2316 | |
| 2317 | /* Used by PM_L4PER_MCSPI2_WKDEP */ |
| 2318 | #define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT 0 |
| 2319 | #define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH 0x1 |
| 2320 | #define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) |
| 2321 | |
| 2322 | /* Used by PM_L4PER_MCSPI2_WKDEP */ |
| 2323 | #define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT 3 |
| 2324 | #define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH 0x1 |
| 2325 | #define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) |
| 2326 | |
| 2327 | /* Used by PM_L4PER_MCSPI3_WKDEP */ |
| 2328 | #define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT 0 |
| 2329 | #define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH 0x1 |
| 2330 | #define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) |
| 2331 | |
| 2332 | /* Used by PM_L4PER_MCSPI3_WKDEP */ |
| 2333 | #define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT 3 |
| 2334 | #define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH 0x1 |
| 2335 | #define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) |
| 2336 | |
| 2337 | /* Used by PM_L4PER_MCSPI4_WKDEP */ |
| 2338 | #define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT 0 |
| 2339 | #define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH 0x1 |
| 2340 | #define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) |
| 2341 | |
| 2342 | /* Used by PM_L4PER_MCSPI4_WKDEP */ |
| 2343 | #define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT 3 |
| 2344 | #define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH 0x1 |
| 2345 | #define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) |
| 2346 | |
| 2347 | /* Used by PM_L3INIT_MMC1_WKDEP */ |
| 2348 | #define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT 2 |
| 2349 | #define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH 0x1 |
| 2350 | #define OMAP54XX_WKUPDEP_MMC1_DSP_MASK (1 << 2) |
| 2351 | |
| 2352 | /* Used by PM_L3INIT_MMC1_WKDEP */ |
| 2353 | #define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT 1 |
| 2354 | #define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH 0x1 |
| 2355 | #define OMAP54XX_WKUPDEP_MMC1_IPU_MASK (1 << 1) |
| 2356 | |
| 2357 | /* Used by PM_L3INIT_MMC1_WKDEP */ |
| 2358 | #define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT 0 |
| 2359 | #define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH 0x1 |
| 2360 | #define OMAP54XX_WKUPDEP_MMC1_MPU_MASK (1 << 0) |
| 2361 | |
| 2362 | /* Used by PM_L3INIT_MMC1_WKDEP */ |
| 2363 | #define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT 3 |
| 2364 | #define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH 0x1 |
| 2365 | #define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK (1 << 3) |
| 2366 | |
| 2367 | /* Used by PM_L3INIT_MMC2_WKDEP */ |
| 2368 | #define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT 2 |
| 2369 | #define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH 0x1 |
| 2370 | #define OMAP54XX_WKUPDEP_MMC2_DSP_MASK (1 << 2) |
| 2371 | |
| 2372 | /* Used by PM_L3INIT_MMC2_WKDEP */ |
| 2373 | #define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT 1 |
| 2374 | #define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH 0x1 |
| 2375 | #define OMAP54XX_WKUPDEP_MMC2_IPU_MASK (1 << 1) |
| 2376 | |
| 2377 | /* Used by PM_L3INIT_MMC2_WKDEP */ |
| 2378 | #define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT 0 |
| 2379 | #define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH 0x1 |
| 2380 | #define OMAP54XX_WKUPDEP_MMC2_MPU_MASK (1 << 0) |
| 2381 | |
| 2382 | /* Used by PM_L3INIT_MMC2_WKDEP */ |
| 2383 | #define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT 3 |
| 2384 | #define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH 0x1 |
| 2385 | #define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK (1 << 3) |
| 2386 | |
| 2387 | /* Used by PM_L4PER_MMC3_WKDEP */ |
| 2388 | #define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT 1 |
| 2389 | #define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH 0x1 |
| 2390 | #define OMAP54XX_WKUPDEP_MMC3_IPU_MASK (1 << 1) |
| 2391 | |
| 2392 | /* Used by PM_L4PER_MMC3_WKDEP */ |
| 2393 | #define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT 0 |
| 2394 | #define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH 0x1 |
| 2395 | #define OMAP54XX_WKUPDEP_MMC3_MPU_MASK (1 << 0) |
| 2396 | |
| 2397 | /* Used by PM_L4PER_MMC3_WKDEP */ |
| 2398 | #define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT 3 |
| 2399 | #define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH 0x1 |
| 2400 | #define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK (1 << 3) |
| 2401 | |
| 2402 | /* Used by PM_L4PER_MMC4_WKDEP */ |
| 2403 | #define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT 0 |
| 2404 | #define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH 0x1 |
| 2405 | #define OMAP54XX_WKUPDEP_MMC4_MPU_MASK (1 << 0) |
| 2406 | |
| 2407 | /* Used by PM_L4PER_MMC4_WKDEP */ |
| 2408 | #define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT 3 |
| 2409 | #define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH 0x1 |
| 2410 | #define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK (1 << 3) |
| 2411 | |
| 2412 | /* Used by PM_L4PER_MMC5_WKDEP */ |
| 2413 | #define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT 0 |
| 2414 | #define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH 0x1 |
| 2415 | #define OMAP54XX_WKUPDEP_MMC5_MPU_MASK (1 << 0) |
| 2416 | |
| 2417 | /* Used by PM_L4PER_MMC5_WKDEP */ |
| 2418 | #define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT 3 |
| 2419 | #define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH 0x1 |
| 2420 | #define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK (1 << 3) |
| 2421 | |
| 2422 | /* Used by PM_L3INIT_SATA_WKDEP */ |
| 2423 | #define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT 0 |
| 2424 | #define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH 0x1 |
| 2425 | #define OMAP54XX_WKUPDEP_SATA_MPU_MASK (1 << 0) |
| 2426 | |
| 2427 | /* Used by PM_ABE_SLIMBUS1_WKDEP */ |
| 2428 | #define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT 6 |
| 2429 | #define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH 0x1 |
| 2430 | #define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK (1 << 6) |
| 2431 | |
| 2432 | /* Used by PM_ABE_SLIMBUS1_WKDEP */ |
| 2433 | #define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 |
| 2434 | #define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH 0x1 |
| 2435 | #define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) |
| 2436 | |
| 2437 | /* Used by PM_ABE_SLIMBUS1_WKDEP */ |
| 2438 | #define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT 2 |
| 2439 | #define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH 0x1 |
| 2440 | #define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK (1 << 2) |
| 2441 | |
| 2442 | /* Used by PM_ABE_SLIMBUS1_WKDEP */ |
| 2443 | #define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 |
| 2444 | #define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH 0x1 |
| 2445 | #define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) |
| 2446 | |
| 2447 | /* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ |
| 2448 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT 1 |
| 2449 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH 0x1 |
| 2450 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK (1 << 1) |
| 2451 | |
| 2452 | /* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ |
| 2453 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT 0 |
| 2454 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH 0x1 |
| 2455 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK (1 << 0) |
| 2456 | |
| 2457 | /* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */ |
| 2458 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT 0 |
| 2459 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH 0x1 |
| 2460 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK (1 << 0) |
| 2461 | |
| 2462 | /* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */ |
| 2463 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT 0 |
| 2464 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH 0x1 |
| 2465 | #define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK (1 << 0) |
| 2466 | |
| 2467 | /* Used by PM_L4PER_TIMER10_WKDEP */ |
| 2468 | #define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT 0 |
| 2469 | #define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH 0x1 |
| 2470 | #define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK (1 << 0) |
| 2471 | |
| 2472 | /* Used by PM_L4PER_TIMER11_WKDEP */ |
| 2473 | #define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT 1 |
| 2474 | #define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH 0x1 |
| 2475 | #define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK (1 << 1) |
| 2476 | |
| 2477 | /* Used by PM_L4PER_TIMER11_WKDEP */ |
| 2478 | #define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT 0 |
| 2479 | #define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH 0x1 |
| 2480 | #define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK (1 << 0) |
| 2481 | |
| 2482 | /* Used by PM_WKUPAON_TIMER12_WKDEP */ |
| 2483 | #define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT 0 |
| 2484 | #define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH 0x1 |
| 2485 | #define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK (1 << 0) |
| 2486 | |
| 2487 | /* Used by PM_WKUPAON_TIMER1_WKDEP */ |
| 2488 | #define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT 0 |
| 2489 | #define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH 0x1 |
| 2490 | #define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK (1 << 0) |
| 2491 | |
| 2492 | /* Used by PM_L4PER_TIMER2_WKDEP */ |
| 2493 | #define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT 0 |
| 2494 | #define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH 0x1 |
| 2495 | #define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK (1 << 0) |
| 2496 | |
| 2497 | /* Used by PM_L4PER_TIMER3_WKDEP */ |
| 2498 | #define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT 1 |
| 2499 | #define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH 0x1 |
| 2500 | #define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK (1 << 1) |
| 2501 | |
| 2502 | /* Used by PM_L4PER_TIMER3_WKDEP */ |
| 2503 | #define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT 0 |
| 2504 | #define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH 0x1 |
| 2505 | #define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK (1 << 0) |
| 2506 | |
| 2507 | /* Used by PM_L4PER_TIMER4_WKDEP */ |
| 2508 | #define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT 1 |
| 2509 | #define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH 0x1 |
| 2510 | #define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK (1 << 1) |
| 2511 | |
| 2512 | /* Used by PM_L4PER_TIMER4_WKDEP */ |
| 2513 | #define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT 0 |
| 2514 | #define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH 0x1 |
| 2515 | #define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK (1 << 0) |
| 2516 | |
| 2517 | /* Used by PM_ABE_TIMER5_WKDEP */ |
| 2518 | #define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT 2 |
| 2519 | #define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH 0x1 |
| 2520 | #define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK (1 << 2) |
| 2521 | |
| 2522 | /* Used by PM_ABE_TIMER5_WKDEP */ |
| 2523 | #define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT 0 |
| 2524 | #define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH 0x1 |
| 2525 | #define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK (1 << 0) |
| 2526 | |
| 2527 | /* Used by PM_ABE_TIMER6_WKDEP */ |
| 2528 | #define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT 2 |
| 2529 | #define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH 0x1 |
| 2530 | #define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK (1 << 2) |
| 2531 | |
| 2532 | /* Used by PM_ABE_TIMER6_WKDEP */ |
| 2533 | #define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT 0 |
| 2534 | #define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH 0x1 |
| 2535 | #define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK (1 << 0) |
| 2536 | |
| 2537 | /* Used by PM_ABE_TIMER7_WKDEP */ |
| 2538 | #define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT 2 |
| 2539 | #define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH 0x1 |
| 2540 | #define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK (1 << 2) |
| 2541 | |
| 2542 | /* Used by PM_ABE_TIMER7_WKDEP */ |
| 2543 | #define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT 0 |
| 2544 | #define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH 0x1 |
| 2545 | #define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK (1 << 0) |
| 2546 | |
| 2547 | /* Used by PM_ABE_TIMER8_WKDEP */ |
| 2548 | #define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT 2 |
| 2549 | #define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH 0x1 |
| 2550 | #define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK (1 << 2) |
| 2551 | |
| 2552 | /* Used by PM_ABE_TIMER8_WKDEP */ |
| 2553 | #define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT 0 |
| 2554 | #define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH 0x1 |
| 2555 | #define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK (1 << 0) |
| 2556 | |
| 2557 | /* Used by PM_L4PER_TIMER9_WKDEP */ |
| 2558 | #define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT 1 |
| 2559 | #define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH 0x1 |
| 2560 | #define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK (1 << 1) |
| 2561 | |
| 2562 | /* Used by PM_L4PER_TIMER9_WKDEP */ |
| 2563 | #define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT 0 |
| 2564 | #define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH 0x1 |
| 2565 | #define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK (1 << 0) |
| 2566 | |
| 2567 | /* Used by PM_L4PER_UART1_WKDEP */ |
| 2568 | #define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT 0 |
| 2569 | #define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH 0x1 |
| 2570 | #define OMAP54XX_WKUPDEP_UART1_MPU_MASK (1 << 0) |
| 2571 | |
| 2572 | /* Used by PM_L4PER_UART1_WKDEP */ |
| 2573 | #define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT 3 |
| 2574 | #define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH 0x1 |
| 2575 | #define OMAP54XX_WKUPDEP_UART1_SDMA_MASK (1 << 3) |
| 2576 | |
| 2577 | /* Used by PM_L4PER_UART2_WKDEP */ |
| 2578 | #define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT 0 |
| 2579 | #define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH 0x1 |
| 2580 | #define OMAP54XX_WKUPDEP_UART2_MPU_MASK (1 << 0) |
| 2581 | |
| 2582 | /* Used by PM_L4PER_UART2_WKDEP */ |
| 2583 | #define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT 3 |
| 2584 | #define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH 0x1 |
| 2585 | #define OMAP54XX_WKUPDEP_UART2_SDMA_MASK (1 << 3) |
| 2586 | |
| 2587 | /* Used by PM_L4PER_UART3_WKDEP */ |
| 2588 | #define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT 2 |
| 2589 | #define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH 0x1 |
| 2590 | #define OMAP54XX_WKUPDEP_UART3_DSP_MASK (1 << 2) |
| 2591 | |
| 2592 | /* Used by PM_L4PER_UART3_WKDEP */ |
| 2593 | #define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT 1 |
| 2594 | #define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH 0x1 |
| 2595 | #define OMAP54XX_WKUPDEP_UART3_IPU_MASK (1 << 1) |
| 2596 | |
| 2597 | /* Used by PM_L4PER_UART3_WKDEP */ |
| 2598 | #define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT 0 |
| 2599 | #define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH 0x1 |
| 2600 | #define OMAP54XX_WKUPDEP_UART3_MPU_MASK (1 << 0) |
| 2601 | |
| 2602 | /* Used by PM_L4PER_UART3_WKDEP */ |
| 2603 | #define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT 3 |
| 2604 | #define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH 0x1 |
| 2605 | #define OMAP54XX_WKUPDEP_UART3_SDMA_MASK (1 << 3) |
| 2606 | |
| 2607 | /* Used by PM_L4PER_UART4_WKDEP */ |
| 2608 | #define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT 0 |
| 2609 | #define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH 0x1 |
| 2610 | #define OMAP54XX_WKUPDEP_UART4_MPU_MASK (1 << 0) |
| 2611 | |
| 2612 | /* Used by PM_L4PER_UART4_WKDEP */ |
| 2613 | #define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT 3 |
| 2614 | #define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH 0x1 |
| 2615 | #define OMAP54XX_WKUPDEP_UART4_SDMA_MASK (1 << 3) |
| 2616 | |
| 2617 | /* Used by PM_L4PER_UART5_WKDEP */ |
| 2618 | #define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT 0 |
| 2619 | #define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH 0x1 |
| 2620 | #define OMAP54XX_WKUPDEP_UART5_MPU_MASK (1 << 0) |
| 2621 | |
| 2622 | /* Used by PM_L4PER_UART5_WKDEP */ |
| 2623 | #define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT 3 |
| 2624 | #define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH 0x1 |
| 2625 | #define OMAP54XX_WKUPDEP_UART5_SDMA_MASK (1 << 3) |
| 2626 | |
| 2627 | /* Used by PM_L4PER_UART6_WKDEP */ |
| 2628 | #define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT 0 |
| 2629 | #define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH 0x1 |
| 2630 | #define OMAP54XX_WKUPDEP_UART6_MPU_MASK (1 << 0) |
| 2631 | |
| 2632 | /* Used by PM_L4PER_UART6_WKDEP */ |
| 2633 | #define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT 3 |
| 2634 | #define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH 0x1 |
| 2635 | #define OMAP54XX_WKUPDEP_UART6_SDMA_MASK (1 << 3) |
| 2636 | |
| 2637 | /* Used by PM_L3INIT_UNIPRO2_WKDEP */ |
| 2638 | #define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT 0 |
| 2639 | #define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH 0x1 |
| 2640 | #define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK (1 << 0) |
| 2641 | |
| 2642 | /* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ |
| 2643 | #define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT 1 |
| 2644 | #define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH 0x1 |
| 2645 | #define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK (1 << 1) |
| 2646 | |
| 2647 | /* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ |
| 2648 | #define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT 0 |
| 2649 | #define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH 0x1 |
| 2650 | #define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK (1 << 0) |
| 2651 | |
| 2652 | /* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ |
| 2653 | #define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT 1 |
| 2654 | #define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH 0x1 |
| 2655 | #define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK (1 << 1) |
| 2656 | |
| 2657 | /* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ |
| 2658 | #define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT 0 |
| 2659 | #define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH 0x1 |
| 2660 | #define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK (1 << 0) |
| 2661 | |
| 2662 | /* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ |
| 2663 | #define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT 1 |
| 2664 | #define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH 0x1 |
| 2665 | #define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK (1 << 1) |
| 2666 | |
| 2667 | /* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ |
| 2668 | #define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT 0 |
| 2669 | #define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH 0x1 |
| 2670 | #define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK (1 << 0) |
| 2671 | |
| 2672 | /* Used by PM_WKUPAON_WD_TIMER2_WKDEP */ |
| 2673 | #define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT 0 |
| 2674 | #define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH 0x1 |
| 2675 | #define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK (1 << 0) |
| 2676 | |
| 2677 | /* Used by PM_ABE_WD_TIMER3_WKDEP */ |
| 2678 | #define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT 0 |
| 2679 | #define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH 0x1 |
| 2680 | #define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK (1 << 0) |
| 2681 | |
| 2682 | /* Used by PRM_IO_PMCTRL */ |
| 2683 | #define OMAP54XX_WUCLK_CTRL_SHIFT 8 |
| 2684 | #define OMAP54XX_WUCLK_CTRL_WIDTH 0x1 |
| 2685 | #define OMAP54XX_WUCLK_CTRL_MASK (1 << 8) |
| 2686 | |
| 2687 | /* Used by PRM_IO_PMCTRL */ |
| 2688 | #define OMAP54XX_WUCLK_STATUS_SHIFT 9 |
| 2689 | #define OMAP54XX_WUCLK_STATUS_WIDTH 0x1 |
| 2690 | #define OMAP54XX_WUCLK_STATUS_MASK (1 << 9) |
| 2691 | |
| 2692 | /* Used by REVISION_PRM */ |
| 2693 | #define OMAP54XX_X_MAJOR_SHIFT 8 |
| 2694 | #define OMAP54XX_X_MAJOR_WIDTH 0x3 |
| 2695 | #define OMAP54XX_X_MAJOR_MASK (0x7 << 8) |
| 2696 | |
| 2697 | /* Used by REVISION_PRM */ |
| 2698 | #define OMAP54XX_Y_MINOR_SHIFT 0 |
| 2699 | #define OMAP54XX_Y_MINOR_WIDTH 0x6 |
| 2700 | #define OMAP54XX_Y_MINOR_MASK (0x3f << 0) |
| 2701 | #endif |