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review.evervolv.com / android_kernel_oneplus_msm8996 / c4b51a431561f0bacc1740aa27f080bf95c4d6c7 / . / drivers / scsi / mpt2sas / mpi / mpi2.h
blob: 31b5b15a47265060aa8ad2f03810c0559361d36b [file] [log] [blame]
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1/*
sreekanth.reddy@lsi.com8c79d622012-07-17 15:56:10 +0530[diff] [blame]2 * Copyright (c) 2000-2012 LSI Corporation.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
Sreekanth Reddy10ec24e2013-02-01 21:54:13 +0530[diff] [blame]11 * mpi2.h Version: 02.00.27
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]12 *
13 * Version History
14 * ---------------
15 *
16 * Date Version Description
17 * -------- -------- ------------------------------------------------------
18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
22 * Moved ReplyPostHostIndex register to offset 0x6C of the
23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
25 * Added union of request descriptors.
26 * Added union of reply descriptors.
27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
28 * Added define for MPI2_VERSION_02_00.
29 * Fixed the size of the FunctionDependent5 field in the
30 * MPI2_DEFAULT_REPLY structure.
31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
32 * Removed the MPI-defined Fault Codes and extended the
33 * product specific codes up to 0xEFFF.
34 * Added a sixth key value for the WriteSequence register
35 * and changed the flush value to 0x0.
36 * Added message function codes for Diagnostic Buffer Post
37 * and Diagnsotic Release.
38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
43 * Added #defines for marking a reply descriptor as unused.
44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
46 * Moved LUN field defines from mpi2_init.h.
47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
49 * In all request and reply descriptors, replaced VF_ID
50 * field with MSIxIndex field.
51 * Removed DevHandle field from
52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
53 * bytes reserved.
54 * Added RAID Accelerator functionality.
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]56 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
57 * Added MSI-x index mask and shift for Reply Post Host
58 * Index register.
59 * Added function code for Host Based Discovery Action.
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]60 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
61 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
62 * Added defines for product-specific range of message
63 * function codes, 0xF0 to 0xFF.
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]64 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
65 * Added alternative defines for the SGE Direction bit.
Kashyap, Desai9af05d92011-01-04 11:35:41 +0530[diff] [blame]66 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]67 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
68 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]69 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
71 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
nagalakshmi.nandigama@lsi.comc1bc0702011-12-01 07:43:37 +0530[diff] [blame]72 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
nagalakshmi.nandigama@lsi.coma6affbd2011-12-01 07:52:49 +0530[diff] [blame]73 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
nagalakshmi.nandigama@lsi.com609dc442012-03-20 12:03:16 +0530[diff] [blame]74 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
sreekanth.reddy@lsi.com8c79d622012-07-17 15:56:10 +0530[diff] [blame]75 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
76 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
77 * Added Hard Reset delay timings.
Sreekanth Reddy10ec24e2013-02-01 21:54:13 +0530[diff] [blame]78 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]80 * --------------------------------------------------------------------------
81 */
82
83#ifndef MPI2_H
84#define MPI2_H
85
86
87/*****************************************************************************
88*
89* MPI Version Definitions
90*
91*****************************************************************************/
92
93#define MPI2_VERSION_MAJOR (0x02)
94#define MPI2_VERSION_MINOR (0x00)
95#define MPI2_VERSION_MAJOR_MASK (0xFF00)
96#define MPI2_VERSION_MAJOR_SHIFT (8)
97#define MPI2_VERSION_MINOR_MASK (0x00FF)
98#define MPI2_VERSION_MINOR_SHIFT (0)
99#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
100 MPI2_VERSION_MINOR)
101
102#define MPI2_VERSION_02_00 (0x0200)
103
104/* versioning for this MPI header set */
Sreekanth Reddy10ec24e2013-02-01 21:54:13 +0530[diff] [blame]105#define MPI2_HEADER_VERSION_UNIT (0x1B)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]106#define MPI2_HEADER_VERSION_DEV (0x00)
107#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
108#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
109#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
110#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
111#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV)
112
113
114/*****************************************************************************
115*
116* IOC State Definitions
117*
118*****************************************************************************/
119
120#define MPI2_IOC_STATE_RESET (0x00000000)
121#define MPI2_IOC_STATE_READY (0x10000000)
122#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
123#define MPI2_IOC_STATE_FAULT (0x40000000)
124
125#define MPI2_IOC_STATE_MASK (0xF0000000)
126#define MPI2_IOC_STATE_SHIFT (28)
127
128/* Fault state range for prodcut specific codes */
129#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
130#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
131
132
133/*****************************************************************************
134*
135* System Interface Register Definitions
136*
137*****************************************************************************/
138
139typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS
140{
141 U32 Doorbell; /* 0x00 */
142 U32 WriteSequence; /* 0x04 */
143 U32 HostDiagnostic; /* 0x08 */
144 U32 Reserved1; /* 0x0C */
145 U32 DiagRWData; /* 0x10 */
146 U32 DiagRWAddressLow; /* 0x14 */
147 U32 DiagRWAddressHigh; /* 0x18 */
148 U32 Reserved2[5]; /* 0x1C */
149 U32 HostInterruptStatus; /* 0x30 */
150 U32 HostInterruptMask; /* 0x34 */
151 U32 DCRData; /* 0x38 */
152 U32 DCRAddress; /* 0x3C */
153 U32 Reserved3[2]; /* 0x40 */
154 U32 ReplyFreeHostIndex; /* 0x48 */
155 U32 Reserved4[8]; /* 0x4C */
156 U32 ReplyPostHostIndex; /* 0x6C */
157 U32 Reserved5; /* 0x70 */
158 U32 HCBSize; /* 0x74 */
159 U32 HCBAddressLow; /* 0x78 */
160 U32 HCBAddressHigh; /* 0x7C */
161 U32 Reserved6[16]; /* 0x80 */
162 U32 RequestDescriptorPostLow; /* 0xC0 */
163 U32 RequestDescriptorPostHigh; /* 0xC4 */
164 U32 Reserved7[14]; /* 0xC8 */
165} MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS,
166 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t;
167
168/*
169 * Defines for working with the Doorbell register.
170 */
171#define MPI2_DOORBELL_OFFSET (0x00000000)
172
173/* IOC --> System values */
174#define MPI2_DOORBELL_USED (0x08000000)
175#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
176#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
177#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
178#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
179
180/* System --> IOC values */
181#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
182#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
183#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
184#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
185
186
187/*
188 * Defines for the WriteSequence register
189 */
190#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
191#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
192#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
193#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
194#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
195#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
196#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
197#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
198#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
199
200/*
201 * Defines for the HostDiagnostic register
202 */
203#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
204
205#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
206#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
207#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
208
209#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
210#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
211#define MPI2_DIAG_HCB_MODE (0x00000100)
212#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
213#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
214#define MPI2_DIAG_RESET_HISTORY (0x00000020)
215#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
216#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
217#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
218
219/*
220 * Offsets for DiagRWData and address
221 */
222#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
223#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
224#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
225
226/*
227 * Defines for the HostInterruptStatus register
228 */
229#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
230#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
231#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
232#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
233#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
234#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
235#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
236
237/*
238 * Defines for the HostInterruptMask register
239 */
240#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
241#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
242#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
243#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
244#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
245#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
246
247/*
248 * Offsets for DCRData and address
249 */
250#define MPI2_DCR_DATA_OFFSET (0x00000038)
251#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
252
253/*
254 * Offset for the Reply Free Queue
255 */
256#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
257
258/*
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]259 * Defines for the Reply Descriptor Post Queue
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]260 */
261#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]262#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
263#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
264#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]265
266/*
267 * Defines for the HCBSize and address
268 */
269#define MPI2_HCB_SIZE_OFFSET (0x00000074)
270#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
271#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
272
273#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
274#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
275
276/*
277 * Offsets for the Request Queue
278 */
279#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
280#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
281
282
sreekanth.reddy@lsi.com8c79d622012-07-17 15:56:10 +0530[diff] [blame]283/* Hard Reset delay timings */
284#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
285#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
286#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
287
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]288/*****************************************************************************
289*
290* Message Descriptors
291*
292*****************************************************************************/
293
294/* Request Descriptors */
295
296/* Default Request Descriptor */
297typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR
298{
299 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]300 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]301 U16 SMID; /* 0x02 */
302 U16 LMID; /* 0x04 */
303 U16 DescriptorTypeDependent; /* 0x06 */
304} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
305 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
306 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t;
307
308/* defines for the RequestFlags field */
309#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
310#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
311#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
312#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
313#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]314#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]315
316#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
317
318
319/* High Priority Request Descriptor */
320typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR
321{
322 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]323 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]324 U16 SMID; /* 0x02 */
325 U16 LMID; /* 0x04 */
326 U16 Reserved1; /* 0x06 */
327} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
328 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
329 Mpi2HighPriorityRequestDescriptor_t,
330 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t;
331
332
333/* SCSI IO Request Descriptor */
334typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR
335{
336 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]337 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]338 U16 SMID; /* 0x02 */
339 U16 LMID; /* 0x04 */
340 U16 DevHandle; /* 0x06 */
341} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
342 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
343 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t;
344
345
346/* SCSI Target Request Descriptor */
347typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR
348{
349 U8 RequestFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]350 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]351 U16 SMID; /* 0x02 */
352 U16 LMID; /* 0x04 */
353 U16 IoIndex; /* 0x06 */
354} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
355 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
356 Mpi2SCSITargetRequestDescriptor_t,
357 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t;
358
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]359
360/* RAID Accelerator Request Descriptor */
361typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
362 U8 RequestFlags; /* 0x00 */
363 U8 MSIxIndex; /* 0x01 */
364 U16 SMID; /* 0x02 */
365 U16 LMID; /* 0x04 */
366 U16 Reserved; /* 0x06 */
367} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
368 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
369 Mpi2RAIDAcceleratorRequestDescriptor_t,
370 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t;
371
372
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]373/* union of Request Descriptors */
374typedef union _MPI2_REQUEST_DESCRIPTOR_UNION
375{
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]376 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
377 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
378 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
379 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
380 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
381 U64 Words;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]382} MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
383 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t;
384
385
386/* Reply Descriptors */
387
388/* Default Reply Descriptor */
389typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR
390{
391 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]392 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]393 U16 DescriptorTypeDependent1; /* 0x02 */
394 U32 DescriptorTypeDependent2; /* 0x04 */
395} MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
396 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t;
397
398/* defines for the ReplyFlags field */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]399#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
400#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
401#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
402#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
403#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
404#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
405#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]406
407/* values for marking a reply descriptor as unused */
408#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
409#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
410
411/* Address Reply Descriptor */
412typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR
413{
414 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]415 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]416 U16 SMID; /* 0x02 */
417 U32 ReplyFrameAddress; /* 0x04 */
418} MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
419 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t;
420
421#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
422
423
424/* SCSI IO Success Reply Descriptor */
425typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
426{
427 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]428 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]429 U16 SMID; /* 0x02 */
430 U16 TaskTag; /* 0x04 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]431 U16 Reserved1; /* 0x06 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]432} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
433 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
434 Mpi2SCSIIOSuccessReplyDescriptor_t,
435 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t;
436
437
438/* TargetAssist Success Reply Descriptor */
439typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR
440{
441 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]442 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]443 U16 SMID; /* 0x02 */
444 U8 SequenceNumber; /* 0x04 */
445 U8 Reserved1; /* 0x05 */
446 U16 IoIndex; /* 0x06 */
447} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
448 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
449 Mpi2TargetAssistSuccessReplyDescriptor_t,
450 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t;
451
452
453/* Target Command Buffer Reply Descriptor */
454typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR
455{
456 U8 ReplyFlags; /* 0x00 */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]457 U8 MSIxIndex; /* 0x01 */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]458 U8 VP_ID; /* 0x02 */
459 U8 Flags; /* 0x03 */
460 U16 InitiatorDevHandle; /* 0x04 */
461 U16 IoIndex; /* 0x06 */
462} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
463 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
464 Mpi2TargetCommandBufferReplyDescriptor_t,
465 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t;
466
467/* defines for Flags field */
468#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
469
470
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]471/* RAID Accelerator Success Reply Descriptor */
472typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
473 U8 ReplyFlags; /* 0x00 */
474 U8 MSIxIndex; /* 0x01 */
475 U16 SMID; /* 0x02 */
476 U32 Reserved; /* 0x04 */
477} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
478 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
479 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
480 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
481
482
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]483/* union of Reply Descriptors */
484typedef union _MPI2_REPLY_DESCRIPTORS_UNION
485{
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]486 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
487 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
488 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
489 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
490 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
491 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
492 U64 Words;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]493} MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION,
nagalakshmi.nandigama@lsi.com609dc442012-03-20 12:03:16 +0530[diff] [blame]494Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t;
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]495
496
497
498/*****************************************************************************
499*
500* Message Functions
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]501*
502*****************************************************************************/
503
504#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
505#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
506#define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
507#define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
508#define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
509#define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
510#define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
511#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
512#define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
513#define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
514#define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
515#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
516#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
517#define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
518#define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
519#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
520#define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
521#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
522#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
523#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
524#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
525#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
526#define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
527#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
528#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]529#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/
Kashyap, Desaif4af3c12009-12-16 18:55:54 +0530[diff] [blame]530/* Host Based Discovery Action */
531#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]532/* Power Management Control */
533#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
nagalakshmi.nandigama@lsi.comf9d979c2011-10-19 15:36:05 +0530[diff] [blame]534/* Send Host Message */
535#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
Kashyap, Desai203d65b2010-06-17 13:37:59 +0530[diff] [blame]536/* beginning of product-specific range */
537#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
538/* end of product-specific range */
539#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
540
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]541
542
543
544/* Doorbell functions */
545#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]546#define MPI2_FUNCTION_HANDSHAKE (0x42)
547
548
549/*****************************************************************************
550*
551* IOC Status Values
552*
553*****************************************************************************/
554
555/* mask for IOCStatus status value */
556#define MPI2_IOCSTATUS_MASK (0x7FFF)
557
558/****************************************************************************
559* Common IOCStatus values for all replies
560****************************************************************************/
561
562#define MPI2_IOCSTATUS_SUCCESS (0x0000)
563#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
564#define MPI2_IOCSTATUS_BUSY (0x0002)
565#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
566#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
567#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
568#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
569#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
570#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
571#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
572
573/****************************************************************************
574* Config IOCStatus values
575****************************************************************************/
576
577#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
578#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
579#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
580#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
581#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
582#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
583
584/****************************************************************************
585* SCSI IO Reply
586****************************************************************************/
587
588#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
589#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
590#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
591#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
592#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
593#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
594#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
595#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
596#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
597#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
598#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
599#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
600
601/****************************************************************************
602* For use by SCSI Initiator and SCSI Target end-to-end data protection
603****************************************************************************/
604
605#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
606#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
607#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
608
609/****************************************************************************
610* SCSI Target values
611****************************************************************************/
612
613#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
614#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
615#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
616#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
617#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
618#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
619#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
620#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
621#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
622#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
623
624/****************************************************************************
625* Serial Attached SCSI values
626****************************************************************************/
627
628#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
629#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
630
631/****************************************************************************
632* Diagnostic Buffer Post / Diagnostic Release values
633****************************************************************************/
634
635#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
636
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]637/****************************************************************************
638* RAID Accelerator values
639****************************************************************************/
640
641#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]642
643/****************************************************************************
644* IOCStatus flag to indicate that log info is available
645****************************************************************************/
646
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]647#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]648
649/****************************************************************************
650* IOCLogInfo Types
651****************************************************************************/
652
653#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
654#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
655#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
656#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
657#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
658#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
659#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
660#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
661
662
663/*****************************************************************************
664*
665* Standard Message Structures
666*
667*****************************************************************************/
668
669/****************************************************************************
670* Request Message Header for all request messages
671****************************************************************************/
672
673typedef struct _MPI2_REQUEST_HEADER
674{
675 U16 FunctionDependent1; /* 0x00 */
676 U8 ChainOffset; /* 0x02 */
677 U8 Function; /* 0x03 */
678 U16 FunctionDependent2; /* 0x04 */
679 U8 FunctionDependent3; /* 0x06 */
680 U8 MsgFlags; /* 0x07 */
681 U8 VP_ID; /* 0x08 */
682 U8 VF_ID; /* 0x09 */
683 U16 Reserved1; /* 0x0A */
684} MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER,
685 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t;
686
687
688/****************************************************************************
689* Default Reply
690****************************************************************************/
691
692typedef struct _MPI2_DEFAULT_REPLY
693{
694 U16 FunctionDependent1; /* 0x00 */
695 U8 MsgLength; /* 0x02 */
696 U8 Function; /* 0x03 */
697 U16 FunctionDependent2; /* 0x04 */
698 U8 FunctionDependent3; /* 0x06 */
699 U8 MsgFlags; /* 0x07 */
700 U8 VP_ID; /* 0x08 */
701 U8 VF_ID; /* 0x09 */
702 U16 Reserved1; /* 0x0A */
703 U16 FunctionDependent5; /* 0x0C */
704 U16 IOCStatus; /* 0x0E */
705 U32 IOCLogInfo; /* 0x10 */
706} MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY,
707 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t;
708
709
710/* common version structure/union used in messages and configuration pages */
711
712typedef struct _MPI2_VERSION_STRUCT
713{
714 U8 Dev; /* 0x00 */
715 U8 Unit; /* 0x01 */
716 U8 Minor; /* 0x02 */
717 U8 Major; /* 0x03 */
718} MPI2_VERSION_STRUCT;
719
720typedef union _MPI2_VERSION_UNION
721{
722 MPI2_VERSION_STRUCT Struct;
723 U32 Word;
724} MPI2_VERSION_UNION;
725
726
727/* LUN field defines, common to many structures */
728#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
729#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
730#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
731#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
732#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
733#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
734
735
736/*****************************************************************************
737*
738* Fusion-MPT MPI Scatter Gather Elements
739*
740*****************************************************************************/
741
742/****************************************************************************
743* MPI Simple Element structures
744****************************************************************************/
745
746typedef struct _MPI2_SGE_SIMPLE32
747{
748 U32 FlagsLength;
749 U32 Address;
750} MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32,
751 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t;
752
753typedef struct _MPI2_SGE_SIMPLE64
754{
755 U32 FlagsLength;
756 U64 Address;
757} MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64,
758 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t;
759
760typedef struct _MPI2_SGE_SIMPLE_UNION
761{
762 U32 FlagsLength;
763 union
764 {
765 U32 Address32;
766 U64 Address64;
767 } u;
768} MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION,
769 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t;
770
771
772/****************************************************************************
773* MPI Chain Element structures
774****************************************************************************/
775
776typedef struct _MPI2_SGE_CHAIN32
777{
778 U16 Length;
779 U8 NextChainOffset;
780 U8 Flags;
781 U32 Address;
782} MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32,
783 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t;
784
785typedef struct _MPI2_SGE_CHAIN64
786{
787 U16 Length;
788 U8 NextChainOffset;
789 U8 Flags;
790 U64 Address;
791} MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64,
792 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t;
793
794typedef struct _MPI2_SGE_CHAIN_UNION
795{
796 U16 Length;
797 U8 NextChainOffset;
798 U8 Flags;
799 union
800 {
801 U32 Address32;
802 U64 Address64;
803 } u;
804} MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION,
805 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t;
806
807
808/****************************************************************************
809* MPI Transaction Context Element structures
810****************************************************************************/
811
812typedef struct _MPI2_SGE_TRANSACTION32
813{
814 U8 Reserved;
815 U8 ContextSize;
816 U8 DetailsLength;
817 U8 Flags;
818 U32 TransactionContext[1];
819 U32 TransactionDetails[1];
820} MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32,
821 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t;
822
823typedef struct _MPI2_SGE_TRANSACTION64
824{
825 U8 Reserved;
826 U8 ContextSize;
827 U8 DetailsLength;
828 U8 Flags;
829 U32 TransactionContext[2];
830 U32 TransactionDetails[1];
831} MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64,
832 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t;
833
834typedef struct _MPI2_SGE_TRANSACTION96
835{
836 U8 Reserved;
837 U8 ContextSize;
838 U8 DetailsLength;
839 U8 Flags;
840 U32 TransactionContext[3];
841 U32 TransactionDetails[1];
842} MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96,
843 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t;
844
845typedef struct _MPI2_SGE_TRANSACTION128
846{
847 U8 Reserved;
848 U8 ContextSize;
849 U8 DetailsLength;
850 U8 Flags;
851 U32 TransactionContext[4];
852 U32 TransactionDetails[1];
853} MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128,
854 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128;
855
856typedef struct _MPI2_SGE_TRANSACTION_UNION
857{
858 U8 Reserved;
859 U8 ContextSize;
860 U8 DetailsLength;
861 U8 Flags;
862 union
863 {
864 U32 TransactionContext32[1];
865 U32 TransactionContext64[2];
866 U32 TransactionContext96[3];
867 U32 TransactionContext128[4];
868 } u;
869 U32 TransactionDetails[1];
870} MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION,
871 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t;
872
873
874/****************************************************************************
875* MPI SGE union for IO SGL's
876****************************************************************************/
877
878typedef struct _MPI2_MPI_SGE_IO_UNION
879{
880 union
881 {
882 MPI2_SGE_SIMPLE_UNION Simple;
883 MPI2_SGE_CHAIN_UNION Chain;
884 } u;
885} MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION,
886 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t;
887
888
889/****************************************************************************
890* MPI SGE union for SGL's with Simple and Transaction elements
891****************************************************************************/
892
893typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION
894{
895 union
896 {
897 MPI2_SGE_SIMPLE_UNION Simple;
898 MPI2_SGE_TRANSACTION_UNION Transaction;
899 } u;
900} MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
901 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t;
902
903
904/****************************************************************************
905* All MPI SGE types union
906****************************************************************************/
907
908typedef struct _MPI2_MPI_SGE_UNION
909{
910 union
911 {
912 MPI2_SGE_SIMPLE_UNION Simple;
913 MPI2_SGE_CHAIN_UNION Chain;
914 MPI2_SGE_TRANSACTION_UNION Transaction;
915 } u;
916} MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION,
917 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t;
918
919
920/****************************************************************************
921* MPI SGE field definition and masks
922****************************************************************************/
923
924/* Flags field bit definitions */
925
926#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
927#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
928#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
929#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
930#define MPI2_SGE_FLAGS_DIRECTION (0x04)
931#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
932#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
933
934#define MPI2_SGE_FLAGS_SHIFT (24)
935
936#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
937#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
938
939/* Element Type */
940
941#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
942#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
943#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
944#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
945
946/* Address location */
947
948#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
949
950/* Direction */
951
952#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
953#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
954
Kashyap, Desai7d061402010-11-13 04:36:14 +0530[diff] [blame]955#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
956#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
957
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]958/* Address Size */
959
960#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
961#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
962
963/* Context Size */
964
965#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
966#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
967#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
968#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
969
970#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
971#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
972
973/****************************************************************************
974* MPI SGE operation Macros
975****************************************************************************/
976
977/* SIMPLE FlagsLength manipulations... */
978#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
979#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT)
980#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
981#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
982
983#define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l))
984
985#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
986#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
987#define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l)
988
989/* CAUTION - The following are READ-MODIFY-WRITE! */
990#define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f)
991#define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l)
992
993#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT)
994
995
996/*****************************************************************************
997*
998* Fusion-MPT IEEE Scatter Gather Elements
999*
1000*****************************************************************************/
1001
1002/****************************************************************************
1003* IEEE Simple Element structures
1004****************************************************************************/
1005
1006typedef struct _MPI2_IEEE_SGE_SIMPLE32
1007{
1008 U32 Address;
1009 U32 FlagsLength;
1010} MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32,
1011 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t;
1012
1013typedef struct _MPI2_IEEE_SGE_SIMPLE64
1014{
1015 U64 Address;
1016 U32 Length;
1017 U16 Reserved1;
1018 U8 Reserved2;
1019 U8 Flags;
1020} MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64,
1021 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t;
1022
1023typedef union _MPI2_IEEE_SGE_SIMPLE_UNION
1024{
1025 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1026 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1027} MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1028 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t;
1029
1030
1031/****************************************************************************
1032* IEEE Chain Element structures
1033****************************************************************************/
1034
1035typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1036
1037typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1038
1039typedef union _MPI2_IEEE_SGE_CHAIN_UNION
1040{
1041 MPI2_IEEE_SGE_CHAIN32 Chain32;
1042 MPI2_IEEE_SGE_CHAIN64 Chain64;
1043} MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1044 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t;
1045
1046
1047/****************************************************************************
1048* All IEEE SGE types union
1049****************************************************************************/
1050
1051typedef struct _MPI2_IEEE_SGE_UNION
1052{
1053 union
1054 {
1055 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1056 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1057 } u;
1058} MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION,
1059 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t;
1060
1061
1062/****************************************************************************
1063* IEEE SGE field definitions and masks
1064****************************************************************************/
1065
1066/* Flags field bit definitions */
1067
1068#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1069
1070#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1071
1072#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1073
1074/* Element Type */
1075
1076#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1077#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1078
1079/* Data Location Address Space */
1080
1081#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1082#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]1083 /* IEEE Simple Element only */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1084#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]1085 /* IEEE Simple Element only */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1086#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1087#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]1088 /* IEEE Simple Element only */
nagalakshmi.nandigama@lsi.comc1bc0702011-12-01 07:43:37 +0530[diff] [blame]1089#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
Kashyap, Desaice7b1812011-06-14 10:55:45 +0530[diff] [blame]1090 /* IEEE Chain Element only */
nagalakshmi.nandigama@lsi.comc1bc0702011-12-01 07:43:37 +0530[diff] [blame]1091#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1092 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1093
1094/****************************************************************************
1095* IEEE SGE operation Macros
1096****************************************************************************/
1097
1098/* SIMPLE FlagsLength manipulations... */
1099#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1100#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1101#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1102
1103#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l))
1104
1105#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1106#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1107#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l)
1108
1109/* CAUTION - The following are READ-MODIFY-WRITE! */
1110#define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f)
1111#define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l)
1112
1113
1114
1115
1116/*****************************************************************************
1117*
1118* Fusion-MPT MPI/IEEE Scatter Gather Unions
1119*
1120*****************************************************************************/
1121
1122typedef union _MPI2_SIMPLE_SGE_UNION
1123{
1124 MPI2_SGE_SIMPLE_UNION MpiSimple;
1125 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1126} MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION,
1127 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t;
1128
1129
1130typedef union _MPI2_SGE_IO_UNION
1131{
1132 MPI2_SGE_SIMPLE_UNION MpiSimple;
1133 MPI2_SGE_CHAIN_UNION MpiChain;
1134 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1135 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1136} MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION,
1137 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t;
1138
1139
1140/****************************************************************************
1141*
1142* Values for SGLFlags field, used in many request messages with an SGL
1143*
1144****************************************************************************/
1145
1146/* values for MPI SGL Data Location Address Space subfield */
1147#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1148#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1149#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1150#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1151#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1152/* values for SGL Type subfield */
1153#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1154#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1155#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1156#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1157
1158
1159#endif
1160