blob: f9cc4bc9c7983493f1883d37ec24d58304258368 [file] [log] [blame]
Magnus Dammf411fad2011-12-14 01:36:12 +09001/*
2 * r8a7779 processor support - INTC hardware block
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/io.h>
Rob Herring520f7bd2012-12-27 13:10:24 -060025#include <linux/irqchip/arm-gic.h>
Magnus Dammf411fad2011-12-14 01:36:12 +090026#include <mach/common.h>
Simon Hormanc58a1542013-01-29 14:21:46 +090027#include <linux/irqchip.h>
Magnus Dammf411fad2011-12-14 01:36:12 +090028#include <mach/intc.h>
29#include <mach/r8a7779.h>
Magnus Dammf411fad2011-12-14 01:36:12 +090030#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32
Arnd Bergmann0a4b04d2012-09-14 20:08:08 +000033#define INT2SMSKCR0 IOMEM(0xfe7822a0)
34#define INT2SMSKCR1 IOMEM(0xfe7822a4)
35#define INT2SMSKCR2 IOMEM(0xfe7822a8)
36#define INT2SMSKCR3 IOMEM(0xfe7822ac)
37#define INT2SMSKCR4 IOMEM(0xfe7822b0)
Magnus Dammf411fad2011-12-14 01:36:12 +090038
Arnd Bergmann0a4b04d2012-09-14 20:08:08 +000039#define INT2NTSR0 IOMEM(0xfe700060)
40#define INT2NTSR1 IOMEM(0xfe700064)
Phil Edworthy86f887c2012-06-23 01:12:09 +020041
Magnus Dammf411fad2011-12-14 01:36:12 +090042static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
43{
44 return 0; /* always allow wakeup */
45}
46
Simon Hormanc58a1542013-01-29 14:21:46 +090047static void __init r8a7779_init_irq_common(void)
Magnus Dammf411fad2011-12-14 01:36:12 +090048{
Magnus Dammf411fad2011-12-14 01:36:12 +090049 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
50
Phil Edworthy86f887c2012-06-23 01:12:09 +020051 /* route all interrupts to ARM */
52 __raw_writel(0xffffffff, INT2NTSR0);
53 __raw_writel(0x3fffffff, INT2NTSR1);
54
Magnus Dammf411fad2011-12-14 01:36:12 +090055 /* unmask all known interrupts in INTCS2 */
56 __raw_writel(0xfffffff0, INT2SMSKCR0);
57 __raw_writel(0xfff7ffff, INT2SMSKCR1);
58 __raw_writel(0xfffbffdf, INT2SMSKCR2);
59 __raw_writel(0xbffffffc, INT2SMSKCR3);
60 __raw_writel(0x003fee3f, INT2SMSKCR4);
61}
Simon Hormanc58a1542013-01-29 14:21:46 +090062
63void __init r8a7779_init_irq(void)
64{
65 void __iomem *gic_dist_base = IOMEM(0xf0001000);
66 void __iomem *gic_cpu_base = IOMEM(0xf0000100);
67
68 /* use GIC to handle interrupts */
69 gic_init(0, 29, gic_dist_base, gic_cpu_base);
70
71 r8a7779_init_irq_common();
72}
73
74#ifdef CONFIG_OF
75void __init r8a7779_init_irq_dt(void)
76{
77 irqchip_init();
78 r8a7779_init_irq_common();
79}
80#endif