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review.evervolv.com / android_kernel_oneplus_msm8996 / c5a4e6d725654045e548b1a1f33059a44a06910f / . / drivers / video / via / share.h
blob: 62bed2b12d6e09a6dc6c58458c71e1f132f937ea [file] [log] [blame]
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#ifndef __SHARE_H__
23#define __SHARE_H__
24
25/* Define Return Value */
26#define FAIL -1
27#define OK 1
28
29#ifndef NULL
30#define NULL 0
31#endif
32
33/* Define Bit Field */
34#define BIT0 0x01
35#define BIT1 0x02
36#define BIT2 0x04
37#define BIT3 0x08
38#define BIT4 0x10
39#define BIT5 0x20
40#define BIT6 0x40
41#define BIT7 0x80
42
43/* Video Memory Size */
44#define VIDEO_MEMORY_SIZE_16M 0x1000000
45
Jonathan Corbet64a6bd62010-05-05 13:42:49 -0600[diff] [blame]46/*
47 * Lengths of the VPIT structure arrays.
48 */
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]49#define StdCR 0x19
50#define StdSR 0x04
51#define StdGR 0x09
52#define StdAR 0x14
53
54#define PatchCR 11
55
56/* Display path */
57#define IGA1 1
58#define IGA2 2
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]59
60/* Define Color Depth */
61#define MODE_8BPP 1
62#define MODE_16BPP 2
63#define MODE_32BPP 4
64
65#define GR20 0x20
66#define GR21 0x21
67#define GR22 0x22
68
69/* Sequencer Registers */
70#define SR01 0x01
71#define SR10 0x10
72#define SR12 0x12
73#define SR15 0x15
74#define SR16 0x16
75#define SR17 0x17
76#define SR18 0x18
77#define SR1B 0x1B
78#define SR1A 0x1A
79#define SR1C 0x1C
80#define SR1D 0x1D
81#define SR1E 0x1E
82#define SR1F 0x1F
83#define SR20 0x20
84#define SR21 0x21
85#define SR22 0x22
86#define SR2A 0x2A
87#define SR2D 0x2D
88#define SR2E 0x2E
89
90#define SR30 0x30
91#define SR39 0x39
92#define SR3D 0x3D
93#define SR3E 0x3E
94#define SR3F 0x3F
95#define SR40 0x40
96#define SR43 0x43
97#define SR44 0x44
98#define SR45 0x45
99#define SR46 0x46
100#define SR47 0x47
101#define SR48 0x48
102#define SR49 0x49
103#define SR4A 0x4A
104#define SR4B 0x4B
105#define SR4C 0x4C
106#define SR52 0x52
Harald Welte0306ab12009-09-22 16:47:35 -0700[diff] [blame]107#define SR57 0x57
108#define SR58 0x58
109#define SR59 0x59
110#define SR5D 0x5D
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]111#define SR5E 0x5E
112#define SR65 0x65
113
114/* CRT Controller Registers */
115#define CR00 0x00
116#define CR01 0x01
117#define CR02 0x02
118#define CR03 0x03
119#define CR04 0x04
120#define CR05 0x05
121#define CR06 0x06
122#define CR07 0x07
123#define CR08 0x08
124#define CR09 0x09
125#define CR0A 0x0A
126#define CR0B 0x0B
127#define CR0C 0x0C
128#define CR0D 0x0D
129#define CR0E 0x0E
130#define CR0F 0x0F
131#define CR10 0x10
132#define CR11 0x11
133#define CR12 0x12
134#define CR13 0x13
135#define CR14 0x14
136#define CR15 0x15
137#define CR16 0x16
138#define CR17 0x17
139#define CR18 0x18
140
141/* Extend CRT Controller Registers */
142#define CR30 0x30
143#define CR31 0x31
144#define CR32 0x32
145#define CR33 0x33
146#define CR34 0x34
147#define CR35 0x35
148#define CR36 0x36
149#define CR37 0x37
150#define CR38 0x38
151#define CR39 0x39
152#define CR3A 0x3A
153#define CR3B 0x3B
154#define CR3C 0x3C
155#define CR3D 0x3D
156#define CR3E 0x3E
157#define CR3F 0x3F
158#define CR40 0x40
159#define CR41 0x41
160#define CR42 0x42
161#define CR43 0x43
162#define CR44 0x44
163#define CR45 0x45
164#define CR46 0x46
165#define CR47 0x47
166#define CR48 0x48
167#define CR49 0x49
168#define CR4A 0x4A
169#define CR4B 0x4B
170#define CR4C 0x4C
171#define CR4D 0x4D
172#define CR4E 0x4E
173#define CR4F 0x4F
174#define CR50 0x50
175#define CR51 0x51
176#define CR52 0x52
177#define CR53 0x53
178#define CR54 0x54
179#define CR55 0x55
180#define CR56 0x56
181#define CR57 0x57
182#define CR58 0x58
183#define CR59 0x59
184#define CR5A 0x5A
185#define CR5B 0x5B
186#define CR5C 0x5C
187#define CR5D 0x5D
188#define CR5E 0x5E
189#define CR5F 0x5F
190#define CR60 0x60
191#define CR61 0x61
192#define CR62 0x62
193#define CR63 0x63
194#define CR64 0x64
195#define CR65 0x65
196#define CR66 0x66
197#define CR67 0x67
198#define CR68 0x68
199#define CR69 0x69
200#define CR6A 0x6A
201#define CR6B 0x6B
202#define CR6C 0x6C
203#define CR6D 0x6D
204#define CR6E 0x6E
205#define CR6F 0x6F
206#define CR70 0x70
207#define CR71 0x71
208#define CR72 0x72
209#define CR73 0x73
210#define CR74 0x74
211#define CR75 0x75
212#define CR76 0x76
213#define CR77 0x77
214#define CR78 0x78
215#define CR79 0x79
216#define CR7A 0x7A
217#define CR7B 0x7B
218#define CR7C 0x7C
219#define CR7D 0x7D
220#define CR7E 0x7E
221#define CR7F 0x7F
222#define CR80 0x80
223#define CR81 0x81
224#define CR82 0x82
225#define CR83 0x83
226#define CR84 0x84
227#define CR85 0x85
228#define CR86 0x86
229#define CR87 0x87
230#define CR88 0x88
231#define CR89 0x89
232#define CR8A 0x8A
233#define CR8B 0x8B
234#define CR8C 0x8C
235#define CR8D 0x8D
236#define CR8E 0x8E
237#define CR8F 0x8F
238#define CR90 0x90
239#define CR91 0x91
240#define CR92 0x92
241#define CR93 0x93
242#define CR94 0x94
243#define CR95 0x95
244#define CR96 0x96
245#define CR97 0x97
246#define CR98 0x98
247#define CR99 0x99
248#define CR9A 0x9A
249#define CR9B 0x9B
250#define CR9C 0x9C
251#define CR9D 0x9D
252#define CR9E 0x9E
253#define CR9F 0x9F
254#define CRA0 0xA0
255#define CRA1 0xA1
256#define CRA2 0xA2
257#define CRA3 0xA3
258#define CRD2 0xD2
259#define CRD3 0xD3
260#define CRD4 0xD4
261
262/* LUT Table*/
263#define LUT_DATA 0x3C9 /* DACDATA */
264#define LUT_INDEX_READ 0x3C7 /* DACRX */
265#define LUT_INDEX_WRITE 0x3C8 /* DACWX */
266#define DACMASK 0x3C6
267
268/* Definition Device */
269#define DEVICE_CRT 0x01
270#define DEVICE_DVI 0x03
271#define DEVICE_LCD 0x04
272
273/* Device output interface */
274#define INTERFACE_NONE 0x00
275#define INTERFACE_ANALOG_RGB 0x01
276#define INTERFACE_DVP0 0x02
277#define INTERFACE_DVP1 0x03
278#define INTERFACE_DFP_HIGH 0x04
279#define INTERFACE_DFP_LOW 0x05
280#define INTERFACE_DFP 0x06
281#define INTERFACE_LVDS0 0x07
282#define INTERFACE_LVDS1 0x08
283#define INTERFACE_LVDS0LVDS1 0x09
284#define INTERFACE_TMDS 0x0A
285
286#define HW_LAYOUT_LCD_ONLY 0x01
287#define HW_LAYOUT_DVI_ONLY 0x02
288#define HW_LAYOUT_LCD_DVI 0x03
289#define HW_LAYOUT_LCD1_LCD2 0x04
290#define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10
291
292/* Definition Refresh Rate */
Florian Tobias Schandinatc5a4e6d2011-04-23 22:24:52 +0000[diff] [blame^]293#define REFRESH_49 49
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]294#define REFRESH_50 50
295#define REFRESH_60 60
296#define REFRESH_75 75
297#define REFRESH_85 85
298#define REFRESH_100 100
299#define REFRESH_120 120
300
301/* Definition Sync Polarity*/
302#define NEGATIVE 1
303#define POSITIVE 0
304
305/*480x640@60 Sync Polarity (GTF)
306*/
307#define M480X640_R60_HSP NEGATIVE
308#define M480X640_R60_VSP POSITIVE
309
310/*640x480@60 Sync Polarity (VESA Mode)
311*/
312#define M640X480_R60_HSP NEGATIVE
313#define M640X480_R60_VSP NEGATIVE
314
315/*640x480@75 Sync Polarity (VESA Mode)
316*/
317#define M640X480_R75_HSP NEGATIVE
318#define M640X480_R75_VSP NEGATIVE
319
320/*640x480@85 Sync Polarity (VESA Mode)
321*/
322#define M640X480_R85_HSP NEGATIVE
323#define M640X480_R85_VSP NEGATIVE
324
325/*640x480@100 Sync Polarity (GTF Mode)
326*/
327#define M640X480_R100_HSP NEGATIVE
328#define M640X480_R100_VSP POSITIVE
329
330/*640x480@120 Sync Polarity (GTF Mode)
331*/
332#define M640X480_R120_HSP NEGATIVE
333#define M640X480_R120_VSP POSITIVE
334
335/*720x480@60 Sync Polarity (GTF Mode)
336*/
337#define M720X480_R60_HSP NEGATIVE
338#define M720X480_R60_VSP POSITIVE
339
340/*720x576@60 Sync Polarity (GTF Mode)
341*/
342#define M720X576_R60_HSP NEGATIVE
343#define M720X576_R60_VSP POSITIVE
344
345/*800x600@60 Sync Polarity (VESA Mode)
346*/
347#define M800X600_R60_HSP POSITIVE
348#define M800X600_R60_VSP POSITIVE
349
350/*800x600@75 Sync Polarity (VESA Mode)
351*/
352#define M800X600_R75_HSP POSITIVE
353#define M800X600_R75_VSP POSITIVE
354
355/*800x600@85 Sync Polarity (VESA Mode)
356*/
357#define M800X600_R85_HSP POSITIVE
358#define M800X600_R85_VSP POSITIVE
359
360/*800x600@100 Sync Polarity (GTF Mode)
361*/
362#define M800X600_R100_HSP NEGATIVE
363#define M800X600_R100_VSP POSITIVE
364
365/*800x600@120 Sync Polarity (GTF Mode)
366*/
367#define M800X600_R120_HSP NEGATIVE
368#define M800X600_R120_VSP POSITIVE
369
370/*800x480@60 Sync Polarity (CVT Mode)
371*/
372#define M800X480_R60_HSP NEGATIVE
373#define M800X480_R60_VSP POSITIVE
374
375/*848x480@60 Sync Polarity (CVT Mode)
376*/
377#define M848X480_R60_HSP NEGATIVE
378#define M848X480_R60_VSP POSITIVE
379
380/*852x480@60 Sync Polarity (GTF Mode)
381*/
382#define M852X480_R60_HSP NEGATIVE
383#define M852X480_R60_VSP POSITIVE
384
385/*1024x512@60 Sync Polarity (GTF Mode)
386*/
387#define M1024X512_R60_HSP NEGATIVE
388#define M1024X512_R60_VSP POSITIVE
389
390/*1024x600@60 Sync Polarity (GTF Mode)
391*/
392#define M1024X600_R60_HSP NEGATIVE
393#define M1024X600_R60_VSP POSITIVE
394
395/*1024x768@60 Sync Polarity (VESA Mode)
396*/
397#define M1024X768_R60_HSP NEGATIVE
398#define M1024X768_R60_VSP NEGATIVE
399
400/*1024x768@75 Sync Polarity (VESA Mode)
401*/
402#define M1024X768_R75_HSP POSITIVE
403#define M1024X768_R75_VSP POSITIVE
404
405/*1024x768@85 Sync Polarity (VESA Mode)
406*/
407#define M1024X768_R85_HSP POSITIVE
408#define M1024X768_R85_VSP POSITIVE
409
410/*1024x768@100 Sync Polarity (GTF Mode)
411*/
412#define M1024X768_R100_HSP NEGATIVE
413#define M1024X768_R100_VSP POSITIVE
414
415/*1152x864@75 Sync Polarity (VESA Mode)
416*/
417#define M1152X864_R75_HSP POSITIVE
418#define M1152X864_R75_VSP POSITIVE
419
420/*1280x720@60 Sync Polarity (GTF Mode)
421*/
422#define M1280X720_R60_HSP NEGATIVE
423#define M1280X720_R60_VSP POSITIVE
424
425/* 1280x768@50 Sync Polarity (GTF Mode) */
426#define M1280X768_R50_HSP NEGATIVE
427#define M1280X768_R50_VSP POSITIVE
428
429/*1280x768@60 Sync Polarity (GTF Mode)
430*/
431#define M1280X768_R60_HSP NEGATIVE
432#define M1280X768_R60_VSP POSITIVE
433
434/*1280x800@60 Sync Polarity (CVT Mode)
435*/
436#define M1280X800_R60_HSP NEGATIVE
437#define M1280X800_R60_VSP POSITIVE
438
439/*1280x960@60 Sync Polarity (VESA Mode)
440*/
441#define M1280X960_R60_HSP POSITIVE
442#define M1280X960_R60_VSP POSITIVE
443
444/*1280x1024@60 Sync Polarity (VESA Mode)
445*/
446#define M1280X1024_R60_HSP POSITIVE
447#define M1280X1024_R60_VSP POSITIVE
448
449/* 1360x768@60 Sync Polarity (CVT Mode) */
450#define M1360X768_R60_HSP POSITIVE
451#define M1360X768_R60_VSP POSITIVE
452
453/* 1360x768@60 Sync Polarity (CVT Reduce Blanking Mode) */
454#define M1360X768_RB_R60_HSP POSITIVE
455#define M1360X768_RB_R60_VSP NEGATIVE
456
457/* 1368x768@50 Sync Polarity (GTF Mode) */
458#define M1368X768_R50_HSP NEGATIVE
459#define M1368X768_R50_VSP POSITIVE
460
461/* 1368x768@60 Sync Polarity (VESA Mode) */
462#define M1368X768_R60_HSP NEGATIVE
463#define M1368X768_R60_VSP POSITIVE
464
465/*1280x1024@75 Sync Polarity (VESA Mode)
466*/
467#define M1280X1024_R75_HSP POSITIVE
468#define M1280X1024_R75_VSP POSITIVE
469
470/*1280x1024@85 Sync Polarity (VESA Mode)
471*/
472#define M1280X1024_R85_HSP POSITIVE
473#define M1280X1024_R85_VSP POSITIVE
474
475/*1440x1050@60 Sync Polarity (GTF Mode)
476*/
477#define M1440X1050_R60_HSP NEGATIVE
478#define M1440X1050_R60_VSP POSITIVE
479
480/*1600x1200@60 Sync Polarity (VESA Mode)
481*/
482#define M1600X1200_R60_HSP POSITIVE
483#define M1600X1200_R60_VSP POSITIVE
484
485/*1600x1200@75 Sync Polarity (VESA Mode)
486*/
487#define M1600X1200_R75_HSP POSITIVE
488#define M1600X1200_R75_VSP POSITIVE
489
490/* 1680x1050@60 Sync Polarity (CVT Mode) */
491#define M1680x1050_R60_HSP NEGATIVE
492#define M1680x1050_R60_VSP NEGATIVE
493
494/* 1680x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
495#define M1680x1050_RB_R60_HSP POSITIVE
496#define M1680x1050_RB_R60_VSP NEGATIVE
497
498/* 1680x1050@75 Sync Polarity (CVT Mode) */
499#define M1680x1050_R75_HSP NEGATIVE
500#define M1680x1050_R75_VSP POSITIVE
501
502/*1920x1080@60 Sync Polarity (CVT Mode)
503*/
504#define M1920X1080_R60_HSP NEGATIVE
505#define M1920X1080_R60_VSP POSITIVE
506
507/* 1920x1080@60 Sync Polarity (CVT Reduce Blanking Mode) */
508#define M1920X1080_RB_R60_HSP POSITIVE
509#define M1920X1080_RB_R60_VSP NEGATIVE
510
511/*1920x1440@60 Sync Polarity (VESA Mode)
512*/
513#define M1920X1440_R60_HSP NEGATIVE
514#define M1920X1440_R60_VSP POSITIVE
515
516/*1920x1440@75 Sync Polarity (VESA Mode)
517*/
518#define M1920X1440_R75_HSP NEGATIVE
519#define M1920X1440_R75_VSP POSITIVE
520
521#if 0
522/* 1400x1050@60 Sync Polarity (VESA Mode) */
523#define M1400X1050_R60_HSP NEGATIVE
524#define M1400X1050_R60_VSP NEGATIVE
525#endif
526
527/* 1400x1050@60 Sync Polarity (CVT Mode) */
528#define M1400X1050_R60_HSP NEGATIVE
529#define M1400X1050_R60_VSP POSITIVE
530
531/* 1400x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */
532#define M1400X1050_RB_R60_HSP POSITIVE
533#define M1400X1050_RB_R60_VSP NEGATIVE
534
535/* 1400x1050@75 Sync Polarity (CVT Mode) */
536#define M1400X1050_R75_HSP NEGATIVE
537#define M1400X1050_R75_VSP POSITIVE
538
539/* 960x600@60 Sync Polarity (CVT Mode) */
540#define M960X600_R60_HSP NEGATIVE
541#define M960X600_R60_VSP POSITIVE
542
543/* 1000x600@60 Sync Polarity (GTF Mode) */
544#define M1000X600_R60_HSP NEGATIVE
545#define M1000X600_R60_VSP POSITIVE
546
547/* 1024x576@60 Sync Polarity (GTF Mode) */
548#define M1024X576_R60_HSP NEGATIVE
549#define M1024X576_R60_VSP POSITIVE
550
551/*1024x600@60 Sync Polarity (GTF Mode)*/
552#define M1024X600_R60_HSP NEGATIVE
553#define M1024X600_R60_VSP POSITIVE
554
555/* 1088x612@60 Sync Polarity (CVT Mode) */
556#define M1088X612_R60_HSP NEGATIVE
557#define M1088X612_R60_VSP POSITIVE
558
559/* 1152x720@60 Sync Polarity (CVT Mode) */
560#define M1152X720_R60_HSP NEGATIVE
561#define M1152X720_R60_VSP POSITIVE
562
563/* 1200x720@60 Sync Polarity (GTF Mode) */
564#define M1200X720_R60_HSP NEGATIVE
565#define M1200X720_R60_VSP POSITIVE
566
Chris Ballc205d932009-06-07 13:59:51 -0400[diff] [blame]567/* 1200x900@60 Sync Polarity (DCON) */
568#define M1200X900_R60_HSP NEGATIVE
569#define M1200X900_R60_VSP NEGATIVE
570
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]571/* 1280x600@60 Sync Polarity (GTF Mode) */
572#define M1280x600_R60_HSP NEGATIVE
573#define M1280x600_R60_VSP POSITIVE
574
575/* 1280x720@50 Sync Polarity (GTF Mode) */
576#define M1280X720_R50_HSP NEGATIVE
577#define M1280X720_R50_VSP POSITIVE
578
579/* 1280x720@60 Sync Polarity (CEA Mode) */
580#define M1280X720_CEA_R60_HSP POSITIVE
581#define M1280X720_CEA_R60_VSP POSITIVE
582
583/* 1440x900@60 Sync Polarity (CVT Mode) */
584#define M1440X900_R60_HSP NEGATIVE
585#define M1440X900_R60_VSP POSITIVE
586
587/* 1440x900@75 Sync Polarity (CVT Mode) */
588#define M1440X900_R75_HSP NEGATIVE
589#define M1440X900_R75_VSP POSITIVE
590
591/* 1440x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
592#define M1440X900_RB_R60_HSP POSITIVE
593#define M1440X900_RB_R60_VSP NEGATIVE
594
595/* 1600x900@60 Sync Polarity (CVT Mode) */
596#define M1600X900_R60_HSP NEGATIVE
597#define M1600X900_R60_VSP POSITIVE
598
599/* 1600x900@60 Sync Polarity (CVT Reduce Blanking Mode) */
600#define M1600X900_RB_R60_HSP POSITIVE
601#define M1600X900_RB_R60_VSP NEGATIVE
602
603/* 1600x1024@60 Sync Polarity (GTF Mode) */
604#define M1600X1024_R60_HSP NEGATIVE
605#define M1600X1024_R60_VSP POSITIVE
606
607/* 1792x1344@60 Sync Polarity (DMT Mode) */
608#define M1792x1344_R60_HSP NEGATIVE
609#define M1792x1344_R60_VSP POSITIVE
610
611/* 1856x1392@60 Sync Polarity (DMT Mode) */
612#define M1856x1392_R60_HSP NEGATIVE
613#define M1856x1392_R60_VSP POSITIVE
614
615/* 1920x1200@60 Sync Polarity (CVT Mode) */
616#define M1920X1200_R60_HSP NEGATIVE
617#define M1920X1200_R60_VSP POSITIVE
618
619/* 1920x1200@60 Sync Polarity (CVT Reduce Blanking Mode) */
620#define M1920X1200_RB_R60_HSP POSITIVE
621#define M1920X1200_RB_R60_VSP NEGATIVE
622
623/* 1920x1080@60 Sync Polarity (CEA Mode) */
624#define M1920X1080_CEA_R60_HSP POSITIVE
625#define M1920X1080_CEA_R60_VSP POSITIVE
626
627/* 2048x1536@60 Sync Polarity (CVT Mode) */
628#define M2048x1536_R60_HSP NEGATIVE
629#define M2048x1536_R60_VSP POSITIVE
630
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]631/* Definition CRTC Timing Index */
632#define H_TOTAL_INDEX 0
633#define H_ADDR_INDEX 1
634#define H_BLANK_START_INDEX 2
635#define H_BLANK_END_INDEX 3
636#define H_SYNC_START_INDEX 4
637#define H_SYNC_END_INDEX 5
638#define V_TOTAL_INDEX 6
639#define V_ADDR_INDEX 7
640#define V_BLANK_START_INDEX 8
641#define V_BLANK_END_INDEX 9
642#define V_SYNC_START_INDEX 10
643#define V_SYNC_END_INDEX 11
644#define H_TOTAL_SHADOW_INDEX 12
645#define H_BLANK_END_SHADOW_INDEX 13
646#define V_TOTAL_SHADOW_INDEX 14
647#define V_ADDR_SHADOW_INDEX 15
648#define V_BLANK_SATRT_SHADOW_INDEX 16
649#define V_BLANK_END_SHADOW_INDEX 17
650#define V_SYNC_SATRT_SHADOW_INDEX 18
651#define V_SYNC_END_SHADOW_INDEX 19
652
653/* Definition Video Mode Pixel Clock (picoseconds)
654*/
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]655#define RES_640X480_60HZ_PIXCLOCK 39722
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]656
657/* LCD display method
658*/
659#define LCD_EXPANDSION 0x00
660#define LCD_CENTERING 0x01
661
662/* LCD mode
663*/
664#define LCD_OPENLDI 0x00
665#define LCD_SPWG 0x01
666
667/* Define display timing
668*/
669struct display_timing {
670 u16 hor_total;
671 u16 hor_addr;
672 u16 hor_blank_start;
673 u16 hor_blank_end;
674 u16 hor_sync_start;
675 u16 hor_sync_end;
676 u16 ver_total;
677 u16 ver_addr;
678 u16 ver_blank_start;
679 u16 ver_blank_end;
680 u16 ver_sync_start;
681 u16 ver_sync_end;
682};
683
684struct crt_mode_table {
685 int refresh_rate;
Joseph Chan37773cf2008-10-15 22:03:26 -0700[diff] [blame]686 int h_sync_polarity;
687 int v_sync_polarity;
688 struct display_timing crtc;
689};
690
691struct io_reg {
692 int port;
693 u8 index;
694 u8 mask;
695 u8 value;
696};
697
698#endif /* __SHARE_H__ */