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review.evervolv.com / android_kernel_oneplus_msm8996 / c5f336cc003dfa071aaa7a01ed1c16232b227aa4 / . / sound / soc / codecs / wm8915.c
blob: 4a3c5cc77e552745ba49514afb480a1c38edea10 [file] [log] [blame]
Mark Brownc93993a2011-02-08 14:09:41 +0000[diff] [blame]1/*
2 * wm8915.c - WM8915 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
22#include <linux/delay.h>
23#include <linux/regulator/consumer.h>
24#include <linux/slab.h>
25#include <linux/workqueue.h>
26#include <sound/core.h>
27#include <sound/jack.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <trace/events/asoc.h>
34
35#include <sound/wm8915.h>
36#include "wm8915.h"
37
38#define WM8915_AIFS 2
39
40#define HPOUT1L 1
41#define HPOUT1R 2
42#define HPOUT2L 4
43#define HPOUT2R 8
44
45#define WM8915_NUM_SUPPLIES 6
46static const char *wm8915_supply_names[WM8915_NUM_SUPPLIES] = {
47 "DCVDD",
48 "DBVDD",
49 "AVDD1",
50 "AVDD2",
51 "CPVDD",
52 "MICVDD",
53};
54
55struct wm8915_priv {
56 struct snd_soc_codec *codec;
57
58 int ldo1ena;
59
60 int sysclk;
61
62 int fll_src;
63 int fll_fref;
64 int fll_fout;
65
66 struct completion fll_lock;
67
68 u16 dcs_pending;
69 struct completion dcs_done;
70
71 u16 hpout_ena;
72 u16 hpout_pending;
73
74 struct regulator_bulk_data supplies[WM8915_NUM_SUPPLIES];
75 struct notifier_block disable_nb[WM8915_NUM_SUPPLIES];
76
77 struct wm8915_pdata pdata;
78
79 int rx_rate[WM8915_AIFS];
80
81 /* Platform dependant ReTune mobile configuration */
82 int num_retune_mobile_texts;
83 const char **retune_mobile_texts;
84 int retune_mobile_cfg[2];
85 struct soc_enum retune_mobile_enum;
86
87 struct snd_soc_jack *jack;
88 bool detecting;
89 bool jack_mic;
90 wm8915_polarity_fn polarity_cb;
91
92#ifdef CONFIG_GPIOLIB
93 struct gpio_chip gpio_chip;
94#endif
95};
96
97/* We can't use the same notifier block for more than one supply and
98 * there's no way I can see to get from a callback to the caller
99 * except container_of().
100 */
101#define WM8915_REGULATOR_EVENT(n) \
102static int wm8915_regulator_event_##n(struct notifier_block *nb, \
103 unsigned long event, void *data) \
104{ \
105 struct wm8915_priv *wm8915 = container_of(nb, struct wm8915_priv, \
106 disable_nb[n]); \
107 if (event & REGULATOR_EVENT_DISABLE) { \
108 wm8915->codec->cache_sync = 1; \
109 } \
110 return 0; \
111}
112
113WM8915_REGULATOR_EVENT(0)
114WM8915_REGULATOR_EVENT(1)
115WM8915_REGULATOR_EVENT(2)
116WM8915_REGULATOR_EVENT(3)
117WM8915_REGULATOR_EVENT(4)
118WM8915_REGULATOR_EVENT(5)
119
120static const u16 wm8915_reg[WM8915_MAX_REGISTER] = {
121 [WM8915_SOFTWARE_RESET] = 0x8915,
122 [WM8915_POWER_MANAGEMENT_7] = 0x10,
123 [WM8915_DAC1_HPOUT1_VOLUME] = 0x88,
124 [WM8915_DAC2_HPOUT2_VOLUME] = 0x88,
125 [WM8915_DAC1_LEFT_VOLUME] = 0x2c0,
126 [WM8915_DAC1_RIGHT_VOLUME] = 0x2c0,
127 [WM8915_DAC2_LEFT_VOLUME] = 0x2c0,
128 [WM8915_DAC2_RIGHT_VOLUME] = 0x2c0,
129 [WM8915_OUTPUT1_LEFT_VOLUME] = 0x80,
130 [WM8915_OUTPUT1_RIGHT_VOLUME] = 0x80,
131 [WM8915_OUTPUT2_LEFT_VOLUME] = 0x80,
132 [WM8915_OUTPUT2_RIGHT_VOLUME] = 0x80,
133 [WM8915_MICBIAS_1] = 0x39,
134 [WM8915_MICBIAS_2] = 0x39,
135 [WM8915_LDO_1] = 0x3,
136 [WM8915_LDO_2] = 0x13,
137 [WM8915_ACCESSORY_DETECT_MODE_1] = 0x4,
138 [WM8915_HEADPHONE_DETECT_1] = 0x20,
139 [WM8915_MIC_DETECT_1] = 0x7600,
140 [WM8915_MIC_DETECT_2] = 0xbf,
141 [WM8915_CHARGE_PUMP_1] = 0x1f25,
142 [WM8915_CHARGE_PUMP_2] = 0xab19,
143 [WM8915_DC_SERVO_5] = 0x2a2a,
144 [WM8915_CONTROL_INTERFACE_1] = 0x8004,
145 [WM8915_CLOCKING_1] = 0x10,
146 [WM8915_AIF_RATE] = 0x83,
147 [WM8915_FLL_CONTROL_4] = 0x5dc0,
148 [WM8915_FLL_CONTROL_5] = 0xc84,
149 [WM8915_FLL_EFS_2] = 0x2,
150 [WM8915_AIF1_TX_LRCLK_1] = 0x80,
151 [WM8915_AIF1_TX_LRCLK_2] = 0x8,
152 [WM8915_AIF1_RX_LRCLK_1] = 0x80,
153 [WM8915_AIF1TX_DATA_CONFIGURATION_1] = 0x1818,
154 [WM8915_AIF1RX_DATA_CONFIGURATION] = 0x1818,
155 [WM8915_AIF1TX_TEST] = 0x7,
156 [WM8915_AIF2_TX_LRCLK_1] = 0x80,
157 [WM8915_AIF2_TX_LRCLK_2] = 0x8,
158 [WM8915_AIF2_RX_LRCLK_1] = 0x80,
159 [WM8915_AIF2TX_DATA_CONFIGURATION_1] = 0x1818,
160 [WM8915_AIF2RX_DATA_CONFIGURATION] = 0x1818,
161 [WM8915_AIF2TX_TEST] = 0x1,
162 [WM8915_DSP1_TX_LEFT_VOLUME] = 0xc0,
163 [WM8915_DSP1_TX_RIGHT_VOLUME] = 0xc0,
164 [WM8915_DSP1_RX_LEFT_VOLUME] = 0xc0,
165 [WM8915_DSP1_RX_RIGHT_VOLUME] = 0xc0,
166 [WM8915_DSP1_TX_FILTERS] = 0x2000,
167 [WM8915_DSP1_RX_FILTERS_1] = 0x200,
168 [WM8915_DSP1_RX_FILTERS_2] = 0x10,
169 [WM8915_DSP1_DRC_1] = 0x98,
170 [WM8915_DSP1_DRC_2] = 0x845,
171 [WM8915_DSP1_RX_EQ_GAINS_1] = 0x6318,
172 [WM8915_DSP1_RX_EQ_GAINS_2] = 0x6300,
173 [WM8915_DSP1_RX_EQ_BAND_1_A] = 0xfca,
174 [WM8915_DSP1_RX_EQ_BAND_1_B] = 0x400,
175 [WM8915_DSP1_RX_EQ_BAND_1_PG] = 0xd8,
176 [WM8915_DSP1_RX_EQ_BAND_2_A] = 0x1eb5,
177 [WM8915_DSP1_RX_EQ_BAND_2_B] = 0xf145,
178 [WM8915_DSP1_RX_EQ_BAND_2_C] = 0xb75,
179 [WM8915_DSP1_RX_EQ_BAND_2_PG] = 0x1c5,
180 [WM8915_DSP1_RX_EQ_BAND_3_A] = 0x1c58,
181 [WM8915_DSP1_RX_EQ_BAND_3_B] = 0xf373,
182 [WM8915_DSP1_RX_EQ_BAND_3_C] = 0xa54,
183 [WM8915_DSP1_RX_EQ_BAND_3_PG] = 0x558,
184 [WM8915_DSP1_RX_EQ_BAND_4_A] = 0x168e,
185 [WM8915_DSP1_RX_EQ_BAND_4_B] = 0xf829,
186 [WM8915_DSP1_RX_EQ_BAND_4_C] = 0x7ad,
187 [WM8915_DSP1_RX_EQ_BAND_4_PG] = 0x1103,
188 [WM8915_DSP1_RX_EQ_BAND_5_A] = 0x564,
189 [WM8915_DSP1_RX_EQ_BAND_5_B] = 0x559,
190 [WM8915_DSP1_RX_EQ_BAND_5_PG] = 0x4000,
191 [WM8915_DSP2_TX_LEFT_VOLUME] = 0xc0,
192 [WM8915_DSP2_TX_RIGHT_VOLUME] = 0xc0,
193 [WM8915_DSP2_RX_LEFT_VOLUME] = 0xc0,
194 [WM8915_DSP2_RX_RIGHT_VOLUME] = 0xc0,
195 [WM8915_DSP2_TX_FILTERS] = 0x2000,
196 [WM8915_DSP2_RX_FILTERS_1] = 0x200,
197 [WM8915_DSP2_RX_FILTERS_2] = 0x10,
198 [WM8915_DSP2_DRC_1] = 0x98,
199 [WM8915_DSP2_DRC_2] = 0x845,
200 [WM8915_DSP2_RX_EQ_GAINS_1] = 0x6318,
201 [WM8915_DSP2_RX_EQ_GAINS_2] = 0x6300,
202 [WM8915_DSP2_RX_EQ_BAND_1_A] = 0xfca,
203 [WM8915_DSP2_RX_EQ_BAND_1_B] = 0x400,
204 [WM8915_DSP2_RX_EQ_BAND_1_PG] = 0xd8,
205 [WM8915_DSP2_RX_EQ_BAND_2_A] = 0x1eb5,
206 [WM8915_DSP2_RX_EQ_BAND_2_B] = 0xf145,
207 [WM8915_DSP2_RX_EQ_BAND_2_C] = 0xb75,
208 [WM8915_DSP2_RX_EQ_BAND_2_PG] = 0x1c5,
209 [WM8915_DSP2_RX_EQ_BAND_3_A] = 0x1c58,
210 [WM8915_DSP2_RX_EQ_BAND_3_B] = 0xf373,
211 [WM8915_DSP2_RX_EQ_BAND_3_C] = 0xa54,
212 [WM8915_DSP2_RX_EQ_BAND_3_PG] = 0x558,
213 [WM8915_DSP2_RX_EQ_BAND_4_A] = 0x168e,
214 [WM8915_DSP2_RX_EQ_BAND_4_B] = 0xf829,
215 [WM8915_DSP2_RX_EQ_BAND_4_C] = 0x7ad,
216 [WM8915_DSP2_RX_EQ_BAND_4_PG] = 0x1103,
217 [WM8915_DSP2_RX_EQ_BAND_5_A] = 0x564,
218 [WM8915_DSP2_RX_EQ_BAND_5_B] = 0x559,
219 [WM8915_DSP2_RX_EQ_BAND_5_PG] = 0x4000,
220 [WM8915_OVERSAMPLING] = 0xd,
221 [WM8915_SIDETONE] = 0x1040,
222 [WM8915_GPIO_1] = 0xa101,
223 [WM8915_GPIO_2] = 0xa101,
224 [WM8915_GPIO_3] = 0xa101,
225 [WM8915_GPIO_4] = 0xa101,
226 [WM8915_GPIO_5] = 0xa101,
227 [WM8915_PULL_CONTROL_2] = 0x140,
228 [WM8915_INTERRUPT_STATUS_1_MASK] = 0x1f,
229 [WM8915_INTERRUPT_STATUS_2_MASK] = 0x1ecf,
230 [WM8915_RIGHT_PDM_SPEAKER] = 0x1,
231 [WM8915_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69,
232 [WM8915_PDM_SPEAKER_VOLUME] = 0x66,
233 [WM8915_WRITE_SEQUENCER_0] = 0x1,
234 [WM8915_WRITE_SEQUENCER_1] = 0x1,
235 [WM8915_WRITE_SEQUENCER_3] = 0x6,
236 [WM8915_WRITE_SEQUENCER_4] = 0x40,
237 [WM8915_WRITE_SEQUENCER_5] = 0x1,
238 [WM8915_WRITE_SEQUENCER_6] = 0xf,
239 [WM8915_WRITE_SEQUENCER_7] = 0x6,
240 [WM8915_WRITE_SEQUENCER_8] = 0x1,
241 [WM8915_WRITE_SEQUENCER_9] = 0x3,
242 [WM8915_WRITE_SEQUENCER_10] = 0x104,
243 [WM8915_WRITE_SEQUENCER_12] = 0x60,
244 [WM8915_WRITE_SEQUENCER_13] = 0x11,
245 [WM8915_WRITE_SEQUENCER_14] = 0x401,
246 [WM8915_WRITE_SEQUENCER_16] = 0x50,
247 [WM8915_WRITE_SEQUENCER_17] = 0x3,
248 [WM8915_WRITE_SEQUENCER_18] = 0x100,
249 [WM8915_WRITE_SEQUENCER_20] = 0x51,
250 [WM8915_WRITE_SEQUENCER_21] = 0x3,
251 [WM8915_WRITE_SEQUENCER_22] = 0x104,
252 [WM8915_WRITE_SEQUENCER_23] = 0xa,
253 [WM8915_WRITE_SEQUENCER_24] = 0x60,
254 [WM8915_WRITE_SEQUENCER_25] = 0x3b,
255 [WM8915_WRITE_SEQUENCER_26] = 0x502,
256 [WM8915_WRITE_SEQUENCER_27] = 0x100,
257 [WM8915_WRITE_SEQUENCER_28] = 0x2fff,
258 [WM8915_WRITE_SEQUENCER_32] = 0x2fff,
259 [WM8915_WRITE_SEQUENCER_36] = 0x2fff,
260 [WM8915_WRITE_SEQUENCER_40] = 0x2fff,
261 [WM8915_WRITE_SEQUENCER_44] = 0x2fff,
262 [WM8915_WRITE_SEQUENCER_48] = 0x2fff,
263 [WM8915_WRITE_SEQUENCER_52] = 0x2fff,
264 [WM8915_WRITE_SEQUENCER_56] = 0x2fff,
265 [WM8915_WRITE_SEQUENCER_60] = 0x2fff,
266 [WM8915_WRITE_SEQUENCER_64] = 0x1,
267 [WM8915_WRITE_SEQUENCER_65] = 0x1,
268 [WM8915_WRITE_SEQUENCER_67] = 0x6,
269 [WM8915_WRITE_SEQUENCER_68] = 0x40,
270 [WM8915_WRITE_SEQUENCER_69] = 0x1,
271 [WM8915_WRITE_SEQUENCER_70] = 0xf,
272 [WM8915_WRITE_SEQUENCER_71] = 0x6,
273 [WM8915_WRITE_SEQUENCER_72] = 0x1,
274 [WM8915_WRITE_SEQUENCER_73] = 0x3,
275 [WM8915_WRITE_SEQUENCER_74] = 0x104,
276 [WM8915_WRITE_SEQUENCER_76] = 0x60,
277 [WM8915_WRITE_SEQUENCER_77] = 0x11,
278 [WM8915_WRITE_SEQUENCER_78] = 0x401,
279 [WM8915_WRITE_SEQUENCER_80] = 0x50,
280 [WM8915_WRITE_SEQUENCER_81] = 0x3,
281 [WM8915_WRITE_SEQUENCER_82] = 0x100,
282 [WM8915_WRITE_SEQUENCER_84] = 0x60,
283 [WM8915_WRITE_SEQUENCER_85] = 0x3b,
284 [WM8915_WRITE_SEQUENCER_86] = 0x502,
285 [WM8915_WRITE_SEQUENCER_87] = 0x100,
286 [WM8915_WRITE_SEQUENCER_88] = 0x2fff,
287 [WM8915_WRITE_SEQUENCER_92] = 0x2fff,
288 [WM8915_WRITE_SEQUENCER_96] = 0x2fff,
289 [WM8915_WRITE_SEQUENCER_100] = 0x2fff,
290 [WM8915_WRITE_SEQUENCER_104] = 0x2fff,
291 [WM8915_WRITE_SEQUENCER_108] = 0x2fff,
292 [WM8915_WRITE_SEQUENCER_112] = 0x2fff,
293 [WM8915_WRITE_SEQUENCER_116] = 0x2fff,
294 [WM8915_WRITE_SEQUENCER_120] = 0x2fff,
295 [WM8915_WRITE_SEQUENCER_124] = 0x2fff,
296 [WM8915_WRITE_SEQUENCER_128] = 0x1,
297 [WM8915_WRITE_SEQUENCER_129] = 0x1,
298 [WM8915_WRITE_SEQUENCER_131] = 0x6,
299 [WM8915_WRITE_SEQUENCER_132] = 0x40,
300 [WM8915_WRITE_SEQUENCER_133] = 0x1,
301 [WM8915_WRITE_SEQUENCER_134] = 0xf,
302 [WM8915_WRITE_SEQUENCER_135] = 0x6,
303 [WM8915_WRITE_SEQUENCER_136] = 0x1,
304 [WM8915_WRITE_SEQUENCER_137] = 0x3,
305 [WM8915_WRITE_SEQUENCER_138] = 0x106,
306 [WM8915_WRITE_SEQUENCER_140] = 0x61,
307 [WM8915_WRITE_SEQUENCER_141] = 0x11,
308 [WM8915_WRITE_SEQUENCER_142] = 0x401,
309 [WM8915_WRITE_SEQUENCER_144] = 0x50,
310 [WM8915_WRITE_SEQUENCER_145] = 0x3,
311 [WM8915_WRITE_SEQUENCER_146] = 0x102,
312 [WM8915_WRITE_SEQUENCER_148] = 0x51,
313 [WM8915_WRITE_SEQUENCER_149] = 0x3,
314 [WM8915_WRITE_SEQUENCER_150] = 0x106,
315 [WM8915_WRITE_SEQUENCER_151] = 0xa,
316 [WM8915_WRITE_SEQUENCER_152] = 0x61,
317 [WM8915_WRITE_SEQUENCER_153] = 0x3b,
318 [WM8915_WRITE_SEQUENCER_154] = 0x502,
319 [WM8915_WRITE_SEQUENCER_155] = 0x100,
320 [WM8915_WRITE_SEQUENCER_156] = 0x2fff,
321 [WM8915_WRITE_SEQUENCER_160] = 0x2fff,
322 [WM8915_WRITE_SEQUENCER_164] = 0x2fff,
323 [WM8915_WRITE_SEQUENCER_168] = 0x2fff,
324 [WM8915_WRITE_SEQUENCER_172] = 0x2fff,
325 [WM8915_WRITE_SEQUENCER_176] = 0x2fff,
326 [WM8915_WRITE_SEQUENCER_180] = 0x2fff,
327 [WM8915_WRITE_SEQUENCER_184] = 0x2fff,
328 [WM8915_WRITE_SEQUENCER_188] = 0x2fff,
329 [WM8915_WRITE_SEQUENCER_192] = 0x1,
330 [WM8915_WRITE_SEQUENCER_193] = 0x1,
331 [WM8915_WRITE_SEQUENCER_195] = 0x6,
332 [WM8915_WRITE_SEQUENCER_196] = 0x40,
333 [WM8915_WRITE_SEQUENCER_197] = 0x1,
334 [WM8915_WRITE_SEQUENCER_198] = 0xf,
335 [WM8915_WRITE_SEQUENCER_199] = 0x6,
336 [WM8915_WRITE_SEQUENCER_200] = 0x1,
337 [WM8915_WRITE_SEQUENCER_201] = 0x3,
338 [WM8915_WRITE_SEQUENCER_202] = 0x106,
339 [WM8915_WRITE_SEQUENCER_204] = 0x61,
340 [WM8915_WRITE_SEQUENCER_205] = 0x11,
341 [WM8915_WRITE_SEQUENCER_206] = 0x401,
342 [WM8915_WRITE_SEQUENCER_208] = 0x50,
343 [WM8915_WRITE_SEQUENCER_209] = 0x3,
344 [WM8915_WRITE_SEQUENCER_210] = 0x102,
345 [WM8915_WRITE_SEQUENCER_212] = 0x61,
346 [WM8915_WRITE_SEQUENCER_213] = 0x3b,
347 [WM8915_WRITE_SEQUENCER_214] = 0x502,
348 [WM8915_WRITE_SEQUENCER_215] = 0x100,
349 [WM8915_WRITE_SEQUENCER_216] = 0x2fff,
350 [WM8915_WRITE_SEQUENCER_220] = 0x2fff,
351 [WM8915_WRITE_SEQUENCER_224] = 0x2fff,
352 [WM8915_WRITE_SEQUENCER_228] = 0x2fff,
353 [WM8915_WRITE_SEQUENCER_232] = 0x2fff,
354 [WM8915_WRITE_SEQUENCER_236] = 0x2fff,
355 [WM8915_WRITE_SEQUENCER_240] = 0x2fff,
356 [WM8915_WRITE_SEQUENCER_244] = 0x2fff,
357 [WM8915_WRITE_SEQUENCER_248] = 0x2fff,
358 [WM8915_WRITE_SEQUENCER_252] = 0x2fff,
359 [WM8915_WRITE_SEQUENCER_256] = 0x60,
360 [WM8915_WRITE_SEQUENCER_258] = 0x601,
361 [WM8915_WRITE_SEQUENCER_260] = 0x50,
362 [WM8915_WRITE_SEQUENCER_262] = 0x100,
363 [WM8915_WRITE_SEQUENCER_264] = 0x1,
364 [WM8915_WRITE_SEQUENCER_266] = 0x104,
365 [WM8915_WRITE_SEQUENCER_267] = 0x100,
366 [WM8915_WRITE_SEQUENCER_268] = 0x2fff,
367 [WM8915_WRITE_SEQUENCER_272] = 0x2fff,
368 [WM8915_WRITE_SEQUENCER_276] = 0x2fff,
369 [WM8915_WRITE_SEQUENCER_280] = 0x2fff,
370 [WM8915_WRITE_SEQUENCER_284] = 0x2fff,
371 [WM8915_WRITE_SEQUENCER_288] = 0x2fff,
372 [WM8915_WRITE_SEQUENCER_292] = 0x2fff,
373 [WM8915_WRITE_SEQUENCER_296] = 0x2fff,
374 [WM8915_WRITE_SEQUENCER_300] = 0x2fff,
375 [WM8915_WRITE_SEQUENCER_304] = 0x2fff,
376 [WM8915_WRITE_SEQUENCER_308] = 0x2fff,
377 [WM8915_WRITE_SEQUENCER_312] = 0x2fff,
378 [WM8915_WRITE_SEQUENCER_316] = 0x2fff,
379 [WM8915_WRITE_SEQUENCER_320] = 0x61,
380 [WM8915_WRITE_SEQUENCER_322] = 0x601,
381 [WM8915_WRITE_SEQUENCER_324] = 0x50,
382 [WM8915_WRITE_SEQUENCER_326] = 0x102,
383 [WM8915_WRITE_SEQUENCER_328] = 0x1,
384 [WM8915_WRITE_SEQUENCER_330] = 0x106,
385 [WM8915_WRITE_SEQUENCER_331] = 0x100,
386 [WM8915_WRITE_SEQUENCER_332] = 0x2fff,
387 [WM8915_WRITE_SEQUENCER_336] = 0x2fff,
388 [WM8915_WRITE_SEQUENCER_340] = 0x2fff,
389 [WM8915_WRITE_SEQUENCER_344] = 0x2fff,
390 [WM8915_WRITE_SEQUENCER_348] = 0x2fff,
391 [WM8915_WRITE_SEQUENCER_352] = 0x2fff,
392 [WM8915_WRITE_SEQUENCER_356] = 0x2fff,
393 [WM8915_WRITE_SEQUENCER_360] = 0x2fff,
394 [WM8915_WRITE_SEQUENCER_364] = 0x2fff,
395 [WM8915_WRITE_SEQUENCER_368] = 0x2fff,
396 [WM8915_WRITE_SEQUENCER_372] = 0x2fff,
397 [WM8915_WRITE_SEQUENCER_376] = 0x2fff,
398 [WM8915_WRITE_SEQUENCER_380] = 0x2fff,
399 [WM8915_WRITE_SEQUENCER_384] = 0x60,
400 [WM8915_WRITE_SEQUENCER_386] = 0x601,
401 [WM8915_WRITE_SEQUENCER_388] = 0x61,
402 [WM8915_WRITE_SEQUENCER_390] = 0x601,
403 [WM8915_WRITE_SEQUENCER_392] = 0x50,
404 [WM8915_WRITE_SEQUENCER_394] = 0x300,
405 [WM8915_WRITE_SEQUENCER_396] = 0x1,
406 [WM8915_WRITE_SEQUENCER_398] = 0x304,
407 [WM8915_WRITE_SEQUENCER_400] = 0x40,
408 [WM8915_WRITE_SEQUENCER_402] = 0xf,
409 [WM8915_WRITE_SEQUENCER_404] = 0x1,
410 [WM8915_WRITE_SEQUENCER_407] = 0x100,
411};
412
413static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
414static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
415static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
416static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
417static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
418static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
419static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
420
421static const char *sidetone_hpf_text[] = {
422 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
423};
424
425static const struct soc_enum sidetone_hpf =
426 SOC_ENUM_SINGLE(WM8915_SIDETONE, 7, 6, sidetone_hpf_text);
427
428static const char *hpf_mode_text[] = {
429 "HiFi", "Custom", "Voice"
430};
431
432static const struct soc_enum dsp1tx_hpf_mode =
433 SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
434
435static const struct soc_enum dsp2tx_hpf_mode =
436 SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
437
438static const char *hpf_cutoff_text[] = {
439 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
440};
441
442static const struct soc_enum dsp1tx_hpf_cutoff =
443 SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
444
445static const struct soc_enum dsp2tx_hpf_cutoff =
446 SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
447
448static void wm8915_set_retune_mobile(struct snd_soc_codec *codec, int block)
449{
450 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
451 struct wm8915_pdata *pdata = &wm8915->pdata;
452 int base, best, best_val, save, i, cfg, iface;
453
454 if (!wm8915->num_retune_mobile_texts)
455 return;
456
457 switch (block) {
458 case 0:
459 base = WM8915_DSP1_RX_EQ_GAINS_1;
460 if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
461 WM8915_DSP1RX_SRC)
462 iface = 1;
463 else
464 iface = 0;
465 break;
466 case 1:
467 base = WM8915_DSP1_RX_EQ_GAINS_2;
468 if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
469 WM8915_DSP2RX_SRC)
470 iface = 1;
471 else
472 iface = 0;
473 break;
474 default:
475 return;
476 }
477
478 /* Find the version of the currently selected configuration
479 * with the nearest sample rate. */
480 cfg = wm8915->retune_mobile_cfg[block];
481 best = 0;
482 best_val = INT_MAX;
483 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
484 if (strcmp(pdata->retune_mobile_cfgs[i].name,
485 wm8915->retune_mobile_texts[cfg]) == 0 &&
486 abs(pdata->retune_mobile_cfgs[i].rate
487 - wm8915->rx_rate[iface]) < best_val) {
488 best = i;
489 best_val = abs(pdata->retune_mobile_cfgs[i].rate
490 - wm8915->rx_rate[iface]);
491 }
492 }
493
494 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
495 block,
496 pdata->retune_mobile_cfgs[best].name,
497 pdata->retune_mobile_cfgs[best].rate,
498 wm8915->rx_rate[iface]);
499
500 /* The EQ will be disabled while reconfiguring it, remember the
501 * current configuration.
502 */
503 save = snd_soc_read(codec, base);
504 save &= WM8915_DSP1RX_EQ_ENA;
505
506 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
507 snd_soc_update_bits(codec, base + i, 0xffff,
508 pdata->retune_mobile_cfgs[best].regs[i]);
509
510 snd_soc_update_bits(codec, base, WM8915_DSP1RX_EQ_ENA, save);
511}
512
513/* Icky as hell but saves code duplication */
514static int wm8915_get_retune_mobile_block(const char *name)
515{
516 if (strcmp(name, "DSP1 EQ Mode") == 0)
517 return 0;
518 if (strcmp(name, "DSP2 EQ Mode") == 0)
519 return 1;
520 return -EINVAL;
521}
522
523static int wm8915_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
524 struct snd_ctl_elem_value *ucontrol)
525{
526 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
527 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
528 struct wm8915_pdata *pdata = &wm8915->pdata;
529 int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
530 int value = ucontrol->value.integer.value[0];
531
532 if (block < 0)
533 return block;
534
535 if (value >= pdata->num_retune_mobile_cfgs)
536 return -EINVAL;
537
538 wm8915->retune_mobile_cfg[block] = value;
539
540 wm8915_set_retune_mobile(codec, block);
541
542 return 0;
543}
544
545static int wm8915_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
546 struct snd_ctl_elem_value *ucontrol)
547{
548 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
549 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
550 int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
551
552 ucontrol->value.enumerated.item[0] = wm8915->retune_mobile_cfg[block];
553
554 return 0;
555}
556
557static const struct snd_kcontrol_new wm8915_snd_controls[] = {
558SOC_DOUBLE_R_TLV("Capture Volume", WM8915_LEFT_LINE_INPUT_VOLUME,
559 WM8915_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
560SOC_DOUBLE_R("Capture ZC Switch", WM8915_LEFT_LINE_INPUT_VOLUME,
561 WM8915_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
562
563SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8915_DAC1_MIXER_VOLUMES,
564 0, 5, 24, 0, sidetone_tlv),
565SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8915_DAC2_MIXER_VOLUMES,
566 0, 5, 24, 0, sidetone_tlv),
567SOC_SINGLE("Sidetone LPF Switch", WM8915_SIDETONE, 12, 1, 0),
568SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
569SOC_SINGLE("Sidetone HPF Switch", WM8915_SIDETONE, 6, 1, 0),
570
571SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8915_DSP1_TX_LEFT_VOLUME,
572 WM8915_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
573SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8915_DSP2_TX_LEFT_VOLUME,
574 WM8915_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
575
576SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8915_DSP1_TX_FILTERS,
577 13, 1, 0),
578SOC_DOUBLE("DSP1 Capture HPF Switch", WM8915_DSP1_TX_FILTERS, 12, 11, 1, 0),
579SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
580SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
581
582SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8915_DSP2_TX_FILTERS,
583 13, 1, 0),
584SOC_DOUBLE("DSP2 Capture HPF Switch", WM8915_DSP2_TX_FILTERS, 12, 11, 1, 0),
585SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
586SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
587
588SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8915_DSP1_RX_LEFT_VOLUME,
589 WM8915_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
590SOC_SINGLE("DSP1 Playback Switch", WM8915_DSP1_RX_FILTERS_1, 9, 1, 1),
591
592SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8915_DSP2_RX_LEFT_VOLUME,
593 WM8915_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
594SOC_SINGLE("DSP2 Playback Switch", WM8915_DSP2_RX_FILTERS_1, 9, 1, 1),
595
596SOC_DOUBLE_R_TLV("DAC1 Volume", WM8915_DAC1_LEFT_VOLUME,
597 WM8915_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
598SOC_DOUBLE_R("DAC1 Switch", WM8915_DAC1_LEFT_VOLUME,
599 WM8915_DAC1_RIGHT_VOLUME, 9, 1, 1),
600
601SOC_DOUBLE_R_TLV("DAC2 Volume", WM8915_DAC2_LEFT_VOLUME,
602 WM8915_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
603SOC_DOUBLE_R("DAC2 Switch", WM8915_DAC2_LEFT_VOLUME,
604 WM8915_DAC2_RIGHT_VOLUME, 9, 1, 1),
605
606SOC_SINGLE("Speaker High Performance Switch", WM8915_OVERSAMPLING, 3, 1, 0),
607SOC_SINGLE("DMIC High Performance Switch", WM8915_OVERSAMPLING, 2, 1, 0),
608SOC_SINGLE("ADC High Performance Switch", WM8915_OVERSAMPLING, 1, 1, 0),
609SOC_SINGLE("DAC High Performance Switch", WM8915_OVERSAMPLING, 0, 1, 0),
610
611SOC_SINGLE("DAC Soft Mute Switch", WM8915_DAC_SOFTMUTE, 1, 1, 0),
612SOC_SINGLE("DAC Slow Soft Mute Switch", WM8915_DAC_SOFTMUTE, 0, 1, 0),
613
614SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8915_DAC1_HPOUT1_VOLUME, 0, 4,
615 8, 0, out_digital_tlv),
616SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8915_DAC2_HPOUT2_VOLUME, 0, 4,
617 8, 0, out_digital_tlv),
618
619SOC_DOUBLE_R_TLV("Output 1 Volume", WM8915_OUTPUT1_LEFT_VOLUME,
620 WM8915_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
621SOC_DOUBLE_R("Output 1 ZC Switch", WM8915_OUTPUT1_LEFT_VOLUME,
622 WM8915_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
623
624SOC_DOUBLE_R_TLV("Output 2 Volume", WM8915_OUTPUT2_LEFT_VOLUME,
625 WM8915_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
626SOC_DOUBLE_R("Output 2 ZC Switch", WM8915_OUTPUT2_LEFT_VOLUME,
627 WM8915_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
628
629SOC_DOUBLE_TLV("Speaker Volume", WM8915_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
630 spk_tlv),
631SOC_DOUBLE_R("Speaker Switch", WM8915_LEFT_PDM_SPEAKER,
632 WM8915_RIGHT_PDM_SPEAKER, 3, 1, 1),
633SOC_DOUBLE_R("Speaker ZC Switch", WM8915_LEFT_PDM_SPEAKER,
634 WM8915_RIGHT_PDM_SPEAKER, 2, 1, 0),
635
636SOC_SINGLE("DSP1 EQ Switch", WM8915_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
637SOC_SINGLE("DSP2 EQ Switch", WM8915_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
638};
639
640static const struct snd_kcontrol_new wm8915_eq_controls[] = {
641SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
642 eq_tlv),
643SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
644 eq_tlv),
645SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
646 eq_tlv),
647SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
648 eq_tlv),
649SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
650 eq_tlv),
651
652SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
653 eq_tlv),
654SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
655 eq_tlv),
656SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
657 eq_tlv),
658SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
659 eq_tlv),
660SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
661 eq_tlv),
662};
663
664static int cp_event(struct snd_soc_dapm_widget *w,
665 struct snd_kcontrol *kcontrol, int event)
666{
667 switch (event) {
668 case SND_SOC_DAPM_POST_PMU:
669 msleep(5);
670 break;
671 default:
672 BUG();
673 return -EINVAL;
674 }
675
676 return 0;
677}
678
679static int rmv_short_event(struct snd_soc_dapm_widget *w,
680 struct snd_kcontrol *kcontrol, int event)
681{
682 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
683
684 /* Record which outputs we enabled */
685 switch (event) {
686 case SND_SOC_DAPM_PRE_PMD:
687 wm8915->hpout_pending &= ~w->shift;
688 break;
689 case SND_SOC_DAPM_PRE_PMU:
690 wm8915->hpout_pending |= w->shift;
691 break;
692 default:
693 BUG();
694 return -EINVAL;
695 }
696
697 return 0;
698}
699
700static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
701{
702 struct i2c_client *i2c = to_i2c_client(codec->dev);
703 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
704 int i, ret;
705 unsigned long timeout = 200;
706
707 snd_soc_write(codec, WM8915_DC_SERVO_2, mask);
708
709 /* Use the interrupt if possible */
710 do {
711 if (i2c->irq) {
712 timeout = wait_for_completion_timeout(&wm8915->dcs_done,
713 msecs_to_jiffies(200));
714 if (timeout == 0)
715 dev_err(codec->dev, "DC servo timed out\n");
716
717 } else {
718 msleep(1);
719 if (--i) {
720 timeout = 0;
721 break;
722 }
723 }
724
725 ret = snd_soc_read(codec, WM8915_DC_SERVO_2);
726 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
727 } while (ret & mask);
728
729 if (timeout == 0)
730 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
731 else
732 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
733}
734
735static void wm8915_seq_notifier(struct snd_soc_dapm_context *dapm,
736 enum snd_soc_dapm_type event, int subseq)
737{
738 struct snd_soc_codec *codec = container_of(dapm,
739 struct snd_soc_codec, dapm);
740 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
741 u16 val, mask;
742
743 /* Complete any pending DC servo starts */
744 if (wm8915->dcs_pending) {
745 dev_dbg(codec->dev, "Starting DC servo for %x\n",
746 wm8915->dcs_pending);
747
748 /* Trigger a startup sequence */
749 wait_for_dc_servo(codec, wm8915->dcs_pending
750 << WM8915_DCS_TRIG_STARTUP_0_SHIFT);
751
752 wm8915->dcs_pending = 0;
753 }
754
755 if (wm8915->hpout_pending != wm8915->hpout_ena) {
756 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
757 wm8915->hpout_ena, wm8915->hpout_pending);
758
759 val = 0;
760 mask = 0;
761 if (wm8915->hpout_pending & HPOUT1L) {
762 val |= WM8915_HPOUT1L_RMV_SHORT;
763 mask |= WM8915_HPOUT1L_RMV_SHORT;
764 } else {
765 mask |= WM8915_HPOUT1L_RMV_SHORT |
766 WM8915_HPOUT1L_OUTP |
767 WM8915_HPOUT1L_DLY;
768 }
769
770 if (wm8915->hpout_pending & HPOUT1R) {
771 val |= WM8915_HPOUT1R_RMV_SHORT;
772 mask |= WM8915_HPOUT1R_RMV_SHORT;
773 } else {
774 mask |= WM8915_HPOUT1R_RMV_SHORT |
775 WM8915_HPOUT1R_OUTP |
776 WM8915_HPOUT1R_DLY;
777 }
778
779 snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_1, mask, val);
780
781 val = 0;
782 mask = 0;
783 if (wm8915->hpout_pending & HPOUT2L) {
784 val |= WM8915_HPOUT2L_RMV_SHORT;
785 mask |= WM8915_HPOUT2L_RMV_SHORT;
786 } else {
787 mask |= WM8915_HPOUT2L_RMV_SHORT |
788 WM8915_HPOUT2L_OUTP |
789 WM8915_HPOUT2L_DLY;
790 }
791
792 if (wm8915->hpout_pending & HPOUT2R) {
793 val |= WM8915_HPOUT2R_RMV_SHORT;
794 mask |= WM8915_HPOUT2R_RMV_SHORT;
795 } else {
796 mask |= WM8915_HPOUT2R_RMV_SHORT |
797 WM8915_HPOUT2R_OUTP |
798 WM8915_HPOUT2R_DLY;
799 }
800
801 snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_2, mask, val);
802
803 wm8915->hpout_ena = wm8915->hpout_pending;
804 }
805}
806
807static int dcs_start(struct snd_soc_dapm_widget *w,
808 struct snd_kcontrol *kcontrol, int event)
809{
810 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
811
812 switch (event) {
813 case SND_SOC_DAPM_POST_PMU:
814 wm8915->dcs_pending |= 1 << w->shift;
815 break;
816 default:
817 BUG();
818 return -EINVAL;
819 }
820
821 return 0;
822}
823
824static const char *sidetone_text[] = {
825 "IN1", "IN2",
826};
827
828static const struct soc_enum left_sidetone_enum =
829 SOC_ENUM_SINGLE(WM8915_SIDETONE, 0, 2, sidetone_text);
830
831static const struct snd_kcontrol_new left_sidetone =
832 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
833
834static const struct soc_enum right_sidetone_enum =
835 SOC_ENUM_SINGLE(WM8915_SIDETONE, 1, 2, sidetone_text);
836
837static const struct snd_kcontrol_new right_sidetone =
838 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
839
840static const char *spk_text[] = {
841 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
842};
843
844static const struct soc_enum spkl_enum =
845 SOC_ENUM_SINGLE(WM8915_LEFT_PDM_SPEAKER, 0, 4, spk_text);
846
847static const struct snd_kcontrol_new spkl_mux =
848 SOC_DAPM_ENUM("SPKL", spkl_enum);
849
850static const struct soc_enum spkr_enum =
851 SOC_ENUM_SINGLE(WM8915_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
852
853static const struct snd_kcontrol_new spkr_mux =
854 SOC_DAPM_ENUM("SPKR", spkr_enum);
855
856static const char *dsp1rx_text[] = {
857 "AIF1", "AIF2"
858};
859
860static const struct soc_enum dsp1rx_enum =
861 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
862
863static const struct snd_kcontrol_new dsp1rx =
864 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
865
866static const char *dsp2rx_text[] = {
867 "AIF2", "AIF1"
868};
869
870static const struct soc_enum dsp2rx_enum =
871 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
872
873static const struct snd_kcontrol_new dsp2rx =
874 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
875
876static const char *aif2tx_text[] = {
877 "DSP2", "DSP1", "AIF1"
878};
879
880static const struct soc_enum aif2tx_enum =
881 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
882
883static const struct snd_kcontrol_new aif2tx =
884 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
885
886static const char *inmux_text[] = {
887 "ADC", "DMIC1", "DMIC2"
888};
889
890static const struct soc_enum in1_enum =
891 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 0, 3, inmux_text);
892
893static const struct snd_kcontrol_new in1_mux =
894 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
895
896static const struct soc_enum in2_enum =
897 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 4, 3, inmux_text);
898
899static const struct snd_kcontrol_new in2_mux =
900 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
901
902static const struct snd_kcontrol_new dac2r_mix[] = {
903SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
904 5, 1, 0),
905SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
906 4, 1, 0),
907SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
908SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
909};
910
911static const struct snd_kcontrol_new dac2l_mix[] = {
912SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
913 5, 1, 0),
914SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
915 4, 1, 0),
916SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
917SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
918};
919
920static const struct snd_kcontrol_new dac1r_mix[] = {
921SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
922 5, 1, 0),
923SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
924 4, 1, 0),
925SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
926SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
927};
928
929static const struct snd_kcontrol_new dac1l_mix[] = {
930SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
931 5, 1, 0),
932SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
933 4, 1, 0),
934SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
935SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
936};
937
938static const struct snd_kcontrol_new dsp1txl[] = {
939SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
940 1, 1, 0),
941SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
942 0, 1, 0),
943};
944
945static const struct snd_kcontrol_new dsp1txr[] = {
946SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
947 1, 1, 0),
948SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
949 0, 1, 0),
950};
951
952static const struct snd_kcontrol_new dsp2txl[] = {
953SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
954 1, 1, 0),
955SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
956 0, 1, 0),
957};
958
959static const struct snd_kcontrol_new dsp2txr[] = {
960SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
961 1, 1, 0),
962SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
963 0, 1, 0),
964};
965
966
967static const struct snd_soc_dapm_widget wm8915_dapm_widgets[] = {
968SND_SOC_DAPM_INPUT("IN1LN"),
969SND_SOC_DAPM_INPUT("IN1LP"),
970SND_SOC_DAPM_INPUT("IN1RN"),
971SND_SOC_DAPM_INPUT("IN1RP"),
972
973SND_SOC_DAPM_INPUT("IN2LN"),
974SND_SOC_DAPM_INPUT("IN2LP"),
975SND_SOC_DAPM_INPUT("IN2RN"),
976SND_SOC_DAPM_INPUT("IN2RP"),
977
978SND_SOC_DAPM_INPUT("DMIC1DAT"),
979SND_SOC_DAPM_INPUT("DMIC2DAT"),
980
981SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8915_AIF_CLOCKING_1, 0, 0, NULL, 0),
982SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8915_CLOCKING_1, 1, 0, NULL, 0),
983SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8915_CLOCKING_1, 2, 0, NULL, 0),
984SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8915_CHARGE_PUMP_1, 15, 0, cp_event,
985 SND_SOC_DAPM_POST_PMU),
986
987SND_SOC_DAPM_SUPPLY("LDO2", WM8915_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
988SND_SOC_DAPM_MICBIAS("MICB2", WM8915_POWER_MANAGEMENT_1, 9, 0),
989SND_SOC_DAPM_MICBIAS("MICB1", WM8915_POWER_MANAGEMENT_1, 8, 0),
990
991SND_SOC_DAPM_PGA("IN1L PGA", WM8915_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
992SND_SOC_DAPM_PGA("IN1R PGA", WM8915_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
993
994SND_SOC_DAPM_PGA("ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
995
996SND_SOC_DAPM_MUX("IN1 Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
997SND_SOC_DAPM_MUX("IN2 Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
998
999SND_SOC_DAPM_PGA("IN1L", WM8915_POWER_MANAGEMENT_7, 2, 0, NULL, 0),
1000SND_SOC_DAPM_PGA("IN1R", WM8915_POWER_MANAGEMENT_7, 3, 0, NULL, 0),
1001SND_SOC_DAPM_PGA("IN2L", WM8915_POWER_MANAGEMENT_7, 6, 0, NULL, 0),
1002SND_SOC_DAPM_PGA("IN2R", WM8915_POWER_MANAGEMENT_7, 7, 0, NULL, 0),
1003
1004/* FIXME - these need to be concentrator widgets */
1005SND_SOC_DAPM_SUPPLY("DMIC2", WM8915_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1006SND_SOC_DAPM_SUPPLY("DMIC1", WM8915_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1007
1008SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8915_POWER_MANAGEMENT_3, 5, 0),
1009SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8915_POWER_MANAGEMENT_3, 4, 0),
1010SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8915_POWER_MANAGEMENT_3, 3, 0),
1011SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8915_POWER_MANAGEMENT_3, 2, 0),
1012
1013SND_SOC_DAPM_ADC("ADCL", NULL, WM8915_POWER_MANAGEMENT_3, 1, 0),
1014SND_SOC_DAPM_ADC("ADCR", NULL, WM8915_POWER_MANAGEMENT_3, 0, 0),
1015
1016SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1017SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1018
1019SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 11, 0),
1020SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 10, 0),
1021SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 9, 0),
1022SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 8, 0),
1023
1024SND_SOC_DAPM_MIXER("DSP2TXL", WM8915_POWER_MANAGEMENT_5, 11, 0,
1025 dsp2txl, ARRAY_SIZE(dsp2txl)),
1026SND_SOC_DAPM_MIXER("DSP2TXR", WM8915_POWER_MANAGEMENT_5, 10, 0,
1027 dsp2txr, ARRAY_SIZE(dsp2txr)),
1028SND_SOC_DAPM_MIXER("DSP1TXL", WM8915_POWER_MANAGEMENT_5, 9, 0,
1029 dsp1txl, ARRAY_SIZE(dsp1txl)),
1030SND_SOC_DAPM_MIXER("DSP1TXR", WM8915_POWER_MANAGEMENT_5, 8, 0,
1031 dsp1txr, ARRAY_SIZE(dsp1txr)),
1032
1033SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1034 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1035SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1036 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1037SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1038 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1039SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1040 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1041
1042SND_SOC_DAPM_DAC("DAC2L", NULL, WM8915_POWER_MANAGEMENT_5, 3, 0),
1043SND_SOC_DAPM_DAC("DAC2R", NULL, WM8915_POWER_MANAGEMENT_5, 2, 0),
1044SND_SOC_DAPM_DAC("DAC1L", NULL, WM8915_POWER_MANAGEMENT_5, 1, 0),
1045SND_SOC_DAPM_DAC("DAC1R", NULL, WM8915_POWER_MANAGEMENT_5, 0, 0),
1046
1047SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1,
1048 WM8915_POWER_MANAGEMENT_4, 9, 0),
1049SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2,
1050 WM8915_POWER_MANAGEMENT_4, 8, 0),
1051
1052SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1,
1053 WM8915_POWER_MANAGEMENT_6, 9, 0),
1054SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2,
1055 WM8915_POWER_MANAGEMENT_6, 8, 0),
1056
1057SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1058 WM8915_POWER_MANAGEMENT_4, 5, 0),
1059SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1060 WM8915_POWER_MANAGEMENT_4, 4, 0),
1061SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1062 WM8915_POWER_MANAGEMENT_4, 3, 0),
1063SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1064 WM8915_POWER_MANAGEMENT_4, 2, 0),
1065SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1066 WM8915_POWER_MANAGEMENT_4, 1, 0),
1067SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1068 WM8915_POWER_MANAGEMENT_4, 0, 0),
1069
1070SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1071 WM8915_POWER_MANAGEMENT_6, 5, 0),
1072SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1073 WM8915_POWER_MANAGEMENT_6, 4, 0),
1074SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1075 WM8915_POWER_MANAGEMENT_6, 3, 0),
1076SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1077 WM8915_POWER_MANAGEMENT_6, 2, 0),
1078SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1079 WM8915_POWER_MANAGEMENT_6, 1, 0),
1080SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1081 WM8915_POWER_MANAGEMENT_6, 0, 0),
1082
1083/* We route as stereo pairs so define some dummy widgets to squash
1084 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1085SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1086SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1087SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1088SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1089SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1090
1091SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1092SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1093SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1094
1095SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1096SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1097SND_SOC_DAPM_PGA("SPKL PGA", WM8915_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1098SND_SOC_DAPM_PGA("SPKR PGA", WM8915_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1099
1100SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8915_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1101SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8915_ANALOGUE_HP_2, 5, 0, NULL, 0),
1102SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8915_DC_SERVO_1, 2, 0, dcs_start,
1103 SND_SOC_DAPM_POST_PMU),
1104SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8915_ANALOGUE_HP_2, 6, 0, NULL, 0),
1105SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1106 rmv_short_event,
1107 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1108
1109SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8915_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1110SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8915_ANALOGUE_HP_2, 1, 0, NULL, 0),
1111SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8915_DC_SERVO_1, 3, 0, dcs_start,
1112 SND_SOC_DAPM_POST_PMU),
1113SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8915_ANALOGUE_HP_2, 2, 0, NULL, 0),
1114SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1115 rmv_short_event,
1116 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1117
1118SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8915_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1119SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8915_ANALOGUE_HP_1, 5, 0, NULL, 0),
1120SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8915_DC_SERVO_1, 0, 0, dcs_start,
1121 SND_SOC_DAPM_POST_PMU),
1122SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8915_ANALOGUE_HP_1, 6, 0, NULL, 0),
1123SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1124 rmv_short_event,
1125 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1126
1127SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8915_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1128SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8915_ANALOGUE_HP_1, 1, 0, NULL, 0),
1129SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8915_DC_SERVO_1, 1, 0, dcs_start,
1130 SND_SOC_DAPM_POST_PMU),
1131SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8915_ANALOGUE_HP_1, 2, 0, NULL, 0),
1132SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1133 rmv_short_event,
1134 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1135
1136SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1137SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1138SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1139SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1140SND_SOC_DAPM_OUTPUT("SPKDAT"),
1141};
1142
1143static const struct snd_soc_dapm_route wm8915_dapm_routes[] = {
1144 { "AIFCLK", NULL, "SYSCLK" },
1145 { "SYSDSPCLK", NULL, "SYSCLK" },
1146 { "Charge Pump", NULL, "SYSCLK" },
1147
1148 { "MICB1", NULL, "LDO2" },
1149 { "MICB2", NULL, "LDO2" },
1150
1151 { "IN1L PGA", NULL, "IN2LN" },
1152 { "IN1L PGA", NULL, "IN2LP" },
1153 { "IN1L PGA", NULL, "IN1LN" },
1154 { "IN1L PGA", NULL, "IN1LP" },
1155
1156 { "IN1R PGA", NULL, "IN2RN" },
1157 { "IN1R PGA", NULL, "IN2RP" },
1158 { "IN1R PGA", NULL, "IN1RN" },
1159 { "IN1R PGA", NULL, "IN1RP" },
1160
1161 { "ADCL", NULL, "IN1L PGA" },
1162
1163 { "ADCR", NULL, "IN1R PGA" },
1164
1165 { "DMIC1L", NULL, "DMIC1DAT" },
1166 { "DMIC1R", NULL, "DMIC1DAT" },
1167 { "DMIC2L", NULL, "DMIC2DAT" },
1168 { "DMIC2R", NULL, "DMIC2DAT" },
1169
1170 { "DMIC2L", NULL, "DMIC2" },
1171 { "DMIC2R", NULL, "DMIC2" },
1172 { "DMIC1L", NULL, "DMIC1" },
1173 { "DMIC1R", NULL, "DMIC1" },
1174
1175 { "ADC", NULL, "ADCL" },
1176 { "ADC", NULL, "ADCR" },
1177
1178 { "IN1 Mux", "ADC", "ADC" },
1179 { "IN1 Mux", "DMIC1", "DMIC1" },
1180 { "IN1 Mux", "DMIC2", "DMIC2" },
1181
1182 { "IN2 Mux", "ADC", "ADC" },
1183 { "IN2 Mux", "DMIC1", "DMIC1" },
1184 { "IN2 Mux", "DMIC2", "DMIC2" },
1185
1186 { "Left Sidetone", "IN1", "IN1 Mux" },
1187 { "Left Sidetone", "IN2", "IN2 Mux" },
1188
1189 { "Right Sidetone", "IN1", "IN1 Mux" },
1190 { "Right Sidetone", "IN2", "IN2 Mux" },
1191
1192 { "DSP1TXL", "IN1 Switch", "IN1 Mux" },
1193 { "DSP1TXR", "IN1 Switch", "IN1 Mux" },
1194
1195 { "DSP2TXL", "IN1 Switch", "IN2 Mux" },
1196 { "DSP2TXR", "IN1 Switch", "IN2 Mux" },
1197
1198 { "AIF1TX0", NULL, "DSP1TXL" },
1199 { "AIF1TX1", NULL, "DSP1TXR" },
1200 { "AIF1TX2", NULL, "DSP2TXL" },
1201 { "AIF1TX3", NULL, "DSP2TXR" },
1202 { "AIF1TX4", NULL, "AIF2RX0" },
1203 { "AIF1TX5", NULL, "AIF2RX1" },
1204
1205 { "AIF1RX0", NULL, "AIFCLK" },
1206 { "AIF1RX1", NULL, "AIFCLK" },
1207 { "AIF1RX2", NULL, "AIFCLK" },
1208 { "AIF1RX3", NULL, "AIFCLK" },
1209 { "AIF1RX4", NULL, "AIFCLK" },
1210 { "AIF1RX5", NULL, "AIFCLK" },
1211
1212 { "AIF2RX0", NULL, "AIFCLK" },
1213 { "AIF2RX1", NULL, "AIFCLK" },
1214
1215 { "DSP1RXL", NULL, "SYSDSPCLK" },
1216 { "DSP1RXR", NULL, "SYSDSPCLK" },
1217 { "DSP2RXL", NULL, "SYSDSPCLK" },
1218 { "DSP2RXR", NULL, "SYSDSPCLK" },
1219 { "DSP1TXL", NULL, "SYSDSPCLK" },
1220 { "DSP1TXR", NULL, "SYSDSPCLK" },
1221 { "DSP2TXL", NULL, "SYSDSPCLK" },
1222 { "DSP2TXR", NULL, "SYSDSPCLK" },
1223
1224 { "AIF1RXA", NULL, "AIF1RX0" },
1225 { "AIF1RXA", NULL, "AIF1RX1" },
1226 { "AIF1RXB", NULL, "AIF1RX2" },
1227 { "AIF1RXB", NULL, "AIF1RX3" },
1228 { "AIF1RXC", NULL, "AIF1RX4" },
1229 { "AIF1RXC", NULL, "AIF1RX5" },
1230
1231 { "AIF2RX", NULL, "AIF2RX0" },
1232 { "AIF2RX", NULL, "AIF2RX1" },
1233
1234 { "AIF2TX", "DSP2", "DSP2TX" },
1235 { "AIF2TX", "DSP1", "DSP1RX" },
1236 { "AIF2TX", "AIF1", "AIF1RXC" },
1237
1238 { "DSP1RXL", NULL, "DSP1RX" },
1239 { "DSP1RXR", NULL, "DSP1RX" },
1240 { "DSP2RXL", NULL, "DSP2RX" },
1241 { "DSP2RXR", NULL, "DSP2RX" },
1242
1243 { "DSP2TX", NULL, "DSP2TXL" },
1244 { "DSP2TX", NULL, "DSP2TXR" },
1245
1246 { "DSP1RX", "AIF1", "AIF1RXA" },
1247 { "DSP1RX", "AIF2", "AIF2RX" },
1248
1249 { "DSP2RX", "AIF1", "AIF1RXB" },
1250 { "DSP2RX", "AIF2", "AIF2RX" },
1251
1252 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1253 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1254 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1255 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1256
1257 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1258 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1259 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1260 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1261
1262 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1263 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1264 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1265 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1266
1267 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1268 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1269 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1270 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1271
1272 { "DAC1L", NULL, "DAC1L Mixer" },
1273 { "DAC1R", NULL, "DAC1R Mixer" },
1274 { "DAC2L", NULL, "DAC2L Mixer" },
1275 { "DAC2R", NULL, "DAC2R Mixer" },
1276
1277 { "HPOUT2L PGA", NULL, "Charge Pump" },
1278 { "HPOUT2L PGA", NULL, "DAC2L" },
1279 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1280 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1281 { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1282 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1283
1284 { "HPOUT2R PGA", NULL, "Charge Pump" },
1285 { "HPOUT2R PGA", NULL, "DAC2R" },
1286 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1287 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1288 { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1289 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1290
1291 { "HPOUT1L PGA", NULL, "Charge Pump" },
1292 { "HPOUT1L PGA", NULL, "DAC1L" },
1293 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1294 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1295 { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1296 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1297
1298 { "HPOUT1R PGA", NULL, "Charge Pump" },
1299 { "HPOUT1R PGA", NULL, "DAC1R" },
1300 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1301 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1302 { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1303 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1304
1305 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1306 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1307 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1308 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1309
1310 { "SPKL", "DAC1L", "DAC1L" },
1311 { "SPKL", "DAC1R", "DAC1R" },
1312 { "SPKL", "DAC2L", "DAC2L" },
1313 { "SPKL", "DAC2R", "DAC2R" },
1314
1315 { "SPKR", "DAC1L", "DAC1L" },
1316 { "SPKR", "DAC1R", "DAC1R" },
1317 { "SPKR", "DAC2L", "DAC2L" },
1318 { "SPKR", "DAC2R", "DAC2R" },
1319
1320 { "SPKL PGA", NULL, "SPKL" },
1321 { "SPKR PGA", NULL, "SPKR" },
1322
1323 { "SPKDAT", NULL, "SPKL PGA" },
1324 { "SPKDAT", NULL, "SPKR PGA" },
1325};
1326
1327static int wm8915_readable_register(struct snd_soc_codec *codec,
1328 unsigned int reg)
1329{
1330 /* Due to the sparseness of the register map the compiler
1331 * output from an explicit switch statement ends up being much
1332 * more efficient than a table.
1333 */
1334 switch (reg) {
1335 case WM8915_SOFTWARE_RESET:
1336 case WM8915_POWER_MANAGEMENT_1:
1337 case WM8915_POWER_MANAGEMENT_2:
1338 case WM8915_POWER_MANAGEMENT_3:
1339 case WM8915_POWER_MANAGEMENT_4:
1340 case WM8915_POWER_MANAGEMENT_5:
1341 case WM8915_POWER_MANAGEMENT_6:
1342 case WM8915_POWER_MANAGEMENT_7:
1343 case WM8915_POWER_MANAGEMENT_8:
1344 case WM8915_LEFT_LINE_INPUT_VOLUME:
1345 case WM8915_RIGHT_LINE_INPUT_VOLUME:
1346 case WM8915_LINE_INPUT_CONTROL:
1347 case WM8915_DAC1_HPOUT1_VOLUME:
1348 case WM8915_DAC2_HPOUT2_VOLUME:
1349 case WM8915_DAC1_LEFT_VOLUME:
1350 case WM8915_DAC1_RIGHT_VOLUME:
1351 case WM8915_DAC2_LEFT_VOLUME:
1352 case WM8915_DAC2_RIGHT_VOLUME:
1353 case WM8915_OUTPUT1_LEFT_VOLUME:
1354 case WM8915_OUTPUT1_RIGHT_VOLUME:
1355 case WM8915_OUTPUT2_LEFT_VOLUME:
1356 case WM8915_OUTPUT2_RIGHT_VOLUME:
1357 case WM8915_MICBIAS_1:
1358 case WM8915_MICBIAS_2:
1359 case WM8915_LDO_1:
1360 case WM8915_LDO_2:
1361 case WM8915_ACCESSORY_DETECT_MODE_1:
1362 case WM8915_ACCESSORY_DETECT_MODE_2:
1363 case WM8915_HEADPHONE_DETECT_1:
1364 case WM8915_HEADPHONE_DETECT_2:
1365 case WM8915_MIC_DETECT_1:
1366 case WM8915_MIC_DETECT_2:
1367 case WM8915_MIC_DETECT_3:
1368 case WM8915_CHARGE_PUMP_1:
1369 case WM8915_CHARGE_PUMP_2:
1370 case WM8915_DC_SERVO_1:
1371 case WM8915_DC_SERVO_2:
1372 case WM8915_DC_SERVO_3:
1373 case WM8915_DC_SERVO_5:
1374 case WM8915_DC_SERVO_6:
1375 case WM8915_DC_SERVO_7:
1376 case WM8915_DC_SERVO_READBACK_0:
1377 case WM8915_ANALOGUE_HP_1:
1378 case WM8915_ANALOGUE_HP_2:
1379 case WM8915_CHIP_REVISION:
1380 case WM8915_CONTROL_INTERFACE_1:
1381 case WM8915_WRITE_SEQUENCER_CTRL_1:
1382 case WM8915_WRITE_SEQUENCER_CTRL_2:
1383 case WM8915_AIF_CLOCKING_1:
1384 case WM8915_AIF_CLOCKING_2:
1385 case WM8915_CLOCKING_1:
1386 case WM8915_CLOCKING_2:
1387 case WM8915_AIF_RATE:
1388 case WM8915_FLL_CONTROL_1:
1389 case WM8915_FLL_CONTROL_2:
1390 case WM8915_FLL_CONTROL_3:
1391 case WM8915_FLL_CONTROL_4:
1392 case WM8915_FLL_CONTROL_5:
1393 case WM8915_FLL_CONTROL_6:
1394 case WM8915_FLL_EFS_1:
1395 case WM8915_FLL_EFS_2:
1396 case WM8915_AIF1_CONTROL:
1397 case WM8915_AIF1_BCLK:
1398 case WM8915_AIF1_TX_LRCLK_1:
1399 case WM8915_AIF1_TX_LRCLK_2:
1400 case WM8915_AIF1_RX_LRCLK_1:
1401 case WM8915_AIF1_RX_LRCLK_2:
1402 case WM8915_AIF1TX_DATA_CONFIGURATION_1:
1403 case WM8915_AIF1TX_DATA_CONFIGURATION_2:
1404 case WM8915_AIF1RX_DATA_CONFIGURATION:
1405 case WM8915_AIF1TX_CHANNEL_0_CONFIGURATION:
1406 case WM8915_AIF1TX_CHANNEL_1_CONFIGURATION:
1407 case WM8915_AIF1TX_CHANNEL_2_CONFIGURATION:
1408 case WM8915_AIF1TX_CHANNEL_3_CONFIGURATION:
1409 case WM8915_AIF1TX_CHANNEL_4_CONFIGURATION:
1410 case WM8915_AIF1TX_CHANNEL_5_CONFIGURATION:
1411 case WM8915_AIF1RX_CHANNEL_0_CONFIGURATION:
1412 case WM8915_AIF1RX_CHANNEL_1_CONFIGURATION:
1413 case WM8915_AIF1RX_CHANNEL_2_CONFIGURATION:
1414 case WM8915_AIF1RX_CHANNEL_3_CONFIGURATION:
1415 case WM8915_AIF1RX_CHANNEL_4_CONFIGURATION:
1416 case WM8915_AIF1RX_CHANNEL_5_CONFIGURATION:
1417 case WM8915_AIF1RX_MONO_CONFIGURATION:
1418 case WM8915_AIF1TX_TEST:
1419 case WM8915_AIF2_CONTROL:
1420 case WM8915_AIF2_BCLK:
1421 case WM8915_AIF2_TX_LRCLK_1:
1422 case WM8915_AIF2_TX_LRCLK_2:
1423 case WM8915_AIF2_RX_LRCLK_1:
1424 case WM8915_AIF2_RX_LRCLK_2:
1425 case WM8915_AIF2TX_DATA_CONFIGURATION_1:
1426 case WM8915_AIF2TX_DATA_CONFIGURATION_2:
1427 case WM8915_AIF2RX_DATA_CONFIGURATION:
1428 case WM8915_AIF2TX_CHANNEL_0_CONFIGURATION:
1429 case WM8915_AIF2TX_CHANNEL_1_CONFIGURATION:
1430 case WM8915_AIF2RX_CHANNEL_0_CONFIGURATION:
1431 case WM8915_AIF2RX_CHANNEL_1_CONFIGURATION:
1432 case WM8915_AIF2RX_MONO_CONFIGURATION:
1433 case WM8915_AIF2TX_TEST:
1434 case WM8915_DSP1_TX_LEFT_VOLUME:
1435 case WM8915_DSP1_TX_RIGHT_VOLUME:
1436 case WM8915_DSP1_RX_LEFT_VOLUME:
1437 case WM8915_DSP1_RX_RIGHT_VOLUME:
1438 case WM8915_DSP1_TX_FILTERS:
1439 case WM8915_DSP1_RX_FILTERS_1:
1440 case WM8915_DSP1_RX_FILTERS_2:
1441 case WM8915_DSP1_DRC_1:
1442 case WM8915_DSP1_DRC_2:
1443 case WM8915_DSP1_DRC_3:
1444 case WM8915_DSP1_DRC_4:
1445 case WM8915_DSP1_DRC_5:
1446 case WM8915_DSP1_RX_EQ_GAINS_1:
1447 case WM8915_DSP1_RX_EQ_GAINS_2:
1448 case WM8915_DSP1_RX_EQ_BAND_1_A:
1449 case WM8915_DSP1_RX_EQ_BAND_1_B:
1450 case WM8915_DSP1_RX_EQ_BAND_1_PG:
1451 case WM8915_DSP1_RX_EQ_BAND_2_A:
1452 case WM8915_DSP1_RX_EQ_BAND_2_B:
1453 case WM8915_DSP1_RX_EQ_BAND_2_C:
1454 case WM8915_DSP1_RX_EQ_BAND_2_PG:
1455 case WM8915_DSP1_RX_EQ_BAND_3_A:
1456 case WM8915_DSP1_RX_EQ_BAND_3_B:
1457 case WM8915_DSP1_RX_EQ_BAND_3_C:
1458 case WM8915_DSP1_RX_EQ_BAND_3_PG:
1459 case WM8915_DSP1_RX_EQ_BAND_4_A:
1460 case WM8915_DSP1_RX_EQ_BAND_4_B:
1461 case WM8915_DSP1_RX_EQ_BAND_4_C:
1462 case WM8915_DSP1_RX_EQ_BAND_4_PG:
1463 case WM8915_DSP1_RX_EQ_BAND_5_A:
1464 case WM8915_DSP1_RX_EQ_BAND_5_B:
1465 case WM8915_DSP1_RX_EQ_BAND_5_PG:
1466 case WM8915_DSP2_TX_LEFT_VOLUME:
1467 case WM8915_DSP2_TX_RIGHT_VOLUME:
1468 case WM8915_DSP2_RX_LEFT_VOLUME:
1469 case WM8915_DSP2_RX_RIGHT_VOLUME:
1470 case WM8915_DSP2_TX_FILTERS:
1471 case WM8915_DSP2_RX_FILTERS_1:
1472 case WM8915_DSP2_RX_FILTERS_2:
1473 case WM8915_DSP2_DRC_1:
1474 case WM8915_DSP2_DRC_2:
1475 case WM8915_DSP2_DRC_3:
1476 case WM8915_DSP2_DRC_4:
1477 case WM8915_DSP2_DRC_5:
1478 case WM8915_DSP2_RX_EQ_GAINS_1:
1479 case WM8915_DSP2_RX_EQ_GAINS_2:
1480 case WM8915_DSP2_RX_EQ_BAND_1_A:
1481 case WM8915_DSP2_RX_EQ_BAND_1_B:
1482 case WM8915_DSP2_RX_EQ_BAND_1_PG:
1483 case WM8915_DSP2_RX_EQ_BAND_2_A:
1484 case WM8915_DSP2_RX_EQ_BAND_2_B:
1485 case WM8915_DSP2_RX_EQ_BAND_2_C:
1486 case WM8915_DSP2_RX_EQ_BAND_2_PG:
1487 case WM8915_DSP2_RX_EQ_BAND_3_A:
1488 case WM8915_DSP2_RX_EQ_BAND_3_B:
1489 case WM8915_DSP2_RX_EQ_BAND_3_C:
1490 case WM8915_DSP2_RX_EQ_BAND_3_PG:
1491 case WM8915_DSP2_RX_EQ_BAND_4_A:
1492 case WM8915_DSP2_RX_EQ_BAND_4_B:
1493 case WM8915_DSP2_RX_EQ_BAND_4_C:
1494 case WM8915_DSP2_RX_EQ_BAND_4_PG:
1495 case WM8915_DSP2_RX_EQ_BAND_5_A:
1496 case WM8915_DSP2_RX_EQ_BAND_5_B:
1497 case WM8915_DSP2_RX_EQ_BAND_5_PG:
1498 case WM8915_DAC1_MIXER_VOLUMES:
1499 case WM8915_DAC1_LEFT_MIXER_ROUTING:
1500 case WM8915_DAC1_RIGHT_MIXER_ROUTING:
1501 case WM8915_DAC2_MIXER_VOLUMES:
1502 case WM8915_DAC2_LEFT_MIXER_ROUTING:
1503 case WM8915_DAC2_RIGHT_MIXER_ROUTING:
1504 case WM8915_DSP1_TX_LEFT_MIXER_ROUTING:
1505 case WM8915_DSP1_TX_RIGHT_MIXER_ROUTING:
1506 case WM8915_DSP2_TX_LEFT_MIXER_ROUTING:
1507 case WM8915_DSP2_TX_RIGHT_MIXER_ROUTING:
1508 case WM8915_DSP_TX_MIXER_SELECT:
1509 case WM8915_DAC_SOFTMUTE:
1510 case WM8915_OVERSAMPLING:
1511 case WM8915_SIDETONE:
1512 case WM8915_GPIO_1:
1513 case WM8915_GPIO_2:
1514 case WM8915_GPIO_3:
1515 case WM8915_GPIO_4:
1516 case WM8915_GPIO_5:
1517 case WM8915_PULL_CONTROL_1:
1518 case WM8915_PULL_CONTROL_2:
1519 case WM8915_INTERRUPT_STATUS_1:
1520 case WM8915_INTERRUPT_STATUS_2:
1521 case WM8915_INTERRUPT_RAW_STATUS_2:
1522 case WM8915_INTERRUPT_STATUS_1_MASK:
1523 case WM8915_INTERRUPT_STATUS_2_MASK:
1524 case WM8915_INTERRUPT_CONTROL:
1525 case WM8915_LEFT_PDM_SPEAKER:
1526 case WM8915_RIGHT_PDM_SPEAKER:
1527 case WM8915_PDM_SPEAKER_MUTE_SEQUENCE:
1528 case WM8915_PDM_SPEAKER_VOLUME:
1529 return 1;
1530 default:
1531 return 0;
1532 }
1533}
1534
1535static int wm8915_volatile_register(struct snd_soc_codec *codec,
1536 unsigned int reg)
1537{
1538 switch (reg) {
1539 case WM8915_SOFTWARE_RESET:
1540 case WM8915_CHIP_REVISION:
1541 case WM8915_LDO_1:
1542 case WM8915_LDO_2:
1543 case WM8915_INTERRUPT_STATUS_1:
1544 case WM8915_INTERRUPT_STATUS_2:
1545 case WM8915_INTERRUPT_RAW_STATUS_2:
1546 case WM8915_DC_SERVO_READBACK_0:
1547 case WM8915_DC_SERVO_2:
1548 case WM8915_DC_SERVO_6:
1549 case WM8915_DC_SERVO_7:
1550 case WM8915_FLL_CONTROL_6:
1551 case WM8915_MIC_DETECT_3:
1552 case WM8915_HEADPHONE_DETECT_1:
1553 case WM8915_HEADPHONE_DETECT_2:
1554 return 1;
1555 default:
1556 return 0;
1557 }
1558}
1559
1560static int wm8915_reset(struct snd_soc_codec *codec)
1561{
1562 return snd_soc_write(codec, WM8915_SOFTWARE_RESET, 0x8915);
1563}
1564
1565static int wm8915_set_bias_level(struct snd_soc_codec *codec,
1566 enum snd_soc_bias_level level)
1567{
1568 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1569 int ret;
1570
1571 switch (level) {
1572 case SND_SOC_BIAS_ON:
1573 break;
1574
1575 case SND_SOC_BIAS_PREPARE:
1576 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1577 snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
1578 WM8915_BG_ENA, WM8915_BG_ENA);
1579 msleep(2);
1580 }
1581 break;
1582
1583 case SND_SOC_BIAS_STANDBY:
1584 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1585 ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
1586 wm8915->supplies);
1587 if (ret != 0) {
1588 dev_err(codec->dev,
1589 "Failed to enable supplies: %d\n",
1590 ret);
1591 return ret;
1592 }
1593
1594 if (wm8915->pdata.ldo_ena >= 0) {
1595 gpio_set_value_cansleep(wm8915->pdata.ldo_ena,
1596 1);
1597 msleep(5);
1598 }
1599
1600 codec->cache_only = false;
1601 snd_soc_cache_sync(codec);
1602 }
1603
1604 snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
1605 WM8915_BG_ENA, 0);
1606 break;
1607
1608 case SND_SOC_BIAS_OFF:
1609 codec->cache_only = true;
1610 if (wm8915->pdata.ldo_ena >= 0)
1611 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
1612 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies),
1613 wm8915->supplies);
1614 break;
1615 }
1616
1617 codec->dapm.bias_level = level;
1618
1619 return 0;
1620}
1621
1622static int wm8915_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1623{
1624 struct snd_soc_codec *codec = dai->codec;
1625 int aifctrl = 0;
1626 int bclk = 0;
1627 int lrclk_tx = 0;
1628 int lrclk_rx = 0;
1629 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1630
1631 switch (dai->id) {
1632 case 0:
1633 aifctrl_reg = WM8915_AIF1_CONTROL;
1634 bclk_reg = WM8915_AIF1_BCLK;
1635 lrclk_tx_reg = WM8915_AIF1_TX_LRCLK_2;
1636 lrclk_rx_reg = WM8915_AIF1_RX_LRCLK_2;
1637 break;
1638 case 1:
1639 aifctrl_reg = WM8915_AIF2_CONTROL;
1640 bclk_reg = WM8915_AIF2_BCLK;
1641 lrclk_tx_reg = WM8915_AIF2_TX_LRCLK_2;
1642 lrclk_rx_reg = WM8915_AIF2_RX_LRCLK_2;
1643 break;
1644 default:
1645 BUG();
1646 return -EINVAL;
1647 }
1648
1649 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1650 case SND_SOC_DAIFMT_NB_NF:
1651 break;
1652 case SND_SOC_DAIFMT_IB_NF:
1653 bclk |= WM8915_AIF1_BCLK_INV;
1654 break;
1655 case SND_SOC_DAIFMT_NB_IF:
1656 lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
1657 lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
1658 break;
1659 case SND_SOC_DAIFMT_IB_IF:
1660 bclk |= WM8915_AIF1_BCLK_INV;
1661 lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
1662 lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
1663 break;
1664 }
1665
1666 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1667 case SND_SOC_DAIFMT_CBS_CFS:
1668 break;
1669 case SND_SOC_DAIFMT_CBS_CFM:
1670 lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
1671 lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
1672 break;
1673 case SND_SOC_DAIFMT_CBM_CFS:
1674 bclk |= WM8915_AIF1_BCLK_MSTR;
1675 break;
1676 case SND_SOC_DAIFMT_CBM_CFM:
1677 bclk |= WM8915_AIF1_BCLK_MSTR;
1678 lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
1679 lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
1680 break;
1681 default:
1682 return -EINVAL;
1683 }
1684
1685 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1686 case SND_SOC_DAIFMT_DSP_A:
1687 break;
1688 case SND_SOC_DAIFMT_DSP_B:
1689 aifctrl |= 1;
1690 break;
1691 case SND_SOC_DAIFMT_I2S:
1692 aifctrl |= 2;
1693 break;
1694 case SND_SOC_DAIFMT_LEFT_J:
1695 aifctrl |= 3;
1696 break;
1697 default:
1698 return -EINVAL;
1699 }
1700
1701 snd_soc_update_bits(codec, aifctrl_reg, WM8915_AIF1_FMT_MASK, aifctrl);
1702 snd_soc_update_bits(codec, bclk_reg,
1703 WM8915_AIF1_BCLK_INV | WM8915_AIF1_BCLK_MSTR,
1704 bclk);
1705 snd_soc_update_bits(codec, lrclk_tx_reg,
1706 WM8915_AIF1TX_LRCLK_INV |
1707 WM8915_AIF1TX_LRCLK_MSTR,
1708 lrclk_tx);
1709 snd_soc_update_bits(codec, lrclk_rx_reg,
1710 WM8915_AIF1RX_LRCLK_INV |
1711 WM8915_AIF1RX_LRCLK_MSTR,
1712 lrclk_rx);
1713
1714 return 0;
1715}
1716
1717static const int bclk_divs[] = {
1718 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1719};
1720
1721static const int dsp_divs[] = {
1722 48000, 32000, 16000, 8000
1723};
1724
1725static int wm8915_hw_params(struct snd_pcm_substream *substream,
1726 struct snd_pcm_hw_params *params,
1727 struct snd_soc_dai *dai)
1728{
1729 struct snd_soc_codec *codec = dai->codec;
1730 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1731 int bits, i, bclk_rate, best, cur_val;
1732 int aifdata = 0;
1733 int bclk = 0;
1734 int lrclk = 0;
1735 int dsp = 0;
1736 int aifdata_reg, bclk_reg, lrclk_reg, dsp_shift;
1737
1738 if (!wm8915->sysclk) {
1739 dev_err(codec->dev, "SYSCLK not configured\n");
1740 return -EINVAL;
1741 }
1742
1743 switch (dai->id) {
1744 case 0:
1745 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1746 (snd_soc_read(codec, WM8915_GPIO_1)) & WM8915_GP1_FN_MASK) {
1747 aifdata_reg = WM8915_AIF1RX_DATA_CONFIGURATION;
1748 lrclk_reg = WM8915_AIF1_RX_LRCLK_1;
1749 } else {
1750 aifdata_reg = WM8915_AIF1TX_DATA_CONFIGURATION_1;
1751 lrclk_reg = WM8915_AIF1_TX_LRCLK_1;
1752 }
1753 bclk_reg = WM8915_AIF1_BCLK;
1754 dsp_shift = 0;
1755 break;
1756 case 1:
1757 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1758 (snd_soc_read(codec, WM8915_GPIO_2)) & WM8915_GP2_FN_MASK) {
1759 aifdata_reg = WM8915_AIF2RX_DATA_CONFIGURATION;
1760 lrclk_reg = WM8915_AIF2_RX_LRCLK_1;
1761 } else {
1762 aifdata_reg = WM8915_AIF2TX_DATA_CONFIGURATION_1;
1763 lrclk_reg = WM8915_AIF2_TX_LRCLK_1;
1764 }
1765 bclk_reg = WM8915_AIF2_BCLK;
1766 dsp_shift = WM8915_DSP2_DIV_SHIFT;
1767 break;
1768 default:
1769 BUG();
1770 return -EINVAL;
1771 }
1772
1773 bclk_rate = snd_soc_params_to_bclk(params);
1774 if (bclk_rate < 0) {
1775 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1776 return bclk_rate;
1777 }
1778
1779 /* Needs looking at for TDM */
1780 bits = snd_pcm_format_width(params_format(params));
1781 if (bits < 0)
1782 return bits;
1783 aifdata |= (bits << WM8915_AIF1TX_WL_SHIFT) | bits;
1784
1785 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1786 if (dsp_divs[i] == params_rate(params))
1787 break;
1788 }
1789 if (i == ARRAY_SIZE(dsp_divs)) {
1790 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1791 params_rate(params));
1792 return -EINVAL;
1793 }
1794 dsp |= i << dsp_shift;
1795
1796 /* Pick a divisor for BCLK as close as we can get to ideal */
1797 best = 0;
1798 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1799 cur_val = (wm8915->sysclk / bclk_divs[i]) - bclk_rate;
1800 if (cur_val < 0) /* BCLK table is sorted */
1801 break;
1802 best = i;
1803 }
1804 bclk_rate = wm8915->sysclk / bclk_divs[best];
1805 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1806 bclk_divs[best], bclk_rate);
1807 bclk |= best;
1808
1809 lrclk = bclk_rate / params_rate(params);
1810 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1811 lrclk, bclk_rate / lrclk);
1812
1813 snd_soc_update_bits(codec, aifdata_reg,
1814 WM8915_AIF1TX_WL_MASK |
1815 WM8915_AIF1TX_SLOT_LEN_MASK,
1816 aifdata);
1817 snd_soc_update_bits(codec, bclk_reg, WM8915_AIF1_BCLK_DIV_MASK, bclk);
1818 snd_soc_update_bits(codec, lrclk_reg, WM8915_AIF1RX_RATE_MASK,
1819 lrclk);
1820 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_2,
1821 WM8915_DSP1_DIV_SHIFT << dsp_shift, dsp);
1822
1823 wm8915->rx_rate[dai->id] = params_rate(params);
1824
1825 return 0;
1826}
1827
1828static int wm8915_set_sysclk(struct snd_soc_dai *dai,
1829 int clk_id, unsigned int freq, int dir)
1830{
1831 struct snd_soc_codec *codec = dai->codec;
1832 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1833 int lfclk = 0;
Mark Brownc5f336c2011-04-21 14:16:14 +0100[diff] [blame^]1834 int ratediv = 0;
Mark Brownc93993a2011-02-08 14:09:41 +0000[diff] [blame]1835 int src;
1836 int old;
1837
1838 /* Disable SYSCLK while we reconfigure */
1839 old = snd_soc_read(codec, WM8915_AIF_CLOCKING_1);
1840 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1841 WM8915_SYSCLK_ENA, 0);
1842
1843 switch (clk_id) {
1844 case WM8915_SYSCLK_MCLK1:
1845 wm8915->sysclk = freq;
1846 src = 0;
1847 break;
1848 case WM8915_SYSCLK_MCLK2:
1849 wm8915->sysclk = freq;
1850 src = 1;
1851 break;
1852 case WM8915_SYSCLK_FLL:
1853 wm8915->sysclk = freq;
1854 src = 2;
1855 break;
1856 default:
1857 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1858 return -EINVAL;
1859 }
1860
1861 switch (wm8915->sysclk) {
1862 case 6144000:
1863 snd_soc_update_bits(codec, WM8915_AIF_RATE,
1864 WM8915_SYSCLK_RATE, 0);
1865 break;
Mark Brownc5f336c2011-04-21 14:16:14 +0100[diff] [blame^]1866 case 24576000:
1867 ratediv = WM8915_SYSCLK_DIV;
Mark Brownc93993a2011-02-08 14:09:41 +0000[diff] [blame]1868 case 12288000:
1869 snd_soc_update_bits(codec, WM8915_AIF_RATE,
1870 WM8915_SYSCLK_RATE, WM8915_SYSCLK_RATE);
1871 break;
1872 case 32000:
1873 case 32768:
1874 lfclk = WM8915_LFCLK_ENA;
1875 break;
1876 default:
1877 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1878 wm8915->sysclk);
1879 return -EINVAL;
1880 }
1881
1882 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
Mark Brownc5f336c2011-04-21 14:16:14 +0100[diff] [blame^]1883 WM8915_SYSCLK_SRC_MASK | WM8915_SYSCLK_DIV_MASK,
1884 src << WM8915_SYSCLK_SRC_SHIFT | ratediv);
Mark Brownc93993a2011-02-08 14:09:41 +0000[diff] [blame]1885 snd_soc_update_bits(codec, WM8915_CLOCKING_1, WM8915_LFCLK_ENA, lfclk);
1886 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1887 WM8915_SYSCLK_ENA, old);
1888
1889 return 0;
1890}
1891
1892struct _fll_div {
1893 u16 fll_fratio;
1894 u16 fll_outdiv;
1895 u16 fll_refclk_div;
1896 u16 fll_loop_gain;
1897 u16 fll_ref_freq;
1898 u16 n;
1899 u16 theta;
1900 u16 lambda;
1901};
1902
1903static struct {
1904 unsigned int min;
1905 unsigned int max;
1906 u16 fll_fratio;
1907 int ratio;
1908} fll_fratios[] = {
1909 { 0, 64000, 4, 16 },
1910 { 64000, 128000, 3, 8 },
1911 { 128000, 256000, 2, 4 },
1912 { 256000, 1000000, 1, 2 },
1913 { 1000000, 13500000, 0, 1 },
1914};
1915
1916static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1917 unsigned int Fout)
1918{
1919 unsigned int target;
1920 unsigned int div;
1921 unsigned int fratio, gcd_fll;
1922 int i;
1923
1924 /* Fref must be <=13.5MHz */
1925 div = 1;
1926 fll_div->fll_refclk_div = 0;
1927 while ((Fref / div) > 13500000) {
1928 div *= 2;
1929 fll_div->fll_refclk_div++;
1930
1931 if (div > 8) {
1932 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1933 Fref);
1934 return -EINVAL;
1935 }
1936 }
1937
1938 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1939
1940 /* Apply the division for our remaining calculations */
1941 Fref /= div;
1942
1943 if (Fref >= 3000000)
1944 fll_div->fll_loop_gain = 5;
1945 else
1946 fll_div->fll_loop_gain = 0;
1947
1948 if (Fref >= 48000)
1949 fll_div->fll_ref_freq = 0;
1950 else
1951 fll_div->fll_ref_freq = 1;
1952
1953 /* Fvco should be 90-100MHz; don't check the upper bound */
1954 div = 2;
1955 while (Fout * div < 90000000) {
1956 div++;
1957 if (div > 64) {
1958 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1959 Fout);
1960 return -EINVAL;
1961 }
1962 }
1963 target = Fout * div;
1964 fll_div->fll_outdiv = div - 1;
1965
1966 pr_debug("FLL Fvco=%dHz\n", target);
1967
1968 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1969 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1970 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1971 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1972 fratio = fll_fratios[i].ratio;
1973 break;
1974 }
1975 }
1976 if (i == ARRAY_SIZE(fll_fratios)) {
1977 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1978 return -EINVAL;
1979 }
1980
1981 fll_div->n = target / (fratio * Fref);
1982
1983 if (target % Fref == 0) {
1984 fll_div->theta = 0;
1985 fll_div->lambda = 0;
1986 } else {
1987 gcd_fll = gcd(target, fratio * Fref);
1988
1989 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1990 / gcd_fll;
1991 fll_div->lambda = (fratio * Fref) / gcd_fll;
1992 }
1993
1994 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1995 fll_div->n, fll_div->theta, fll_div->lambda);
1996 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1997 fll_div->fll_fratio, fll_div->fll_outdiv,
1998 fll_div->fll_refclk_div);
1999
2000 return 0;
2001}
2002
Mark Brown01b07e22011-04-11 23:39:10 -0700[diff] [blame]2003static int wm8915_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
Mark Brownc93993a2011-02-08 14:09:41 +0000[diff] [blame]2004 unsigned int Fref, unsigned int Fout)
2005{
Mark Brownc93993a2011-02-08 14:09:41 +0000[diff] [blame]2006 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2007 struct _fll_div fll_div;
2008 unsigned long timeout;
2009 int ret, reg;
2010
2011 /* Any change? */
2012 if (source == wm8915->fll_src && Fref == wm8915->fll_fref &&
2013 Fout == wm8915->fll_fout)
2014 return 0;
2015
2016 if (Fout == 0) {
2017 dev_dbg(codec->dev, "FLL disabled\n");
2018
2019 wm8915->fll_fref = 0;
2020 wm8915->fll_fout = 0;
2021
2022 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
2023 WM8915_FLL_ENA, 0);
2024
2025 return 0;
2026 }
2027
2028 ret = fll_factors(&fll_div, Fref, Fout);
2029 if (ret != 0)
2030 return ret;
2031
2032 switch (source) {
2033 case WM8915_FLL_MCLK1:
2034 reg = 0;
2035 break;
2036 case WM8915_FLL_MCLK2:
2037 reg = 1;
2038 case WM8915_FLL_DACLRCLK1:
2039 reg = 2;
2040 break;
2041 case WM8915_FLL_BCLK1:
2042 reg = 3;
2043 break;
2044 default:
2045 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2046 return -EINVAL;
2047 }
2048
2049 reg |= fll_div.fll_refclk_div << WM8915_FLL_REFCLK_DIV_SHIFT;
2050 reg |= fll_div.fll_ref_freq << WM8915_FLL_REF_FREQ_SHIFT;
2051
2052 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_5,
2053 WM8915_FLL_REFCLK_DIV_MASK | WM8915_FLL_REF_FREQ |
2054 WM8915_FLL_REFCLK_SRC_MASK, reg);
2055
2056 reg = 0;
2057 if (fll_div.theta || fll_div.lambda)
2058 reg |= WM8915_FLL_EFS_ENA | (3 << WM8915_FLL_LFSR_SEL_SHIFT);
2059 else
2060 reg |= 1 << WM8915_FLL_LFSR_SEL_SHIFT;
2061 snd_soc_write(codec, WM8915_FLL_EFS_2, reg);
2062
2063 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_2,
2064 WM8915_FLL_OUTDIV_MASK |
2065 WM8915_FLL_FRATIO_MASK,
2066 (fll_div.fll_outdiv << WM8915_FLL_OUTDIV_SHIFT) |
2067 (fll_div.fll_fratio));
2068
2069 snd_soc_write(codec, WM8915_FLL_CONTROL_3, fll_div.theta);
2070
2071 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_4,
2072 WM8915_FLL_N_MASK | WM8915_FLL_LOOP_GAIN_MASK,
2073 (fll_div.n << WM8915_FLL_N_SHIFT) |
2074 fll_div.fll_loop_gain);
2075
2076 snd_soc_write(codec, WM8915_FLL_EFS_1, fll_div.lambda);
2077
2078 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
2079 WM8915_FLL_ENA, WM8915_FLL_ENA);
2080
2081 /* The FLL supports live reconfiguration - kick that in case we were
2082 * already enabled.
2083 */
2084 snd_soc_write(codec, WM8915_FLL_CONTROL_6, WM8915_FLL_SWITCH_CLK);
2085
2086 /* Wait for the FLL to lock, using the interrupt if possible */
2087 if (Fref > 1000000)
2088 timeout = usecs_to_jiffies(300);
2089 else
2090 timeout = msecs_to_jiffies(2);
2091
2092 wait_for_completion_timeout(&wm8915->fll_lock, timeout);
2093
2094 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2095
2096 wm8915->fll_fref = Fref;
2097 wm8915->fll_fout = Fout;
2098 wm8915->fll_src = source;
2099
2100 return 0;
2101}
2102
2103#ifdef CONFIG_GPIOLIB
2104static inline struct wm8915_priv *gpio_to_wm8915(struct gpio_chip *chip)
2105{
2106 return container_of(chip, struct wm8915_priv, gpio_chip);
2107}
2108
2109static void wm8915_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2110{
2111 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2112 struct snd_soc_codec *codec = wm8915->codec;
2113
2114 snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2115 WM8915_GP1_LVL, !!value << WM8915_GP1_LVL_SHIFT);
2116}
2117
2118static int wm8915_gpio_direction_out(struct gpio_chip *chip,
2119 unsigned offset, int value)
2120{
2121 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2122 struct snd_soc_codec *codec = wm8915->codec;
2123 int val;
2124
2125 val = (1 << WM8915_GP1_FN_SHIFT) | (!!value << WM8915_GP1_LVL_SHIFT);
2126
2127 return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2128 WM8915_GP1_FN_MASK | WM8915_GP1_DIR |
2129 WM8915_GP1_LVL, val);
2130}
2131
2132static int wm8915_gpio_get(struct gpio_chip *chip, unsigned offset)
2133{
2134 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2135 struct snd_soc_codec *codec = wm8915->codec;
2136 int ret;
2137
2138 ret = snd_soc_read(codec, WM8915_GPIO_1 + offset);
2139 if (ret < 0)
2140 return ret;
2141
2142 return (ret & WM8915_GP1_LVL) != 0;
2143}
2144
2145static int wm8915_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2146{
2147 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2148 struct snd_soc_codec *codec = wm8915->codec;
2149
2150 return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2151 WM8915_GP1_FN_MASK | WM8915_GP1_DIR,
2152 (1 << WM8915_GP1_FN_SHIFT) |
2153 (1 << WM8915_GP1_DIR_SHIFT));
2154}
2155
2156static struct gpio_chip wm8915_template_chip = {
2157 .label = "wm8915",
2158 .owner = THIS_MODULE,
2159 .direction_output = wm8915_gpio_direction_out,
2160 .set = wm8915_gpio_set,
2161 .direction_input = wm8915_gpio_direction_in,
2162 .get = wm8915_gpio_get,
2163 .can_sleep = 1,
2164};
2165
2166static void wm8915_init_gpio(struct snd_soc_codec *codec)
2167{
2168 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2169 int ret;
2170
2171 wm8915->gpio_chip = wm8915_template_chip;
2172 wm8915->gpio_chip.ngpio = 5;
2173 wm8915->gpio_chip.dev = codec->dev;
2174
2175 if (wm8915->pdata.gpio_base)
2176 wm8915->gpio_chip.base = wm8915->pdata.gpio_base;
2177 else
2178 wm8915->gpio_chip.base = -1;
2179
2180 ret = gpiochip_add(&wm8915->gpio_chip);
2181 if (ret != 0)
2182 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2183}
2184
2185static void wm8915_free_gpio(struct snd_soc_codec *codec)
2186{
2187 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2188 int ret;
2189
2190 ret = gpiochip_remove(&wm8915->gpio_chip);
2191 if (ret != 0)
2192 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2193}
2194#else
2195static void wm8915_init_gpio(struct snd_soc_codec *codec)
2196{
2197}
2198
2199static void wm8915_free_gpio(struct snd_soc_codec *codec)
2200{
2201}
2202#endif
2203
2204/**
2205 * wm8915_detect - Enable default WM8915 jack detection
2206 *
2207 * The WM8915 has advanced accessory detection support for headsets.
2208 * This function provides a default implementation which integrates
2209 * the majority of this functionality with minimal user configuration.
2210 *
2211 * This will detect headset, headphone and short circuit button and
2212 * will also detect inverted microphone ground connections and update
2213 * the polarity of the connections.
2214 */
2215int wm8915_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2216 wm8915_polarity_fn polarity_cb)
2217{
2218 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2219
2220 wm8915->jack = jack;
2221 wm8915->detecting = true;
2222 wm8915->polarity_cb = polarity_cb;
2223
2224 if (wm8915->polarity_cb)
2225 wm8915->polarity_cb(codec, 0);
2226
2227 /* Clear discarge to avoid noise during detection */
2228 snd_soc_update_bits(codec, WM8915_MICBIAS_1,
2229 WM8915_MICB1_DISCH, 0);
2230 snd_soc_update_bits(codec, WM8915_MICBIAS_2,
2231 WM8915_MICB2_DISCH, 0);
2232
2233 /* LDO2 powers the microphones, SYSCLK clocks detection */
2234 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2235 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2236
2237 /* We start off just enabling microphone detection - even a
2238 * plain headphone will trigger detection.
2239 */
2240 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2241 WM8915_MICD_ENA, WM8915_MICD_ENA);
2242
2243 /* Slowest detection rate, gives debounce for initial detection */
2244 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2245 WM8915_MICD_RATE_MASK,
2246 WM8915_MICD_RATE_MASK);
2247
2248 /* Enable interrupts and we're off */
2249 snd_soc_update_bits(codec, WM8915_INTERRUPT_STATUS_2_MASK,
2250 WM8915_IM_MICD_EINT, 0);
2251
2252 return 0;
2253}
2254EXPORT_SYMBOL_GPL(wm8915_detect);
2255
2256static void wm8915_micd(struct snd_soc_codec *codec)
2257{
2258 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2259 int val, reg;
2260
2261 val = snd_soc_read(codec, WM8915_MIC_DETECT_3);
2262
2263 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2264
2265 if (!(val & WM8915_MICD_VALID)) {
2266 dev_warn(codec->dev, "Microphone detection state invalid\n");
2267 return;
2268 }
2269
2270 /* No accessory, reset everything and report removal */
2271 if (!(val & WM8915_MICD_STS)) {
2272 dev_dbg(codec->dev, "Jack removal detected\n");
2273 wm8915->jack_mic = false;
2274 wm8915->detecting = true;
2275 snd_soc_jack_report(wm8915->jack, 0,
2276 SND_JACK_HEADSET | SND_JACK_BTN_0);
2277 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2278 WM8915_MICD_RATE_MASK,
2279 WM8915_MICD_RATE_MASK);
2280 return;
2281 }
2282
2283 /* If the measurement is very high we've got a microphone but
2284 * do a little debounce to account for mechanical issues.
2285 */
2286 if (val & 0x400) {
2287 dev_dbg(codec->dev, "Microphone detected\n");
2288 snd_soc_jack_report(wm8915->jack, SND_JACK_HEADSET,
2289 SND_JACK_HEADSET | SND_JACK_BTN_0);
2290 wm8915->jack_mic = true;
2291 wm8915->detecting = false;
2292 }
2293
2294 /* If we detected a lower impedence during initial startup
2295 * then we probably have the wrong polarity, flip it. Don't
2296 * do this for the lowest impedences to speed up detection of
2297 * plain headphones.
2298 */
2299 if (wm8915->detecting && (val & 0x3f0)) {
2300 reg = snd_soc_read(codec, WM8915_ACCESSORY_DETECT_MODE_2);
2301 reg ^= WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
2302 WM8915_MICD_BIAS_SRC;
2303 snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
2304 WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
2305 WM8915_MICD_BIAS_SRC, reg);
2306
2307 if (wm8915->polarity_cb)
2308 wm8915->polarity_cb(codec,
2309 (reg & WM8915_MICD_SRC) != 0);
2310
2311 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2312 (reg & WM8915_MICD_SRC) != 0);
2313
2314 return;
2315 }
2316
2317 /* Don't distinguish between buttons, just report any low
2318 * impedence as BTN_0.
2319 */
2320 if (val & 0x3fc) {
2321 if (wm8915->jack_mic) {
2322 dev_dbg(codec->dev, "Mic button detected\n");
2323 snd_soc_jack_report(wm8915->jack,
2324 SND_JACK_HEADSET | SND_JACK_BTN_0,
2325 SND_JACK_HEADSET | SND_JACK_BTN_0);
2326 } else {
2327 dev_dbg(codec->dev, "Headphone detected\n");
2328 snd_soc_jack_report(wm8915->jack,
2329 SND_JACK_HEADPHONE,
2330 SND_JACK_HEADSET |
2331 SND_JACK_BTN_0);
2332 wm8915->detecting = false;
2333 }
2334 }
2335
2336 /* Increase poll rate to give better responsiveness for buttons */
2337 if (!wm8915->detecting)
2338 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2339 WM8915_MICD_RATE_MASK,
2340 5 << WM8915_MICD_RATE_SHIFT);
2341}
2342
2343static irqreturn_t wm8915_irq(int irq, void *data)
2344{
2345 struct snd_soc_codec *codec = data;
2346 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2347 int irq_val;
2348
2349 irq_val = snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2);
2350 if (irq_val < 0) {
2351 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2352 irq_val);
2353 return IRQ_NONE;
2354 }
2355 irq_val &= ~snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2_MASK);
2356
2357 if (irq_val & (WM8915_DCS_DONE_01_EINT | WM8915_DCS_DONE_23_EINT)) {
2358 dev_dbg(codec->dev, "DC servo IRQ\n");
2359 complete(&wm8915->dcs_done);
2360 }
2361
2362 if (irq_val & WM8915_FIFOS_ERR_EINT)
2363 dev_err(codec->dev, "Digital core FIFO error\n");
2364
2365 if (irq_val & WM8915_FLL_LOCK_EINT) {
2366 dev_dbg(codec->dev, "FLL locked\n");
2367 complete(&wm8915->fll_lock);
2368 }
2369
2370 if (irq_val & WM8915_MICD_EINT)
2371 wm8915_micd(codec);
2372
2373 if (irq_val) {
2374 snd_soc_write(codec, WM8915_INTERRUPT_STATUS_2, irq_val);
2375
2376 return IRQ_HANDLED;
2377 } else {
2378 return IRQ_NONE;
2379 }
2380}
2381
2382static void wm8915_retune_mobile_pdata(struct snd_soc_codec *codec)
2383{
2384 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2385 struct wm8915_pdata *pdata = &wm8915->pdata;
2386
2387 struct snd_kcontrol_new controls[] = {
2388 SOC_ENUM_EXT("DSP1 EQ Mode",
2389 wm8915->retune_mobile_enum,
2390 wm8915_get_retune_mobile_enum,
2391 wm8915_put_retune_mobile_enum),
2392 SOC_ENUM_EXT("DSP2 EQ Mode",
2393 wm8915->retune_mobile_enum,
2394 wm8915_get_retune_mobile_enum,
2395 wm8915_put_retune_mobile_enum),
2396 };
2397 int ret, i, j;
2398 const char **t;
2399
2400 /* We need an array of texts for the enum API but the number
2401 * of texts is likely to be less than the number of
2402 * configurations due to the sample rate dependency of the
2403 * configurations. */
2404 wm8915->num_retune_mobile_texts = 0;
2405 wm8915->retune_mobile_texts = NULL;
2406 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2407 for (j = 0; j < wm8915->num_retune_mobile_texts; j++) {
2408 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2409 wm8915->retune_mobile_texts[j]) == 0)
2410 break;
2411 }
2412
2413 if (j != wm8915->num_retune_mobile_texts)
2414 continue;
2415
2416 /* Expand the array... */
2417 t = krealloc(wm8915->retune_mobile_texts,
2418 sizeof(char *) *
2419 (wm8915->num_retune_mobile_texts + 1),
2420 GFP_KERNEL);
2421 if (t == NULL)
2422 continue;
2423
2424 /* ...store the new entry... */
2425 t[wm8915->num_retune_mobile_texts] =
2426 pdata->retune_mobile_cfgs[i].name;
2427
2428 /* ...and remember the new version. */
2429 wm8915->num_retune_mobile_texts++;
2430 wm8915->retune_mobile_texts = t;
2431 }
2432
2433 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2434 wm8915->num_retune_mobile_texts);
2435
2436 wm8915->retune_mobile_enum.max = wm8915->num_retune_mobile_texts;
2437 wm8915->retune_mobile_enum.texts = wm8915->retune_mobile_texts;
2438
2439 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2440 if (ret != 0)
2441 dev_err(codec->dev,
2442 "Failed to add ReTune Mobile controls: %d\n", ret);
2443}
2444
2445static int wm8915_probe(struct snd_soc_codec *codec)
2446{
2447 int ret;
2448 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2449 struct i2c_client *i2c = to_i2c_client(codec->dev);
2450 struct snd_soc_dapm_context *dapm = &codec->dapm;
2451 int i, irq_flags;
2452
2453 wm8915->codec = codec;
2454
2455 init_completion(&wm8915->dcs_done);
2456 init_completion(&wm8915->fll_lock);
2457
2458 dapm->idle_bias_off = true;
2459 dapm->bias_level = SND_SOC_BIAS_OFF;
2460
2461 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2462 if (ret != 0) {
2463 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2464 goto err;
2465 }
2466
2467 for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
2468 wm8915->supplies[i].supply = wm8915_supply_names[i];
2469
2470 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8915->supplies),
2471 wm8915->supplies);
2472 if (ret != 0) {
2473 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2474 goto err;
2475 }
2476
2477 wm8915->disable_nb[0].notifier_call = wm8915_regulator_event_0;
2478 wm8915->disable_nb[1].notifier_call = wm8915_regulator_event_1;
2479 wm8915->disable_nb[2].notifier_call = wm8915_regulator_event_2;
2480 wm8915->disable_nb[3].notifier_call = wm8915_regulator_event_3;
2481 wm8915->disable_nb[4].notifier_call = wm8915_regulator_event_4;
2482 wm8915->disable_nb[5].notifier_call = wm8915_regulator_event_5;
2483
2484 /* This should really be moved into the regulator core */
2485 for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) {
2486 ret = regulator_register_notifier(wm8915->supplies[i].consumer,
2487 &wm8915->disable_nb[i]);
2488 if (ret != 0) {
2489 dev_err(codec->dev,
2490 "Failed to register regulator notifier: %d\n",
2491 ret);
2492 }
2493 }
2494
2495 ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
2496 wm8915->supplies);
2497 if (ret != 0) {
2498 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2499 goto err_get;
2500 }
2501
2502 if (wm8915->pdata.ldo_ena >= 0) {
2503 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 1);
2504 msleep(5);
2505 }
2506
2507 ret = snd_soc_read(codec, WM8915_SOFTWARE_RESET);
2508 if (ret < 0) {
2509 dev_err(codec->dev, "Failed to read ID register: %d\n", ret);
2510 goto err_enable;
2511 }
2512 if (ret != 0x8915) {
2513 dev_err(codec->dev, "Device is not a WM8915, ID %x\n", ret);
2514 ret = -EINVAL;
2515 goto err_enable;
2516 }
2517
2518 ret = snd_soc_read(codec, WM8915_CHIP_REVISION);
2519 if (ret < 0) {
2520 dev_err(codec->dev, "Failed to read device revision: %d\n",
2521 ret);
2522 goto err_enable;
2523 }
2524
2525 dev_info(codec->dev, "revision %c\n",
2526 (ret & WM8915_CHIP_REV_MASK) + 'A');
2527
2528 if (wm8915->pdata.ldo_ena >= 0) {
2529 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
2530 } else {
2531 ret = wm8915_reset(codec);
2532 if (ret < 0) {
2533 dev_err(codec->dev, "Failed to issue reset\n");
2534 goto err_enable;
2535 }
2536 }
2537
2538 codec->cache_only = true;
2539
2540 /* Apply platform data settings */
2541 snd_soc_update_bits(codec, WM8915_LINE_INPUT_CONTROL,
2542 WM8915_INL_MODE_MASK | WM8915_INR_MODE_MASK,
2543 wm8915->pdata.inl_mode << WM8915_INL_MODE_SHIFT |
2544 wm8915->pdata.inr_mode);
2545
2546 for (i = 0; i < ARRAY_SIZE(wm8915->pdata.gpio_default); i++) {
2547 if (!wm8915->pdata.gpio_default[i])
2548 continue;
2549
2550 snd_soc_write(codec, WM8915_GPIO_1 + i,
2551 wm8915->pdata.gpio_default[i] & 0xffff);
2552 }
2553
2554 if (wm8915->pdata.spkmute_seq)
2555 snd_soc_update_bits(codec, WM8915_PDM_SPEAKER_MUTE_SEQUENCE,
2556 WM8915_SPK_MUTE_ENDIAN |
2557 WM8915_SPK_MUTE_SEQ1_MASK,
2558 wm8915->pdata.spkmute_seq);
2559
2560 snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
2561 WM8915_MICD_BIAS_SRC | WM8915_HPOUT1FB_SRC |
2562 WM8915_MICD_SRC, wm8915->pdata.micdet_def);
2563
2564 /* Latch volume update bits */
2565 snd_soc_update_bits(codec, WM8915_LEFT_LINE_INPUT_VOLUME,
2566 WM8915_IN1_VU, WM8915_IN1_VU);
2567 snd_soc_update_bits(codec, WM8915_RIGHT_LINE_INPUT_VOLUME,
2568 WM8915_IN1_VU, WM8915_IN1_VU);
2569
2570 snd_soc_update_bits(codec, WM8915_DAC1_LEFT_VOLUME,
2571 WM8915_DAC1_VU, WM8915_DAC1_VU);
2572 snd_soc_update_bits(codec, WM8915_DAC1_RIGHT_VOLUME,
2573 WM8915_DAC1_VU, WM8915_DAC1_VU);
2574 snd_soc_update_bits(codec, WM8915_DAC2_LEFT_VOLUME,
2575 WM8915_DAC2_VU, WM8915_DAC2_VU);
2576 snd_soc_update_bits(codec, WM8915_DAC2_RIGHT_VOLUME,
2577 WM8915_DAC2_VU, WM8915_DAC2_VU);
2578
2579 snd_soc_update_bits(codec, WM8915_OUTPUT1_LEFT_VOLUME,
2580 WM8915_DAC1_VU, WM8915_DAC1_VU);
2581 snd_soc_update_bits(codec, WM8915_OUTPUT1_RIGHT_VOLUME,
2582 WM8915_DAC1_VU, WM8915_DAC1_VU);
2583 snd_soc_update_bits(codec, WM8915_OUTPUT2_LEFT_VOLUME,
2584 WM8915_DAC2_VU, WM8915_DAC2_VU);
2585 snd_soc_update_bits(codec, WM8915_OUTPUT2_RIGHT_VOLUME,
2586 WM8915_DAC2_VU, WM8915_DAC2_VU);
2587
2588 snd_soc_update_bits(codec, WM8915_DSP1_TX_LEFT_VOLUME,
2589 WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
2590 snd_soc_update_bits(codec, WM8915_DSP1_TX_RIGHT_VOLUME,
2591 WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
2592 snd_soc_update_bits(codec, WM8915_DSP2_TX_LEFT_VOLUME,
2593 WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
2594 snd_soc_update_bits(codec, WM8915_DSP2_TX_RIGHT_VOLUME,
2595 WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
2596
2597 snd_soc_update_bits(codec, WM8915_DSP1_RX_LEFT_VOLUME,
2598 WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
2599 snd_soc_update_bits(codec, WM8915_DSP1_RX_RIGHT_VOLUME,
2600 WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
2601 snd_soc_update_bits(codec, WM8915_DSP2_RX_LEFT_VOLUME,
2602 WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
2603 snd_soc_update_bits(codec, WM8915_DSP2_RX_RIGHT_VOLUME,
2604 WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
2605
2606 /* No support currently for the underclocked TDM modes and
2607 * pick a default TDM layout with each channel pair working with
2608 * slots 0 and 1. */
2609 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_0_CONFIGURATION,
2610 WM8915_AIF1RX_CHAN0_SLOTS_MASK |
2611 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2612 1 << WM8915_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2613 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_1_CONFIGURATION,
2614 WM8915_AIF1RX_CHAN1_SLOTS_MASK |
2615 WM8915_AIF1RX_CHAN1_START_SLOT_MASK,
2616 1 << WM8915_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2617 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_2_CONFIGURATION,
2618 WM8915_AIF1RX_CHAN2_SLOTS_MASK |
2619 WM8915_AIF1RX_CHAN2_START_SLOT_MASK,
2620 1 << WM8915_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2621 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_3_CONFIGURATION,
2622 WM8915_AIF1RX_CHAN3_SLOTS_MASK |
2623 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2624 1 << WM8915_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2625 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_4_CONFIGURATION,
2626 WM8915_AIF1RX_CHAN4_SLOTS_MASK |
2627 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2628 1 << WM8915_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2629 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_5_CONFIGURATION,
2630 WM8915_AIF1RX_CHAN5_SLOTS_MASK |
2631 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2632 1 << WM8915_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2633
2634 snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_0_CONFIGURATION,
2635 WM8915_AIF2RX_CHAN0_SLOTS_MASK |
2636 WM8915_AIF2RX_CHAN0_START_SLOT_MASK,
2637 1 << WM8915_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2638 snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_1_CONFIGURATION,
2639 WM8915_AIF2RX_CHAN1_SLOTS_MASK |
2640 WM8915_AIF2RX_CHAN1_START_SLOT_MASK,
2641 1 << WM8915_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2642
2643 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_0_CONFIGURATION,
2644 WM8915_AIF1TX_CHAN0_SLOTS_MASK |
2645 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2646 1 << WM8915_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2647 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
2648 WM8915_AIF1TX_CHAN1_SLOTS_MASK |
2649 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2650 1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2651 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_2_CONFIGURATION,
2652 WM8915_AIF1TX_CHAN2_SLOTS_MASK |
2653 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2654 1 << WM8915_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2655 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_3_CONFIGURATION,
2656 WM8915_AIF1TX_CHAN3_SLOTS_MASK |
2657 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2658 1 << WM8915_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2659 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_4_CONFIGURATION,
2660 WM8915_AIF1TX_CHAN4_SLOTS_MASK |
2661 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2662 1 << WM8915_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2663 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_5_CONFIGURATION,
2664 WM8915_AIF1TX_CHAN5_SLOTS_MASK |
2665 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2666 1 << WM8915_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2667
2668 snd_soc_update_bits(codec, WM8915_AIF2TX_CHANNEL_0_CONFIGURATION,
2669 WM8915_AIF2TX_CHAN0_SLOTS_MASK |
2670 WM8915_AIF2TX_CHAN0_START_SLOT_MASK,
2671 1 << WM8915_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2672 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
2673 WM8915_AIF2TX_CHAN1_SLOTS_MASK |
2674 WM8915_AIF2TX_CHAN1_START_SLOT_MASK,
2675 1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2676
2677 if (wm8915->pdata.num_retune_mobile_cfgs)
2678 wm8915_retune_mobile_pdata(codec);
2679 else
2680 snd_soc_add_controls(codec, wm8915_eq_controls,
2681 ARRAY_SIZE(wm8915_eq_controls));
2682
2683 /* If the TX LRCLK pins are not in LRCLK mode configure the
2684 * AIFs to source their clocks from the RX LRCLKs.
2685 */
2686 if ((snd_soc_read(codec, WM8915_GPIO_1)))
2687 snd_soc_update_bits(codec, WM8915_AIF1_TX_LRCLK_2,
2688 WM8915_AIF1TX_LRCLK_MODE,
2689 WM8915_AIF1TX_LRCLK_MODE);
2690
2691 if ((snd_soc_read(codec, WM8915_GPIO_2)))
2692 snd_soc_update_bits(codec, WM8915_AIF2_TX_LRCLK_2,
2693 WM8915_AIF2TX_LRCLK_MODE,
2694 WM8915_AIF2TX_LRCLK_MODE);
2695
2696 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2697
2698 wm8915_init_gpio(codec);
2699
2700 if (i2c->irq) {
2701 if (wm8915->pdata.irq_flags)
2702 irq_flags = wm8915->pdata.irq_flags;
2703 else
2704 irq_flags = IRQF_TRIGGER_LOW;
2705
2706 irq_flags |= IRQF_ONESHOT;
2707
2708 ret = request_threaded_irq(i2c->irq, NULL, wm8915_irq,
2709 irq_flags, "wm8915", codec);
2710 if (ret == 0) {
2711 /* Unmask the interrupt */
2712 snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
2713 WM8915_IM_IRQ, 0);
2714
2715 /* Enable error reporting and DC servo status */
2716 snd_soc_update_bits(codec,
2717 WM8915_INTERRUPT_STATUS_2_MASK,
2718 WM8915_IM_DCS_DONE_23_EINT |
2719 WM8915_IM_DCS_DONE_01_EINT |
2720 WM8915_IM_FLL_LOCK_EINT |
2721 WM8915_IM_FIFOS_ERR_EINT,
2722 0);
2723 } else {
2724 dev_err(codec->dev, "Failed to request IRQ: %d\n",
2725 ret);
2726 }
2727 }
2728
2729 return 0;
2730
2731err_enable:
2732 if (wm8915->pdata.ldo_ena >= 0)
2733 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
2734
2735 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2736err_get:
2737 regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2738err:
2739 return ret;
2740}
2741
2742static int wm8915_remove(struct snd_soc_codec *codec)
2743{
2744 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2745 struct i2c_client *i2c = to_i2c_client(codec->dev);
2746 int i;
2747
2748 snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
2749 WM8915_IM_IRQ, WM8915_IM_IRQ);
2750
2751 if (i2c->irq)
2752 free_irq(i2c->irq, codec);
2753
2754 wm8915_free_gpio(codec);
2755
2756 for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
2757 regulator_unregister_notifier(wm8915->supplies[i].consumer,
2758 &wm8915->disable_nb[i]);
2759 regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2760
2761 return 0;
2762}
2763
2764static struct snd_soc_codec_driver soc_codec_dev_wm8915 = {
2765 .probe = wm8915_probe,
2766 .remove = wm8915_remove,
2767 .set_bias_level = wm8915_set_bias_level,
2768 .seq_notifier = wm8915_seq_notifier,
2769 .reg_cache_size = WM8915_MAX_REGISTER + 1,
2770 .reg_word_size = sizeof(u16),
2771 .reg_cache_default = wm8915_reg,
2772 .volatile_register = wm8915_volatile_register,
2773 .readable_register = wm8915_readable_register,
2774 .compress_type = SND_SOC_RBTREE_COMPRESSION,
2775 .controls = wm8915_snd_controls,
2776 .num_controls = ARRAY_SIZE(wm8915_snd_controls),
2777 .dapm_widgets = wm8915_dapm_widgets,
2778 .num_dapm_widgets = ARRAY_SIZE(wm8915_dapm_widgets),
2779 .dapm_routes = wm8915_dapm_routes,
2780 .num_dapm_routes = ARRAY_SIZE(wm8915_dapm_routes),
Mark Brown01b07e22011-04-11 23:39:10 -0700[diff] [blame]2781 .set_pll = wm8915_set_fll,
Mark Brownc93993a2011-02-08 14:09:41 +0000[diff] [blame]2782};
2783
2784#define WM8915_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2785 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
2786#define WM8915_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2787 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2788 SNDRV_PCM_FMTBIT_S32_LE)
2789
2790static struct snd_soc_dai_ops wm8915_dai_ops = {
2791 .set_fmt = wm8915_set_fmt,
2792 .hw_params = wm8915_hw_params,
2793 .set_sysclk = wm8915_set_sysclk,
Mark Brownc93993a2011-02-08 14:09:41 +0000[diff] [blame]2794};
2795
2796static struct snd_soc_dai_driver wm8915_dai[] = {
2797 {
2798 .name = "wm8915-aif1",
2799 .playback = {
2800 .stream_name = "AIF1 Playback",
2801 .channels_min = 1,
2802 .channels_max = 6,
2803 .rates = WM8915_RATES,
2804 .formats = WM8915_FORMATS,
2805 },
2806 .capture = {
2807 .stream_name = "AIF1 Capture",
2808 .channels_min = 1,
2809 .channels_max = 6,
2810 .rates = WM8915_RATES,
2811 .formats = WM8915_FORMATS,
2812 },
2813 .ops = &wm8915_dai_ops,
2814 },
2815 {
2816 .name = "wm8915-aif2",
2817 .playback = {
2818 .stream_name = "AIF2 Playback",
2819 .channels_min = 1,
2820 .channels_max = 2,
2821 .rates = WM8915_RATES,
2822 .formats = WM8915_FORMATS,
2823 },
2824 .capture = {
2825 .stream_name = "AIF2 Capture",
2826 .channels_min = 1,
2827 .channels_max = 2,
2828 .rates = WM8915_RATES,
2829 .formats = WM8915_FORMATS,
2830 },
2831 .ops = &wm8915_dai_ops,
2832 },
2833};
2834
2835static __devinit int wm8915_i2c_probe(struct i2c_client *i2c,
2836 const struct i2c_device_id *id)
2837{
2838 struct wm8915_priv *wm8915;
2839 int ret;
2840
2841 wm8915 = kzalloc(sizeof(struct wm8915_priv), GFP_KERNEL);
2842 if (wm8915 == NULL)
2843 return -ENOMEM;
2844
2845 i2c_set_clientdata(i2c, wm8915);
2846
2847 if (dev_get_platdata(&i2c->dev))
2848 memcpy(&wm8915->pdata, dev_get_platdata(&i2c->dev),
2849 sizeof(wm8915->pdata));
2850
2851 if (wm8915->pdata.ldo_ena > 0) {
2852 ret = gpio_request_one(wm8915->pdata.ldo_ena,
2853 GPIOF_OUT_INIT_LOW, "WM8915 ENA");
2854 if (ret < 0) {
2855 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2856 wm8915->pdata.ldo_ena, ret);
2857 goto err;
2858 }
2859 }
2860
2861 ret = snd_soc_register_codec(&i2c->dev,
2862 &soc_codec_dev_wm8915, wm8915_dai,
2863 ARRAY_SIZE(wm8915_dai));
2864 if (ret < 0)
2865 goto err_gpio;
2866
2867 return ret;
2868
2869err_gpio:
2870 if (wm8915->pdata.ldo_ena > 0)
2871 gpio_free(wm8915->pdata.ldo_ena);
2872err:
2873 kfree(wm8915);
2874
2875 return ret;
2876}
2877
2878static __devexit int wm8915_i2c_remove(struct i2c_client *client)
2879{
2880 struct wm8915_priv *wm8915 = i2c_get_clientdata(client);
2881
2882 snd_soc_unregister_codec(&client->dev);
2883 if (wm8915->pdata.ldo_ena > 0)
2884 gpio_free(wm8915->pdata.ldo_ena);
2885 kfree(i2c_get_clientdata(client));
2886 return 0;
2887}
2888
2889static const struct i2c_device_id wm8915_i2c_id[] = {
2890 { "wm8915", 0 },
2891 { }
2892};
2893MODULE_DEVICE_TABLE(i2c, wm8915_i2c_id);
2894
2895static struct i2c_driver wm8915_i2c_driver = {
2896 .driver = {
2897 .name = "wm8915",
2898 .owner = THIS_MODULE,
2899 },
2900 .probe = wm8915_i2c_probe,
2901 .remove = __devexit_p(wm8915_i2c_remove),
2902 .id_table = wm8915_i2c_id,
2903};
2904
2905static int __init wm8915_modinit(void)
2906{
2907 int ret;
2908
2909 ret = i2c_add_driver(&wm8915_i2c_driver);
2910 if (ret != 0) {
2911 printk(KERN_ERR "Failed to register WM8915 I2C driver: %d\n",
2912 ret);
2913 }
2914
2915 return ret;
2916}
2917module_init(wm8915_modinit);
2918
2919static void __exit wm8915_exit(void)
2920{
2921 i2c_del_driver(&wm8915_i2c_driver);
2922}
2923module_exit(wm8915_exit);
2924
2925MODULE_DESCRIPTION("ASoC WM8915 driver");
2926MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2927MODULE_LICENSE("GPL");