blob: bec8bb297ad827bc8d756b1788d90129b13eb935 [file] [log] [blame]
Peter De Schrijveradd29e62011-10-12 14:53:05 +03001/dts-v1/;
2
Peter De Schrijveradd29e62011-10-12 14:53:05 +03003/include/ "tegra20.dtsi"
4
5/ {
6 model = "NVIDIA Tegra2 Ventana evaluation board";
7 compatible = "nvidia,ventana", "nvidia,tegra20";
8
Peter De Schrijveradd29e62011-10-12 14:53:05 +03009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Peter De Schrijveradd29e62011-10-12 14:53:05 +030011 };
12
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060013 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060014 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma", "gme";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gmb", "spia",
32 "spib", "spic";
33 nvidia,function = "gmi";
34 };
35 cdev1 {
36 nvidia,pins = "cdev1";
37 nvidia,function = "plla_out";
38 };
39 cdev2 {
40 nvidia,pins = "cdev2";
41 nvidia,function = "pllp_out4";
42 };
43 crtp {
44 nvidia,pins = "crtp", "lm1";
45 nvidia,function = "crt";
46 };
47 csus {
48 nvidia,pins = "csus";
49 nvidia,function = "vi_sensor_clk";
50 };
51 dap1 {
52 nvidia,pins = "dap1";
53 nvidia,function = "dap1";
54 };
55 dap2 {
56 nvidia,pins = "dap2";
57 nvidia,function = "dap2";
58 };
59 dap3 {
60 nvidia,pins = "dap3";
61 nvidia,function = "dap3";
62 };
63 dap4 {
64 nvidia,pins = "dap4";
65 nvidia,function = "dap4";
66 };
67 ddc {
68 nvidia,pins = "ddc", "owc", "spdi", "spdo",
69 "uac";
70 nvidia,function = "rsvd2";
71 };
72 dta {
73 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
74 nvidia,function = "vi";
75 };
76 dtf {
77 nvidia,pins = "dtf";
78 nvidia,function = "i2c3";
79 };
80 gmc {
81 nvidia,pins = "gmc";
82 nvidia,function = "uartd";
83 };
84 gmd {
85 nvidia,pins = "gmd";
86 nvidia,function = "sflash";
87 };
88 gpu {
89 nvidia,pins = "gpu";
90 nvidia,function = "pwm";
91 };
92 gpu7 {
93 nvidia,pins = "gpu7";
94 nvidia,function = "rtck";
95 };
96 gpv {
97 nvidia,pins = "gpv", "slxa", "slxk";
98 nvidia,function = "pcie";
99 };
100 hdint {
101 nvidia,pins = "hdint", "pta";
102 nvidia,function = "hdmi";
103 };
104 i2cp {
105 nvidia,pins = "i2cp";
106 nvidia,function = "i2cp";
107 };
108 irrx {
109 nvidia,pins = "irrx", "irtx";
110 nvidia,function = "uartb";
111 };
112 kbca {
113 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
114 "kbce", "kbcf";
115 nvidia,function = "kbc";
116 };
117 lcsn {
118 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
119 "lsdi", "lvp0";
120 nvidia,function = "rsvd4";
121 };
122 ld0 {
123 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
124 "ld5", "ld6", "ld7", "ld8", "ld9",
125 "ld10", "ld11", "ld12", "ld13", "ld14",
126 "ld15", "ld16", "ld17", "ldi", "lhp0",
127 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
128 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
129 "lspi", "lvp1", "lvs";
130 nvidia,function = "displaya";
131 };
132 pmc {
133 nvidia,pins = "pmc";
134 nvidia,function = "pwr_on";
135 };
136 rm {
137 nvidia,pins = "rm";
138 nvidia,function = "i2c1";
139 };
140 sdb {
141 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
142 nvidia,function = "sdio3";
143 };
144 sdio1 {
145 nvidia,pins = "sdio1";
146 nvidia,function = "sdio1";
147 };
148 slxd {
149 nvidia,pins = "slxd";
150 nvidia,function = "spdif";
151 };
152 spid {
153 nvidia,pins = "spid", "spie", "spif";
154 nvidia,function = "spi1";
155 };
156 spig {
157 nvidia,pins = "spig", "spih";
158 nvidia,function = "spi2_alt";
159 };
160 uaa {
161 nvidia,pins = "uaa", "uab", "uda";
162 nvidia,function = "ulpi";
163 };
164 uad {
165 nvidia,pins = "uad";
166 nvidia,function = "irda";
167 };
168 uca {
169 nvidia,pins = "uca", "ucb";
170 nvidia,function = "uartc";
171 };
172 conf_ata {
173 nvidia,pins = "ata", "atb", "atc", "atd",
174 "cdev1", "cdev2", "dap1", "dap2",
175 "dap4", "ddc", "dtf", "gma", "gmc",
176 "gme", "gpu", "gpu7", "i2cp", "irrx",
177 "irtx", "pta", "rm", "sdc", "sdd",
178 "slxc", "slxd", "slxk", "spdi", "spdo",
179 "uac", "uad", "uca", "ucb", "uda";
180 nvidia,pull = <0>;
181 nvidia,tristate = <0>;
182 };
183 conf_ate {
184 nvidia,pins = "ate", "csus", "dap3", "gmd",
185 "gpv", "owc", "spia", "spib", "spic",
186 "spid", "spie", "spig";
187 nvidia,pull = <0>;
188 nvidia,tristate = <1>;
189 };
190 conf_ck32 {
191 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
192 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
193 nvidia,pull = <0>;
194 };
195 conf_crtp {
196 nvidia,pins = "crtp", "gmb", "slxa", "spih";
197 nvidia,pull = <2>;
198 nvidia,tristate = <1>;
199 };
200 conf_dta {
201 nvidia,pins = "dta", "dtb", "dtc", "dtd";
202 nvidia,pull = <1>;
203 nvidia,tristate = <0>;
204 };
205 conf_dte {
206 nvidia,pins = "dte", "spif";
207 nvidia,pull = <1>;
208 nvidia,tristate = <1>;
209 };
210 conf_hdint {
211 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
212 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
213 nvidia,tristate = <1>;
214 };
215 conf_kbca {
216 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
217 "kbce", "kbcf", "sdio1", "uaa", "uab";
218 nvidia,pull = <2>;
219 nvidia,tristate = <0>;
220 };
221 conf_lc {
222 nvidia,pins = "lc", "ls";
223 nvidia,pull = <2>;
224 };
225 conf_ld0 {
226 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
227 "ld5", "ld6", "ld7", "ld8", "ld9",
228 "ld10", "ld11", "ld12", "ld13", "ld14",
229 "ld15", "ld16", "ld17", "ldi", "lhp0",
230 "lhp1", "lhp2", "lhs", "lm0", "lpp",
231 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
232 "lvp1", "lvs", "pmc", "sdb";
233 nvidia,tristate = <0>;
234 };
235 conf_ld17_0 {
236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
237 "ld23_22";
238 nvidia,pull = <1>;
239 };
Wei Nic7294292012-09-21 16:54:58 +0800240 drive_sdio1 {
241 nvidia,pins = "drive_sdio1";
242 nvidia,high-speed-mode = <0>;
243 nvidia,schmitt = <1>;
244 nvidia,low-power-mode = <3>;
245 nvidia,pull-down-strength = <31>;
246 nvidia,pull-up-strength = <31>;
247 nvidia,slew-rate-rising = <3>;
248 nvidia,slew-rate-falling = <3>;
249 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600250 };
251 };
252
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600253 i2s@70002800 {
254 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600255 };
256
257 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600258 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600259 clock-frequency = <216000000>;
260 };
261
Stephen Warren88950f32011-11-21 14:44:09 -0700262 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600263 status = "okay";
Stephen Warren88950f32011-11-21 14:44:09 -0700264 clock-frequency = <400000>;
Stephen Warren797acf72012-01-11 16:09:57 -0700265
266 wm8903: wm8903@1a {
267 compatible = "wlf,wm8903";
268 reg = <0x1a>;
269 interrupt-parent = <&gpio>;
Stephen Warren95decf82012-05-11 16:11:38 -0600270 interrupts = <187 0x04>;
Stephen Warren797acf72012-01-11 16:09:57 -0700271
272 gpio-controller;
273 #gpio-cells = <2>;
274
275 micdet-cfg = <0>;
276 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600277 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Stephen Warren797acf72012-01-11 16:09:57 -0700278 };
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530279
280 /* ALS and proximity sensor */
281 isl29018@44 {
282 compatible = "isil,isl29018";
283 reg = <0x44>;
284 interrupt-parent = <&gpio>;
285 interrupts = <202 0x04>; /*gpio PZ2 */
286 };
Stephen Warren88950f32011-11-21 14:44:09 -0700287 };
288
289 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600290 status = "okay";
Stephen Warren88950f32011-11-21 14:44:09 -0700291 clock-frequency = <400000>;
292 };
293
294 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600295 status = "okay";
Stephen Warren88950f32011-11-21 14:44:09 -0700296 clock-frequency = <400000>;
297 };
298
299 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600300 status = "okay";
Stephen Warren88950f32011-11-21 14:44:09 -0700301 clock-frequency = <400000>;
Stephen Warren017a0102012-06-20 16:53:41 -0600302
303 pmic: tps6586x@34 {
304 compatible = "ti,tps6586x";
305 reg = <0x34>;
306 interrupts = <0 86 0x4>;
307
Stephen Warren44b12ef2012-09-11 11:42:26 -0600308 ti,system-power-controller;
309
Stephen Warren017a0102012-06-20 16:53:41 -0600310 #gpio-cells = <2>;
311 gpio-controller;
312
313 sys-supply = <&vdd_5v0_reg>;
314 vin-sm0-supply = <&sys_reg>;
315 vin-sm1-supply = <&sys_reg>;
316 vin-sm2-supply = <&sys_reg>;
317 vinldo01-supply = <&sm2_reg>;
318 vinldo23-supply = <&sm2_reg>;
319 vinldo4-supply = <&sm2_reg>;
320 vinldo678-supply = <&sm2_reg>;
321 vinldo9-supply = <&sm2_reg>;
322
323 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600324 sys_reg: sys {
Stephen Warren017a0102012-06-20 16:53:41 -0600325 regulator-name = "vdd_sys";
326 regulator-always-on;
327 };
328
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600329 sm0 {
Stephen Warren017a0102012-06-20 16:53:41 -0600330 regulator-name = "vdd_sm0,vdd_core";
331 regulator-min-microvolt = <1200000>;
332 regulator-max-microvolt = <1200000>;
333 regulator-always-on;
334 };
335
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600336 sm1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600337 regulator-name = "vdd_sm1,vdd_cpu";
338 regulator-min-microvolt = <1000000>;
339 regulator-max-microvolt = <1000000>;
340 regulator-always-on;
341 };
342
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600343 sm2_reg: sm2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600344 regulator-name = "vdd_sm2,vin_ldo*";
345 regulator-min-microvolt = <3700000>;
346 regulator-max-microvolt = <3700000>;
347 regulator-always-on;
348 };
349
350 /* LDO0 is not connected to anything */
351
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600352 ldo1 {
Stephen Warren017a0102012-06-20 16:53:41 -0600353 regulator-name = "vdd_ldo1,avdd_pll*";
354 regulator-min-microvolt = <1100000>;
355 regulator-max-microvolt = <1100000>;
356 regulator-always-on;
357 };
358
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600359 ldo2 {
Stephen Warren017a0102012-06-20 16:53:41 -0600360 regulator-name = "vdd_ldo2,vdd_rtc";
361 regulator-min-microvolt = <1200000>;
362 regulator-max-microvolt = <1200000>;
363 };
364
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600365 ldo3 {
Stephen Warren017a0102012-06-20 16:53:41 -0600366 regulator-name = "vdd_ldo3,avdd_usb*";
367 regulator-min-microvolt = <3300000>;
368 regulator-max-microvolt = <3300000>;
369 regulator-always-on;
370 };
371
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600372 ldo4 {
Stephen Warren017a0102012-06-20 16:53:41 -0600373 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
374 regulator-min-microvolt = <1800000>;
375 regulator-max-microvolt = <1800000>;
376 regulator-always-on;
377 };
378
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600379 ldo5 {
Stephen Warren017a0102012-06-20 16:53:41 -0600380 regulator-name = "vdd_ldo5,vcore_mmc";
381 regulator-min-microvolt = <2850000>;
382 regulator-max-microvolt = <2850000>;
383 regulator-always-on;
384 };
385
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600386 ldo6 {
Stephen Warren017a0102012-06-20 16:53:41 -0600387 regulator-name = "vdd_ldo6,avdd_vdac";
388 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <1800000>;
390 };
391
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600392 ldo7 {
Stephen Warren017a0102012-06-20 16:53:41 -0600393 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
394 regulator-min-microvolt = <3300000>;
395 regulator-max-microvolt = <3300000>;
396 };
397
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600398 ldo8 {
Stephen Warren017a0102012-06-20 16:53:41 -0600399 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
400 regulator-min-microvolt = <1800000>;
401 regulator-max-microvolt = <1800000>;
402 };
403
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600404 ldo9 {
Stephen Warren017a0102012-06-20 16:53:41 -0600405 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
406 regulator-min-microvolt = <2850000>;
407 regulator-max-microvolt = <2850000>;
408 regulator-always-on;
409 };
410
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600411 ldo_rtc {
Stephen Warren017a0102012-06-20 16:53:41 -0600412 regulator-name = "vdd_rtc_out,vdd_cell";
413 regulator-min-microvolt = <3300000>;
414 regulator-max-microvolt = <3300000>;
415 regulator-always-on;
416 };
417 };
418 };
419 };
420
421 pmc {
422 nvidia,invert-interrupt;
Stephen Warren88950f32011-11-21 14:44:09 -0700423 };
424
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600425 usb@c5000000 {
426 status = "okay";
427 };
428
Stephen Warrenc04abb32012-05-11 17:03:26 -0600429 usb@c5004000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600430 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600431 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
432 };
433
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600434 usb@c5008000 {
435 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600436 };
437
Wei Nic7294292012-09-21 16:54:58 +0800438 sdhci@c8000000 {
439 status = "okay";
440 power-gpios = <&gpio 86 0>; /* gpio PK6 */
441 bus-width = <4>;
442 };
443
Stephen Warrenc04abb32012-05-11 17:03:26 -0600444 sdhci@c8000400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600445 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600446 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
447 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
448 power-gpios = <&gpio 70 0>; /* gpio PI6 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200449 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600450 };
451
452 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600453 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200454 bus-width = <8>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600455 };
456
Stephen Warren017a0102012-06-20 16:53:41 -0600457 regulators {
458 compatible = "simple-bus";
459 #address-cells = <1>;
460 #size-cells = <0>;
461
462 vdd_5v0_reg: regulator@0 {
463 compatible = "regulator-fixed";
464 reg = <0>;
465 regulator-name = "vdd_5v0";
466 regulator-min-microvolt = <5000000>;
467 regulator-max-microvolt = <5000000>;
468 regulator-always-on;
469 };
470
471 regulator@1 {
472 compatible = "regulator-fixed";
473 reg = <1>;
474 regulator-name = "vdd_1v5";
475 regulator-min-microvolt = <1500000>;
476 regulator-max-microvolt = <1500000>;
477 gpio = <&pmic 0 0>;
478 };
479
480 regulator@2 {
481 compatible = "regulator-fixed";
482 reg = <2>;
483 regulator-name = "vdd_1v2";
484 regulator-min-microvolt = <1200000>;
485 regulator-max-microvolt = <1200000>;
486 gpio = <&pmic 1 0>;
487 enable-active-high;
488 };
489
490 regulator@3 {
491 compatible = "regulator-fixed";
492 reg = <3>;
493 regulator-name = "vdd_pnl";
494 regulator-min-microvolt = <2800000>;
495 regulator-max-microvolt = <2800000>;
496 gpio = <&gpio 22 0>; /* gpio PC6 */
497 enable-active-high;
498 };
499
500 regulator@4 {
501 compatible = "regulator-fixed";
502 reg = <4>;
503 regulator-name = "vdd_bl";
504 regulator-min-microvolt = <2800000>;
505 regulator-max-microvolt = <2800000>;
506 gpio = <&gpio 176 0>; /* gpio PW0 */
507 enable-active-high;
508 };
509 };
510
Stephen Warren797acf72012-01-11 16:09:57 -0700511 sound {
512 compatible = "nvidia,tegra-audio-wm8903-ventana",
513 "nvidia,tegra-audio-wm8903";
514 nvidia,model = "NVIDIA Tegra Ventana";
515
516 nvidia,audio-routing =
517 "Headphone Jack", "HPOUTR",
518 "Headphone Jack", "HPOUTL",
519 "Int Spk", "ROP",
520 "Int Spk", "RON",
521 "Int Spk", "LOP",
522 "Int Spk", "LON",
523 "Mic Jack", "MICBIAS",
524 "IN1L", "Mic Jack";
525
526 nvidia,i2s-controller = <&tegra_i2s1>;
527 nvidia,audio-codec = <&wm8903>;
528
529 nvidia,spkr-en-gpios = <&wm8903 2 0>;
530 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
Stephen Warrenc44e4382012-05-11 16:21:10 -0600531 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
Stephen Warren797acf72012-01-11 16:09:57 -0700532 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
533 };
Peter De Schrijveradd29e62011-10-12 14:53:05 +0300534};