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review.evervolv.com / android_kernel_oneplus_msm8996 / c896ed0fd72505104db3e78fffe3d8c604d25277 / . / arch / arm / boot / dts / kirkwood.dtsi
blob: 2388f9936ebfd129f67524d4c27a1d2f46be8f72 [file] [log] [blame]
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]1/include/ "skeleton.dtsi"
2
3/ {
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]4 compatible = "marvell,kirkwood";
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]5 interrupt-parent = <&intc>;
6
7 intc: interrupt-controller {
8 compatible = "marvell,orion-intc", "marvell,intc";
9 interrupt-controller;
10 #interrupt-cells = <1>;
11 reg = <0xf1020204 0x04>,
12 <0xf1020214 0x04>;
13 };
Jason Cooper3d468b62012-02-27 16:07:13 +0000[diff] [blame]14
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]15 ocp@f1000000 {
16 compatible = "simple-bus";
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]17 ranges = <0x00000000 0xf1000000 0x4000000
18 0xf5000000 0xf5000000 0x0000400>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]19 #address-cells = <1>;
20 #size-cells = <1>;
21
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]22 core_clk: core-clocks@10030 {
23 compatible = "marvell,kirkwood-core-clock";
24 reg = <0x10030 0x4>;
25 #clock-cells = <1>;
26 };
27
Andrew Lunn278b45b2012-06-27 13:40:04 +0200[diff] [blame]28 gpio0: gpio@10100 {
29 compatible = "marvell,orion-gpio";
30 #gpio-cells = <2>;
31 gpio-controller;
32 reg = <0x10100 0x40>;
33 ngpio = <32>;
34 interrupts = <35>, <36>, <37>, <38>;
35 };
36
37 gpio1: gpio@10140 {
38 compatible = "marvell,orion-gpio";
39 #gpio-cells = <2>;
40 gpio-controller;
41 reg = <0x10140 0x40>;
42 ngpio = <18>;
43 interrupts = <39>, <40>, <41>;
44 };
45
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]46 serial@12000 {
47 compatible = "ns16550a";
48 reg = <0x12000 0x100>;
49 reg-shift = <2>;
50 interrupts = <33>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]51 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]52 /* set clock-frequency in board dts */
53 status = "disabled";
54 };
55
56 serial@12100 {
57 compatible = "ns16550a";
58 reg = <0x12100 0x100>;
59 reg-shift = <2>;
60 interrupts = <34>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]61 clocks = <&gate_clk 7>;
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]62 /* set clock-frequency in board dts */
63 status = "disabled";
64 };
Jason Coopere871b872012-03-06 23:55:04 +0000[diff] [blame]65
66 rtc@10300 {
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]67 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
Jason Coopere871b872012-03-06 23:55:04 +0000[diff] [blame]68 reg = <0x10300 0x20>;
69 interrupts = <53>;
70 };
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]71
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]72 spi@10600 {
73 compatible = "marvell,orion-spi";
74 #address-cells = <1>;
75 #size-cells = <0>;
76 cell-index = <0>;
77 interrupts = <23>;
78 reg = <0x10600 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]79 clocks = <&gate_clk 7>;
Michael Walle76372122012-06-06 20:30:57 +0200[diff] [blame]80 status = "disabled";
81 };
82
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]83 gate_clk: clock-gating-control@2011c {
84 compatible = "marvell,kirkwood-gating-clock";
85 reg = <0x2011c 0x4>;
86 clocks = <&core_clk 0>;
87 #clock-cells = <1>;
88 };
89
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]90 wdt@20300 {
91 compatible = "marvell,orion-wdt";
92 reg = <0x20300 0x28>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]93 clocks = <&gate_clk 7>;
Andrew Lunn1e7bad02012-06-10 15:20:06 +0200[diff] [blame]94 status = "okay";
95 };
96
Andrew Lunnc896ed02012-11-18 11:44:57 +0100[diff] [blame^]97 xor@60800 {
98 compatible = "marvell,orion-xor";
99 reg = <0x60800 0x100
100 0x60A00 0x100>;
101 status = "okay";
102 clocks = <&gate_clk 8>;
103
104 xor00 {
105 interrupts = <5>;
106 dmacap,memcpy;
107 dmacap,xor;
108 };
109 xor01 {
110 interrupts = <6>;
111 dmacap,memcpy;
112 dmacap,xor;
113 dmacap,memset;
114 };
115 };
116
117 xor@60900 {
118 compatible = "marvell,orion-xor";
119 reg = <0x60900 0x100
120 0xd0B00 0x100>;
121 status = "okay";
122 clocks = <&gate_clk 16>;
123
124 xor00 {
125 interrupts = <7>;
126 dmacap,memcpy;
127 dmacap,xor;
128 };
129 xor01 {
130 interrupts = <8>;
131 dmacap,memcpy;
132 dmacap,xor;
133 dmacap,memset;
134 };
135 };
136
Andrew Lunn97b414e2012-06-10 16:45:37 +0200[diff] [blame]137 sata@80000 {
138 compatible = "marvell,orion-sata";
139 reg = <0x80000 0x5000>;
140 interrupts = <21>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]141 clocks = <&gate_clk 14>, <&gate_clk 15>;
142 clock-names = "0", "1";
Andrew Lunn97b414e2012-06-10 16:45:37 +0200[diff] [blame]143 status = "disabled";
144 };
145
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]146 nand@3000000 {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 cle = <0>;
150 ale = <1>;
151 bank-width = <1>;
Andrew Lunn77843502012-07-18 19:22:54 +0200[diff] [blame]152 compatible = "marvell,orion-nand";
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]153 reg = <0x3000000 0x400>;
154 chip-delay = <25>;
155 /* set partition map and/or chip-delay in board dts */
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]156 clocks = <&gate_clk 7>;
Jamie Lentin858156b2012-04-18 11:06:42 +0100[diff] [blame]157 status = "disabled";
158 };
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]159
160 i2c@11000 {
161 compatible = "marvell,mv64xxx-i2c";
162 reg = <0x11000 0x20>;
163 #address-cells = <1>;
164 #size-cells = <0>;
165 interrupts = <29>;
166 clock-frequency = <100000>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]167 clocks = <&gate_clk 7>;
Andrew Lunne91cac02012-07-20 13:51:55 +0200[diff] [blame]168 status = "disabled";
169 };
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]170
171 crypto@30000 {
172 compatible = "marvell,orion-crypto";
173 reg = <0x30000 0x10000>,
174 <0xf5000000 0x800>;
175 reg-names = "regs", "sram";
176 interrupts = <22>;
Andrew Lunn1611f872012-11-17 15:22:28 +0100[diff] [blame]177 clocks = <&gate_clk 17>;
Andrew Lunnf37fbd32012-09-03 20:29:34 +0200[diff] [blame]178 status = "okay";
179 };
Jason Cooper163f2ce2012-03-15 01:00:27 +0000[diff] [blame]180 };
181};