| Atsushi Nemoto | b27311e | 2008-09-01 22:22:40 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Toshiba RBTX4939 interrupt routines |
| 3 | * Based on linux/arch/mips/txx9/rbtx4938/irq.c, |
| 4 | * and RBTX49xx patch from CELF patch archive. |
| 5 | * |
| 6 | * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation |
| 7 | * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the |
| 8 | * terms of the GNU General Public License version 2. This program is |
| 9 | * licensed "as is" without any warranty of any kind, whether express |
| 10 | * or implied. |
| 11 | */ |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/interrupt.h> |
| David Howells | ca4d3e67 | 2010-10-07 14:08:54 +0100 | [diff] [blame^] | 14 | #include <linux/irq.h> |
| Atsushi Nemoto | b27311e | 2008-09-01 22:22:40 +0900 | [diff] [blame] | 15 | #include <asm/mipsregs.h> |
| 16 | #include <asm/txx9/rbtx4939.h> |
| 17 | |
| 18 | /* |
| 19 | * RBTX4939 IOC controller definition |
| 20 | */ |
| 21 | |
| 22 | static void rbtx4939_ioc_irq_unmask(unsigned int irq) |
| 23 | { |
| 24 | int ioc_nr = irq - RBTX4939_IRQ_IOC; |
| 25 | |
| 26 | writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr); |
| 27 | } |
| 28 | |
| 29 | static void rbtx4939_ioc_irq_mask(unsigned int irq) |
| 30 | { |
| 31 | int ioc_nr = irq - RBTX4939_IRQ_IOC; |
| 32 | |
| 33 | writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr); |
| 34 | mmiowb(); |
| 35 | } |
| 36 | |
| 37 | static struct irq_chip rbtx4939_ioc_irq_chip = { |
| 38 | .name = "IOC", |
| 39 | .ack = rbtx4939_ioc_irq_mask, |
| 40 | .mask = rbtx4939_ioc_irq_mask, |
| 41 | .mask_ack = rbtx4939_ioc_irq_mask, |
| 42 | .unmask = rbtx4939_ioc_irq_unmask, |
| 43 | }; |
| 44 | |
| 45 | |
| 46 | static inline int rbtx4939_ioc_irqroute(void) |
| 47 | { |
| 48 | unsigned char istat = readb(rbtx4939_ifac2_addr); |
| 49 | |
| 50 | if (unlikely(istat == 0)) |
| 51 | return -1; |
| 52 | return RBTX4939_IRQ_IOC + __fls8(istat); |
| 53 | } |
| 54 | |
| 55 | static int rbtx4939_irq_dispatch(int pending) |
| 56 | { |
| 57 | int irq; |
| 58 | |
| 59 | if (pending & CAUSEF_IP7) |
| 60 | return MIPS_CPU_IRQ_BASE + 7; |
| 61 | irq = tx4939_irq(); |
| 62 | if (likely(irq >= 0)) { |
| 63 | /* redirect IOC interrupts */ |
| 64 | switch (irq) { |
| 65 | case RBTX4939_IRQ_IOCINT: |
| 66 | irq = rbtx4939_ioc_irqroute(); |
| 67 | break; |
| 68 | } |
| 69 | } else if (pending & CAUSEF_IP0) |
| 70 | irq = MIPS_CPU_IRQ_BASE + 0; |
| 71 | else if (pending & CAUSEF_IP1) |
| 72 | irq = MIPS_CPU_IRQ_BASE + 1; |
| 73 | else |
| 74 | irq = -1; |
| 75 | return irq; |
| 76 | } |
| 77 | |
| 78 | void __init rbtx4939_irq_setup(void) |
| 79 | { |
| 80 | int i; |
| 81 | |
| 82 | /* mask all IOC interrupts */ |
| 83 | writeb(0, rbtx4939_ien_addr); |
| 84 | |
| 85 | /* clear SoftInt interrupts */ |
| 86 | writeb(0, rbtx4939_softint_addr); |
| 87 | |
| 88 | txx9_irq_dispatch = rbtx4939_irq_dispatch; |
| 89 | |
| 90 | tx4939_irq_init(); |
| 91 | for (i = RBTX4939_IRQ_IOC; |
| 92 | i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++) |
| 93 | set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip, |
| 94 | handle_level_irq); |
| 95 | |
| 96 | set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq); |
| 97 | } |