| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 1996 Paul Mackerras. |
| 3 | */ |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | |
| 5 | #define GETREG(reg) \ |
| 6 | static inline int get_ ## reg (void) \ |
| 7 | { int ret; asm volatile ("mf" #reg " %0" : "=r" (ret) :); return ret; } |
| 8 | |
| 9 | #define SETREG(reg) \ |
| 10 | static inline void set_ ## reg (int val) \ |
| 11 | { asm volatile ("mt" #reg " %0" : : "r" (val)); } |
| 12 | |
| 13 | GETREG(msr) |
| 14 | SETREG(msr) |
| 15 | GETREG(cr) |
| 16 | |
| 17 | #define GSETSPR(n, name) \ |
| 18 | static inline int get_ ## name (void) \ |
| 19 | { int ret; asm volatile ("mfspr %0," #n : "=r" (ret) : ); return ret; } \ |
| 20 | static inline void set_ ## name (int val) \ |
| 21 | { asm volatile ("mtspr " #n ",%0" : : "r" (val)); } |
| 22 | |
| 23 | GSETSPR(0, mq) |
| 24 | GSETSPR(1, xer) |
| 25 | GSETSPR(4, rtcu) |
| 26 | GSETSPR(5, rtcl) |
| 27 | GSETSPR(8, lr) |
| 28 | GSETSPR(9, ctr) |
| 29 | GSETSPR(18, dsisr) |
| 30 | GSETSPR(19, dar) |
| 31 | GSETSPR(22, dec) |
| 32 | GSETSPR(25, sdr1) |
| 33 | GSETSPR(26, srr0) |
| 34 | GSETSPR(27, srr1) |
| 35 | GSETSPR(272, sprg0) |
| 36 | GSETSPR(273, sprg1) |
| 37 | GSETSPR(274, sprg2) |
| 38 | GSETSPR(275, sprg3) |
| 39 | GSETSPR(282, ear) |
| 40 | GSETSPR(287, pvr) |
| 41 | #ifndef CONFIG_8xx |
| 42 | GSETSPR(528, bat0u) |
| 43 | GSETSPR(529, bat0l) |
| 44 | GSETSPR(530, bat1u) |
| 45 | GSETSPR(531, bat1l) |
| 46 | GSETSPR(532, bat2u) |
| 47 | GSETSPR(533, bat2l) |
| 48 | GSETSPR(534, bat3u) |
| 49 | GSETSPR(535, bat3l) |
| 50 | GSETSPR(1008, hid0) |
| 51 | GSETSPR(1009, hid1) |
| 52 | GSETSPR(1010, iabr) |
| 53 | GSETSPR(1013, dabr) |
| 54 | GSETSPR(1023, pir) |
| 55 | #else |
| 56 | GSETSPR(144, cmpa) |
| 57 | GSETSPR(145, cmpb) |
| 58 | GSETSPR(146, cmpc) |
| 59 | GSETSPR(147, cmpd) |
| 60 | GSETSPR(158, ictrl) |
| 61 | #endif |
| 62 | |
| 63 | static inline int get_sr(int n) |
| 64 | { |
| 65 | int ret; |
| 66 | |
| 67 | asm (" mfsrin %0,%1" : "=r" (ret) : "r" (n << 28)); |
| 68 | return ret; |
| 69 | } |
| 70 | |
| 71 | static inline void set_sr(int n, int val) |
| 72 | { |
| 73 | asm ("mtsrin %0,%1" : : "r" (val), "r" (n << 28)); |
| 74 | } |
| 75 | |
| 76 | static inline void store_inst(void *p) |
| 77 | { |
| 78 | asm volatile ("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r" (p)); |
| 79 | } |
| 80 | |
| 81 | static inline void cflush(void *p) |
| 82 | { |
| 83 | asm volatile ("dcbf 0,%0; icbi 0,%0" : : "r" (p)); |
| 84 | } |
| 85 | |
| 86 | static inline void cinval(void *p) |
| 87 | { |
| 88 | asm volatile ("dcbi 0,%0; icbi 0,%0" : : "r" (p)); |
| 89 | } |
| 90 | |