| Magnus Damm | 9799165 | 2011-04-29 02:28:08 +0900 | [diff] [blame] | 1 | /* |
| 2 | * sh7372 lowlevel sleep code for "Core Standby Mode" |
| 3 | * |
| 4 | * Copyright (C) 2011 Magnus Damm |
| 5 | * |
| 6 | * In "Core Standby Mode" the ARM core is off, but L2 cache is still on |
| 7 | * |
| 8 | * Based on mach-omap2/sleep34xx.S |
| 9 | * |
| 10 | * (C) Copyright 2007 Texas Instruments |
| 11 | * Karthik Dasu <karthik-dp@ti.com> |
| 12 | * |
| 13 | * (C) Copyright 2004 Texas Instruments, <www.ti.com> |
| 14 | * Richard Woodruff <r-woodruff2@ti.com> |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or |
| 17 | * modify it under the terms of the GNU General Public License as |
| 18 | * published by the Free Software Foundation; either version 2 of |
| 19 | * the License, or (at your option) any later version. |
| 20 | * |
| 21 | * This program is distributed in the hope that it will be useful, |
| 22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
| 24 | * GNU General Public License for more details. |
| 25 | * |
| 26 | * You should have received a copy of the GNU General Public License |
| 27 | * along with this program; if not, write to the Free Software |
| 28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 29 | * MA 02111-1307 USA |
| 30 | */ |
| 31 | |
| 32 | #include <linux/linkage.h> |
| Magnus Damm | 06b8416 | 2011-09-25 23:18:42 +0200 | [diff] [blame] | 33 | #include <linux/init.h> |
| 34 | #include <asm/memory.h> |
| Magnus Damm | 9799165 | 2011-04-29 02:28:08 +0900 | [diff] [blame] | 35 | #include <asm/assembler.h> |
| 36 | |
| Magnus Damm | 9799165 | 2011-04-29 02:28:08 +0900 | [diff] [blame] | 37 | .align 12 |
| 38 | .text |
| Magnus Damm | cf33835 | 2011-09-25 23:20:49 +0200 | [diff] [blame^] | 39 | .global sh7372_resume_core_standby_a3sm |
| 40 | sh7372_resume_core_standby_a3sm: |
| Magnus Damm | 06b8416 | 2011-09-25 23:18:42 +0200 | [diff] [blame] | 41 | ldr pc, 1f |
| 42 | 1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET |
| Magnus Damm | cf33835 | 2011-09-25 23:20:49 +0200 | [diff] [blame^] | 43 | |
| 44 | .global sh7372_do_idle_a3sm |
| 45 | sh7372_do_idle_a3sm: |
| 46 | /* |
| 47 | * Clear the SCTLR.C bit to prevent further data cache |
| 48 | * allocation. Clearing SCTLR.C would make all the data accesses |
| 49 | * strongly ordered and would not hit the cache. |
| 50 | */ |
| 51 | mrc p15, 0, r0, c1, c0, 0 |
| 52 | bic r0, r0, #(1 << 2) @ Disable the C bit |
| 53 | mcr p15, 0, r0, c1, c0, 0 |
| 54 | isb |
| 55 | |
| 56 | /* disable L2 cache in the aux control register */ |
| 57 | mrc p15, 0, r10, c1, c0, 1 |
| 58 | bic r10, r10, #2 |
| 59 | mcr p15, 0, r10, c1, c0, 1 |
| 60 | |
| 61 | /* |
| 62 | * Invalidate data cache again. |
| 63 | */ |
| 64 | ldr r1, kernel_flush |
| 65 | blx r1 |
| 66 | /* |
| 67 | * The kernel doesn't interwork: v7_flush_dcache_all in particluar will |
| 68 | * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. |
| 69 | * This sequence switches back to ARM. Note that .align may insert a |
| 70 | * nop: bx pc needs to be word-aligned in order to work. |
| 71 | */ |
| 72 | THUMB( .thumb ) |
| 73 | THUMB( .align ) |
| 74 | THUMB( bx pc ) |
| 75 | THUMB( nop ) |
| 76 | .arm |
| 77 | |
| 78 | /* Data memory barrier and Data sync barrier */ |
| 79 | dsb |
| 80 | dmb |
| 81 | |
| 82 | #define SPDCR 0xe6180008 |
| 83 | #define A3SM (1 << 12) |
| 84 | |
| 85 | /* A3SM power down */ |
| 86 | ldr r0, =SPDCR |
| 87 | ldr r1, =A3SM |
| 88 | str r1, [r0] |
| 89 | 1: |
| 90 | b 1b |
| 91 | |
| 92 | kernel_flush: |
| 93 | .word v7_flush_dcache_all |