| Balaji Rao | 5ec271e | 2009-01-09 01:51:01 +0100 | [diff] [blame] | 1 | #ifndef __LINUX_MFD_PCF50633_PMIC_H | 
|  | 2 | #define __LINUX_MFD_PCF50633_PMIC_H | 
|  | 3 |  | 
|  | 4 | #include <linux/mfd/pcf50633/core.h> | 
|  | 5 | #include <linux/platform_device.h> | 
|  | 6 |  | 
|  | 7 | #define PCF50633_REG_AUTOOUT	0x1a | 
|  | 8 | #define PCF50633_REG_AUTOENA	0x1b | 
|  | 9 | #define PCF50633_REG_AUTOCTL	0x1c | 
|  | 10 | #define PCF50633_REG_AUTOMXC	0x1d | 
|  | 11 | #define PCF50633_REG_DOWN1OUT	0x1e | 
|  | 12 | #define PCF50633_REG_DOWN1ENA	0x1f | 
|  | 13 | #define PCF50633_REG_DOWN1CTL	0x20 | 
|  | 14 | #define PCF50633_REG_DOWN1MXC	0x21 | 
|  | 15 | #define PCF50633_REG_DOWN2OUT	0x22 | 
|  | 16 | #define PCF50633_REG_DOWN2ENA	0x23 | 
|  | 17 | #define PCF50633_REG_DOWN2CTL	0x24 | 
|  | 18 | #define PCF50633_REG_DOWN2MXC	0x25 | 
|  | 19 | #define PCF50633_REG_MEMLDOOUT	0x26 | 
|  | 20 | #define PCF50633_REG_MEMLDOENA	0x27 | 
|  | 21 | #define PCF50633_REG_LDO1OUT	0x2d | 
|  | 22 | #define PCF50633_REG_LDO1ENA	0x2e | 
|  | 23 | #define PCF50633_REG_LDO2OUT	0x2f | 
|  | 24 | #define PCF50633_REG_LDO2ENA	0x30 | 
|  | 25 | #define PCF50633_REG_LDO3OUT	0x31 | 
|  | 26 | #define PCF50633_REG_LDO3ENA	0x32 | 
|  | 27 | #define PCF50633_REG_LDO4OUT	0x33 | 
|  | 28 | #define PCF50633_REG_LDO4ENA	0x34 | 
|  | 29 | #define PCF50633_REG_LDO5OUT	0x35 | 
|  | 30 | #define PCF50633_REG_LDO5ENA	0x36 | 
|  | 31 | #define PCF50633_REG_LDO6OUT	0x37 | 
|  | 32 | #define PCF50633_REG_LDO6ENA	0x38 | 
|  | 33 | #define PCF50633_REG_HCLDOOUT	0x39 | 
|  | 34 | #define PCF50633_REG_HCLDOENA	0x3a | 
|  | 35 | #define PCF50633_REG_HCLDOOVL	0x40 | 
|  | 36 |  | 
|  | 37 | enum pcf50633_regulator_enable { | 
|  | 38 | PCF50633_REGULATOR_ON		= 0x01, | 
|  | 39 | PCF50633_REGULATOR_ON_GPIO1	= 0x02, | 
|  | 40 | PCF50633_REGULATOR_ON_GPIO2	= 0x04, | 
|  | 41 | PCF50633_REGULATOR_ON_GPIO3	= 0x08, | 
|  | 42 | }; | 
|  | 43 | #define PCF50633_REGULATOR_ON_MASK	0x0f | 
|  | 44 |  | 
|  | 45 | enum pcf50633_regulator_phase { | 
|  | 46 | PCF50633_REGULATOR_ACTPH1	= 0x00, | 
|  | 47 | PCF50633_REGULATOR_ACTPH2	= 0x10, | 
|  | 48 | PCF50633_REGULATOR_ACTPH3	= 0x20, | 
|  | 49 | PCF50633_REGULATOR_ACTPH4	= 0x30, | 
|  | 50 | }; | 
|  | 51 | #define PCF50633_REGULATOR_ACTPH_MASK	0x30 | 
|  | 52 |  | 
|  | 53 | enum pcf50633_regulator_id { | 
|  | 54 | PCF50633_REGULATOR_AUTO, | 
|  | 55 | PCF50633_REGULATOR_DOWN1, | 
|  | 56 | PCF50633_REGULATOR_DOWN2, | 
|  | 57 | PCF50633_REGULATOR_LDO1, | 
|  | 58 | PCF50633_REGULATOR_LDO2, | 
|  | 59 | PCF50633_REGULATOR_LDO3, | 
|  | 60 | PCF50633_REGULATOR_LDO4, | 
|  | 61 | PCF50633_REGULATOR_LDO5, | 
|  | 62 | PCF50633_REGULATOR_LDO6, | 
|  | 63 | PCF50633_REGULATOR_HCLDO, | 
|  | 64 | PCF50633_REGULATOR_MEMLDO, | 
|  | 65 | }; | 
|  | 66 | #endif | 
|  | 67 |  |