| Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| Juergen Beisert | d0f349f | 2008-07-05 10:02:50 +0200 | [diff] [blame^] | 3 | * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de) |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 |
| 8 | * of the License, or (at your option) any later version. |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
| 17 | * MA 02110-1301, USA. |
| Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #ifndef __ASM_ARCH_MXC_H__ |
| 21 | #define __ASM_ARCH_MXC_H__ |
| 22 | |
| 23 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ |
| 24 | #error "Do not include directly." |
| 25 | #endif |
| 26 | |
| Robert Schwebel | d2db9aa | 2008-04-02 10:29:30 +0100 | [diff] [blame] | 27 | /* clean up all things that are not used */ |
| 28 | #ifndef CONFIG_ARCH_MX3 |
| 29 | # define cpu_is_mx31() (0) |
| 30 | #endif |
| 31 | |
| Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 32 | /* |
| 33 | ***************************************** |
| Quinn Jensen | 52c543f | 2007-07-09 22:06:53 +0100 | [diff] [blame] | 34 | * AVIC Registers * |
| 35 | ***************************************** |
| 36 | */ |
| 37 | #define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR) |
| 38 | #define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */ |
| 39 | #define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */ |
| 40 | #define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */ |
| 41 | #define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */ |
| 42 | #define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */ |
| 43 | #define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */ |
| 44 | #define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */ |
| 45 | #define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */ |
| 46 | #define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */ |
| 47 | #define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */ |
| 48 | #define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */ |
| 49 | #define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */ |
| 50 | #define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */ |
| 51 | #define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */ |
| 52 | #define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */ |
| 53 | #define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */ |
| 54 | #define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */ |
| 55 | #define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */ |
| 56 | #define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */ |
| 57 | #define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */ |
| 58 | #define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */ |
| 59 | #define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */ |
| 60 | #define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */ |
| 61 | #define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */ |
| 62 | #define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */ |
| 63 | #define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */ |
| 64 | |
| 65 | #define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20) |
| 66 | #define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24) |
| 67 | #define IIM_PROD_REV_SH 3 |
| 68 | #define IIM_PROD_REV_LEN 5 |
| 69 | |
| Robert Schwebel | f304fc4 | 2008-03-28 10:59:08 +0100 | [diff] [blame] | 70 | #endif /* __ASM_ARCH_MXC_H__ */ |