| Kumar Gala | d0fc2ea | 2008-07-07 11:28:33 -0500 | [diff] [blame^] | 1 | * Freescale 83xx DMA Controller |
| 2 | |
| 3 | Freescale PowerPC 83xx have on chip general purpose DMA controllers. |
| 4 | |
| 5 | Required properties: |
| 6 | |
| 7 | - compatible : compatible list, contains 2 entries, first is |
| 8 | "fsl,CHIP-dma", where CHIP is the processor |
| 9 | (mpc8349, mpc8360, etc.) and the second is |
| 10 | "fsl,elo-dma" |
| 11 | - reg : <registers mapping for DMA general status reg> |
| 12 | - ranges : Should be defined as specified in 1) to describe the |
| 13 | DMA controller channels. |
| 14 | - cell-index : controller index. 0 for controller @ 0x8100 |
| 15 | - interrupts : <interrupt mapping for DMA IRQ> |
| 16 | - interrupt-parent : optional, if needed for interrupt mapping |
| 17 | |
| 18 | |
| 19 | - DMA channel nodes: |
| 20 | - compatible : compatible list, contains 2 entries, first is |
| 21 | "fsl,CHIP-dma-channel", where CHIP is the processor |
| 22 | (mpc8349, mpc8350, etc.) and the second is |
| 23 | "fsl,elo-dma-channel" |
| 24 | - reg : <registers mapping for channel> |
| 25 | - cell-index : dma channel index starts at 0. |
| 26 | |
| 27 | Optional properties: |
| 28 | - interrupts : <interrupt mapping for DMA channel IRQ> |
| 29 | (on 83xx this is expected to be identical to |
| 30 | the interrupts property of the parent node) |
| 31 | - interrupt-parent : optional, if needed for interrupt mapping |
| 32 | |
| 33 | Example: |
| 34 | dma@82a8 { |
| 35 | #address-cells = <1>; |
| 36 | #size-cells = <1>; |
| 37 | compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; |
| 38 | reg = <82a8 4>; |
| 39 | ranges = <0 8100 1a4>; |
| 40 | interrupt-parent = <&ipic>; |
| 41 | interrupts = <47 8>; |
| 42 | cell-index = <0>; |
| 43 | dma-channel@0 { |
| 44 | compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| 45 | cell-index = <0>; |
| 46 | reg = <0 80>; |
| 47 | }; |
| 48 | dma-channel@80 { |
| 49 | compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| 50 | cell-index = <1>; |
| 51 | reg = <80 80>; |
| 52 | }; |
| 53 | dma-channel@100 { |
| 54 | compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| 55 | cell-index = <2>; |
| 56 | reg = <100 80>; |
| 57 | }; |
| 58 | dma-channel@180 { |
| 59 | compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; |
| 60 | cell-index = <3>; |
| 61 | reg = <180 80>; |
| 62 | }; |
| 63 | }; |
| 64 | |
| 65 | * Freescale 85xx/86xx DMA Controller |
| 66 | |
| 67 | Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers. |
| 68 | |
| 69 | Required properties: |
| 70 | |
| 71 | - compatible : compatible list, contains 2 entries, first is |
| 72 | "fsl,CHIP-dma", where CHIP is the processor |
| 73 | (mpc8540, mpc8540, etc.) and the second is |
| 74 | "fsl,eloplus-dma" |
| 75 | - reg : <registers mapping for DMA general status reg> |
| 76 | - cell-index : controller index. 0 for controller @ 0x21000, |
| 77 | 1 for controller @ 0xc000 |
| 78 | - ranges : Should be defined as specified in 1) to describe the |
| 79 | DMA controller channels. |
| 80 | |
| 81 | - DMA channel nodes: |
| 82 | - compatible : compatible list, contains 2 entries, first is |
| 83 | "fsl,CHIP-dma-channel", where CHIP is the processor |
| 84 | (mpc8540, mpc8560, etc.) and the second is |
| 85 | "fsl,eloplus-dma-channel" |
| 86 | - cell-index : dma channel index starts at 0. |
| 87 | - reg : <registers mapping for channel> |
| 88 | - interrupts : <interrupt mapping for DMA channel IRQ> |
| 89 | - interrupt-parent : optional, if needed for interrupt mapping |
| 90 | |
| 91 | Example: |
| 92 | dma@21300 { |
| 93 | #address-cells = <1>; |
| 94 | #size-cells = <1>; |
| 95 | compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; |
| 96 | reg = <21300 4>; |
| 97 | ranges = <0 21100 200>; |
| 98 | cell-index = <0>; |
| 99 | dma-channel@0 { |
| 100 | compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; |
| 101 | reg = <0 80>; |
| 102 | cell-index = <0>; |
| 103 | interrupt-parent = <&mpic>; |
| 104 | interrupts = <14 2>; |
| 105 | }; |
| 106 | dma-channel@80 { |
| 107 | compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; |
| 108 | reg = <80 80>; |
| 109 | cell-index = <1>; |
| 110 | interrupt-parent = <&mpic>; |
| 111 | interrupts = <15 2>; |
| 112 | }; |
| 113 | dma-channel@100 { |
| 114 | compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; |
| 115 | reg = <100 80>; |
| 116 | cell-index = <2>; |
| 117 | interrupt-parent = <&mpic>; |
| 118 | interrupts = <16 2>; |
| 119 | }; |
| 120 | dma-channel@180 { |
| 121 | compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; |
| 122 | reg = <180 80>; |
| 123 | cell-index = <3>; |
| 124 | interrupt-parent = <&mpic>; |
| 125 | interrupts = <17 2>; |
| 126 | }; |
| 127 | }; |