Gitiles
Code Review Sign In
review.evervolv.com / android_kernel_oneplus_msm8996 / d2d50aa97d695d83ccb2341488d977e8cfe36555 / . / arch / blackfin / mach-bf561 / ints-priority.c
blob: 86e3b0ee93f426994498c330210e2232939b488a [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]1/*
2 * File: arch/blackfin/mach-bf561/ints-priority.c
3 * Based on: arch/blackfin/mach-bf537/ints-priority.c
4 * Author: Michael Hennerich
5 *
6 * Created:
Simon Arlottd2d50aa2007-06-11 15:31:30 +0800[diff] [blame^]7 * Description: Set up the interrupt priorities
Bryan Wu1394f032007-05-06 14:50:22 -0700[diff] [blame]8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <asm/blackfin.h>
32#include <asm/irq.h>
33
34void program_IAR(void)
35{
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SICA_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
38 ((CONFIG_IRQ_DMA1_ERROR - 7) << IRQ_DMA1_ERROR_POS) |
39 ((CONFIG_IRQ_DMA2_ERROR - 7) << IRQ_DMA2_ERROR_POS) |
40 ((CONFIG_IRQ_IMDMA_ERROR - 7) << IRQ_IMDMA_ERROR_POS) |
41 ((CONFIG_IRQ_PPI0_ERROR - 7) << IRQ_PPI0_ERROR_POS) |
42 ((CONFIG_IRQ_PPI1_ERROR - 7) << IRQ_PPI1_ERROR_POS) |
43 ((CONFIG_IRQ_SPORT0_ERROR - 7) << IRQ_SPORT0_ERROR_POS) |
44 ((CONFIG_IRQ_SPORT1_ERROR - 7) << IRQ_SPORT1_ERROR_POS));
45
46 bfin_write_SICA_IAR1(((CONFIG_IRQ_SPI_ERROR - 7) << IRQ_SPI_ERROR_POS) |
47 ((CONFIG_IRQ_UART_ERROR - 7) << IRQ_UART_ERROR_POS) |
48 ((CONFIG_IRQ_RESERVED_ERROR - 7) << IRQ_RESERVED_ERROR_POS) |
49 ((CONFIG_IRQ_DMA1_0 - 7) << IRQ_DMA1_0_POS) |
50 ((CONFIG_IRQ_DMA1_1 - 7) << IRQ_DMA1_1_POS) |
51 ((CONFIG_IRQ_DMA1_2 - 7) << IRQ_DMA1_2_POS) |
52 ((CONFIG_IRQ_DMA1_3 - 7) << IRQ_DMA1_3_POS) |
53 ((CONFIG_IRQ_DMA1_4 - 7) << IRQ_DMA1_4_POS));
54
55 bfin_write_SICA_IAR2(((CONFIG_IRQ_DMA1_5 - 7) << IRQ_DMA1_5_POS) |
56 ((CONFIG_IRQ_DMA1_6 - 7) << IRQ_DMA1_6_POS) |
57 ((CONFIG_IRQ_DMA1_7 - 7) << IRQ_DMA1_7_POS) |
58 ((CONFIG_IRQ_DMA1_8 - 7) << IRQ_DMA1_8_POS) |
59 ((CONFIG_IRQ_DMA1_9 - 7) << IRQ_DMA1_9_POS) |
60 ((CONFIG_IRQ_DMA1_10 - 7) << IRQ_DMA1_10_POS) |
61 ((CONFIG_IRQ_DMA1_11 - 7) << IRQ_DMA1_11_POS) |
62 ((CONFIG_IRQ_DMA2_0 - 7) << IRQ_DMA2_0_POS));
63
64 bfin_write_SICA_IAR3(((CONFIG_IRQ_DMA2_1 - 7) << IRQ_DMA2_1_POS) |
65 ((CONFIG_IRQ_DMA2_2 - 7) << IRQ_DMA2_2_POS) |
66 ((CONFIG_IRQ_DMA2_3 - 7) << IRQ_DMA2_3_POS) |
67 ((CONFIG_IRQ_DMA2_4 - 7) << IRQ_DMA2_4_POS) |
68 ((CONFIG_IRQ_DMA2_5 - 7) << IRQ_DMA2_5_POS) |
69 ((CONFIG_IRQ_DMA2_6 - 7) << IRQ_DMA2_6_POS) |
70 ((CONFIG_IRQ_DMA2_7 - 7) << IRQ_DMA2_7_POS) |
71 ((CONFIG_IRQ_DMA2_8 - 7) << IRQ_DMA2_8_POS));
72
73 bfin_write_SICA_IAR4(((CONFIG_IRQ_DMA2_9 - 7) << IRQ_DMA2_9_POS) |
74 ((CONFIG_IRQ_DMA2_10 - 7) << IRQ_DMA2_10_POS) |
75 ((CONFIG_IRQ_DMA2_11 - 7) << IRQ_DMA2_11_POS) |
76 ((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
77 ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS) |
78 ((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
79 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
80 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS));
81
82 bfin_write_SICA_IAR5(((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
83 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
84 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
85 ((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
86 ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
87 ((CONFIG_IRQ_TIMER10 - 7) << IRQ_TIMER10_POS) |
88 ((CONFIG_IRQ_TIMER11 - 7) << IRQ_TIMER11_POS) |
89 ((CONFIG_IRQ_PROG0_INTA - 7) << IRQ_PROG0_INTA_POS));
90
91 bfin_write_SICA_IAR6(((CONFIG_IRQ_PROG0_INTB - 7) << IRQ_PROG0_INTB_POS) |
92 ((CONFIG_IRQ_PROG1_INTA - 7) << IRQ_PROG1_INTA_POS) |
93 ((CONFIG_IRQ_PROG1_INTB - 7) << IRQ_PROG1_INTB_POS) |
94 ((CONFIG_IRQ_PROG2_INTA - 7) << IRQ_PROG2_INTA_POS) |
95 ((CONFIG_IRQ_PROG2_INTB - 7) << IRQ_PROG2_INTB_POS) |
96 ((CONFIG_IRQ_DMA1_WRRD0 - 7) << IRQ_DMA1_WRRD0_POS) |
97 ((CONFIG_IRQ_DMA1_WRRD1 - 7) << IRQ_DMA1_WRRD1_POS) |
98 ((CONFIG_IRQ_DMA2_WRRD0 - 7) << IRQ_DMA2_WRRD0_POS));
99
100 bfin_write_SICA_IAR7(((CONFIG_IRQ_DMA2_WRRD1 - 7) << IRQ_DMA2_WRRD1_POS) |
101 ((CONFIG_IRQ_IMDMA_WRRD0 - 7) << IRQ_IMDMA_WRRD0_POS) |
102 ((CONFIG_IRQ_IMDMA_WRRD1 - 7) << IRQ_IMDMA_WRRD1_POS) |
103 ((CONFIG_IRQ_WDTIMER - 7) << IRQ_WDTIMER_POS) |
104 (0 << IRQ_RESERVED_1_POS) | (0 << IRQ_RESERVED_2_POS) |
105 (0 << IRQ_SUPPLE_0_POS) | (0 << IRQ_SUPPLE_1_POS));
106
107 SSYNC();
108}