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Cyril Chemparathy4d1e7842010-05-18 12:51:19 -04001/*
2 * Texas Instruments TNETV107X SoC devices
3 *
4 * Copyright (C) 2010 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/dma-mapping.h>
19#include <linux/clk.h>
20#include <linux/slab.h>
21
22#include <mach/common.h>
23#include <mach/irqs.h>
24#include <mach/edma.h>
25#include <mach/tnetv107x.h>
26
27#include "clock.h"
28
29/* Base addresses for on-chip devices */
30#define TNETV107X_TPCC_BASE 0x01c00000
31#define TNETV107X_TPTC0_BASE 0x01c10000
32#define TNETV107X_TPTC1_BASE 0x01c10400
33#define TNETV107X_WDOG_BASE 0x08086700
34#define TNETV107X_SDIO0_BASE 0x08088700
35#define TNETV107X_SDIO1_BASE 0x08088800
Cyril Chemparathyd45b1ed2010-09-20 12:26:41 -040036#define TNETV107X_KEYPAD_BASE 0x08088a00
Cyril Chemparathy4d1e7842010-05-18 12:51:19 -040037#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000
38#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
39#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000
40#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000
41#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
42
43/* TNETV107X specific EDMA3 information */
44#define EDMA_TNETV107X_NUM_DMACH 64
45#define EDMA_TNETV107X_NUM_TCC 64
46#define EDMA_TNETV107X_NUM_PARAMENTRY 128
47#define EDMA_TNETV107X_NUM_EVQUE 2
48#define EDMA_TNETV107X_NUM_TC 2
49#define EDMA_TNETV107X_CHMAP_EXIST 0
50#define EDMA_TNETV107X_NUM_REGIONS 4
51#define TNETV107X_DMACH2EVENT_MAP0 0x3C0CE000u
52#define TNETV107X_DMACH2EVENT_MAP1 0x000FFFFFu
53
54#define TNETV107X_DMACH_SDIO0_RX 26
55#define TNETV107X_DMACH_SDIO0_TX 27
56#define TNETV107X_DMACH_SDIO1_RX 28
57#define TNETV107X_DMACH_SDIO1_TX 29
58
59static const s8 edma_tc_mapping[][2] = {
60 /* event queue no TC no */
61 { 0, 0 },
62 { 1, 1 },
63 { -1, -1 }
64};
65
66static const s8 edma_priority_mapping[][2] = {
67 /* event queue no Prio */
68 { 0, 3 },
69 { 1, 7 },
70 { -1, -1 }
71};
72
Sekhar Noribc3ac9f2010-06-29 11:35:12 +053073static struct edma_soc_info edma_cc0_info = {
74 .n_channel = EDMA_TNETV107X_NUM_DMACH,
75 .n_region = EDMA_TNETV107X_NUM_REGIONS,
76 .n_slot = EDMA_TNETV107X_NUM_PARAMENTRY,
77 .n_tc = EDMA_TNETV107X_NUM_TC,
78 .n_cc = 1,
79 .queue_tc_mapping = edma_tc_mapping,
80 .queue_priority_mapping = edma_priority_mapping,
81};
82
83static struct edma_soc_info *tnetv107x_edma_info[EDMA_MAX_CC] = {
84 &edma_cc0_info,
Cyril Chemparathy4d1e7842010-05-18 12:51:19 -040085};
86
87static struct resource edma_resources[] = {
88 {
89 .name = "edma_cc0",
90 .start = TNETV107X_TPCC_BASE,
91 .end = TNETV107X_TPCC_BASE + SZ_32K - 1,
92 .flags = IORESOURCE_MEM,
93 },
94 {
95 .name = "edma_tc0",
96 .start = TNETV107X_TPTC0_BASE,
97 .end = TNETV107X_TPTC0_BASE + SZ_1K - 1,
98 .flags = IORESOURCE_MEM,
99 },
100 {
101 .name = "edma_tc1",
102 .start = TNETV107X_TPTC1_BASE,
103 .end = TNETV107X_TPTC1_BASE + SZ_1K - 1,
104 .flags = IORESOURCE_MEM,
105 },
106 {
107 .name = "edma0",
108 .start = IRQ_TNETV107X_TPCC,
109 .flags = IORESOURCE_IRQ,
110 },
111 {
112 .name = "edma0_err",
113 .start = IRQ_TNETV107X_TPCC_ERR,
114 .flags = IORESOURCE_IRQ,
115 },
116};
117
118static struct platform_device edma_device = {
119 .name = "edma",
120 .id = -1,
121 .num_resources = ARRAY_SIZE(edma_resources),
122 .resource = edma_resources,
Sekhar Noribc3ac9f2010-06-29 11:35:12 +0530123 .dev.platform_data = tnetv107x_edma_info,
Cyril Chemparathy4d1e7842010-05-18 12:51:19 -0400124};
125
126static struct plat_serial8250_port serial_data[] = {
127 {
128 .mapbase = TNETV107X_UART0_BASE,
129 .irq = IRQ_TNETV107X_UART0,
130 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
131 UPF_FIXED_TYPE | UPF_IOREMAP,
132 .type = PORT_AR7,
133 .iotype = UPIO_MEM32,
134 .regshift = 2,
135 },
136 {
137 .mapbase = TNETV107X_UART1_BASE,
138 .irq = IRQ_TNETV107X_UART1,
139 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
140 UPF_FIXED_TYPE | UPF_IOREMAP,
141 .type = PORT_AR7,
142 .iotype = UPIO_MEM32,
143 .regshift = 2,
144 },
145 {
146 .mapbase = TNETV107X_UART2_BASE,
147 .irq = IRQ_TNETV107X_UART2,
148 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
149 UPF_FIXED_TYPE | UPF_IOREMAP,
150 .type = PORT_AR7,
151 .iotype = UPIO_MEM32,
152 .regshift = 2,
153 },
154 {
155 .flags = 0,
156 },
157};
158
159struct platform_device tnetv107x_serial_device = {
160 .name = "serial8250",
161 .id = PLAT8250_DEV_PLATFORM,
162 .dev.platform_data = serial_data,
163};
164
165static struct resource mmc0_resources[] = {
166 { /* Memory mapped registers */
167 .start = TNETV107X_SDIO0_BASE,
168 .end = TNETV107X_SDIO0_BASE + 0x0ff,
169 .flags = IORESOURCE_MEM
170 },
171 { /* MMC interrupt */
172 .start = IRQ_TNETV107X_MMC0,
173 .flags = IORESOURCE_IRQ
174 },
175 { /* SDIO interrupt */
176 .start = IRQ_TNETV107X_SDIO0,
177 .flags = IORESOURCE_IRQ
178 },
179 { /* DMA RX */
180 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_RX),
181 .flags = IORESOURCE_DMA
182 },
183 { /* DMA TX */
184 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO0_TX),
185 .flags = IORESOURCE_DMA
186 },
187};
188
189static struct resource mmc1_resources[] = {
190 { /* Memory mapped registers */
191 .start = TNETV107X_SDIO1_BASE,
192 .end = TNETV107X_SDIO1_BASE + 0x0ff,
193 .flags = IORESOURCE_MEM
194 },
195 { /* MMC interrupt */
196 .start = IRQ_TNETV107X_MMC1,
197 .flags = IORESOURCE_IRQ
198 },
199 { /* SDIO interrupt */
200 .start = IRQ_TNETV107X_SDIO1,
201 .flags = IORESOURCE_IRQ
202 },
203 { /* DMA RX */
204 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_RX),
205 .flags = IORESOURCE_DMA
206 },
207 { /* DMA TX */
208 .start = EDMA_CTLR_CHAN(0, TNETV107X_DMACH_SDIO1_TX),
209 .flags = IORESOURCE_DMA
210 },
211};
212
213static u64 mmc0_dma_mask = DMA_BIT_MASK(32);
214static u64 mmc1_dma_mask = DMA_BIT_MASK(32);
215
216static struct platform_device mmc_devices[2] = {
217 {
218 .name = "davinci_mmc",
219 .id = 0,
220 .dev = {
221 .dma_mask = &mmc0_dma_mask,
222 .coherent_dma_mask = DMA_BIT_MASK(32),
223 },
224 .num_resources = ARRAY_SIZE(mmc0_resources),
225 .resource = mmc0_resources
226 },
227 {
228 .name = "davinci_mmc",
229 .id = 1,
230 .dev = {
231 .dma_mask = &mmc1_dma_mask,
232 .coherent_dma_mask = DMA_BIT_MASK(32),
233 },
234 .num_resources = ARRAY_SIZE(mmc1_resources),
235 .resource = mmc1_resources
236 },
237};
238
239static const u32 emif_windows[] = {
240 TNETV107X_ASYNC_EMIF_DATA_CE0_BASE, TNETV107X_ASYNC_EMIF_DATA_CE1_BASE,
241 TNETV107X_ASYNC_EMIF_DATA_CE2_BASE, TNETV107X_ASYNC_EMIF_DATA_CE3_BASE,
242};
243
244static const u32 emif_window_sizes[] = { SZ_256M, SZ_64M, SZ_64M, SZ_64M };
245
246static struct resource wdt_resources[] = {
247 {
248 .start = TNETV107X_WDOG_BASE,
249 .end = TNETV107X_WDOG_BASE + SZ_4K - 1,
250 .flags = IORESOURCE_MEM,
251 },
252};
253
254struct platform_device tnetv107x_wdt_device = {
255 .name = "tnetv107x_wdt",
256 .id = 0,
257 .num_resources = ARRAY_SIZE(wdt_resources),
258 .resource = wdt_resources,
259};
260
261static int __init nand_init(int chipsel, struct davinci_nand_pdata *data)
262{
263 struct resource res[2];
264 struct platform_device *pdev;
265 u32 range;
266 int ret;
267
268 /* Figure out the resource range from the ale/cle masks */
269 range = max(data->mask_cle, data->mask_ale);
270 range = PAGE_ALIGN(range + 4) - 1;
271
272 if (range >= emif_window_sizes[chipsel])
273 return -EINVAL;
274
275 pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
276 if (!pdev)
277 return -ENOMEM;
278
279 pdev->name = "davinci_nand";
280 pdev->id = chipsel;
281 pdev->dev.platform_data = data;
282
283 memset(res, 0, sizeof(res));
284
285 res[0].start = emif_windows[chipsel];
286 res[0].end = res[0].start + range;
287 res[0].flags = IORESOURCE_MEM;
288
289 res[1].start = TNETV107X_ASYNC_EMIF_CNTRL_BASE;
290 res[1].end = res[1].start + SZ_4K - 1;
291 res[1].flags = IORESOURCE_MEM;
292
293 ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
294 if (ret < 0) {
295 kfree(pdev);
296 return ret;
297 }
298
299 return platform_device_register(pdev);
300}
301
Cyril Chemparathyd45b1ed2010-09-20 12:26:41 -0400302static struct resource keypad_resources[] = {
303 {
304 .start = TNETV107X_KEYPAD_BASE,
305 .end = TNETV107X_KEYPAD_BASE + 0xff,
306 .flags = IORESOURCE_MEM,
307 },
308 {
309 .start = IRQ_TNETV107X_KEYPAD,
310 .flags = IORESOURCE_IRQ,
311 .name = "press",
312 },
313 {
314 .start = IRQ_TNETV107X_KEYPAD_FREE,
315 .flags = IORESOURCE_IRQ,
316 .name = "release",
317 },
318};
319
320static struct platform_device keypad_device = {
321 .name = "tnetv107x-keypad",
322 .num_resources = ARRAY_SIZE(keypad_resources),
323 .resource = keypad_resources,
324};
325
Cyril Chemparathy4d1e7842010-05-18 12:51:19 -0400326void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
327{
328 int i;
329
330 platform_device_register(&edma_device);
331 platform_device_register(&tnetv107x_wdt_device);
332
333 if (info->serial_config)
334 davinci_serial_init(info->serial_config);
335
336 for (i = 0; i < 2; i++)
337 if (info->mmc_config[i]) {
338 mmc_devices[i].dev.platform_data = info->mmc_config[i];
339 platform_device_register(&mmc_devices[i]);
340 }
341
342 for (i = 0; i < 4; i++)
343 if (info->nand_config[i])
344 nand_init(i, info->nand_config[i]);
Cyril Chemparathyd45b1ed2010-09-20 12:26:41 -0400345
346 if (info->keypad_config) {
347 keypad_device.dev.platform_data = info->keypad_config;
348 platform_device_register(&keypad_device);
349 }
Cyril Chemparathy4d1e7842010-05-18 12:51:19 -0400350}