| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 1 | # | 
|  | 2 | #	EDAC Kconfig | 
| Doug Thompson | 4577ca5 | 2009-04-02 16:58:43 -0700 | [diff] [blame] | 3 | #	Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 4 | #	Licensed and distributed under the GPL | 
|  | 5 | # | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 6 |  | 
| Jan Engelhardt | 751cb5e | 2007-07-15 23:39:27 -0700 | [diff] [blame] | 7 | menuconfig EDAC | 
| GeunSik Lim | e24aca6 | 2009-06-17 16:28:02 -0700 | [diff] [blame] | 8 | bool "EDAC (Error Detection And Correction) reporting" | 
| Martin Schwidefsky | e25df12 | 2007-05-10 15:45:57 +0200 | [diff] [blame] | 9 | depends on HAS_IOMEM | 
| Andrew Morton | 4c6a1c1 | 2007-07-26 10:41:10 -0700 | [diff] [blame] | 10 | depends on X86 || PPC | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 11 | help | 
|  | 12 | EDAC is designed to report errors in the core system. | 
|  | 13 | These are low-level errors that are reported in the CPU or | 
| Douglas Thompson | 8cb2a39 | 2007-07-19 01:50:12 -0700 | [diff] [blame] | 14 | supporting chipset or other subsystems: | 
|  | 15 | memory errors, cache errors, PCI errors, thermal throttling, etc.. | 
|  | 16 | If unsure, select 'Y'. | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 17 |  | 
| Tim Small | 57c432b | 2006-03-09 17:33:50 -0800 | [diff] [blame] | 18 | If this code is reporting problems on your system, please | 
|  | 19 | see the EDAC project web pages for more information at: | 
|  | 20 |  | 
|  | 21 | <http://bluesmoke.sourceforge.net/> | 
|  | 22 |  | 
|  | 23 | and: | 
|  | 24 |  | 
|  | 25 | <http://buttersideup.com/edacwiki> | 
|  | 26 |  | 
|  | 27 | There is also a mailing list for the EDAC project, which can | 
|  | 28 | be found via the sourceforge page. | 
|  | 29 |  | 
| Jan Engelhardt | 751cb5e | 2007-07-15 23:39:27 -0700 | [diff] [blame] | 30 | if EDAC | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 31 |  | 
|  | 32 | comment "Reporting subsystems" | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 33 |  | 
|  | 34 | config EDAC_DEBUG | 
|  | 35 | bool "Debugging" | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 36 | help | 
|  | 37 | This turns on debugging information for the entire EDAC | 
|  | 38 | sub-system. You can insert module with "debug_level=x", current | 
|  | 39 | there're four debug levels (x=0,1,2,3 from low to high). | 
|  | 40 | Usually you should select 'N'. | 
|  | 41 |  | 
| Hitoshi Mitake | cc18e3c | 2009-04-02 16:58:43 -0700 | [diff] [blame] | 42 | config EDAC_DEBUG_VERBOSE | 
|  | 43 | bool "More verbose debugging" | 
|  | 44 | depends on EDAC_DEBUG | 
|  | 45 | help | 
|  | 46 | This option makes debugging information more verbose. | 
|  | 47 | Source file name and line number where debugging message | 
|  | 48 | printed will be added to debugging message. | 
|  | 49 |  | 
| Borislav Petkov | 0d18b2e | 2009-10-02 15:31:48 +0200 | [diff] [blame] | 50 | config EDAC_DECODE_MCE | 
|  | 51 | tristate "Decode MCEs in human-readable form (only on AMD for now)" | 
|  | 52 | depends on CPU_SUP_AMD && X86_MCE | 
|  | 53 | default y | 
|  | 54 | ---help--- | 
|  | 55 | Enable this option if you want to decode Machine Check Exceptions | 
|  | 56 | occuring on your machine in human-readable form. | 
|  | 57 |  | 
|  | 58 | You should definitely say Y here in case you want to decode MCEs | 
|  | 59 | which occur really early upon boot, before the module infrastructure | 
|  | 60 | has been initialized. | 
|  | 61 |  | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 62 | config EDAC_MM_EDAC | 
|  | 63 | tristate "Main Memory EDAC (Error Detection And Correction) reporting" | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 64 | help | 
|  | 65 | Some systems are able to detect and correct errors in main | 
|  | 66 | memory.  EDAC can report statistics on memory error | 
|  | 67 | detection and correction (EDAC - or commonly referred to ECC | 
|  | 68 | errors).  EDAC will also try to decode where these errors | 
|  | 69 | occurred so that a particular failing memory module can be | 
|  | 70 | replaced.  If unsure, select 'Y'. | 
|  | 71 |  | 
| Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 72 | config EDAC_AMD64 | 
|  | 73 | tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h" | 
| Borislav Petkov | 0d18b2e | 2009-10-02 15:31:48 +0200 | [diff] [blame] | 74 | depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE | 
| Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 75 | help | 
| Borislav Petkov | 3d37329 | 2009-05-20 20:18:46 +0200 | [diff] [blame] | 76 | Support for error detection and correction on the AMD 64 | 
|  | 77 | Families of Memory Controllers (K8, F10h and F11h) | 
| Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 78 |  | 
|  | 79 | config EDAC_AMD64_ERROR_INJECTION | 
|  | 80 | bool "Sysfs Error Injection facilities" | 
|  | 81 | depends on EDAC_AMD64 | 
|  | 82 | help | 
|  | 83 | Recent Opterons (Family 10h and later) provide for Memory Error | 
|  | 84 | Injection into the ECC detection circuits. The amd64_edac module | 
|  | 85 | allows the operator/user to inject Uncorrectable and Correctable | 
|  | 86 | errors into DRAM. | 
|  | 87 |  | 
|  | 88 | When enabled, in each of the respective memory controller directories | 
|  | 89 | (/sys/devices/system/edac/mc/mcX), there are 3 input files: | 
|  | 90 |  | 
|  | 91 | - inject_section (0..3, 16-byte section of 64-byte cacheline), | 
|  | 92 | - inject_word (0..8, 16-bit word of 16-byte section), | 
|  | 93 | - inject_ecc_vector (hex ecc vector: select bits of inject word) | 
|  | 94 |  | 
|  | 95 | In addition, there are two control files, inject_read and inject_write, | 
|  | 96 | which trigger the DRAM ECC Read and Write respectively. | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 97 |  | 
|  | 98 | config EDAC_AMD76X | 
|  | 99 | tristate "AMD 76x (760, 762, 768)" | 
| Dave Jones | 90cbc45 | 2006-02-03 03:04:11 -0800 | [diff] [blame] | 100 | depends on EDAC_MM_EDAC && PCI && X86_32 | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 101 | help | 
|  | 102 | Support for error detection and correction on the AMD 76x | 
|  | 103 | series of chipsets used with the Athlon processor. | 
|  | 104 |  | 
|  | 105 | config EDAC_E7XXX | 
|  | 106 | tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" | 
| Dave Peterson | 39f1d8d | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 107 | depends on EDAC_MM_EDAC && PCI && X86_32 | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 108 | help | 
|  | 109 | Support for error detection and correction on the Intel | 
|  | 110 | E7205, E7500, E7501 and E7505 server chipsets. | 
|  | 111 |  | 
|  | 112 | config EDAC_E752X | 
| Andrei Konovalov | 5135b79 | 2008-04-29 01:03:13 -0700 | [diff] [blame] | 113 | tristate "Intel e752x (e7520, e7525, e7320) and 3100" | 
| Randy Dunlap | da960a6 | 2006-03-31 02:30:34 -0800 | [diff] [blame] | 114 | depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 115 | help | 
|  | 116 | Support for error detection and correction on the Intel | 
|  | 117 | E7520, E7525, E7320 server chipsets. | 
|  | 118 |  | 
| Tim Small | 5a2c675 | 2007-07-19 01:49:42 -0700 | [diff] [blame] | 119 | config EDAC_I82443BXGX | 
|  | 120 | tristate "Intel 82443BX/GX (440BX/GX)" | 
|  | 121 | depends on EDAC_MM_EDAC && PCI && X86_32 | 
| Andrew Morton | 28f96eea | 2007-07-19 01:49:45 -0700 | [diff] [blame] | 122 | depends on BROKEN | 
| Tim Small | 5a2c675 | 2007-07-19 01:49:42 -0700 | [diff] [blame] | 123 | help | 
|  | 124 | Support for error detection and correction on the Intel | 
|  | 125 | 82443BX/GX memory controllers (440BX/GX chipsets). | 
|  | 126 |  | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 127 | config EDAC_I82875P | 
|  | 128 | tristate "Intel 82875p (D82875P, E7210)" | 
| Dave Peterson | 39f1d8d | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 129 | depends on EDAC_MM_EDAC && PCI && X86_32 | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 130 | help | 
|  | 131 | Support for error detection and correction on the Intel | 
|  | 132 | DP82785P and E7210 server chipsets. | 
|  | 133 |  | 
| Ranganathan Desikan | 420390f | 2007-07-19 01:50:31 -0700 | [diff] [blame] | 134 | config EDAC_I82975X | 
|  | 135 | tristate "Intel 82975x (D82975x)" | 
|  | 136 | depends on EDAC_MM_EDAC && PCI && X86 | 
|  | 137 | help | 
|  | 138 | Support for error detection and correction on the Intel | 
|  | 139 | DP82975x server chipsets. | 
|  | 140 |  | 
| Jason Uhlenkott | 535c6a5 | 2007-07-19 01:49:48 -0700 | [diff] [blame] | 141 | config EDAC_I3000 | 
|  | 142 | tristate "Intel 3000/3010" | 
| Jason Uhlenkott | f5c0454 | 2008-02-07 00:15:01 -0800 | [diff] [blame] | 143 | depends on EDAC_MM_EDAC && PCI && X86 | 
| Jason Uhlenkott | 535c6a5 | 2007-07-19 01:49:48 -0700 | [diff] [blame] | 144 | help | 
|  | 145 | Support for error detection and correction on the Intel | 
|  | 146 | 3000 and 3010 server chipsets. | 
|  | 147 |  | 
| Jason Uhlenkott | dd8ef1d | 2009-09-23 15:57:27 -0700 | [diff] [blame] | 148 | config EDAC_I3200 | 
|  | 149 | tristate "Intel 3200" | 
|  | 150 | depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL | 
|  | 151 | help | 
|  | 152 | Support for error detection and correction on the Intel | 
|  | 153 | 3200 and 3210 server chipsets. | 
|  | 154 |  | 
| Hitoshi Mitake | df8bc08 | 2008-10-29 14:00:50 -0700 | [diff] [blame] | 155 | config EDAC_X38 | 
|  | 156 | tristate "Intel X38" | 
|  | 157 | depends on EDAC_MM_EDAC && PCI && X86 | 
|  | 158 | help | 
|  | 159 | Support for error detection and correction on the Intel | 
|  | 160 | X38 server chipsets. | 
|  | 161 |  | 
| Mauro Carvalho Chehab | 920c8df | 2009-01-06 14:43:00 -0800 | [diff] [blame] | 162 | config EDAC_I5400 | 
|  | 163 | tristate "Intel 5400 (Seaburg) chipsets" | 
|  | 164 | depends on EDAC_MM_EDAC && PCI && X86 | 
|  | 165 | help | 
|  | 166 | Support for error detection and correction the Intel | 
|  | 167 | i5400 MCH chipset (Seaburg). | 
|  | 168 |  | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 169 | config EDAC_I82860 | 
|  | 170 | tristate "Intel 82860" | 
| Dave Peterson | 39f1d8d | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 171 | depends on EDAC_MM_EDAC && PCI && X86_32 | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 172 | help | 
|  | 173 | Support for error detection and correction on the Intel | 
|  | 174 | 82860 chipset. | 
|  | 175 |  | 
|  | 176 | config EDAC_R82600 | 
|  | 177 | tristate "Radisys 82600 embedded chipset" | 
| Dave Peterson | 39f1d8d | 2006-03-26 01:38:50 -0800 | [diff] [blame] | 178 | depends on EDAC_MM_EDAC && PCI && X86_32 | 
| Alan Cox | da9bb1d | 2006-01-18 17:44:13 -0800 | [diff] [blame] | 179 | help | 
|  | 180 | Support for error detection and correction on the Radisys | 
|  | 181 | 82600 embedded chipset. | 
|  | 182 |  | 
| Eric Wollesen | eb60705 | 2007-07-19 01:49:39 -0700 | [diff] [blame] | 183 | config EDAC_I5000 | 
|  | 184 | tristate "Intel Greencreek/Blackford chipset" | 
|  | 185 | depends on EDAC_MM_EDAC && X86 && PCI | 
|  | 186 | help | 
|  | 187 | Support for error detection and correction the Intel | 
|  | 188 | Greekcreek/Blackford chipsets. | 
|  | 189 |  | 
| Arthur Jones | 8f421c59 | 2008-07-25 01:49:04 -0700 | [diff] [blame] | 190 | config EDAC_I5100 | 
|  | 191 | tristate "Intel San Clemente MCH" | 
|  | 192 | depends on EDAC_MM_EDAC && X86 && PCI | 
|  | 193 | help | 
|  | 194 | Support for error detection and correction the Intel | 
|  | 195 | San Clemente MCH. | 
|  | 196 |  | 
| Dave Jiang | a9a753d | 2008-02-07 00:14:55 -0800 | [diff] [blame] | 197 | config EDAC_MPC85XX | 
| Ira W. Snyder | b484625 | 2009-09-23 15:57:25 -0700 | [diff] [blame] | 198 | tristate "Freescale MPC83xx / MPC85xx" | 
|  | 199 | depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || MPC85xx) | 
| Dave Jiang | a9a753d | 2008-02-07 00:14:55 -0800 | [diff] [blame] | 200 | help | 
|  | 201 | Support for error detection and correction on the Freescale | 
| Ira W. Snyder | b484625 | 2009-09-23 15:57:25 -0700 | [diff] [blame] | 202 | MPC8349, MPC8560, MPC8540, MPC8548 | 
| Dave Jiang | a9a753d | 2008-02-07 00:14:55 -0800 | [diff] [blame] | 203 |  | 
| Dave Jiang | 4f4aeea | 2008-02-07 00:14:56 -0800 | [diff] [blame] | 204 | config EDAC_MV64X60 | 
|  | 205 | tristate "Marvell MV64x60" | 
|  | 206 | depends on EDAC_MM_EDAC && MV64X60 | 
|  | 207 | help | 
|  | 208 | Support for error detection and correction on the Marvell | 
|  | 209 | MV64360 and MV64460 chipsets. | 
|  | 210 |  | 
| Egor Martovetsky | 7d8536f | 2007-07-19 01:50:24 -0700 | [diff] [blame] | 211 | config EDAC_PASEMI | 
|  | 212 | tristate "PA Semi PWRficient" | 
|  | 213 | depends on EDAC_MM_EDAC && PCI | 
| Doug Thompson | ddcc305 | 2007-07-26 10:41:16 -0700 | [diff] [blame] | 214 | depends on PPC_PASEMI | 
| Egor Martovetsky | 7d8536f | 2007-07-19 01:50:24 -0700 | [diff] [blame] | 215 | help | 
|  | 216 | Support for error detection and correction on PA Semi | 
|  | 217 | PWRficient. | 
|  | 218 |  | 
| Benjamin Herrenschmidt | 48764e4 | 2008-02-07 00:14:53 -0800 | [diff] [blame] | 219 | config EDAC_CELL | 
|  | 220 | tristate "Cell Broadband Engine memory controller" | 
| Benjamin Krill | def434c | 2008-11-27 16:15:44 +0100 | [diff] [blame] | 221 | depends on EDAC_MM_EDAC && PPC_CELL_COMMON | 
| Benjamin Herrenschmidt | 48764e4 | 2008-02-07 00:14:53 -0800 | [diff] [blame] | 222 | help | 
|  | 223 | Support for error detection and correction on the | 
|  | 224 | Cell Broadband Engine internal memory controller | 
|  | 225 | on platform without a hypervisor | 
| Egor Martovetsky | 7d8536f | 2007-07-19 01:50:24 -0700 | [diff] [blame] | 226 |  | 
| Grant Erickson | dba7a77 | 2009-04-02 16:58:45 -0700 | [diff] [blame] | 227 | config EDAC_PPC4XX | 
|  | 228 | tristate "PPC4xx IBM DDR2 Memory Controller" | 
|  | 229 | depends on EDAC_MM_EDAC && 4xx | 
|  | 230 | help | 
|  | 231 | This enables support for EDAC on the ECC memory used | 
|  | 232 | with the IBM DDR2 memory controller found in various | 
|  | 233 | PowerPC 4xx embedded processors such as the 405EX[r], | 
|  | 234 | 440SP, 440SPe, 460EX, 460GT and 460SX. | 
|  | 235 |  | 
| Harry Ciao | e876558 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 236 | config EDAC_AMD8131 | 
|  | 237 | tristate "AMD8131 HyperTransport PCI-X Tunnel" | 
| Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 238 | depends on EDAC_MM_EDAC && PCI && PPC_MAPLE | 
| Harry Ciao | e876558 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 239 | help | 
|  | 240 | Support for error detection and correction on the | 
|  | 241 | AMD8131 HyperTransport PCI-X Tunnel chip. | 
| Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 242 | Note, add more Kconfig dependency if it's adopted | 
|  | 243 | on some machine other than Maple. | 
| Harry Ciao | e876558 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 244 |  | 
| Harry Ciao | 58b4ce6 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 245 | config EDAC_AMD8111 | 
|  | 246 | tristate "AMD8111 HyperTransport I/O Hub" | 
| Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 247 | depends on EDAC_MM_EDAC && PCI && PPC_MAPLE | 
| Harry Ciao | 58b4ce6 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 248 | help | 
|  | 249 | Support for error detection and correction on the | 
|  | 250 | AMD8111 HyperTransport I/O Hub chip. | 
| Harry Ciao | 715fe7a | 2009-05-28 14:34:43 -0700 | [diff] [blame] | 251 | Note, add more Kconfig dependency if it's adopted | 
|  | 252 | on some machine other than Maple. | 
| Harry Ciao | 58b4ce6 | 2009-04-02 16:58:51 -0700 | [diff] [blame] | 253 |  | 
| Harry Ciao | 2a9036a | 2009-06-17 16:27:58 -0700 | [diff] [blame] | 254 | config EDAC_CPC925 | 
|  | 255 | tristate "IBM CPC925 Memory Controller (PPC970FX)" | 
|  | 256 | depends on EDAC_MM_EDAC && PPC64 | 
|  | 257 | help | 
|  | 258 | Support for error detection and correction on the | 
|  | 259 | IBM CPC925 Bridge and Memory Controller, which is | 
|  | 260 | a companion chip to the PowerPC 970 family of | 
|  | 261 | processors. | 
|  | 262 |  | 
| Jan Engelhardt | 751cb5e | 2007-07-15 23:39:27 -0700 | [diff] [blame] | 263 | endif # EDAC |