blob: de30b190972811f737222a341cf3bacb78a71f67 [file] [log] [blame]
Maxime Bizon9fcd66e2009-09-18 13:04:58 +02001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Derived from many drivers using generic_serial interface.
7 *
8 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
9 *
10 * Serial driver for BCM63xx integrated UART.
11 *
12 * Hardware flow control was _not_ tested since I only have RX/TX on
13 * my board.
14 */
15
16#if defined(CONFIG_SERIAL_BCM63XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
17#define SUPPORT_SYSRQ
18#endif
19
20#include <linux/kernel.h>
21#include <linux/platform_device.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/module.h>
25#include <linux/console.h>
26#include <linux/clk.h>
27#include <linux/tty.h>
28#include <linux/tty_flip.h>
29#include <linux/sysrq.h>
30#include <linux/serial.h>
31#include <linux/serial_core.h>
32
33#include <bcm63xx_clk.h>
34#include <bcm63xx_irq.h>
35#include <bcm63xx_regs.h>
36#include <bcm63xx_io.h>
37
Maxime Bizon6a2c7ea2010-01-30 18:42:57 +010038#define BCM63XX_NR_UARTS 2
Maxime Bizon9fcd66e2009-09-18 13:04:58 +020039
40static struct uart_port ports[BCM63XX_NR_UARTS];
41
42/*
43 * rx interrupt mask / stat
44 *
45 * mask:
46 * - rx fifo full
47 * - rx fifo above threshold
48 * - rx fifo not empty for too long
49 */
50#define UART_RX_INT_MASK (UART_IR_MASK(UART_IR_RXOVER) | \
51 UART_IR_MASK(UART_IR_RXTHRESH) | \
52 UART_IR_MASK(UART_IR_RXTIMEOUT))
53
54#define UART_RX_INT_STAT (UART_IR_STAT(UART_IR_RXOVER) | \
55 UART_IR_STAT(UART_IR_RXTHRESH) | \
56 UART_IR_STAT(UART_IR_RXTIMEOUT))
57
58/*
59 * tx interrupt mask / stat
60 *
61 * mask:
62 * - tx fifo empty
63 * - tx fifo below threshold
64 */
65#define UART_TX_INT_MASK (UART_IR_MASK(UART_IR_TXEMPTY) | \
66 UART_IR_MASK(UART_IR_TXTRESH))
67
68#define UART_TX_INT_STAT (UART_IR_STAT(UART_IR_TXEMPTY) | \
69 UART_IR_STAT(UART_IR_TXTRESH))
70
71/*
72 * external input interrupt
73 *
74 * mask: any edge on CTS, DCD
75 */
76#define UART_EXTINP_INT_MASK (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \
77 UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD))
78
79/*
80 * handy uart register accessor
81 */
82static inline unsigned int bcm_uart_readl(struct uart_port *port,
83 unsigned int offset)
84{
85 return bcm_readl(port->membase + offset);
86}
87
88static inline void bcm_uart_writel(struct uart_port *port,
89 unsigned int value, unsigned int offset)
90{
91 bcm_writel(value, port->membase + offset);
92}
93
94/*
95 * serial core request to check if uart tx fifo is empty
96 */
97static unsigned int bcm_uart_tx_empty(struct uart_port *port)
98{
99 unsigned int val;
100
101 val = bcm_uart_readl(port, UART_IR_REG);
102 return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0;
103}
104
105/*
106 * serial core request to set RTS and DTR pin state and loopback mode
107 */
108static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
109{
110 unsigned int val;
111
112 val = bcm_uart_readl(port, UART_MCTL_REG);
113 val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK);
114 /* invert of written value is reflected on the pin */
115 if (!(mctrl & TIOCM_DTR))
116 val |= UART_MCTL_DTR_MASK;
117 if (!(mctrl & TIOCM_RTS))
118 val |= UART_MCTL_RTS_MASK;
119 bcm_uart_writel(port, val, UART_MCTL_REG);
120
121 val = bcm_uart_readl(port, UART_CTL_REG);
122 if (mctrl & TIOCM_LOOP)
123 val |= UART_CTL_LOOPBACK_MASK;
124 else
125 val &= ~UART_CTL_LOOPBACK_MASK;
126 bcm_uart_writel(port, val, UART_CTL_REG);
127}
128
129/*
130 * serial core request to return RI, CTS, DCD and DSR pin state
131 */
132static unsigned int bcm_uart_get_mctrl(struct uart_port *port)
133{
134 unsigned int val, mctrl;
135
136 mctrl = 0;
137 val = bcm_uart_readl(port, UART_EXTINP_REG);
138 if (val & UART_EXTINP_RI_MASK)
139 mctrl |= TIOCM_RI;
140 if (val & UART_EXTINP_CTS_MASK)
141 mctrl |= TIOCM_CTS;
142 if (val & UART_EXTINP_DCD_MASK)
143 mctrl |= TIOCM_CD;
144 if (val & UART_EXTINP_DSR_MASK)
145 mctrl |= TIOCM_DSR;
146 return mctrl;
147}
148
149/*
150 * serial core request to disable tx ASAP (used for flow control)
151 */
152static void bcm_uart_stop_tx(struct uart_port *port)
153{
154 unsigned int val;
155
156 val = bcm_uart_readl(port, UART_CTL_REG);
157 val &= ~(UART_CTL_TXEN_MASK);
158 bcm_uart_writel(port, val, UART_CTL_REG);
159
160 val = bcm_uart_readl(port, UART_IR_REG);
161 val &= ~UART_TX_INT_MASK;
162 bcm_uart_writel(port, val, UART_IR_REG);
163}
164
165/*
166 * serial core request to (re)enable tx
167 */
168static void bcm_uart_start_tx(struct uart_port *port)
169{
170 unsigned int val;
171
172 val = bcm_uart_readl(port, UART_IR_REG);
173 val |= UART_TX_INT_MASK;
174 bcm_uart_writel(port, val, UART_IR_REG);
175
176 val = bcm_uart_readl(port, UART_CTL_REG);
177 val |= UART_CTL_TXEN_MASK;
178 bcm_uart_writel(port, val, UART_CTL_REG);
179}
180
181/*
182 * serial core request to stop rx, called before port shutdown
183 */
184static void bcm_uart_stop_rx(struct uart_port *port)
185{
186 unsigned int val;
187
188 val = bcm_uart_readl(port, UART_IR_REG);
189 val &= ~UART_RX_INT_MASK;
190 bcm_uart_writel(port, val, UART_IR_REG);
191}
192
193/*
194 * serial core request to enable modem status interrupt reporting
195 */
196static void bcm_uart_enable_ms(struct uart_port *port)
197{
198 unsigned int val;
199
200 val = bcm_uart_readl(port, UART_IR_REG);
201 val |= UART_IR_MASK(UART_IR_EXTIP);
202 bcm_uart_writel(port, val, UART_IR_REG);
203}
204
205/*
206 * serial core request to start/stop emitting break char
207 */
208static void bcm_uart_break_ctl(struct uart_port *port, int ctl)
209{
210 unsigned long flags;
211 unsigned int val;
212
213 spin_lock_irqsave(&port->lock, flags);
214
215 val = bcm_uart_readl(port, UART_CTL_REG);
216 if (ctl)
217 val |= UART_CTL_XMITBRK_MASK;
218 else
219 val &= ~UART_CTL_XMITBRK_MASK;
220 bcm_uart_writel(port, val, UART_CTL_REG);
221
222 spin_unlock_irqrestore(&port->lock, flags);
223}
224
225/*
226 * return port type in string format
227 */
228static const char *bcm_uart_type(struct uart_port *port)
229{
230 return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL;
231}
232
233/*
234 * read all chars in rx fifo and send them to core
235 */
236static void bcm_uart_do_rx(struct uart_port *port)
237{
Jiri Slaby92a19f92013-01-03 15:53:03 +0100238 struct tty_port *port = &port->state->port;
Maxime Bizon9fcd66e2009-09-18 13:04:58 +0200239 struct tty_struct *tty;
240 unsigned int max_count;
241
242 /* limit number of char read in interrupt, should not be
243 * higher than fifo size anyway since we're much faster than
244 * serial port */
245 max_count = 32;
Jiri Slaby92a19f92013-01-03 15:53:03 +0100246 tty = port->tty;
Maxime Bizon9fcd66e2009-09-18 13:04:58 +0200247 do {
248 unsigned int iestat, c, cstat;
249 char flag;
250
251 /* get overrun/fifo empty information from ier
252 * register */
253 iestat = bcm_uart_readl(port, UART_IR_REG);
Maxime Bizon3bc46b32011-06-10 23:17:58 +0200254
255 if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) {
256 unsigned int val;
257
258 /* fifo reset is required to clear
259 * interrupt */
260 val = bcm_uart_readl(port, UART_CTL_REG);
261 val |= UART_CTL_RSTRXFIFO_MASK;
262 bcm_uart_writel(port, val, UART_CTL_REG);
263
264 port->icount.overrun++;
Jiri Slaby92a19f92013-01-03 15:53:03 +0100265 tty_insert_flip_char(port, 0, TTY_OVERRUN);
Maxime Bizon3bc46b32011-06-10 23:17:58 +0200266 }
267
Maxime Bizon9fcd66e2009-09-18 13:04:58 +0200268 if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
269 break;
270
271 cstat = c = bcm_uart_readl(port, UART_FIFO_REG);
272 port->icount.rx++;
273 flag = TTY_NORMAL;
274 c &= 0xff;
275
276 if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) {
277 /* do stats first */
278 if (cstat & UART_FIFO_BRKDET_MASK) {
279 port->icount.brk++;
280 if (uart_handle_break(port))
281 continue;
282 }
283
284 if (cstat & UART_FIFO_PARERR_MASK)
285 port->icount.parity++;
286 if (cstat & UART_FIFO_FRAMEERR_MASK)
287 port->icount.frame++;
288
289 /* update flag wrt read_status_mask */
290 cstat &= port->read_status_mask;
291 if (cstat & UART_FIFO_BRKDET_MASK)
292 flag = TTY_BREAK;
293 if (cstat & UART_FIFO_FRAMEERR_MASK)
294 flag = TTY_FRAME;
295 if (cstat & UART_FIFO_PARERR_MASK)
296 flag = TTY_PARITY;
297 }
298
299 if (uart_handle_sysrq_char(port, c))
300 continue;
301
Maxime Bizon9fcd66e2009-09-18 13:04:58 +0200302
303 if ((cstat & port->ignore_status_mask) == 0)
Jiri Slaby92a19f92013-01-03 15:53:03 +0100304 tty_insert_flip_char(port, c, flag);
Maxime Bizon9fcd66e2009-09-18 13:04:58 +0200305
306 } while (--max_count);
307
308 tty_flip_buffer_push(tty);
309}
310
311/*
312 * fill tx fifo with chars to send, stop when fifo is about to be full
313 * or when all chars have been sent.
314 */
315static void bcm_uart_do_tx(struct uart_port *port)
316{
317 struct circ_buf *xmit;
318 unsigned int val, max_count;
319
320 if (port->x_char) {
321 bcm_uart_writel(port, port->x_char, UART_FIFO_REG);
322 port->icount.tx++;
323 port->x_char = 0;
324 return;
325 }
326
327 if (uart_tx_stopped(port)) {
328 bcm_uart_stop_tx(port);
329 return;
330 }
331
Maxime Bizonb0371792009-11-15 05:42:18 +0100332 xmit = &port->state->xmit;
Maxime Bizon9fcd66e2009-09-18 13:04:58 +0200333 if (uart_circ_empty(xmit))
334 goto txq_empty;
335
336 val = bcm_uart_readl(port, UART_MCTL_REG);
337 val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT;
338 max_count = port->fifosize - val;
339
340 while (max_count--) {
341 unsigned int c;
342
343 c = xmit->buf[xmit->tail];
344 bcm_uart_writel(port, c, UART_FIFO_REG);
345 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
346 port->icount.tx++;
347 if (uart_circ_empty(xmit))
348 break;
349 }
350
351 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
352 uart_write_wakeup(port);
353
354 if (uart_circ_empty(xmit))
355 goto txq_empty;
356 return;
357
358txq_empty:
359 /* nothing to send, disable transmit interrupt */
360 val = bcm_uart_readl(port, UART_IR_REG);
361 val &= ~UART_TX_INT_MASK;
362 bcm_uart_writel(port, val, UART_IR_REG);
363 return;
364}
365
366/*
367 * process uart interrupt
368 */
369static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id)
370{
371 struct uart_port *port;
372 unsigned int irqstat;
373
374 port = dev_id;
375 spin_lock(&port->lock);
376
377 irqstat = bcm_uart_readl(port, UART_IR_REG);
378 if (irqstat & UART_RX_INT_STAT)
379 bcm_uart_do_rx(port);
380
381 if (irqstat & UART_TX_INT_STAT)
382 bcm_uart_do_tx(port);
383
384 if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) {
385 unsigned int estat;
386
387 estat = bcm_uart_readl(port, UART_EXTINP_REG);
388 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS))
389 uart_handle_cts_change(port,
390 estat & UART_EXTINP_CTS_MASK);
391 if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD))
392 uart_handle_dcd_change(port,
393 estat & UART_EXTINP_DCD_MASK);
394 }
395
396 spin_unlock(&port->lock);
397 return IRQ_HANDLED;
398}
399
400/*
401 * enable rx & tx operation on uart
402 */
403static void bcm_uart_enable(struct uart_port *port)
404{
405 unsigned int val;
406
407 val = bcm_uart_readl(port, UART_CTL_REG);
408 val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
409 bcm_uart_writel(port, val, UART_CTL_REG);
410}
411
412/*
413 * disable rx & tx operation on uart
414 */
415static void bcm_uart_disable(struct uart_port *port)
416{
417 unsigned int val;
418
419 val = bcm_uart_readl(port, UART_CTL_REG);
420 val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
421 UART_CTL_RXEN_MASK);
422 bcm_uart_writel(port, val, UART_CTL_REG);
423}
424
425/*
426 * clear all unread data in rx fifo and unsent data in tx fifo
427 */
428static void bcm_uart_flush(struct uart_port *port)
429{
430 unsigned int val;
431
432 /* empty rx and tx fifo */
433 val = bcm_uart_readl(port, UART_CTL_REG);
434 val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
435 bcm_uart_writel(port, val, UART_CTL_REG);
436
437 /* read any pending char to make sure all irq status are
438 * cleared */
439 (void)bcm_uart_readl(port, UART_FIFO_REG);
440}
441
442/*
443 * serial core request to initialize uart and start rx operation
444 */
445static int bcm_uart_startup(struct uart_port *port)
446{
447 unsigned int val;
448 int ret;
449
450 /* mask all irq and flush port */
451 bcm_uart_disable(port);
452 bcm_uart_writel(port, 0, UART_IR_REG);
453 bcm_uart_flush(port);
454
455 /* clear any pending external input interrupt */
456 (void)bcm_uart_readl(port, UART_EXTINP_REG);
457
458 /* set rx/tx fifo thresh to fifo half size */
459 val = bcm_uart_readl(port, UART_MCTL_REG);
460 val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK);
461 val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT;
462 val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT;
463 bcm_uart_writel(port, val, UART_MCTL_REG);
464
465 /* set rx fifo timeout to 1 char time */
466 val = bcm_uart_readl(port, UART_CTL_REG);
467 val &= ~UART_CTL_RXTMOUTCNT_MASK;
468 val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT;
469 bcm_uart_writel(port, val, UART_CTL_REG);
470
471 /* report any edge on dcd and cts */
472 val = UART_EXTINP_INT_MASK;
473 val |= UART_EXTINP_DCD_NOSENSE_MASK;
474 val |= UART_EXTINP_CTS_NOSENSE_MASK;
475 bcm_uart_writel(port, val, UART_EXTINP_REG);
476
477 /* register irq and enable rx interrupts */
478 ret = request_irq(port->irq, bcm_uart_interrupt, 0,
479 bcm_uart_type(port), port);
480 if (ret)
481 return ret;
482 bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG);
483 bcm_uart_enable(port);
484 return 0;
485}
486
487/*
488 * serial core request to flush & disable uart
489 */
490static void bcm_uart_shutdown(struct uart_port *port)
491{
492 unsigned long flags;
493
494 spin_lock_irqsave(&port->lock, flags);
495 bcm_uart_writel(port, 0, UART_IR_REG);
496 spin_unlock_irqrestore(&port->lock, flags);
497
498 bcm_uart_disable(port);
499 bcm_uart_flush(port);
500 free_irq(port->irq, port);
501}
502
503/*
504 * serial core request to change current uart setting
505 */
506static void bcm_uart_set_termios(struct uart_port *port,
507 struct ktermios *new,
508 struct ktermios *old)
509{
510 unsigned int ctl, baud, quot, ier;
511 unsigned long flags;
512
513 spin_lock_irqsave(&port->lock, flags);
514
515 /* disable uart while changing speed */
516 bcm_uart_disable(port);
517 bcm_uart_flush(port);
518
519 /* update Control register */
520 ctl = bcm_uart_readl(port, UART_CTL_REG);
521 ctl &= ~UART_CTL_BITSPERSYM_MASK;
522
523 switch (new->c_cflag & CSIZE) {
524 case CS5:
525 ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT);
526 break;
527 case CS6:
528 ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT);
529 break;
530 case CS7:
531 ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT);
532 break;
533 default:
534 ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT);
535 break;
536 }
537
538 ctl &= ~UART_CTL_STOPBITS_MASK;
539 if (new->c_cflag & CSTOPB)
540 ctl |= UART_CTL_STOPBITS_2;
541 else
542 ctl |= UART_CTL_STOPBITS_1;
543
544 ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
545 if (new->c_cflag & PARENB)
546 ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
547 ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
548 if (new->c_cflag & PARODD)
549 ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK);
550 bcm_uart_writel(port, ctl, UART_CTL_REG);
551
552 /* update Baudword register */
553 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
554 quot = uart_get_divisor(port, baud) - 1;
555 bcm_uart_writel(port, quot, UART_BAUD_REG);
556
557 /* update Interrupt register */
558 ier = bcm_uart_readl(port, UART_IR_REG);
559
560 ier &= ~UART_IR_MASK(UART_IR_EXTIP);
561 if (UART_ENABLE_MS(port, new->c_cflag))
562 ier |= UART_IR_MASK(UART_IR_EXTIP);
563
564 bcm_uart_writel(port, ier, UART_IR_REG);
565
566 /* update read/ignore mask */
567 port->read_status_mask = UART_FIFO_VALID_MASK;
568 if (new->c_iflag & INPCK) {
569 port->read_status_mask |= UART_FIFO_FRAMEERR_MASK;
570 port->read_status_mask |= UART_FIFO_PARERR_MASK;
571 }
572 if (new->c_iflag & (BRKINT))
573 port->read_status_mask |= UART_FIFO_BRKDET_MASK;
574
575 port->ignore_status_mask = 0;
576 if (new->c_iflag & IGNPAR)
577 port->ignore_status_mask |= UART_FIFO_PARERR_MASK;
578 if (new->c_iflag & IGNBRK)
579 port->ignore_status_mask |= UART_FIFO_BRKDET_MASK;
580 if (!(new->c_cflag & CREAD))
581 port->ignore_status_mask |= UART_FIFO_VALID_MASK;
582
583 uart_update_timeout(port, new->c_cflag, baud);
584 bcm_uart_enable(port);
585 spin_unlock_irqrestore(&port->lock, flags);
586}
587
588/*
589 * serial core request to claim uart iomem
590 */
591static int bcm_uart_request_port(struct uart_port *port)
592{
593 unsigned int size;
594
595 size = RSET_UART_SIZE;
596 if (!request_mem_region(port->mapbase, size, "bcm63xx")) {
597 dev_err(port->dev, "Memory region busy\n");
598 return -EBUSY;
599 }
600
601 port->membase = ioremap(port->mapbase, size);
602 if (!port->membase) {
603 dev_err(port->dev, "Unable to map registers\n");
604 release_mem_region(port->mapbase, size);
605 return -EBUSY;
606 }
607 return 0;
608}
609
610/*
611 * serial core request to release uart iomem
612 */
613static void bcm_uart_release_port(struct uart_port *port)
614{
615 release_mem_region(port->mapbase, RSET_UART_SIZE);
616 iounmap(port->membase);
617}
618
619/*
620 * serial core request to do any port required autoconfiguration
621 */
622static void bcm_uart_config_port(struct uart_port *port, int flags)
623{
624 if (flags & UART_CONFIG_TYPE) {
625 if (bcm_uart_request_port(port))
626 return;
627 port->type = PORT_BCM63XX;
628 }
629}
630
631/*
632 * serial core request to check that port information in serinfo are
633 * suitable
634 */
635static int bcm_uart_verify_port(struct uart_port *port,
636 struct serial_struct *serinfo)
637{
638 if (port->type != PORT_BCM63XX)
639 return -EINVAL;
640 if (port->irq != serinfo->irq)
641 return -EINVAL;
642 if (port->iotype != serinfo->io_type)
643 return -EINVAL;
644 if (port->mapbase != (unsigned long)serinfo->iomem_base)
645 return -EINVAL;
646 return 0;
647}
648
649/* serial core callbacks */
650static struct uart_ops bcm_uart_ops = {
651 .tx_empty = bcm_uart_tx_empty,
652 .get_mctrl = bcm_uart_get_mctrl,
653 .set_mctrl = bcm_uart_set_mctrl,
654 .start_tx = bcm_uart_start_tx,
655 .stop_tx = bcm_uart_stop_tx,
656 .stop_rx = bcm_uart_stop_rx,
657 .enable_ms = bcm_uart_enable_ms,
658 .break_ctl = bcm_uart_break_ctl,
659 .startup = bcm_uart_startup,
660 .shutdown = bcm_uart_shutdown,
661 .set_termios = bcm_uart_set_termios,
662 .type = bcm_uart_type,
663 .release_port = bcm_uart_release_port,
664 .request_port = bcm_uart_request_port,
665 .config_port = bcm_uart_config_port,
666 .verify_port = bcm_uart_verify_port,
667};
668
669
670
671#ifdef CONFIG_SERIAL_BCM63XX_CONSOLE
672static inline void wait_for_xmitr(struct uart_port *port)
673{
674 unsigned int tmout;
675
676 /* Wait up to 10ms for the character(s) to be sent. */
677 tmout = 10000;
678 while (--tmout) {
679 unsigned int val;
680
681 val = bcm_uart_readl(port, UART_IR_REG);
682 if (val & UART_IR_STAT(UART_IR_TXEMPTY))
683 break;
684 udelay(1);
685 }
686
687 /* Wait up to 1s for flow control if necessary */
688 if (port->flags & UPF_CONS_FLOW) {
689 tmout = 1000000;
690 while (--tmout) {
691 unsigned int val;
692
693 val = bcm_uart_readl(port, UART_EXTINP_REG);
694 if (val & UART_EXTINP_CTS_MASK)
695 break;
696 udelay(1);
697 }
698 }
699}
700
701/*
702 * output given char
703 */
704static void bcm_console_putchar(struct uart_port *port, int ch)
705{
706 wait_for_xmitr(port);
707 bcm_uart_writel(port, ch, UART_FIFO_REG);
708}
709
710/*
711 * console core request to output given string
712 */
713static void bcm_console_write(struct console *co, const char *s,
714 unsigned int count)
715{
716 struct uart_port *port;
717 unsigned long flags;
718 int locked;
719
720 port = &ports[co->index];
721
722 local_irq_save(flags);
723 if (port->sysrq) {
724 /* bcm_uart_interrupt() already took the lock */
725 locked = 0;
726 } else if (oops_in_progress) {
727 locked = spin_trylock(&port->lock);
728 } else {
729 spin_lock(&port->lock);
730 locked = 1;
731 }
732
733 /* call helper to deal with \r\n */
734 uart_console_write(port, s, count, bcm_console_putchar);
735
736 /* and wait for char to be transmitted */
737 wait_for_xmitr(port);
738
739 if (locked)
740 spin_unlock(&port->lock);
741 local_irq_restore(flags);
742}
743
744/*
745 * console core request to setup given console, find matching uart
746 * port and setup it.
747 */
748static int bcm_console_setup(struct console *co, char *options)
749{
750 struct uart_port *port;
751 int baud = 9600;
752 int bits = 8;
753 int parity = 'n';
754 int flow = 'n';
755
756 if (co->index < 0 || co->index >= BCM63XX_NR_UARTS)
757 return -EINVAL;
758 port = &ports[co->index];
759 if (!port->membase)
760 return -ENODEV;
761 if (options)
762 uart_parse_options(options, &baud, &parity, &bits, &flow);
763
764 return uart_set_options(port, co, baud, parity, bits, flow);
765}
766
767static struct uart_driver bcm_uart_driver;
768
769static struct console bcm63xx_console = {
770 .name = "ttyS",
771 .write = bcm_console_write,
772 .device = uart_console_device,
773 .setup = bcm_console_setup,
774 .flags = CON_PRINTBUFFER,
775 .index = -1,
776 .data = &bcm_uart_driver,
777};
778
779static int __init bcm63xx_console_init(void)
780{
781 register_console(&bcm63xx_console);
782 return 0;
783}
784
785console_initcall(bcm63xx_console_init);
786
787#define BCM63XX_CONSOLE (&bcm63xx_console)
788#else
789#define BCM63XX_CONSOLE NULL
790#endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */
791
792static struct uart_driver bcm_uart_driver = {
793 .owner = THIS_MODULE,
794 .driver_name = "bcm63xx_uart",
795 .dev_name = "ttyS",
796 .major = TTY_MAJOR,
797 .minor = 64,
Maxime Bizon6a2c7ea2010-01-30 18:42:57 +0100798 .nr = BCM63XX_NR_UARTS,
Maxime Bizon9fcd66e2009-09-18 13:04:58 +0200799 .cons = BCM63XX_CONSOLE,
800};
801
802/*
803 * platform driver probe/remove callback
804 */
Bill Pemberton9671f092012-11-19 13:21:50 -0500805static int bcm_uart_probe(struct platform_device *pdev)
Maxime Bizon9fcd66e2009-09-18 13:04:58 +0200806{
807 struct resource *res_mem, *res_irq;
808 struct uart_port *port;
809 struct clk *clk;
810 int ret;
811
812 if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS)
813 return -EINVAL;
814
815 if (ports[pdev->id].membase)
816 return -EBUSY;
817
818 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
819 if (!res_mem)
820 return -ENODEV;
821
822 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
823 if (!res_irq)
824 return -ENODEV;
825
826 clk = clk_get(&pdev->dev, "periph");
827 if (IS_ERR(clk))
828 return -ENODEV;
829
830 port = &ports[pdev->id];
831 memset(port, 0, sizeof(*port));
832 port->iotype = UPIO_MEM;
833 port->mapbase = res_mem->start;
834 port->irq = res_irq->start;
835 port->ops = &bcm_uart_ops;
836 port->flags = UPF_BOOT_AUTOCONF;
837 port->dev = &pdev->dev;
838 port->fifosize = 16;
839 port->uartclk = clk_get_rate(clk) / 2;
Maxime Bizon6a2c7ea2010-01-30 18:42:57 +0100840 port->line = pdev->id;
Maxime Bizon9fcd66e2009-09-18 13:04:58 +0200841 clk_put(clk);
842
843 ret = uart_add_one_port(&bcm_uart_driver, port);
844 if (ret) {
Maxime Bizona6d07d12010-01-30 18:42:56 +0100845 ports[pdev->id].membase = 0;
Maxime Bizon9fcd66e2009-09-18 13:04:58 +0200846 return ret;
847 }
848 platform_set_drvdata(pdev, port);
849 return 0;
850}
851
Bill Pembertonae8d8a12012-11-19 13:26:18 -0500852static int bcm_uart_remove(struct platform_device *pdev)
Maxime Bizon9fcd66e2009-09-18 13:04:58 +0200853{
854 struct uart_port *port;
855
856 port = platform_get_drvdata(pdev);
857 uart_remove_one_port(&bcm_uart_driver, port);
858 platform_set_drvdata(pdev, NULL);
859 /* mark port as free */
860 ports[pdev->id].membase = 0;
861 return 0;
862}
863
864/*
865 * platform driver stuff
866 */
867static struct platform_driver bcm_uart_platform_driver = {
868 .probe = bcm_uart_probe,
Bill Pemberton2d47b712012-11-19 13:21:34 -0500869 .remove = bcm_uart_remove,
Maxime Bizon9fcd66e2009-09-18 13:04:58 +0200870 .driver = {
871 .owner = THIS_MODULE,
872 .name = "bcm63xx_uart",
873 },
874};
875
876static int __init bcm_uart_init(void)
877{
878 int ret;
879
880 ret = uart_register_driver(&bcm_uart_driver);
881 if (ret)
882 return ret;
883
884 ret = platform_driver_register(&bcm_uart_platform_driver);
885 if (ret)
886 uart_unregister_driver(&bcm_uart_driver);
887
888 return ret;
889}
890
891static void __exit bcm_uart_exit(void)
892{
893 platform_driver_unregister(&bcm_uart_platform_driver);
894 uart_unregister_driver(&bcm_uart_driver);
895}
896
897module_init(bcm_uart_init);
898module_exit(bcm_uart_exit);
899
900MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
901MODULE_DESCRIPTION("Broadcom 63<xx integrated uart driver");
902MODULE_LICENSE("GPL");