| Scott Wood | 2dff417 | 2008-07-11 17:31:15 -0500 | [diff] [blame] | 1 | * Power Management Controller |
| 2 | |
| 3 | Properties: |
| 4 | - compatible: "fsl,<chip>-pmc". |
| 5 | |
| 6 | "fsl,mpc8349-pmc" should be listed for any chip whose PMC is |
| 7 | compatible. "fsl,mpc8313-pmc" should also be listed for any chip |
| 8 | whose PMC is compatible, and implies deep-sleep capability. |
| 9 | |
| 10 | "fsl,mpc8548-pmc" should be listed for any chip whose PMC is |
| 11 | compatible. "fsl,mpc8536-pmc" should also be listed for any chip |
| 12 | whose PMC is compatible, and implies deep-sleep capability. |
| 13 | |
| 14 | "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is |
| 15 | compatible; all statements below that apply to "fsl,mpc8548-pmc" also |
| 16 | apply to "fsl,mpc8641d-pmc". |
| 17 | |
| Matt LaPlante | 19f5946 | 2009-04-27 15:06:31 +0200 | [diff] [blame] | 18 | Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these |
| 19 | bit assignments are indicated via the sleep specifier in each device's |
| Scott Wood | 2dff417 | 2008-07-11 17:31:15 -0500 | [diff] [blame] | 20 | sleep property. |
| 21 | |
| 22 | - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource |
| 23 | is the PMC block, and the second resource is the Clock Configuration |
| 24 | block. |
| 25 | |
| 26 | For devices compatible with "fsl,mpc8548-pmc", the first resource |
| 27 | is a 32-byte block beginning with DEVDISR. |
| 28 | |
| 29 | - interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first |
| 30 | resource is the PMC block interrupt. |
| 31 | |
| 32 | - fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices, |
| 33 | this is a phandle to an "fsl,gtm" node on which timer 4 can be used as |
| 34 | a wakeup source from deep sleep. |
| 35 | |
| 36 | Sleep specifiers: |
| 37 | |
| 38 | fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit |
| 39 | that is set in the cell, the corresponding bit in SCCR will be saved |
| 40 | and cleared on suspend, and restored on resume. This sleep controller |
| 41 | supports disabling and resuming devices at any time. |
| 42 | |
| 43 | fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of |
| 44 | which will be ORed into PMCDR upon suspend, and cleared from PMCDR |
| 45 | upon resume. The first two cells are as described for fsl,mpc8578-pmc. |
| 46 | This sleep controller only supports disabling devices during system |
| 47 | sleep, or permanently. |
| 48 | |
| 49 | fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the |
| 50 | first of which will be ORed into DEVDISR (and the second into |
| 51 | DEVDISR2, if present -- this cell should be zero or absent if the |
| 52 | hardware does not have DEVDISR2) upon a request for permanent device |
| 53 | disabling. This sleep controller does not support configuring devices |
| 54 | to disable during system sleep (unless supported by another compatible |
| 55 | match), or dynamically. |
| 56 | |
| 57 | Example: |
| 58 | |
| 59 | power@b00 { |
| 60 | compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; |
| 61 | reg = <0xb00 0x100 0xa00 0x100>; |
| 62 | interrupts = <80 8>; |
| 63 | }; |