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review.evervolv.com / android_kernel_oneplus_msm8996 / d99a79fcf4cbbc4dc6dc1e21e6860b97357269ea / . / arch / arm / boot / dts / imx6q-sabrelite.dts
blob: 85b7c6c1ecf24d29d916a0a25f7cdf2b7a548b9e [file] [log] [blame]
Richard Zhao3c8276c2011-12-14 09:26:46 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx6q.dtsi"
15
16/ {
17 model = "Freescale i.MX6 Quad SABRE Lite Board";
18 compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
19
20 memory {
21 reg = <0x10000000 0x40000000>;
22 };
23
24 soc {
Fabio Estevamf07439c2012-04-24 20:35:36 -0300[diff] [blame]25 aips-bus@02000000 { /* AIPS1 */
26 spba-bus@02000000 {
27 ecspi@02008000 { /* eCSPI1 */
28 fsl,spi-num-chipselects = <1>;
29 cs-gpios = <&gpio3 19 0>;
30 status = "okay";
31
32 flash: m25p80@0 {
33 compatible = "sst,sst25vf016b";
34 spi-max-frequency = <20000000>;
35 reg = <0>;
36 };
37 };
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]38
39 ssi1: ssi@02028000 {
40 fsl,mode = "i2s-slave";
41 status = "okay";
42 };
Fabio Estevamf07439c2012-04-24 20:35:36 -0300[diff] [blame]43 };
44
45 };
46
Richard Zhao3c8276c2011-12-14 09:26:46 +0800[diff] [blame]47 aips-bus@02100000 { /* AIPS2 */
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]48 ethernet@02188000 {
Richard Zhao3c8276c2011-12-14 09:26:46 +0800[diff] [blame]49 phy-mode = "rgmii";
50 phy-reset-gpios = <&gpio3 23 0>;
51 status = "okay";
52 };
53
54 usdhc@02198000 { /* uSDHC3 */
55 cd-gpios = <&gpio7 0 0>;
56 wp-gpios = <&gpio7 1 0>;
Shawn Guo6f6ea9372012-02-27 17:15:12 +0800[diff] [blame]57 vmmc-supply = <&reg_3p3v>;
Richard Zhao3c8276c2011-12-14 09:26:46 +0800[diff] [blame]58 status = "okay";
59 };
60
61 usdhc@0219c000 { /* uSDHC4 */
62 cd-gpios = <&gpio2 6 0>;
63 wp-gpios = <&gpio2 7 0>;
Shawn Guo6f6ea9372012-02-27 17:15:12 +0800[diff] [blame]64 vmmc-supply = <&reg_3p3v>;
Richard Zhao3c8276c2011-12-14 09:26:46 +0800[diff] [blame]65 status = "okay";
66 };
67
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]68 audmux@021d8000 {
69 status = "okay";
70 };
71
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]72 uart2: serial@021e8000 {
Richard Zhao3c8276c2011-12-14 09:26:46 +0800[diff] [blame]73 status = "okay";
74 };
Richard Zhaoadcec4c2012-02-02 10:12:03 +0800[diff] [blame]75
76 i2c@021a0000 { /* I2C1 */
77 status = "okay";
78 clock-frequency = <100000>;
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame^]79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_i2c1_1>;
Richard Zhaoadcec4c2012-02-02 10:12:03 +0800[diff] [blame]81
82 codec: sgtl5000@0a {
83 compatible = "fsl,sgtl5000";
84 reg = <0x0a>;
85 VDDA-supply = <&reg_2p5v>;
86 VDDIO-supply = <&reg_3p3v>;
87 };
88 };
Richard Zhao3c8276c2011-12-14 09:26:46 +0800[diff] [blame]89 };
90 };
Richard Zhaocf37a8e2012-02-02 10:12:02 +0800[diff] [blame]91
92 regulators {
93 compatible = "simple-bus";
94
95 reg_2p5v: 2p5v {
96 compatible = "regulator-fixed";
97 regulator-name = "2P5V";
98 regulator-min-microvolt = <2500000>;
99 regulator-max-microvolt = <2500000>;
100 regulator-always-on;
101 };
102
103 reg_3p3v: 3p3v {
104 compatible = "regulator-fixed";
105 regulator-name = "3P3V";
106 regulator-min-microvolt = <3300000>;
107 regulator-max-microvolt = <3300000>;
108 regulator-always-on;
109 };
110 };
Richard Zhao3c8276c2011-12-14 09:26:46 +0800[diff] [blame]111};