blob: d4a85b7953448e42af772ddfd6c7a669aec1b4cd [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
Matt Carlsonb86fb2c2011-01-25 15:58:57 +00007 * Copyright (C) 2005-2011 Broadcom Corporation.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * Firmware is:
Michael Chan49cabf42005-06-06 15:15:17 -070010 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 */
17
Linus Torvalds1da177e2005-04-16 15:20:36 -070018
19#include <linux/module.h>
20#include <linux/moduleparam.h>
Matt Carlson6867c842010-07-11 09:31:44 +000021#include <linux/stringify.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <linux/kernel.h>
23#include <linux/types.h>
24#include <linux/compiler.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
Arnaldo Carvalho de Melo14c85022005-12-27 02:43:12 -020027#include <linux/in.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <linux/init.h>
Alexey Dobriyana6b7a402011-06-06 10:43:46 +000029#include <linux/interrupt.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030#include <linux/ioport.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/skbuff.h>
35#include <linux/ethtool.h>
Matt Carlson3110f5f52010-12-06 08:28:50 +000036#include <linux/mdio.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#include <linux/mii.h>
Matt Carlson158d7ab2008-05-29 01:37:54 -070038#include <linux/phy.h>
Matt Carlsona9daf362008-05-25 23:49:44 -070039#include <linux/brcmphy.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <linux/if_vlan.h>
41#include <linux/ip.h>
42#include <linux/tcp.h>
43#include <linux/workqueue.h>
Michael Chan61487482005-09-05 17:53:19 -070044#include <linux/prefetch.h>
Tobias Klauserf9a5f7d2005-10-29 15:09:26 +020045#include <linux/dma-mapping.h>
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -080046#include <linux/firmware.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
48#include <net/checksum.h>
Arnaldo Carvalho de Meloc9bdd4b2007-03-12 20:09:15 -030049#include <net/ip.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51#include <asm/system.h>
Javier Martinez Canillas27fd9de2011-03-26 16:42:31 +000052#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#include <asm/byteorder.h>
Javier Martinez Canillas27fd9de2011-03-26 16:42:31 +000054#include <linux/uaccess.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
David S. Miller49b6e95f2007-03-29 01:38:42 -070056#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070057#include <asm/idprom.h>
David S. Miller49b6e95f2007-03-29 01:38:42 -070058#include <asm/prom.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070059#endif
60
Matt Carlson63532392008-11-03 16:49:57 -080061#define BAR_0 0
62#define BAR_2 2
63
Linus Torvalds1da177e2005-04-16 15:20:36 -070064#include "tg3.h"
65
Joe Perches63c3a662011-04-26 08:12:10 +000066/* Functions & macros to verify TG3_FLAGS types */
67
68static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
69{
70 return test_bit(flag, bits);
71}
72
73static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
74{
75 set_bit(flag, bits);
76}
77
78static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
79{
80 clear_bit(flag, bits);
81}
82
83#define tg3_flag(tp, flag) \
84 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
85#define tg3_flag_set(tp, flag) \
86 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
87#define tg3_flag_clear(tp, flag) \
88 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
89
Linus Torvalds1da177e2005-04-16 15:20:36 -070090#define DRV_MODULE_NAME "tg3"
Matt Carlson6867c842010-07-11 09:31:44 +000091#define TG3_MAJ_NUM 3
Matt Carlsoneaa36662011-08-19 13:58:24 +000092#define TG3_MIN_NUM 120
Matt Carlson6867c842010-07-11 09:31:44 +000093#define DRV_MODULE_VERSION \
94 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
Matt Carlsoneaa36662011-08-19 13:58:24 +000095#define DRV_MODULE_RELDATE "August 18, 2011"
Linus Torvalds1da177e2005-04-16 15:20:36 -070096
Matt Carlsonfd6d3f02011-08-31 11:44:52 +000097#define RESET_KIND_SHUTDOWN 0
98#define RESET_KIND_INIT 1
99#define RESET_KIND_SUSPEND 2
100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101#define TG3_DEF_RX_MODE 0
102#define TG3_DEF_TX_MODE 0
103#define TG3_DEF_MSG_ENABLE \
104 (NETIF_MSG_DRV | \
105 NETIF_MSG_PROBE | \
106 NETIF_MSG_LINK | \
107 NETIF_MSG_TIMER | \
108 NETIF_MSG_IFDOWN | \
109 NETIF_MSG_IFUP | \
110 NETIF_MSG_RX_ERR | \
111 NETIF_MSG_TX_ERR)
112
Matt Carlson520b2752011-06-13 13:39:02 +0000113#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
114
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115/* length of time before we decide the hardware is borked,
116 * and dev->tx_timeout() should be called to fix the problem
117 */
Joe Perches63c3a662011-04-26 08:12:10 +0000118
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119#define TG3_TX_TIMEOUT (5 * HZ)
120
121/* hardware minimum and maximum for a single frame's data payload */
122#define TG3_MIN_MTU 60
123#define TG3_MAX_MTU(tp) \
Joe Perches63c3a662011-04-26 08:12:10 +0000124 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125
126/* These numbers seem to be hard coded in the NIC firmware somehow.
127 * You can't change the ring sizes, but you can change where you place
128 * them in the NIC onboard memory.
129 */
Matt Carlson7cb32cf2010-09-30 10:34:36 +0000130#define TG3_RX_STD_RING_SIZE(tp) \
Joe Perches63c3a662011-04-26 08:12:10 +0000131 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
Matt Carlsonde9f5232011-04-05 14:22:43 +0000132 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133#define TG3_DEF_RX_RING_PENDING 200
Matt Carlson7cb32cf2010-09-30 10:34:36 +0000134#define TG3_RX_JMB_RING_SIZE(tp) \
Joe Perches63c3a662011-04-26 08:12:10 +0000135 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
Matt Carlsonde9f5232011-04-05 14:22:43 +0000136 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137#define TG3_DEF_RX_JUMBO_RING_PENDING 100
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000138#define TG3_RSS_INDIR_TBL_SIZE 128
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139
140/* Do not place this n-ring entries value into the tp struct itself,
141 * we really want to expose these constants to GCC so that modulo et
142 * al. operations are done with shifts and masks instead of with
143 * hw multiply/modulo instructions. Another solution would be to
144 * replace things like '% foo' with '& (foo - 1)'.
145 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
147#define TG3_TX_RING_SIZE 512
148#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
149
Matt Carlson2c49a442010-09-30 10:34:35 +0000150#define TG3_RX_STD_RING_BYTES(tp) \
151 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
152#define TG3_RX_JMB_RING_BYTES(tp) \
153 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
154#define TG3_RX_RCB_RING_BYTES(tp) \
Matt Carlson7cb32cf2010-09-30 10:34:36 +0000155 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
157 TG3_TX_RING_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
159
Matt Carlson287be122009-08-28 13:58:46 +0000160#define TG3_DMA_BYTE_ENAB 64
161
162#define TG3_RX_STD_DMA_SZ 1536
163#define TG3_RX_JMB_DMA_SZ 9046
164
165#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
166
167#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
168#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700169
Matt Carlson2c49a442010-09-30 10:34:35 +0000170#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
171 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
Matt Carlson2b2cdb62009-11-13 13:03:48 +0000172
Matt Carlson2c49a442010-09-30 10:34:35 +0000173#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
174 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
Matt Carlson2b2cdb62009-11-13 13:03:48 +0000175
Matt Carlsond2757fc2010-04-12 06:58:27 +0000176/* Due to a hardware bug, the 5701 can only DMA to memory addresses
177 * that are at least dword aligned when used in PCIX mode. The driver
178 * works around this bug by double copying the packet. This workaround
179 * is built into the normal double copy length check for efficiency.
180 *
181 * However, the double copy is only necessary on those architectures
182 * where unaligned memory accesses are inefficient. For those architectures
183 * where unaligned memory accesses incur little penalty, we can reintegrate
184 * the 5701 in the normal rx path. Doing so saves a device structure
185 * dereference by hardcoding the double copy threshold in place.
186 */
187#define TG3_RX_COPY_THRESHOLD 256
188#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
189 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
190#else
191 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
192#endif
193
Matt Carlson81389f52011-08-31 11:44:49 +0000194#if (NET_IP_ALIGN != 0)
195#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
196#else
197#define TG3_RX_OFFSET(tp) 0
198#endif
199
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200/* minimum number of free TX descriptors required to wake up TX process */
Matt Carlsonf3f3f272009-08-28 14:03:21 +0000201#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
Matt Carlsone31aa982011-07-27 14:20:53 +0000202#define TG3_TX_BD_DMA_MAX 4096
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203
Matt Carlsonad829262008-11-21 17:16:16 -0800204#define TG3_RAW_IP_ALIGN 2
205
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000206#define TG3_FW_UPDATE_TIMEOUT_SEC 5
207
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -0800208#define FIRMWARE_TG3 "tigon/tg3.bin"
209#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
210#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
211
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212static char version[] __devinitdata =
Joe Perches05dbe002010-02-17 19:44:19 +0000213 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214
215MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
216MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
217MODULE_LICENSE("GPL");
218MODULE_VERSION(DRV_MODULE_VERSION);
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -0800219MODULE_FIRMWARE(FIRMWARE_TG3);
220MODULE_FIRMWARE(FIRMWARE_TG3TSO);
221MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
222
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
224module_param(tg3_debug, int, 0);
225MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
226
Alexey Dobriyana3aa1882010-01-07 11:58:11 +0000227static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
Michael Chan126a3362006-09-27 16:03:07 -0700251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
Michael Chan126a3362006-09-27 16:03:07 -0700264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
Michael Chan676917d2006-12-07 00:20:22 -0800268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
Michael Chanb5d37722006-09-27 16:06:21 -0700276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
Matt Carlsond30cdd22007-10-07 23:28:35 -0700278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
Matt Carlson6c7af272007-10-21 16:12:02 -0700280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
Matt Carlson9936bcf2007-10-10 18:03:07 -0700281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
Matt Carlsonc88e6682008-11-03 16:49:18 -0800283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
Matt Carlson2befdce2009-08-28 12:28:45 +0000285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
Matt Carlson321d32a2008-11-21 17:22:19 -0800287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
289 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
Matt Carlson5e7ccf22009-08-25 10:08:42 +0000290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
Matt Carlson5001e2f2009-11-13 13:03:51 +0000291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
292 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
Matt Carlsonb0f75222010-01-20 16:58:11 +0000293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
Matt Carlson302b5002010-06-05 17:24:38 +0000299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
Matt Carlsonba1f3c72011-04-05 14:22:50 +0000300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700301 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
302 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
303 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
304 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
305 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
306 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
307 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
Meelis Roos1dcb14d2011-05-25 05:43:47 +0000308 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
Henrik Kretzschmar13185212006-08-22 00:28:33 -0700309 {}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310};
311
312MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
313
Andreas Mohr50da8592006-08-14 23:54:30 -0700314static const struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 const char string[ETH_GSTRING_LEN];
Matt Carlson48fa55a2011-04-13 11:05:06 +0000316} ethtool_stats_keys[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317 { "rx_octets" },
318 { "rx_fragments" },
319 { "rx_ucast_packets" },
320 { "rx_mcast_packets" },
321 { "rx_bcast_packets" },
322 { "rx_fcs_errors" },
323 { "rx_align_errors" },
324 { "rx_xon_pause_rcvd" },
325 { "rx_xoff_pause_rcvd" },
326 { "rx_mac_ctrl_rcvd" },
327 { "rx_xoff_entered" },
328 { "rx_frame_too_long_errors" },
329 { "rx_jabbers" },
330 { "rx_undersize_packets" },
331 { "rx_in_length_errors" },
332 { "rx_out_length_errors" },
333 { "rx_64_or_less_octet_packets" },
334 { "rx_65_to_127_octet_packets" },
335 { "rx_128_to_255_octet_packets" },
336 { "rx_256_to_511_octet_packets" },
337 { "rx_512_to_1023_octet_packets" },
338 { "rx_1024_to_1522_octet_packets" },
339 { "rx_1523_to_2047_octet_packets" },
340 { "rx_2048_to_4095_octet_packets" },
341 { "rx_4096_to_8191_octet_packets" },
342 { "rx_8192_to_9022_octet_packets" },
343
344 { "tx_octets" },
345 { "tx_collisions" },
346
347 { "tx_xon_sent" },
348 { "tx_xoff_sent" },
349 { "tx_flow_control" },
350 { "tx_mac_errors" },
351 { "tx_single_collisions" },
352 { "tx_mult_collisions" },
353 { "tx_deferred" },
354 { "tx_excessive_collisions" },
355 { "tx_late_collisions" },
356 { "tx_collide_2times" },
357 { "tx_collide_3times" },
358 { "tx_collide_4times" },
359 { "tx_collide_5times" },
360 { "tx_collide_6times" },
361 { "tx_collide_7times" },
362 { "tx_collide_8times" },
363 { "tx_collide_9times" },
364 { "tx_collide_10times" },
365 { "tx_collide_11times" },
366 { "tx_collide_12times" },
367 { "tx_collide_13times" },
368 { "tx_collide_14times" },
369 { "tx_collide_15times" },
370 { "tx_ucast_packets" },
371 { "tx_mcast_packets" },
372 { "tx_bcast_packets" },
373 { "tx_carrier_sense_errors" },
374 { "tx_discards" },
375 { "tx_errors" },
376
377 { "dma_writeq_full" },
378 { "dma_write_prioq_full" },
379 { "rxbds_empty" },
380 { "rx_discards" },
381 { "rx_errors" },
382 { "rx_threshold_hit" },
383
384 { "dma_readq_full" },
385 { "dma_read_prioq_full" },
386 { "tx_comp_queue_full" },
387
388 { "ring_set_send_prod_index" },
389 { "ring_status_update" },
390 { "nic_irqs" },
391 { "nic_avoided_irqs" },
Matt Carlson4452d092011-05-19 12:12:51 +0000392 { "nic_tx_threshold_hit" },
393
394 { "mbuf_lwm_thresh_hit" },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395};
396
Matt Carlson48fa55a2011-04-13 11:05:06 +0000397#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
398
399
Andreas Mohr50da8592006-08-14 23:54:30 -0700400static const struct {
Michael Chan4cafd3f2005-05-29 14:56:34 -0700401 const char string[ETH_GSTRING_LEN];
Matt Carlson48fa55a2011-04-13 11:05:06 +0000402} ethtool_test_keys[] = {
Matt Carlson28a45952011-08-19 13:58:22 +0000403 { "nvram test (online) " },
404 { "link test (online) " },
405 { "register test (offline)" },
406 { "memory test (offline)" },
407 { "mac loopback test (offline)" },
408 { "phy loopback test (offline)" },
Matt Carlson941ec902011-08-19 13:58:23 +0000409 { "ext loopback test (offline)" },
Matt Carlson28a45952011-08-19 13:58:22 +0000410 { "interrupt test (offline)" },
Michael Chan4cafd3f2005-05-29 14:56:34 -0700411};
412
Matt Carlson48fa55a2011-04-13 11:05:06 +0000413#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
414
415
Michael Chanb401e9e2005-12-19 16:27:04 -0800416static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
417{
418 writel(val, tp->regs + off);
419}
420
421static u32 tg3_read32(struct tg3 *tp, u32 off)
422{
Matt Carlsonde6f31e2010-04-12 06:58:30 +0000423 return readl(tp->regs + off);
Michael Chanb401e9e2005-12-19 16:27:04 -0800424}
425
Matt Carlson0d3031d2007-10-10 18:02:43 -0700426static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
427{
428 writel(val, tp->aperegs + off);
429}
430
431static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
432{
Matt Carlsonde6f31e2010-04-12 06:58:30 +0000433 return readl(tp->aperegs + off);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700434}
435
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
437{
Michael Chan68929142005-08-09 20:17:14 -0700438 unsigned long flags;
439
440 spin_lock_irqsave(&tp->indirect_lock, flags);
Michael Chan1ee582d2005-08-09 20:16:46 -0700441 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
442 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
Michael Chan68929142005-08-09 20:17:14 -0700443 spin_unlock_irqrestore(&tp->indirect_lock, flags);
Michael Chan1ee582d2005-08-09 20:16:46 -0700444}
445
446static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
447{
448 writel(val, tp->regs + off);
449 readl(tp->regs + off);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450}
451
Michael Chan68929142005-08-09 20:17:14 -0700452static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
453{
454 unsigned long flags;
455 u32 val;
456
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
459 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
460 spin_unlock_irqrestore(&tp->indirect_lock, flags);
461 return val;
462}
463
464static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
465{
466 unsigned long flags;
467
468 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
469 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
470 TG3_64BIT_REG_LOW, val);
471 return;
472 }
Matt Carlson66711e62009-11-13 13:03:49 +0000473 if (off == TG3_RX_STD_PROD_IDX_REG) {
Michael Chan68929142005-08-09 20:17:14 -0700474 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
475 TG3_64BIT_REG_LOW, val);
476 return;
477 }
478
479 spin_lock_irqsave(&tp->indirect_lock, flags);
480 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
481 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
482 spin_unlock_irqrestore(&tp->indirect_lock, flags);
483
484 /* In indirect mode when disabling interrupts, we also need
485 * to clear the interrupt bit in the GRC local ctrl register.
486 */
487 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
488 (val == 0x1)) {
489 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
490 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
491 }
492}
493
494static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
495{
496 unsigned long flags;
497 u32 val;
498
499 spin_lock_irqsave(&tp->indirect_lock, flags);
500 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
501 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
502 spin_unlock_irqrestore(&tp->indirect_lock, flags);
503 return val;
504}
505
Michael Chanb401e9e2005-12-19 16:27:04 -0800506/* usec_wait specifies the wait time in usec when writing to certain registers
507 * where it is unsafe to read back the register without some delay.
508 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
509 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
510 */
511static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512{
Joe Perches63c3a662011-04-26 08:12:10 +0000513 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
Michael Chanb401e9e2005-12-19 16:27:04 -0800514 /* Non-posted methods */
515 tp->write32(tp, off, val);
516 else {
517 /* Posted method */
518 tg3_write32(tp, off, val);
519 if (usec_wait)
520 udelay(usec_wait);
521 tp->read32(tp, off);
522 }
523 /* Wait again after the read for the posted method to guarantee that
524 * the wait time is met.
525 */
526 if (usec_wait)
527 udelay(usec_wait);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528}
529
Michael Chan09ee9292005-08-09 20:17:00 -0700530static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
531{
532 tp->write32_mbox(tp, off, val);
Joe Perches63c3a662011-04-26 08:12:10 +0000533 if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
Michael Chan68929142005-08-09 20:17:14 -0700534 tp->read32_mbox(tp, off);
Michael Chan09ee9292005-08-09 20:17:00 -0700535}
536
Michael Chan20094932005-08-09 20:16:32 -0700537static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538{
539 void __iomem *mbox = tp->regs + off;
540 writel(val, mbox);
Joe Perches63c3a662011-04-26 08:12:10 +0000541 if (tg3_flag(tp, TXD_MBOX_HWBUG))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542 writel(val, mbox);
Joe Perches63c3a662011-04-26 08:12:10 +0000543 if (tg3_flag(tp, MBOX_WRITE_REORDER))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544 readl(mbox);
545}
546
Michael Chanb5d37722006-09-27 16:06:21 -0700547static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
548{
Matt Carlsonde6f31e2010-04-12 06:58:30 +0000549 return readl(tp->regs + off + GRCMBOX_BASE);
Michael Chanb5d37722006-09-27 16:06:21 -0700550}
551
552static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
553{
554 writel(val, tp->regs + off + GRCMBOX_BASE);
555}
556
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000557#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
Michael Chan09ee9292005-08-09 20:17:00 -0700558#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000559#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
560#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
561#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
Michael Chan20094932005-08-09 20:16:32 -0700562
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000563#define tw32(reg, val) tp->write32(tp, reg, val)
564#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
565#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
566#define tr32(reg) tp->read32(tp, reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567
568static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
569{
Michael Chan68929142005-08-09 20:17:14 -0700570 unsigned long flags;
571
Matt Carlson6ff6f812011-05-19 12:12:54 +0000572 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
Michael Chanb5d37722006-09-27 16:06:21 -0700573 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
574 return;
575
Michael Chan68929142005-08-09 20:17:14 -0700576 spin_lock_irqsave(&tp->indirect_lock, flags);
Joe Perches63c3a662011-04-26 08:12:10 +0000577 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
Michael Chanbbadf502006-04-06 21:46:34 -0700578 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
579 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580
Michael Chanbbadf502006-04-06 21:46:34 -0700581 /* Always leave this as zero. */
582 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
583 } else {
584 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
585 tw32_f(TG3PCI_MEM_WIN_DATA, val);
586
587 /* Always leave this as zero. */
588 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
589 }
Michael Chan68929142005-08-09 20:17:14 -0700590 spin_unlock_irqrestore(&tp->indirect_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591}
592
593static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
594{
Michael Chan68929142005-08-09 20:17:14 -0700595 unsigned long flags;
596
Matt Carlson6ff6f812011-05-19 12:12:54 +0000597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
Michael Chanb5d37722006-09-27 16:06:21 -0700598 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
599 *val = 0;
600 return;
601 }
602
Michael Chan68929142005-08-09 20:17:14 -0700603 spin_lock_irqsave(&tp->indirect_lock, flags);
Joe Perches63c3a662011-04-26 08:12:10 +0000604 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
Michael Chanbbadf502006-04-06 21:46:34 -0700605 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
606 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607
Michael Chanbbadf502006-04-06 21:46:34 -0700608 /* Always leave this as zero. */
609 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
610 } else {
611 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
612 *val = tr32(TG3PCI_MEM_WIN_DATA);
613
614 /* Always leave this as zero. */
615 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
616 }
Michael Chan68929142005-08-09 20:17:14 -0700617 spin_unlock_irqrestore(&tp->indirect_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700618}
619
Matt Carlson0d3031d2007-10-10 18:02:43 -0700620static void tg3_ape_lock_init(struct tg3 *tp)
621{
622 int i;
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000623 u32 regbase, bit;
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000624
625 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
626 regbase = TG3_APE_LOCK_GRANT;
627 else
628 regbase = TG3_APE_PER_LOCK_GRANT;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700629
630 /* Make sure the driver hasn't any stale locks. */
Matt Carlson78f94dc2011-11-04 09:14:58 +0000631 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
632 switch (i) {
633 case TG3_APE_LOCK_PHY0:
634 case TG3_APE_LOCK_PHY1:
635 case TG3_APE_LOCK_PHY2:
636 case TG3_APE_LOCK_PHY3:
637 bit = APE_LOCK_GRANT_DRIVER;
638 break;
639 default:
640 if (!tp->pci_fn)
641 bit = APE_LOCK_GRANT_DRIVER;
642 else
643 bit = 1 << tp->pci_fn;
644 }
645 tg3_ape_write32(tp, regbase + 4 * i, bit);
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000646 }
647
Matt Carlson0d3031d2007-10-10 18:02:43 -0700648}
649
650static int tg3_ape_lock(struct tg3 *tp, int locknum)
651{
652 int i, off;
653 int ret = 0;
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000654 u32 status, req, gnt, bit;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700655
Joe Perches63c3a662011-04-26 08:12:10 +0000656 if (!tg3_flag(tp, ENABLE_APE))
Matt Carlson0d3031d2007-10-10 18:02:43 -0700657 return 0;
658
659 switch (locknum) {
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000660 case TG3_APE_LOCK_GPIO:
661 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
662 return 0;
Matt Carlson33f401a2010-04-05 10:19:27 +0000663 case TG3_APE_LOCK_GRC:
664 case TG3_APE_LOCK_MEM:
Matt Carlson78f94dc2011-11-04 09:14:58 +0000665 if (!tp->pci_fn)
666 bit = APE_LOCK_REQ_DRIVER;
667 else
668 bit = 1 << tp->pci_fn;
Matt Carlson33f401a2010-04-05 10:19:27 +0000669 break;
670 default:
671 return -EINVAL;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700672 }
673
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000674 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
675 req = TG3_APE_LOCK_REQ;
676 gnt = TG3_APE_LOCK_GRANT;
677 } else {
678 req = TG3_APE_PER_LOCK_REQ;
679 gnt = TG3_APE_PER_LOCK_GRANT;
680 }
681
Matt Carlson0d3031d2007-10-10 18:02:43 -0700682 off = 4 * locknum;
683
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000684 tg3_ape_write32(tp, req + off, bit);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700685
686 /* Wait for up to 1 millisecond to acquire lock. */
687 for (i = 0; i < 100; i++) {
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000688 status = tg3_ape_read32(tp, gnt + off);
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000689 if (status == bit)
Matt Carlson0d3031d2007-10-10 18:02:43 -0700690 break;
691 udelay(10);
692 }
693
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000694 if (status != bit) {
Matt Carlson0d3031d2007-10-10 18:02:43 -0700695 /* Revoke the lock request. */
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000696 tg3_ape_write32(tp, gnt + off, bit);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700697 ret = -EBUSY;
698 }
699
700 return ret;
701}
702
703static void tg3_ape_unlock(struct tg3 *tp, int locknum)
704{
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000705 u32 gnt, bit;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700706
Joe Perches63c3a662011-04-26 08:12:10 +0000707 if (!tg3_flag(tp, ENABLE_APE))
Matt Carlson0d3031d2007-10-10 18:02:43 -0700708 return;
709
710 switch (locknum) {
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000711 case TG3_APE_LOCK_GPIO:
712 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
713 return;
Matt Carlson33f401a2010-04-05 10:19:27 +0000714 case TG3_APE_LOCK_GRC:
715 case TG3_APE_LOCK_MEM:
Matt Carlson78f94dc2011-11-04 09:14:58 +0000716 if (!tp->pci_fn)
717 bit = APE_LOCK_GRANT_DRIVER;
718 else
719 bit = 1 << tp->pci_fn;
Matt Carlson33f401a2010-04-05 10:19:27 +0000720 break;
721 default:
722 return;
Matt Carlson0d3031d2007-10-10 18:02:43 -0700723 }
724
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000725 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
726 gnt = TG3_APE_LOCK_GRANT;
727 else
728 gnt = TG3_APE_PER_LOCK_GRANT;
729
Matt Carlson6f5c8f832011-07-13 09:27:31 +0000730 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
Matt Carlson0d3031d2007-10-10 18:02:43 -0700731}
732
Matt Carlsonfd6d3f02011-08-31 11:44:52 +0000733static void tg3_ape_send_event(struct tg3 *tp, u32 event)
734{
735 int i;
736 u32 apedata;
737
738 /* NCSI does not support APE events */
739 if (tg3_flag(tp, APE_HAS_NCSI))
740 return;
741
742 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
743 if (apedata != APE_SEG_SIG_MAGIC)
744 return;
745
746 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
747 if (!(apedata & APE_FW_STATUS_READY))
748 return;
749
750 /* Wait for up to 1 millisecond for APE to service previous event. */
751 for (i = 0; i < 10; i++) {
752 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
753 return;
754
755 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
756
757 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
758 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
759 event | APE_EVENT_STATUS_EVENT_PENDING);
760
761 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
762
763 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
764 break;
765
766 udelay(100);
767 }
768
769 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
770 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
771}
772
773static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
774{
775 u32 event;
776 u32 apedata;
777
778 if (!tg3_flag(tp, ENABLE_APE))
779 return;
780
781 switch (kind) {
782 case RESET_KIND_INIT:
783 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
784 APE_HOST_SEG_SIG_MAGIC);
785 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
786 APE_HOST_SEG_LEN_MAGIC);
787 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
788 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
789 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
790 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
791 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
792 APE_HOST_BEHAV_NO_PHYLOCK);
793 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
794 TG3_APE_HOST_DRVR_STATE_START);
795
796 event = APE_EVENT_STATUS_STATE_START;
797 break;
798 case RESET_KIND_SHUTDOWN:
799 /* With the interface we are currently using,
800 * APE does not track driver state. Wiping
801 * out the HOST SEGMENT SIGNATURE forces
802 * the APE to assume OS absent status.
803 */
804 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
805
806 if (device_may_wakeup(&tp->pdev->dev) &&
807 tg3_flag(tp, WOL_ENABLE)) {
808 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
809 TG3_APE_HOST_WOL_SPEED_AUTO);
810 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
811 } else
812 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
813
814 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
815
816 event = APE_EVENT_STATUS_STATE_UNLOAD;
817 break;
818 case RESET_KIND_SUSPEND:
819 event = APE_EVENT_STATUS_STATE_SUSPEND;
820 break;
821 default:
822 return;
823 }
824
825 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
826
827 tg3_ape_send_event(tp, event);
828}
829
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830static void tg3_disable_ints(struct tg3 *tp)
831{
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000832 int i;
833
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834 tw32(TG3PCI_MISC_HOST_CTRL,
835 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000836 for (i = 0; i < tp->irq_max; i++)
837 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838}
839
Linus Torvalds1da177e2005-04-16 15:20:36 -0700840static void tg3_enable_ints(struct tg3 *tp)
841{
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000842 int i;
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000843
Michael Chanbbe832c2005-06-24 20:20:04 -0700844 tp->irq_sync = 0;
845 wmb();
846
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847 tw32(TG3PCI_MISC_HOST_CTRL,
848 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
Matt Carlsonf19af9c2009-09-01 12:47:49 +0000849
Matt Carlsonf89f38b2010-02-12 14:47:07 +0000850 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000851 for (i = 0; i < tp->irq_cnt; i++) {
852 struct tg3_napi *tnapi = &tp->napi[i];
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000853
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000854 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
Joe Perches63c3a662011-04-26 08:12:10 +0000855 if (tg3_flag(tp, 1SHOT_MSI))
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000856 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
857
Matt Carlsonf89f38b2010-02-12 14:47:07 +0000858 tp->coal_now |= tnapi->coal_now;
Matt Carlson89aeb3b2009-09-01 13:08:58 +0000859 }
Matt Carlsonf19af9c2009-09-01 12:47:49 +0000860
861 /* Force an initial interrupt */
Joe Perches63c3a662011-04-26 08:12:10 +0000862 if (!tg3_flag(tp, TAGGED_STATUS) &&
Matt Carlsonf19af9c2009-09-01 12:47:49 +0000863 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
864 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
865 else
Matt Carlsonf89f38b2010-02-12 14:47:07 +0000866 tw32(HOSTCC_MODE, tp->coal_now);
867
868 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869}
870
Matt Carlson17375d22009-08-28 14:02:18 +0000871static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
Michael Chan04237dd2005-04-25 15:17:17 -0700872{
Matt Carlson17375d22009-08-28 14:02:18 +0000873 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +0000874 struct tg3_hw_status *sblk = tnapi->hw_status;
Michael Chan04237dd2005-04-25 15:17:17 -0700875 unsigned int work_exists = 0;
876
877 /* check for phy events */
Joe Perches63c3a662011-04-26 08:12:10 +0000878 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
Michael Chan04237dd2005-04-25 15:17:17 -0700879 if (sblk->status & SD_STATUS_LINK_CHG)
880 work_exists = 1;
881 }
882 /* check for RX/TX work to do */
Matt Carlsonf3f3f272009-08-28 14:03:21 +0000883 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
Matt Carlson8d9d7cf2009-09-01 13:19:05 +0000884 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
Michael Chan04237dd2005-04-25 15:17:17 -0700885 work_exists = 1;
886
887 return work_exists;
888}
889
Matt Carlson17375d22009-08-28 14:02:18 +0000890/* tg3_int_reenable
Michael Chan04237dd2005-04-25 15:17:17 -0700891 * similar to tg3_enable_ints, but it accurately determines whether there
892 * is new work pending and can return without flushing the PIO write
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400893 * which reenables interrupts
Linus Torvalds1da177e2005-04-16 15:20:36 -0700894 */
Matt Carlson17375d22009-08-28 14:02:18 +0000895static void tg3_int_reenable(struct tg3_napi *tnapi)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896{
Matt Carlson17375d22009-08-28 14:02:18 +0000897 struct tg3 *tp = tnapi->tp;
898
Matt Carlson898a56f2009-08-28 14:02:40 +0000899 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700900 mmiowb();
901
David S. Millerfac9b832005-05-18 22:46:34 -0700902 /* When doing tagged status, this work check is unnecessary.
903 * The last_tag we write above tells the chip which piece of
904 * work we've completed.
905 */
Joe Perches63c3a662011-04-26 08:12:10 +0000906 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
Michael Chan04237dd2005-04-25 15:17:17 -0700907 tw32(HOSTCC_MODE, tp->coalesce_mode |
Matt Carlsonfd2ce372009-09-01 12:51:13 +0000908 HOSTCC_MODE_ENABLE | tnapi->coal_now);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909}
910
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911static void tg3_switch_clocks(struct tg3 *tp)
912{
Matt Carlsonf6eb9b12009-09-01 13:19:53 +0000913 u32 clock_ctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914 u32 orig_clock_ctrl;
915
Joe Perches63c3a662011-04-26 08:12:10 +0000916 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
Michael Chan4cf78e42005-07-25 12:29:19 -0700917 return;
918
Matt Carlsonf6eb9b12009-09-01 13:19:53 +0000919 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
920
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921 orig_clock_ctrl = clock_ctrl;
922 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
923 CLOCK_CTRL_CLKRUN_OENABLE |
924 0x1f);
925 tp->pci_clock_ctrl = clock_ctrl;
926
Joe Perches63c3a662011-04-26 08:12:10 +0000927 if (tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700928 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
Michael Chanb401e9e2005-12-19 16:27:04 -0800929 tw32_wait_f(TG3PCI_CLOCK_CTRL,
930 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700931 }
932 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
Michael Chanb401e9e2005-12-19 16:27:04 -0800933 tw32_wait_f(TG3PCI_CLOCK_CTRL,
934 clock_ctrl |
935 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
936 40);
937 tw32_wait_f(TG3PCI_CLOCK_CTRL,
938 clock_ctrl | (CLOCK_CTRL_ALTCLK),
939 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700940 }
Michael Chanb401e9e2005-12-19 16:27:04 -0800941 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700942}
943
944#define PHY_BUSY_LOOPS 5000
945
946static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
947{
948 u32 frame_val;
949 unsigned int loops;
950 int ret;
951
952 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
953 tw32_f(MAC_MI_MODE,
954 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
955 udelay(80);
956 }
957
958 *val = 0x0;
959
Matt Carlson882e9792009-09-01 13:21:36 +0000960 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
Linus Torvalds1da177e2005-04-16 15:20:36 -0700961 MI_COM_PHY_ADDR_MASK);
962 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
963 MI_COM_REG_ADDR_MASK);
964 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400965
Linus Torvalds1da177e2005-04-16 15:20:36 -0700966 tw32_f(MAC_MI_COM, frame_val);
967
968 loops = PHY_BUSY_LOOPS;
969 while (loops != 0) {
970 udelay(10);
971 frame_val = tr32(MAC_MI_COM);
972
973 if ((frame_val & MI_COM_BUSY) == 0) {
974 udelay(5);
975 frame_val = tr32(MAC_MI_COM);
976 break;
977 }
978 loops -= 1;
979 }
980
981 ret = -EBUSY;
982 if (loops != 0) {
983 *val = frame_val & MI_COM_DATA_MASK;
984 ret = 0;
985 }
986
987 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
988 tw32_f(MAC_MI_MODE, tp->mi_mode);
989 udelay(80);
990 }
991
992 return ret;
993}
994
995static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
996{
997 u32 frame_val;
998 unsigned int loops;
999 int ret;
1000
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001001 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
Matt Carlson221c5632011-06-13 13:39:01 +00001002 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
Michael Chanb5d37722006-09-27 16:06:21 -07001003 return 0;
1004
Linus Torvalds1da177e2005-04-16 15:20:36 -07001005 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1006 tw32_f(MAC_MI_MODE,
1007 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1008 udelay(80);
1009 }
1010
Matt Carlson882e9792009-09-01 13:21:36 +00001011 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
Linus Torvalds1da177e2005-04-16 15:20:36 -07001012 MI_COM_PHY_ADDR_MASK);
1013 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1014 MI_COM_REG_ADDR_MASK);
1015 frame_val |= (val & MI_COM_DATA_MASK);
1016 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001017
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018 tw32_f(MAC_MI_COM, frame_val);
1019
1020 loops = PHY_BUSY_LOOPS;
1021 while (loops != 0) {
1022 udelay(10);
1023 frame_val = tr32(MAC_MI_COM);
1024 if ((frame_val & MI_COM_BUSY) == 0) {
1025 udelay(5);
1026 frame_val = tr32(MAC_MI_COM);
1027 break;
1028 }
1029 loops -= 1;
1030 }
1031
1032 ret = -EBUSY;
1033 if (loops != 0)
1034 ret = 0;
1035
1036 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1037 tw32_f(MAC_MI_MODE, tp->mi_mode);
1038 udelay(80);
1039 }
1040
1041 return ret;
1042}
1043
Matt Carlsonb0988c12011-04-20 07:57:39 +00001044static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1045{
1046 int err;
1047
1048 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1049 if (err)
1050 goto done;
1051
1052 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1053 if (err)
1054 goto done;
1055
1056 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1057 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1058 if (err)
1059 goto done;
1060
1061 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1062
1063done:
1064 return err;
1065}
1066
1067static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1068{
1069 int err;
1070
1071 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1072 if (err)
1073 goto done;
1074
1075 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1076 if (err)
1077 goto done;
1078
1079 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1080 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1081 if (err)
1082 goto done;
1083
1084 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1085
1086done:
1087 return err;
1088}
1089
1090static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1091{
1092 int err;
1093
1094 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1095 if (!err)
1096 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1097
1098 return err;
1099}
1100
1101static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1102{
1103 int err;
1104
1105 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1106 if (!err)
1107 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1108
1109 return err;
1110}
1111
Matt Carlson15ee95c2011-04-20 07:57:40 +00001112static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1113{
1114 int err;
1115
1116 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1117 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1118 MII_TG3_AUXCTL_SHDWSEL_MISC);
1119 if (!err)
1120 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1121
1122 return err;
1123}
1124
Matt Carlsonb4bd2922011-04-20 07:57:41 +00001125static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1126{
1127 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1128 set |= MII_TG3_AUXCTL_MISC_WREN;
1129
1130 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1131}
1132
Matt Carlson1d36ba42011-04-20 07:57:42 +00001133#define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1134 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1135 MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1136 MII_TG3_AUXCTL_ACTL_TX_6DB)
1137
1138#define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1139 tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1140 MII_TG3_AUXCTL_ACTL_TX_6DB);
1141
Matt Carlson95e28692008-05-25 23:44:14 -07001142static int tg3_bmcr_reset(struct tg3 *tp)
1143{
1144 u32 phy_control;
1145 int limit, err;
1146
1147 /* OK, reset it, and poll the BMCR_RESET bit until it
1148 * clears or we time out.
1149 */
1150 phy_control = BMCR_RESET;
1151 err = tg3_writephy(tp, MII_BMCR, phy_control);
1152 if (err != 0)
1153 return -EBUSY;
1154
1155 limit = 5000;
1156 while (limit--) {
1157 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1158 if (err != 0)
1159 return -EBUSY;
1160
1161 if ((phy_control & BMCR_RESET) == 0) {
1162 udelay(40);
1163 break;
1164 }
1165 udelay(10);
1166 }
Roel Kluind4675b52009-02-12 16:33:27 -08001167 if (limit < 0)
Matt Carlson95e28692008-05-25 23:44:14 -07001168 return -EBUSY;
1169
1170 return 0;
1171}
1172
Matt Carlson158d7ab2008-05-29 01:37:54 -07001173static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1174{
Francois Romieu3d165432009-01-19 16:56:50 -08001175 struct tg3 *tp = bp->priv;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001176 u32 val;
1177
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001178 spin_lock_bh(&tp->lock);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001179
1180 if (tg3_readphy(tp, reg, &val))
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001181 val = -EIO;
1182
1183 spin_unlock_bh(&tp->lock);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001184
1185 return val;
1186}
1187
1188static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1189{
Francois Romieu3d165432009-01-19 16:56:50 -08001190 struct tg3 *tp = bp->priv;
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001191 u32 ret = 0;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001192
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001193 spin_lock_bh(&tp->lock);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001194
1195 if (tg3_writephy(tp, reg, val))
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001196 ret = -EIO;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001197
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001198 spin_unlock_bh(&tp->lock);
1199
1200 return ret;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001201}
1202
1203static int tg3_mdio_reset(struct mii_bus *bp)
1204{
1205 return 0;
1206}
1207
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001208static void tg3_mdio_config_5785(struct tg3 *tp)
Matt Carlsona9daf362008-05-25 23:49:44 -07001209{
1210 u32 val;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001211 struct phy_device *phydev;
Matt Carlsona9daf362008-05-25 23:49:44 -07001212
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001213 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001214 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
Matt Carlson6a443a02010-02-17 15:17:04 +00001215 case PHY_ID_BCM50610:
1216 case PHY_ID_BCM50610M:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001217 val = MAC_PHYCFG2_50610_LED_MODES;
1218 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001219 case PHY_ID_BCMAC131:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001220 val = MAC_PHYCFG2_AC131_LED_MODES;
1221 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001222 case PHY_ID_RTL8211C:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001223 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1224 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001225 case PHY_ID_RTL8201E:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001226 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1227 break;
1228 default:
Matt Carlsona9daf362008-05-25 23:49:44 -07001229 return;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001230 }
1231
1232 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1233 tw32(MAC_PHYCFG2, val);
1234
1235 val = tr32(MAC_PHYCFG1);
Matt Carlsonbb85fbb2009-08-25 10:09:07 +00001236 val &= ~(MAC_PHYCFG1_RGMII_INT |
1237 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1238 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001239 tw32(MAC_PHYCFG1, val);
1240
1241 return;
1242 }
1243
Joe Perches63c3a662011-04-26 08:12:10 +00001244 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001245 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1246 MAC_PHYCFG2_FMODE_MASK_MASK |
1247 MAC_PHYCFG2_GMODE_MASK_MASK |
1248 MAC_PHYCFG2_ACT_MASK_MASK |
1249 MAC_PHYCFG2_QUAL_MASK_MASK |
1250 MAC_PHYCFG2_INBAND_ENABLE;
1251
1252 tw32(MAC_PHYCFG2, val);
Matt Carlsona9daf362008-05-25 23:49:44 -07001253
Matt Carlsonbb85fbb2009-08-25 10:09:07 +00001254 val = tr32(MAC_PHYCFG1);
1255 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1256 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
Joe Perches63c3a662011-04-26 08:12:10 +00001257 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1258 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
Matt Carlsona9daf362008-05-25 23:49:44 -07001259 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
Joe Perches63c3a662011-04-26 08:12:10 +00001260 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
Matt Carlsona9daf362008-05-25 23:49:44 -07001261 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1262 }
Matt Carlsonbb85fbb2009-08-25 10:09:07 +00001263 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1264 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1265 tw32(MAC_PHYCFG1, val);
Matt Carlsona9daf362008-05-25 23:49:44 -07001266
Matt Carlsona9daf362008-05-25 23:49:44 -07001267 val = tr32(MAC_EXT_RGMII_MODE);
1268 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1269 MAC_RGMII_MODE_RX_QUALITY |
1270 MAC_RGMII_MODE_RX_ACTIVITY |
1271 MAC_RGMII_MODE_RX_ENG_DET |
1272 MAC_RGMII_MODE_TX_ENABLE |
1273 MAC_RGMII_MODE_TX_LOWPWR |
1274 MAC_RGMII_MODE_TX_RESET);
Joe Perches63c3a662011-04-26 08:12:10 +00001275 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1276 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
Matt Carlsona9daf362008-05-25 23:49:44 -07001277 val |= MAC_RGMII_MODE_RX_INT_B |
1278 MAC_RGMII_MODE_RX_QUALITY |
1279 MAC_RGMII_MODE_RX_ACTIVITY |
1280 MAC_RGMII_MODE_RX_ENG_DET;
Joe Perches63c3a662011-04-26 08:12:10 +00001281 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
Matt Carlsona9daf362008-05-25 23:49:44 -07001282 val |= MAC_RGMII_MODE_TX_ENABLE |
1283 MAC_RGMII_MODE_TX_LOWPWR |
1284 MAC_RGMII_MODE_TX_RESET;
1285 }
1286 tw32(MAC_EXT_RGMII_MODE, val);
1287}
1288
Matt Carlson158d7ab2008-05-29 01:37:54 -07001289static void tg3_mdio_start(struct tg3 *tp)
1290{
Matt Carlson158d7ab2008-05-29 01:37:54 -07001291 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1292 tw32_f(MAC_MI_MODE, tp->mi_mode);
1293 udelay(80);
Matt Carlsona9daf362008-05-25 23:49:44 -07001294
Joe Perches63c3a662011-04-26 08:12:10 +00001295 if (tg3_flag(tp, MDIOBUS_INITED) &&
Matt Carlson9ea48182010-02-17 15:17:01 +00001296 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1297 tg3_mdio_config_5785(tp);
1298}
1299
1300static int tg3_mdio_init(struct tg3 *tp)
1301{
1302 int i;
1303 u32 reg;
1304 struct phy_device *phydev;
1305
Joe Perches63c3a662011-04-26 08:12:10 +00001306 if (tg3_flag(tp, 5717_PLUS)) {
Matt Carlson9c7df912010-06-05 17:24:36 +00001307 u32 is_serdes;
Matt Carlson882e9792009-09-01 13:21:36 +00001308
Matt Carlson69f11c92011-07-13 09:27:30 +00001309 tp->phy_addr = tp->pci_fn + 1;
Matt Carlson882e9792009-09-01 13:21:36 +00001310
Matt Carlsond1ec96a2010-01-12 10:11:38 +00001311 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1312 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1313 else
1314 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1315 TG3_CPMU_PHY_STRAP_IS_SERDES;
Matt Carlson882e9792009-09-01 13:21:36 +00001316 if (is_serdes)
1317 tp->phy_addr += 7;
1318 } else
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001319 tp->phy_addr = TG3_PHY_MII_ADDR;
Matt Carlson882e9792009-09-01 13:21:36 +00001320
Matt Carlson158d7ab2008-05-29 01:37:54 -07001321 tg3_mdio_start(tp);
1322
Joe Perches63c3a662011-04-26 08:12:10 +00001323 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
Matt Carlson158d7ab2008-05-29 01:37:54 -07001324 return 0;
1325
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001326 tp->mdio_bus = mdiobus_alloc();
1327 if (tp->mdio_bus == NULL)
1328 return -ENOMEM;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001329
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001330 tp->mdio_bus->name = "tg3 mdio bus";
1331 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
Matt Carlson158d7ab2008-05-29 01:37:54 -07001332 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001333 tp->mdio_bus->priv = tp;
1334 tp->mdio_bus->parent = &tp->pdev->dev;
1335 tp->mdio_bus->read = &tg3_mdio_read;
1336 tp->mdio_bus->write = &tg3_mdio_write;
1337 tp->mdio_bus->reset = &tg3_mdio_reset;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001338 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001339 tp->mdio_bus->irq = &tp->mdio_irq[0];
Matt Carlson158d7ab2008-05-29 01:37:54 -07001340
1341 for (i = 0; i < PHY_MAX_ADDR; i++)
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001342 tp->mdio_bus->irq[i] = PHY_POLL;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001343
1344 /* The bus registration will look for all the PHYs on the mdio bus.
1345 * Unfortunately, it does not ensure the PHY is powered up before
1346 * accessing the PHY ID registers. A chip reset is the
1347 * quickest way to bring the device back to an operational state..
1348 */
1349 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1350 tg3_bmcr_reset(tp);
1351
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001352 i = mdiobus_register(tp->mdio_bus);
Matt Carlsona9daf362008-05-25 23:49:44 -07001353 if (i) {
Matt Carlsonab96b242010-04-05 10:19:22 +00001354 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001355 mdiobus_free(tp->mdio_bus);
Matt Carlsona9daf362008-05-25 23:49:44 -07001356 return i;
1357 }
Matt Carlson158d7ab2008-05-29 01:37:54 -07001358
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001359 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsona9daf362008-05-25 23:49:44 -07001360
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001361 if (!phydev || !phydev->drv) {
Matt Carlsonab96b242010-04-05 10:19:22 +00001362 dev_warn(&tp->pdev->dev, "No PHY devices\n");
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001363 mdiobus_unregister(tp->mdio_bus);
1364 mdiobus_free(tp->mdio_bus);
1365 return -ENODEV;
1366 }
1367
1368 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
Matt Carlson6a443a02010-02-17 15:17:04 +00001369 case PHY_ID_BCM57780:
Matt Carlson321d32a2008-11-21 17:22:19 -08001370 phydev->interface = PHY_INTERFACE_MODE_GMII;
Matt Carlsonc704dc22009-11-02 14:32:12 +00001371 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
Matt Carlson321d32a2008-11-21 17:22:19 -08001372 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001373 case PHY_ID_BCM50610:
1374 case PHY_ID_BCM50610M:
Matt Carlson32e5a8d2009-11-02 14:31:39 +00001375 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
Matt Carlsonc704dc22009-11-02 14:32:12 +00001376 PHY_BRCM_RX_REFCLK_UNUSED |
Matt Carlson52fae082009-11-02 14:32:38 +00001377 PHY_BRCM_DIS_TXCRXC_NOENRGY |
Matt Carlsonc704dc22009-11-02 14:32:12 +00001378 PHY_BRCM_AUTO_PWRDWN_ENABLE;
Joe Perches63c3a662011-04-26 08:12:10 +00001379 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
Matt Carlsona9daf362008-05-25 23:49:44 -07001380 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
Joe Perches63c3a662011-04-26 08:12:10 +00001381 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
Matt Carlsona9daf362008-05-25 23:49:44 -07001382 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
Joe Perches63c3a662011-04-26 08:12:10 +00001383 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
Matt Carlsona9daf362008-05-25 23:49:44 -07001384 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001385 /* fallthru */
Matt Carlson6a443a02010-02-17 15:17:04 +00001386 case PHY_ID_RTL8211C:
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001387 phydev->interface = PHY_INTERFACE_MODE_RGMII;
Matt Carlsona9daf362008-05-25 23:49:44 -07001388 break;
Matt Carlson6a443a02010-02-17 15:17:04 +00001389 case PHY_ID_RTL8201E:
1390 case PHY_ID_BCMAC131:
Matt Carlsona9daf362008-05-25 23:49:44 -07001391 phydev->interface = PHY_INTERFACE_MODE_MII;
Matt Carlsoncdd4e09d2009-11-02 14:31:11 +00001392 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001393 tp->phy_flags |= TG3_PHYFLG_IS_FET;
Matt Carlsona9daf362008-05-25 23:49:44 -07001394 break;
1395 }
1396
Joe Perches63c3a662011-04-26 08:12:10 +00001397 tg3_flag_set(tp, MDIOBUS_INITED);
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001398
1399 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1400 tg3_mdio_config_5785(tp);
Matt Carlsona9daf362008-05-25 23:49:44 -07001401
1402 return 0;
Matt Carlson158d7ab2008-05-29 01:37:54 -07001403}
1404
1405static void tg3_mdio_fini(struct tg3 *tp)
1406{
Joe Perches63c3a662011-04-26 08:12:10 +00001407 if (tg3_flag(tp, MDIOBUS_INITED)) {
1408 tg3_flag_clear(tp, MDIOBUS_INITED);
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07001409 mdiobus_unregister(tp->mdio_bus);
1410 mdiobus_free(tp->mdio_bus);
Matt Carlson158d7ab2008-05-29 01:37:54 -07001411 }
1412}
1413
Matt Carlson95e28692008-05-25 23:44:14 -07001414/* tp->lock is held. */
Matt Carlson4ba526c2008-08-15 14:10:04 -07001415static inline void tg3_generate_fw_event(struct tg3 *tp)
1416{
1417 u32 val;
1418
1419 val = tr32(GRC_RX_CPU_EVENT);
1420 val |= GRC_RX_CPU_DRIVER_EVENT;
1421 tw32_f(GRC_RX_CPU_EVENT, val);
1422
1423 tp->last_event_jiffies = jiffies;
1424}
1425
1426#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1427
1428/* tp->lock is held. */
Matt Carlson95e28692008-05-25 23:44:14 -07001429static void tg3_wait_for_event_ack(struct tg3 *tp)
1430{
1431 int i;
Matt Carlson4ba526c2008-08-15 14:10:04 -07001432 unsigned int delay_cnt;
1433 long time_remain;
Matt Carlson95e28692008-05-25 23:44:14 -07001434
Matt Carlson4ba526c2008-08-15 14:10:04 -07001435 /* If enough time has passed, no wait is necessary. */
1436 time_remain = (long)(tp->last_event_jiffies + 1 +
1437 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1438 (long)jiffies;
1439 if (time_remain < 0)
1440 return;
1441
1442 /* Check if we can shorten the wait time. */
1443 delay_cnt = jiffies_to_usecs(time_remain);
1444 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1445 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1446 delay_cnt = (delay_cnt >> 3) + 1;
1447
1448 for (i = 0; i < delay_cnt; i++) {
Matt Carlson95e28692008-05-25 23:44:14 -07001449 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1450 break;
Matt Carlson4ba526c2008-08-15 14:10:04 -07001451 udelay(8);
Matt Carlson95e28692008-05-25 23:44:14 -07001452 }
1453}
1454
1455/* tp->lock is held. */
1456static void tg3_ump_link_report(struct tg3 *tp)
1457{
1458 u32 reg;
1459 u32 val;
1460
Joe Perches63c3a662011-04-26 08:12:10 +00001461 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
Matt Carlson95e28692008-05-25 23:44:14 -07001462 return;
1463
1464 tg3_wait_for_event_ack(tp);
1465
1466 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1467
1468 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1469
1470 val = 0;
1471 if (!tg3_readphy(tp, MII_BMCR, &reg))
1472 val = reg << 16;
1473 if (!tg3_readphy(tp, MII_BMSR, &reg))
1474 val |= (reg & 0xffff);
1475 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1476
1477 val = 0;
1478 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1479 val = reg << 16;
1480 if (!tg3_readphy(tp, MII_LPA, &reg))
1481 val |= (reg & 0xffff);
1482 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1483
1484 val = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001485 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
Matt Carlson95e28692008-05-25 23:44:14 -07001486 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1487 val = reg << 16;
1488 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1489 val |= (reg & 0xffff);
1490 }
1491 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1492
1493 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1494 val = reg << 16;
1495 else
1496 val = 0;
1497 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1498
Matt Carlson4ba526c2008-08-15 14:10:04 -07001499 tg3_generate_fw_event(tp);
Matt Carlson95e28692008-05-25 23:44:14 -07001500}
1501
Matt Carlson8d5a89b2011-08-31 11:44:51 +00001502/* tp->lock is held. */
1503static void tg3_stop_fw(struct tg3 *tp)
1504{
1505 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1506 /* Wait for RX cpu to ACK the previous event. */
1507 tg3_wait_for_event_ack(tp);
1508
1509 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1510
1511 tg3_generate_fw_event(tp);
1512
1513 /* Wait for RX cpu to ACK this event. */
1514 tg3_wait_for_event_ack(tp);
1515 }
1516}
1517
Matt Carlsonfd6d3f02011-08-31 11:44:52 +00001518/* tp->lock is held. */
1519static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1520{
1521 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1522 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1523
1524 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1525 switch (kind) {
1526 case RESET_KIND_INIT:
1527 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1528 DRV_STATE_START);
1529 break;
1530
1531 case RESET_KIND_SHUTDOWN:
1532 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1533 DRV_STATE_UNLOAD);
1534 break;
1535
1536 case RESET_KIND_SUSPEND:
1537 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1538 DRV_STATE_SUSPEND);
1539 break;
1540
1541 default:
1542 break;
1543 }
1544 }
1545
1546 if (kind == RESET_KIND_INIT ||
1547 kind == RESET_KIND_SUSPEND)
1548 tg3_ape_driver_state_change(tp, kind);
1549}
1550
1551/* tp->lock is held. */
1552static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1553{
1554 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1555 switch (kind) {
1556 case RESET_KIND_INIT:
1557 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1558 DRV_STATE_START_DONE);
1559 break;
1560
1561 case RESET_KIND_SHUTDOWN:
1562 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1563 DRV_STATE_UNLOAD_DONE);
1564 break;
1565
1566 default:
1567 break;
1568 }
1569 }
1570
1571 if (kind == RESET_KIND_SHUTDOWN)
1572 tg3_ape_driver_state_change(tp, kind);
1573}
1574
1575/* tp->lock is held. */
1576static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1577{
1578 if (tg3_flag(tp, ENABLE_ASF)) {
1579 switch (kind) {
1580 case RESET_KIND_INIT:
1581 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1582 DRV_STATE_START);
1583 break;
1584
1585 case RESET_KIND_SHUTDOWN:
1586 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1587 DRV_STATE_UNLOAD);
1588 break;
1589
1590 case RESET_KIND_SUSPEND:
1591 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1592 DRV_STATE_SUSPEND);
1593 break;
1594
1595 default:
1596 break;
1597 }
1598 }
1599}
1600
1601static int tg3_poll_fw(struct tg3 *tp)
1602{
1603 int i;
1604 u32 val;
1605
1606 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1607 /* Wait up to 20ms for init done. */
1608 for (i = 0; i < 200; i++) {
1609 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1610 return 0;
1611 udelay(100);
1612 }
1613 return -ENODEV;
1614 }
1615
1616 /* Wait for firmware initialization to complete. */
1617 for (i = 0; i < 100000; i++) {
1618 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1619 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1620 break;
1621 udelay(10);
1622 }
1623
1624 /* Chip might not be fitted with firmware. Some Sun onboard
1625 * parts are configured like that. So don't signal the timeout
1626 * of the above loop as an error, but do report the lack of
1627 * running firmware once.
1628 */
1629 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1630 tg3_flag_set(tp, NO_FWARE_REPORTED);
1631
1632 netdev_info(tp->dev, "No firmware running\n");
1633 }
1634
1635 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1636 /* The 57765 A0 needs a little more
1637 * time to do some important work.
1638 */
1639 mdelay(10);
1640 }
1641
1642 return 0;
1643}
1644
Matt Carlson95e28692008-05-25 23:44:14 -07001645static void tg3_link_report(struct tg3 *tp)
1646{
1647 if (!netif_carrier_ok(tp->dev)) {
Joe Perches05dbe002010-02-17 19:44:19 +00001648 netif_info(tp, link, tp->dev, "Link is down\n");
Matt Carlson95e28692008-05-25 23:44:14 -07001649 tg3_ump_link_report(tp);
1650 } else if (netif_msg_link(tp)) {
Joe Perches05dbe002010-02-17 19:44:19 +00001651 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1652 (tp->link_config.active_speed == SPEED_1000 ?
1653 1000 :
1654 (tp->link_config.active_speed == SPEED_100 ?
1655 100 : 10)),
1656 (tp->link_config.active_duplex == DUPLEX_FULL ?
1657 "full" : "half"));
Matt Carlson95e28692008-05-25 23:44:14 -07001658
Joe Perches05dbe002010-02-17 19:44:19 +00001659 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1660 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1661 "on" : "off",
1662 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1663 "on" : "off");
Matt Carlson47007832011-04-20 07:57:43 +00001664
1665 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1666 netdev_info(tp->dev, "EEE is %s\n",
1667 tp->setlpicnt ? "enabled" : "disabled");
1668
Matt Carlson95e28692008-05-25 23:44:14 -07001669 tg3_ump_link_report(tp);
1670 }
1671}
1672
1673static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1674{
1675 u16 miireg;
1676
Steve Glendinninge18ce342008-12-16 02:00:00 -08001677 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
Matt Carlson95e28692008-05-25 23:44:14 -07001678 miireg = ADVERTISE_PAUSE_CAP;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001679 else if (flow_ctrl & FLOW_CTRL_TX)
Matt Carlson95e28692008-05-25 23:44:14 -07001680 miireg = ADVERTISE_PAUSE_ASYM;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001681 else if (flow_ctrl & FLOW_CTRL_RX)
Matt Carlson95e28692008-05-25 23:44:14 -07001682 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1683 else
1684 miireg = 0;
1685
1686 return miireg;
1687}
1688
1689static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1690{
1691 u16 miireg;
1692
Steve Glendinninge18ce342008-12-16 02:00:00 -08001693 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
Matt Carlson95e28692008-05-25 23:44:14 -07001694 miireg = ADVERTISE_1000XPAUSE;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001695 else if (flow_ctrl & FLOW_CTRL_TX)
Matt Carlson95e28692008-05-25 23:44:14 -07001696 miireg = ADVERTISE_1000XPSE_ASYM;
Steve Glendinninge18ce342008-12-16 02:00:00 -08001697 else if (flow_ctrl & FLOW_CTRL_RX)
Matt Carlson95e28692008-05-25 23:44:14 -07001698 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1699 else
1700 miireg = 0;
1701
1702 return miireg;
1703}
1704
Matt Carlson95e28692008-05-25 23:44:14 -07001705static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1706{
1707 u8 cap = 0;
1708
1709 if (lcladv & ADVERTISE_1000XPAUSE) {
1710 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1711 if (rmtadv & LPA_1000XPAUSE)
Steve Glendinninge18ce342008-12-16 02:00:00 -08001712 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
Matt Carlson95e28692008-05-25 23:44:14 -07001713 else if (rmtadv & LPA_1000XPAUSE_ASYM)
Steve Glendinninge18ce342008-12-16 02:00:00 -08001714 cap = FLOW_CTRL_RX;
Matt Carlson95e28692008-05-25 23:44:14 -07001715 } else {
1716 if (rmtadv & LPA_1000XPAUSE)
Steve Glendinninge18ce342008-12-16 02:00:00 -08001717 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
Matt Carlson95e28692008-05-25 23:44:14 -07001718 }
1719 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1720 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
Steve Glendinninge18ce342008-12-16 02:00:00 -08001721 cap = FLOW_CTRL_TX;
Matt Carlson95e28692008-05-25 23:44:14 -07001722 }
1723
1724 return cap;
1725}
1726
Matt Carlsonf51f3562008-05-25 23:45:08 -07001727static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
Matt Carlson95e28692008-05-25 23:44:14 -07001728{
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001729 u8 autoneg;
Matt Carlsonf51f3562008-05-25 23:45:08 -07001730 u8 flowctrl = 0;
Matt Carlson95e28692008-05-25 23:44:14 -07001731 u32 old_rx_mode = tp->rx_mode;
1732 u32 old_tx_mode = tp->tx_mode;
1733
Joe Perches63c3a662011-04-26 08:12:10 +00001734 if (tg3_flag(tp, USE_PHYLIB))
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001735 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001736 else
1737 autoneg = tp->link_config.autoneg;
1738
Joe Perches63c3a662011-04-26 08:12:10 +00001739 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001740 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
Matt Carlsonf51f3562008-05-25 23:45:08 -07001741 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
Matt Carlson95e28692008-05-25 23:44:14 -07001742 else
Steve Glendinningbc02ff92008-12-16 02:00:48 -08001743 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
Matt Carlsonf51f3562008-05-25 23:45:08 -07001744 } else
1745 flowctrl = tp->link_config.flowctrl;
Matt Carlson95e28692008-05-25 23:44:14 -07001746
Matt Carlsonf51f3562008-05-25 23:45:08 -07001747 tp->link_config.active_flowctrl = flowctrl;
Matt Carlson95e28692008-05-25 23:44:14 -07001748
Steve Glendinninge18ce342008-12-16 02:00:00 -08001749 if (flowctrl & FLOW_CTRL_RX)
Matt Carlson95e28692008-05-25 23:44:14 -07001750 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1751 else
1752 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1753
Matt Carlsonf51f3562008-05-25 23:45:08 -07001754 if (old_rx_mode != tp->rx_mode)
Matt Carlson95e28692008-05-25 23:44:14 -07001755 tw32_f(MAC_RX_MODE, tp->rx_mode);
Matt Carlson95e28692008-05-25 23:44:14 -07001756
Steve Glendinninge18ce342008-12-16 02:00:00 -08001757 if (flowctrl & FLOW_CTRL_TX)
Matt Carlson95e28692008-05-25 23:44:14 -07001758 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1759 else
1760 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1761
Matt Carlsonf51f3562008-05-25 23:45:08 -07001762 if (old_tx_mode != tp->tx_mode)
Matt Carlson95e28692008-05-25 23:44:14 -07001763 tw32_f(MAC_TX_MODE, tp->tx_mode);
Matt Carlson95e28692008-05-25 23:44:14 -07001764}
1765
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001766static void tg3_adjust_link(struct net_device *dev)
1767{
1768 u8 oldflowctrl, linkmesg = 0;
1769 u32 mac_mode, lcl_adv, rmt_adv;
1770 struct tg3 *tp = netdev_priv(dev);
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001771 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001772
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001773 spin_lock_bh(&tp->lock);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001774
1775 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1776 MAC_MODE_HALF_DUPLEX);
1777
1778 oldflowctrl = tp->link_config.active_flowctrl;
1779
1780 if (phydev->link) {
1781 lcl_adv = 0;
1782 rmt_adv = 0;
1783
1784 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1785 mac_mode |= MAC_MODE_PORT_MODE_MII;
Matt Carlsonc3df0742009-11-02 14:27:02 +00001786 else if (phydev->speed == SPEED_1000 ||
1787 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001788 mac_mode |= MAC_MODE_PORT_MODE_GMII;
Matt Carlsonc3df0742009-11-02 14:27:02 +00001789 else
1790 mac_mode |= MAC_MODE_PORT_MODE_MII;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001791
1792 if (phydev->duplex == DUPLEX_HALF)
1793 mac_mode |= MAC_MODE_HALF_DUPLEX;
1794 else {
1795 lcl_adv = tg3_advert_flowctrl_1000T(
1796 tp->link_config.flowctrl);
1797
1798 if (phydev->pause)
1799 rmt_adv = LPA_PAUSE_CAP;
1800 if (phydev->asym_pause)
1801 rmt_adv |= LPA_PAUSE_ASYM;
1802 }
1803
1804 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1805 } else
1806 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1807
1808 if (mac_mode != tp->mac_mode) {
1809 tp->mac_mode = mac_mode;
1810 tw32_f(MAC_MODE, tp->mac_mode);
1811 udelay(40);
1812 }
1813
Matt Carlsonfcb389d2008-11-03 16:55:44 -08001814 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1815 if (phydev->speed == SPEED_10)
1816 tw32(MAC_MI_STAT,
1817 MAC_MI_STAT_10MBPS_MODE |
1818 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1819 else
1820 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1821 }
1822
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001823 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1824 tw32(MAC_TX_LENGTHS,
1825 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1826 (6 << TX_LENGTHS_IPG_SHIFT) |
1827 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1828 else
1829 tw32(MAC_TX_LENGTHS,
1830 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1831 (6 << TX_LENGTHS_IPG_SHIFT) |
1832 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1833
1834 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1835 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1836 phydev->speed != tp->link_config.active_speed ||
1837 phydev->duplex != tp->link_config.active_duplex ||
1838 oldflowctrl != tp->link_config.active_flowctrl)
Matt Carlsonc6cdf432010-04-05 10:19:26 +00001839 linkmesg = 1;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001840
1841 tp->link_config.active_speed = phydev->speed;
1842 tp->link_config.active_duplex = phydev->duplex;
1843
Matt Carlson24bb4fb2009-10-05 17:55:29 +00001844 spin_unlock_bh(&tp->lock);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001845
1846 if (linkmesg)
1847 tg3_link_report(tp);
1848}
1849
1850static int tg3_phy_init(struct tg3 *tp)
1851{
1852 struct phy_device *phydev;
1853
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001854 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001855 return 0;
1856
1857 /* Bring the PHY back to a known state. */
1858 tg3_bmcr_reset(tp);
1859
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001860 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001861
1862 /* Attach the MAC to the PHY. */
Kay Sieversfb28ad32008-11-10 13:55:14 -08001863 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
Matt Carlsona9daf362008-05-25 23:49:44 -07001864 phydev->dev_flags, phydev->interface);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001865 if (IS_ERR(phydev)) {
Matt Carlsonab96b242010-04-05 10:19:22 +00001866 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001867 return PTR_ERR(phydev);
1868 }
1869
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001870 /* Mask with MAC supported features. */
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001871 switch (phydev->interface) {
1872 case PHY_INTERFACE_MODE_GMII:
1873 case PHY_INTERFACE_MODE_RGMII:
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001874 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
Matt Carlson321d32a2008-11-21 17:22:19 -08001875 phydev->supported &= (PHY_GBIT_FEATURES |
1876 SUPPORTED_Pause |
1877 SUPPORTED_Asym_Pause);
1878 break;
1879 }
1880 /* fallthru */
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001881 case PHY_INTERFACE_MODE_MII:
1882 phydev->supported &= (PHY_BASIC_FEATURES |
1883 SUPPORTED_Pause |
1884 SUPPORTED_Asym_Pause);
1885 break;
1886 default:
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001887 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlson9c61d6b2008-11-03 16:54:56 -08001888 return -EINVAL;
1889 }
1890
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001891 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001892
1893 phydev->advertising = phydev->supported;
1894
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001895 return 0;
1896}
1897
1898static void tg3_phy_start(struct tg3 *tp)
1899{
1900 struct phy_device *phydev;
1901
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001902 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001903 return;
1904
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001905 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001906
Matt Carlson80096062010-08-02 11:26:06 +00001907 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1908 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001909 phydev->speed = tp->link_config.orig_speed;
1910 phydev->duplex = tp->link_config.orig_duplex;
1911 phydev->autoneg = tp->link_config.orig_autoneg;
1912 phydev->advertising = tp->link_config.orig_advertising;
1913 }
1914
1915 phy_start(phydev);
1916
1917 phy_start_aneg(phydev);
1918}
1919
1920static void tg3_phy_stop(struct tg3 *tp)
1921{
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001922 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001923 return;
1924
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001925 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001926}
1927
1928static void tg3_phy_fini(struct tg3 *tp)
1929{
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001930 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00001931 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001932 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07001933 }
1934}
1935
Matt Carlson941ec902011-08-19 13:58:23 +00001936static int tg3_phy_set_extloopbk(struct tg3 *tp)
1937{
1938 int err;
1939 u32 val;
1940
1941 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
1942 return 0;
1943
1944 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1945 /* Cannot do read-modify-write on 5401 */
1946 err = tg3_phy_auxctl_write(tp,
1947 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1948 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
1949 0x4c20);
1950 goto done;
1951 }
1952
1953 err = tg3_phy_auxctl_read(tp,
1954 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1955 if (err)
1956 return err;
1957
1958 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
1959 err = tg3_phy_auxctl_write(tp,
1960 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
1961
1962done:
1963 return err;
1964}
1965
Matt Carlson7f97a4b2009-08-25 10:10:03 +00001966static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1967{
1968 u32 phytest;
1969
1970 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1971 u32 phy;
1972
1973 tg3_writephy(tp, MII_TG3_FET_TEST,
1974 phytest | MII_TG3_FET_SHADOW_EN);
1975 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1976 if (enable)
1977 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1978 else
1979 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1980 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1981 }
1982 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1983 }
1984}
1985
Matt Carlson6833c042008-11-21 17:18:59 -08001986static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1987{
1988 u32 reg;
1989
Joe Perches63c3a662011-04-26 08:12:10 +00001990 if (!tg3_flag(tp, 5705_PLUS) ||
1991 (tg3_flag(tp, 5717_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001992 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
Matt Carlson6833c042008-11-21 17:18:59 -08001993 return;
1994
Matt Carlsonf07e9af2010-08-02 11:26:07 +00001995 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson7f97a4b2009-08-25 10:10:03 +00001996 tg3_phy_fet_toggle_apd(tp, enable);
1997 return;
1998 }
1999
Matt Carlson6833c042008-11-21 17:18:59 -08002000 reg = MII_TG3_MISC_SHDW_WREN |
2001 MII_TG3_MISC_SHDW_SCR5_SEL |
2002 MII_TG3_MISC_SHDW_SCR5_LPED |
2003 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2004 MII_TG3_MISC_SHDW_SCR5_SDTL |
2005 MII_TG3_MISC_SHDW_SCR5_C125OE;
2006 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
2007 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2008
2009 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2010
2011
2012 reg = MII_TG3_MISC_SHDW_WREN |
2013 MII_TG3_MISC_SHDW_APD_SEL |
2014 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2015 if (enable)
2016 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2017
2018 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2019}
2020
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002021static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2022{
2023 u32 phy;
2024
Joe Perches63c3a662011-04-26 08:12:10 +00002025 if (!tg3_flag(tp, 5705_PLUS) ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002026 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002027 return;
2028
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002029 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002030 u32 ephy;
2031
Matt Carlson535ef6e2009-08-25 10:09:36 +00002032 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2033 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2034
2035 tg3_writephy(tp, MII_TG3_FET_TEST,
2036 ephy | MII_TG3_FET_SHADOW_EN);
2037 if (!tg3_readphy(tp, reg, &phy)) {
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002038 if (enable)
Matt Carlson535ef6e2009-08-25 10:09:36 +00002039 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002040 else
Matt Carlson535ef6e2009-08-25 10:09:36 +00002041 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2042 tg3_writephy(tp, reg, phy);
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002043 }
Matt Carlson535ef6e2009-08-25 10:09:36 +00002044 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002045 }
2046 } else {
Matt Carlson15ee95c2011-04-20 07:57:40 +00002047 int ret;
2048
2049 ret = tg3_phy_auxctl_read(tp,
2050 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2051 if (!ret) {
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002052 if (enable)
2053 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2054 else
2055 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002056 tg3_phy_auxctl_write(tp,
2057 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002058 }
2059 }
2060}
2061
Linus Torvalds1da177e2005-04-16 15:20:36 -07002062static void tg3_phy_set_wirespeed(struct tg3 *tp)
2063{
Matt Carlson15ee95c2011-04-20 07:57:40 +00002064 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002065 u32 val;
2066
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002067 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002068 return;
2069
Matt Carlson15ee95c2011-04-20 07:57:40 +00002070 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2071 if (!ret)
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002072 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2073 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002074}
2075
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002076static void tg3_phy_apply_otp(struct tg3 *tp)
2077{
2078 u32 otp, phy;
2079
2080 if (!tp->phy_otp)
2081 return;
2082
2083 otp = tp->phy_otp;
2084
Matt Carlson1d36ba42011-04-20 07:57:42 +00002085 if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
2086 return;
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002087
2088 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2089 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2090 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2091
2092 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2093 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2094 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2095
2096 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2097 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2098 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2099
2100 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2101 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2102
2103 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2104 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2105
2106 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2107 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2108 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2109
Matt Carlson1d36ba42011-04-20 07:57:42 +00002110 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002111}
2112
Matt Carlson52b02d02010-10-14 10:37:41 +00002113static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2114{
2115 u32 val;
2116
2117 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2118 return;
2119
2120 tp->setlpicnt = 0;
2121
2122 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2123 current_link_up == 1 &&
Matt Carlsona6b68da2010-12-06 08:28:52 +00002124 tp->link_config.active_duplex == DUPLEX_FULL &&
2125 (tp->link_config.active_speed == SPEED_100 ||
2126 tp->link_config.active_speed == SPEED_1000)) {
Matt Carlson52b02d02010-10-14 10:37:41 +00002127 u32 eeectl;
2128
2129 if (tp->link_config.active_speed == SPEED_1000)
2130 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2131 else
2132 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2133
2134 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2135
Matt Carlson3110f5f52010-12-06 08:28:50 +00002136 tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2137 TG3_CL45_D7_EEERES_STAT, &val);
Matt Carlson52b02d02010-10-14 10:37:41 +00002138
Matt Carlsonb0c59432011-05-19 12:12:48 +00002139 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2140 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
Matt Carlson52b02d02010-10-14 10:37:41 +00002141 tp->setlpicnt = 2;
2142 }
2143
2144 if (!tp->setlpicnt) {
Matt Carlsonb715ce92011-07-20 10:20:52 +00002145 if (current_link_up == 1 &&
2146 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2147 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2148 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2149 }
2150
Matt Carlson52b02d02010-10-14 10:37:41 +00002151 val = tr32(TG3_CPMU_EEE_MODE);
2152 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2153 }
2154}
2155
Matt Carlsonb0c59432011-05-19 12:12:48 +00002156static void tg3_phy_eee_enable(struct tg3 *tp)
2157{
2158 u32 val;
2159
2160 if (tp->link_config.active_speed == SPEED_1000 &&
2161 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2162 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2163 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2164 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
Matt Carlsonb715ce92011-07-20 10:20:52 +00002165 val = MII_TG3_DSP_TAP26_ALNOKO |
2166 MII_TG3_DSP_TAP26_RMRXSTO;
2167 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
Matt Carlsonb0c59432011-05-19 12:12:48 +00002168 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2169 }
2170
2171 val = tr32(TG3_CPMU_EEE_MODE);
2172 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2173}
2174
Linus Torvalds1da177e2005-04-16 15:20:36 -07002175static int tg3_wait_macro_done(struct tg3 *tp)
2176{
2177 int limit = 100;
2178
2179 while (limit--) {
2180 u32 tmp32;
2181
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002182 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002183 if ((tmp32 & 0x1000) == 0)
2184 break;
2185 }
2186 }
Roel Kluind4675b52009-02-12 16:33:27 -08002187 if (limit < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002188 return -EBUSY;
2189
2190 return 0;
2191}
2192
2193static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2194{
2195 static const u32 test_pat[4][6] = {
2196 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2197 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2198 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2199 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2200 };
2201 int chan;
2202
2203 for (chan = 0; chan < 4; chan++) {
2204 int i;
2205
2206 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2207 (chan * 0x2000) | 0x0200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002208 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002209
2210 for (i = 0; i < 6; i++)
2211 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2212 test_pat[chan][i]);
2213
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002214 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002215 if (tg3_wait_macro_done(tp)) {
2216 *resetp = 1;
2217 return -EBUSY;
2218 }
2219
2220 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2221 (chan * 0x2000) | 0x0200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002222 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002223 if (tg3_wait_macro_done(tp)) {
2224 *resetp = 1;
2225 return -EBUSY;
2226 }
2227
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002228 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002229 if (tg3_wait_macro_done(tp)) {
2230 *resetp = 1;
2231 return -EBUSY;
2232 }
2233
2234 for (i = 0; i < 6; i += 2) {
2235 u32 low, high;
2236
2237 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2238 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2239 tg3_wait_macro_done(tp)) {
2240 *resetp = 1;
2241 return -EBUSY;
2242 }
2243 low &= 0x7fff;
2244 high &= 0x000f;
2245 if (low != test_pat[chan][i] ||
2246 high != test_pat[chan][i+1]) {
2247 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2248 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2249 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2250
2251 return -EBUSY;
2252 }
2253 }
2254 }
2255
2256 return 0;
2257}
2258
2259static int tg3_phy_reset_chanpat(struct tg3 *tp)
2260{
2261 int chan;
2262
2263 for (chan = 0; chan < 4; chan++) {
2264 int i;
2265
2266 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2267 (chan * 0x2000) | 0x0200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002268 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002269 for (i = 0; i < 6; i++)
2270 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002271 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002272 if (tg3_wait_macro_done(tp))
2273 return -EBUSY;
2274 }
2275
2276 return 0;
2277}
2278
2279static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2280{
2281 u32 reg32, phy9_orig;
2282 int retries, do_phy_reset, err;
2283
2284 retries = 10;
2285 do_phy_reset = 1;
2286 do {
2287 if (do_phy_reset) {
2288 err = tg3_bmcr_reset(tp);
2289 if (err)
2290 return err;
2291 do_phy_reset = 0;
2292 }
2293
2294 /* Disable transmitter and interrupt. */
2295 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2296 continue;
2297
2298 reg32 |= 0x3000;
2299 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2300
2301 /* Set full-duplex, 1000 mbps. */
2302 tg3_writephy(tp, MII_BMCR,
Matt Carlson221c5632011-06-13 13:39:01 +00002303 BMCR_FULLDPLX | BMCR_SPEED1000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002304
2305 /* Set to master mode. */
Matt Carlson221c5632011-06-13 13:39:01 +00002306 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002307 continue;
2308
Matt Carlson221c5632011-06-13 13:39:01 +00002309 tg3_writephy(tp, MII_CTRL1000,
2310 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002311
Matt Carlson1d36ba42011-04-20 07:57:42 +00002312 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2313 if (err)
2314 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002315
2316 /* Block the PHY control access. */
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00002317 tg3_phydsp_write(tp, 0x8005, 0x0800);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002318
2319 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2320 if (!err)
2321 break;
2322 } while (--retries);
2323
2324 err = tg3_phy_reset_chanpat(tp);
2325 if (err)
2326 return err;
2327
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00002328 tg3_phydsp_write(tp, 0x8005, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002329
2330 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002331 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002332
Matt Carlson1d36ba42011-04-20 07:57:42 +00002333 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002334
Matt Carlson221c5632011-06-13 13:39:01 +00002335 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002336
2337 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2338 reg32 &= ~0x3000;
2339 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2340 } else if (!err)
2341 err = -EBUSY;
2342
2343 return err;
2344}
2345
2346/* This will reset the tigon3 PHY if there is no valid
2347 * link unless the FORCE argument is non-zero.
2348 */
2349static int tg3_phy_reset(struct tg3 *tp)
2350{
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002351 u32 val, cpmuctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002352 int err;
2353
Michael Chan60189dd2006-12-17 17:08:07 -08002354 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan60189dd2006-12-17 17:08:07 -08002355 val = tr32(GRC_MISC_CFG);
2356 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2357 udelay(40);
2358 }
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002359 err = tg3_readphy(tp, MII_BMSR, &val);
2360 err |= tg3_readphy(tp, MII_BMSR, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002361 if (err != 0)
2362 return -EBUSY;
2363
Michael Chanc8e1e822006-04-29 18:55:17 -07002364 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2365 netif_carrier_off(tp->dev);
2366 tg3_link_report(tp);
2367 }
2368
Linus Torvalds1da177e2005-04-16 15:20:36 -07002369 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2370 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2371 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2372 err = tg3_phy_reset_5703_4_5(tp);
2373 if (err)
2374 return err;
2375 goto out;
2376 }
2377
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002378 cpmuctrl = 0;
2379 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2380 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2381 cpmuctrl = tr32(TG3_CPMU_CTRL);
2382 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2383 tw32(TG3_CPMU_CTRL,
2384 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2385 }
2386
Linus Torvalds1da177e2005-04-16 15:20:36 -07002387 err = tg3_bmcr_reset(tp);
2388 if (err)
2389 return err;
2390
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002391 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002392 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2393 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002394
2395 tw32(TG3_CPMU_CTRL, cpmuctrl);
2396 }
2397
Matt Carlsonbcb37f62008-11-03 16:52:09 -08002398 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2399 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
Matt Carlsonce057f02007-11-12 21:08:03 -08002400 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2401 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2402 CPMU_LSPD_1000MB_MACCLK_12_5) {
2403 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2404 udelay(40);
2405 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2406 }
2407 }
2408
Joe Perches63c3a662011-04-26 08:12:10 +00002409 if (tg3_flag(tp, 5717_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002410 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
Matt Carlsonecf14102010-01-20 16:58:05 +00002411 return 0;
2412
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002413 tg3_phy_apply_otp(tp);
2414
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002415 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
Matt Carlson6833c042008-11-21 17:18:59 -08002416 tg3_phy_toggle_apd(tp, true);
2417 else
2418 tg3_phy_toggle_apd(tp, false);
2419
Linus Torvalds1da177e2005-04-16 15:20:36 -07002420out:
Matt Carlson1d36ba42011-04-20 07:57:42 +00002421 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2422 !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00002423 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2424 tg3_phydsp_write(tp, 0x000a, 0x0323);
Matt Carlson1d36ba42011-04-20 07:57:42 +00002425 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002426 }
Matt Carlson1d36ba42011-04-20 07:57:42 +00002427
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002428 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00002429 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2430 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002431 }
Matt Carlson1d36ba42011-04-20 07:57:42 +00002432
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002433 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
Matt Carlson1d36ba42011-04-20 07:57:42 +00002434 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2435 tg3_phydsp_write(tp, 0x000a, 0x310b);
2436 tg3_phydsp_write(tp, 0x201f, 0x9506);
2437 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2438 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2439 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002440 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
Matt Carlson1d36ba42011-04-20 07:57:42 +00002441 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2442 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2443 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2444 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2445 tg3_writephy(tp, MII_TG3_TEST1,
2446 MII_TG3_TEST1_TRIM_EN | 0x4);
2447 } else
2448 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2449
2450 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
2451 }
Michael Chanc424cb22006-04-29 18:56:34 -07002452 }
Matt Carlson1d36ba42011-04-20 07:57:42 +00002453
Linus Torvalds1da177e2005-04-16 15:20:36 -07002454 /* Set Extended packet length bit (bit 14) on all chips that */
2455 /* support jumbo frames */
Matt Carlson79eb6902010-02-17 15:17:03 +00002456 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002457 /* Cannot do read-modify-write on 5401 */
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002458 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
Joe Perches63c3a662011-04-26 08:12:10 +00002459 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002460 /* Set bit 14 with read-modify-write to preserve other bits */
Matt Carlson15ee95c2011-04-20 07:57:40 +00002461 err = tg3_phy_auxctl_read(tp,
2462 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2463 if (!err)
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002464 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2465 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002466 }
2467
2468 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2469 * jumbo frames transmission.
2470 */
Joe Perches63c3a662011-04-26 08:12:10 +00002471 if (tg3_flag(tp, JUMBO_CAPABLE)) {
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002472 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
Matt Carlsonc6cdf432010-04-05 10:19:26 +00002473 tg3_writephy(tp, MII_TG3_EXT_CTRL,
Matt Carlsonf833c4c2010-09-15 09:00:01 +00002474 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002475 }
2476
Michael Chan715116a2006-09-27 16:09:25 -07002477 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan715116a2006-09-27 16:09:25 -07002478 /* adjust output voltage */
Matt Carlson535ef6e2009-08-25 10:09:36 +00002479 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
Michael Chan715116a2006-09-27 16:09:25 -07002480 }
2481
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002482 tg3_phy_toggle_automdix(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002483 tg3_phy_set_wirespeed(tp);
2484 return 0;
2485}
2486
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002487#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2488#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2489#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2490 TG3_GPIO_MSG_NEED_VAUX)
2491#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2492 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2493 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2494 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2495 (TG3_GPIO_MSG_DRVR_PRES << 12))
2496
2497#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2498 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2499 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2500 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2501 (TG3_GPIO_MSG_NEED_VAUX << 12))
2502
2503static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2504{
2505 u32 status, shift;
2506
2507 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2508 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2509 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2510 else
2511 status = tr32(TG3_CPMU_DRV_STATUS);
2512
2513 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2514 status &= ~(TG3_GPIO_MSG_MASK << shift);
2515 status |= (newstat << shift);
2516
2517 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2518 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
2519 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2520 else
2521 tw32(TG3_CPMU_DRV_STATUS, status);
2522
2523 return status >> TG3_APE_GPIO_MSG_SHIFT;
2524}
2525
Matt Carlson520b2752011-06-13 13:39:02 +00002526static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2527{
2528 if (!tg3_flag(tp, IS_NIC))
2529 return 0;
2530
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002531 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2532 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2533 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
2534 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2535 return -EIO;
Matt Carlson520b2752011-06-13 13:39:02 +00002536
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002537 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2538
2539 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2540 TG3_GRC_LCLCTL_PWRSW_DELAY);
2541
2542 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2543 } else {
2544 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2545 TG3_GRC_LCLCTL_PWRSW_DELAY);
2546 }
Matt Carlson6f5c8f832011-07-13 09:27:31 +00002547
Matt Carlson520b2752011-06-13 13:39:02 +00002548 return 0;
2549}
2550
2551static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2552{
2553 u32 grc_local_ctrl;
2554
2555 if (!tg3_flag(tp, IS_NIC) ||
2556 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2557 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)
2558 return;
2559
2560 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2561
2562 tw32_wait_f(GRC_LOCAL_CTRL,
2563 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2564 TG3_GRC_LCLCTL_PWRSW_DELAY);
2565
2566 tw32_wait_f(GRC_LOCAL_CTRL,
2567 grc_local_ctrl,
2568 TG3_GRC_LCLCTL_PWRSW_DELAY);
2569
2570 tw32_wait_f(GRC_LOCAL_CTRL,
2571 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2572 TG3_GRC_LCLCTL_PWRSW_DELAY);
2573}
2574
2575static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2576{
2577 if (!tg3_flag(tp, IS_NIC))
2578 return;
2579
2580 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2581 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2582 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2583 (GRC_LCLCTRL_GPIO_OE0 |
2584 GRC_LCLCTRL_GPIO_OE1 |
2585 GRC_LCLCTRL_GPIO_OE2 |
2586 GRC_LCLCTRL_GPIO_OUTPUT0 |
2587 GRC_LCLCTRL_GPIO_OUTPUT1),
2588 TG3_GRC_LCLCTL_PWRSW_DELAY);
2589 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2590 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2591 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2592 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2593 GRC_LCLCTRL_GPIO_OE1 |
2594 GRC_LCLCTRL_GPIO_OE2 |
2595 GRC_LCLCTRL_GPIO_OUTPUT0 |
2596 GRC_LCLCTRL_GPIO_OUTPUT1 |
2597 tp->grc_local_ctrl;
2598 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2599 TG3_GRC_LCLCTL_PWRSW_DELAY);
2600
2601 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2602 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2603 TG3_GRC_LCLCTL_PWRSW_DELAY);
2604
2605 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2606 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2607 TG3_GRC_LCLCTL_PWRSW_DELAY);
2608 } else {
2609 u32 no_gpio2;
2610 u32 grc_local_ctrl = 0;
2611
2612 /* Workaround to prevent overdrawing Amps. */
2613 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2614 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2615 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2616 grc_local_ctrl,
2617 TG3_GRC_LCLCTL_PWRSW_DELAY);
2618 }
2619
2620 /* On 5753 and variants, GPIO2 cannot be used. */
2621 no_gpio2 = tp->nic_sram_data_cfg &
2622 NIC_SRAM_DATA_CFG_NO_GPIO2;
2623
2624 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2625 GRC_LCLCTRL_GPIO_OE1 |
2626 GRC_LCLCTRL_GPIO_OE2 |
2627 GRC_LCLCTRL_GPIO_OUTPUT1 |
2628 GRC_LCLCTRL_GPIO_OUTPUT2;
2629 if (no_gpio2) {
2630 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2631 GRC_LCLCTRL_GPIO_OUTPUT2);
2632 }
2633 tw32_wait_f(GRC_LOCAL_CTRL,
2634 tp->grc_local_ctrl | grc_local_ctrl,
2635 TG3_GRC_LCLCTL_PWRSW_DELAY);
2636
2637 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2638
2639 tw32_wait_f(GRC_LOCAL_CTRL,
2640 tp->grc_local_ctrl | grc_local_ctrl,
2641 TG3_GRC_LCLCTL_PWRSW_DELAY);
2642
2643 if (!no_gpio2) {
2644 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2645 tw32_wait_f(GRC_LOCAL_CTRL,
2646 tp->grc_local_ctrl | grc_local_ctrl,
2647 TG3_GRC_LCLCTL_PWRSW_DELAY);
2648 }
2649 }
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002650}
Matt Carlson6f5c8f832011-07-13 09:27:31 +00002651
Matt Carlsoncd0d7222011-07-13 09:27:33 +00002652static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002653{
2654 u32 msg = 0;
2655
2656 /* Serialize power state transitions */
2657 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2658 return;
2659
Matt Carlsoncd0d7222011-07-13 09:27:33 +00002660 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002661 msg = TG3_GPIO_MSG_NEED_VAUX;
2662
2663 msg = tg3_set_function_status(tp, msg);
2664
2665 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2666 goto done;
2667
2668 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2669 tg3_pwrsrc_switch_to_vaux(tp);
2670 else
2671 tg3_pwrsrc_die_with_vmain(tp);
2672
2673done:
Matt Carlson6f5c8f832011-07-13 09:27:31 +00002674 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
Matt Carlson520b2752011-06-13 13:39:02 +00002675}
2676
Matt Carlsoncd0d7222011-07-13 09:27:33 +00002677static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002678{
Matt Carlson683644b2011-03-09 16:58:23 +00002679 bool need_vaux = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002680
Matt Carlson334355a2010-01-20 16:58:10 +00002681 /* The GPIOs do something completely different on 57765. */
Joe Perches63c3a662011-04-26 08:12:10 +00002682 if (!tg3_flag(tp, IS_NIC) ||
Matt Carlson334355a2010-01-20 16:58:10 +00002683 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002684 return;
2685
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002686 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2687 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2688 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
Matt Carlsoncd0d7222011-07-13 09:27:33 +00002689 tg3_frob_aux_power_5717(tp, include_wol ?
2690 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
Matt Carlson3a1e19d2011-07-13 09:27:32 +00002691 return;
2692 }
2693
2694 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002695 struct net_device *dev_peer;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002696
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002697 dev_peer = pci_get_drvdata(tp->pdev_peer);
Matt Carlson683644b2011-03-09 16:58:23 +00002698
Michael Chanbc1c7562006-03-20 17:48:03 -08002699 /* remove_one() may have been run on the peer. */
Matt Carlson683644b2011-03-09 16:58:23 +00002700 if (dev_peer) {
2701 struct tg3 *tp_peer = netdev_priv(dev_peer);
2702
Joe Perches63c3a662011-04-26 08:12:10 +00002703 if (tg3_flag(tp_peer, INIT_COMPLETE))
Matt Carlson683644b2011-03-09 16:58:23 +00002704 return;
2705
Matt Carlsoncd0d7222011-07-13 09:27:33 +00002706 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
Joe Perches63c3a662011-04-26 08:12:10 +00002707 tg3_flag(tp_peer, ENABLE_ASF))
Matt Carlson683644b2011-03-09 16:58:23 +00002708 need_vaux = true;
2709 }
Michael Chan8c2dc7e2005-12-19 16:26:02 -08002710 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002711
Matt Carlsoncd0d7222011-07-13 09:27:33 +00002712 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2713 tg3_flag(tp, ENABLE_ASF))
Matt Carlson683644b2011-03-09 16:58:23 +00002714 need_vaux = true;
2715
Matt Carlson520b2752011-06-13 13:39:02 +00002716 if (need_vaux)
2717 tg3_pwrsrc_switch_to_vaux(tp);
2718 else
2719 tg3_pwrsrc_die_with_vmain(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002720}
2721
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07002722static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2723{
2724 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2725 return 1;
Matt Carlson79eb6902010-02-17 15:17:03 +00002726 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07002727 if (speed != SPEED_10)
2728 return 1;
2729 } else if (speed == SPEED_10)
2730 return 1;
2731
2732 return 0;
2733}
2734
Linus Torvalds1da177e2005-04-16 15:20:36 -07002735static int tg3_setup_phy(struct tg3 *, int);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002736static int tg3_halt_cpu(struct tg3 *, u32);
2737
Matt Carlson0a459aa2008-11-03 16:54:15 -08002738static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
Michael Chan15c3b692006-03-22 01:06:52 -08002739{
Matt Carlsonce057f02007-11-12 21:08:03 -08002740 u32 val;
2741
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002742 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Michael Chan51297242007-02-13 12:17:57 -08002743 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2744 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2745 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2746
2747 sg_dig_ctrl |=
2748 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2749 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2750 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2751 }
Michael Chan3f7045c2006-09-27 16:02:29 -07002752 return;
Michael Chan51297242007-02-13 12:17:57 -08002753 }
Michael Chan3f7045c2006-09-27 16:02:29 -07002754
Michael Chan60189dd2006-12-17 17:08:07 -08002755 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan60189dd2006-12-17 17:08:07 -08002756 tg3_bmcr_reset(tp);
2757 val = tr32(GRC_MISC_CFG);
2758 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2759 udelay(40);
2760 return;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002761 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Matt Carlson0e5f7842009-11-02 14:26:38 +00002762 u32 phytest;
2763 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2764 u32 phy;
2765
2766 tg3_writephy(tp, MII_ADVERTISE, 0);
2767 tg3_writephy(tp, MII_BMCR,
2768 BMCR_ANENABLE | BMCR_ANRESTART);
2769
2770 tg3_writephy(tp, MII_TG3_FET_TEST,
2771 phytest | MII_TG3_FET_SHADOW_EN);
2772 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2773 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2774 tg3_writephy(tp,
2775 MII_TG3_FET_SHDW_AUXMODE4,
2776 phy);
2777 }
2778 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2779 }
2780 return;
Matt Carlson0a459aa2008-11-03 16:54:15 -08002781 } else if (do_low_power) {
Michael Chan715116a2006-09-27 16:09:25 -07002782 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2783 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
Matt Carlson0a459aa2008-11-03 16:54:15 -08002784
Matt Carlsonb4bd2922011-04-20 07:57:41 +00002785 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2786 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2787 MII_TG3_AUXCTL_PCTL_VREG_11V;
2788 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
Michael Chan715116a2006-09-27 16:09:25 -07002789 }
Michael Chan3f7045c2006-09-27 16:02:29 -07002790
Michael Chan15c3b692006-03-22 01:06:52 -08002791 /* The PHY should not be powered down on some chips because
2792 * of bugs.
2793 */
2794 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2795 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2796 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00002797 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
Michael Chan15c3b692006-03-22 01:06:52 -08002798 return;
Matt Carlsonce057f02007-11-12 21:08:03 -08002799
Matt Carlsonbcb37f62008-11-03 16:52:09 -08002800 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2801 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
Matt Carlsonce057f02007-11-12 21:08:03 -08002802 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2803 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2804 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2805 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2806 }
2807
Michael Chan15c3b692006-03-22 01:06:52 -08002808 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2809}
2810
Matt Carlson3f007892008-11-03 16:51:36 -08002811/* tp->lock is held. */
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002812static int tg3_nvram_lock(struct tg3 *tp)
2813{
Joe Perches63c3a662011-04-26 08:12:10 +00002814 if (tg3_flag(tp, NVRAM)) {
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002815 int i;
2816
2817 if (tp->nvram_lock_cnt == 0) {
2818 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2819 for (i = 0; i < 8000; i++) {
2820 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2821 break;
2822 udelay(20);
2823 }
2824 if (i == 8000) {
2825 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2826 return -ENODEV;
2827 }
2828 }
2829 tp->nvram_lock_cnt++;
2830 }
2831 return 0;
2832}
2833
2834/* tp->lock is held. */
2835static void tg3_nvram_unlock(struct tg3 *tp)
2836{
Joe Perches63c3a662011-04-26 08:12:10 +00002837 if (tg3_flag(tp, NVRAM)) {
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002838 if (tp->nvram_lock_cnt > 0)
2839 tp->nvram_lock_cnt--;
2840 if (tp->nvram_lock_cnt == 0)
2841 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2842 }
2843}
2844
2845/* tp->lock is held. */
2846static void tg3_enable_nvram_access(struct tg3 *tp)
2847{
Joe Perches63c3a662011-04-26 08:12:10 +00002848 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002849 u32 nvaccess = tr32(NVRAM_ACCESS);
2850
2851 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2852 }
2853}
2854
2855/* tp->lock is held. */
2856static void tg3_disable_nvram_access(struct tg3 *tp)
2857{
Joe Perches63c3a662011-04-26 08:12:10 +00002858 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002859 u32 nvaccess = tr32(NVRAM_ACCESS);
2860
2861 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2862 }
2863}
2864
2865static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2866 u32 offset, u32 *val)
2867{
2868 u32 tmp;
2869 int i;
2870
2871 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2872 return -EINVAL;
2873
2874 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2875 EEPROM_ADDR_DEVID_MASK |
2876 EEPROM_ADDR_READ);
2877 tw32(GRC_EEPROM_ADDR,
2878 tmp |
2879 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2880 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2881 EEPROM_ADDR_ADDR_MASK) |
2882 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2883
2884 for (i = 0; i < 1000; i++) {
2885 tmp = tr32(GRC_EEPROM_ADDR);
2886
2887 if (tmp & EEPROM_ADDR_COMPLETE)
2888 break;
2889 msleep(1);
2890 }
2891 if (!(tmp & EEPROM_ADDR_COMPLETE))
2892 return -EBUSY;
2893
Matt Carlson62cedd12009-04-20 14:52:29 -07002894 tmp = tr32(GRC_EEPROM_DATA);
2895
2896 /*
2897 * The data will always be opposite the native endian
2898 * format. Perform a blind byteswap to compensate.
2899 */
2900 *val = swab32(tmp);
2901
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002902 return 0;
2903}
2904
2905#define NVRAM_CMD_TIMEOUT 10000
2906
2907static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2908{
2909 int i;
2910
2911 tw32(NVRAM_CMD, nvram_cmd);
2912 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2913 udelay(10);
2914 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2915 udelay(10);
2916 break;
2917 }
2918 }
2919
2920 if (i == NVRAM_CMD_TIMEOUT)
2921 return -EBUSY;
2922
2923 return 0;
2924}
2925
2926static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2927{
Joe Perches63c3a662011-04-26 08:12:10 +00002928 if (tg3_flag(tp, NVRAM) &&
2929 tg3_flag(tp, NVRAM_BUFFERED) &&
2930 tg3_flag(tp, FLASH) &&
2931 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002932 (tp->nvram_jedecnum == JEDEC_ATMEL))
2933
2934 addr = ((addr / tp->nvram_pagesize) <<
2935 ATMEL_AT45DB0X1B_PAGE_POS) +
2936 (addr % tp->nvram_pagesize);
2937
2938 return addr;
2939}
2940
2941static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2942{
Joe Perches63c3a662011-04-26 08:12:10 +00002943 if (tg3_flag(tp, NVRAM) &&
2944 tg3_flag(tp, NVRAM_BUFFERED) &&
2945 tg3_flag(tp, FLASH) &&
2946 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002947 (tp->nvram_jedecnum == JEDEC_ATMEL))
2948
2949 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2950 tp->nvram_pagesize) +
2951 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2952
2953 return addr;
2954}
2955
Matt Carlsone4f34112009-02-25 14:25:00 +00002956/* NOTE: Data read in from NVRAM is byteswapped according to
2957 * the byteswapping settings for all other register accesses.
2958 * tg3 devices are BE devices, so on a BE machine, the data
2959 * returned will be exactly as it is seen in NVRAM. On a LE
2960 * machine, the 32-bit value will be byteswapped.
2961 */
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002962static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2963{
2964 int ret;
2965
Joe Perches63c3a662011-04-26 08:12:10 +00002966 if (!tg3_flag(tp, NVRAM))
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002967 return tg3_nvram_read_using_eeprom(tp, offset, val);
2968
2969 offset = tg3_nvram_phys_addr(tp, offset);
2970
2971 if (offset > NVRAM_ADDR_MSK)
2972 return -EINVAL;
2973
2974 ret = tg3_nvram_lock(tp);
2975 if (ret)
2976 return ret;
2977
2978 tg3_enable_nvram_access(tp);
2979
2980 tw32(NVRAM_ADDR, offset);
2981 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2982 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2983
2984 if (ret == 0)
Matt Carlsone4f34112009-02-25 14:25:00 +00002985 *val = tr32(NVRAM_RDDATA);
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002986
2987 tg3_disable_nvram_access(tp);
2988
2989 tg3_nvram_unlock(tp);
2990
2991 return ret;
2992}
2993
Matt Carlsona9dc5292009-02-25 14:25:30 +00002994/* Ensures NVRAM data is in bytestream format. */
2995static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002996{
2997 u32 v;
Matt Carlsona9dc5292009-02-25 14:25:30 +00002998 int res = tg3_nvram_read(tp, offset, &v);
Matt Carlsonffbcfed2009-02-25 14:24:28 +00002999 if (!res)
Matt Carlsona9dc5292009-02-25 14:25:30 +00003000 *val = cpu_to_be32(v);
Matt Carlsonffbcfed2009-02-25 14:24:28 +00003001 return res;
3002}
3003
Matt Carlson997b4f12011-08-31 11:44:53 +00003004#define RX_CPU_SCRATCH_BASE 0x30000
3005#define RX_CPU_SCRATCH_SIZE 0x04000
3006#define TX_CPU_SCRATCH_BASE 0x34000
3007#define TX_CPU_SCRATCH_SIZE 0x04000
3008
3009/* tp->lock is held. */
3010static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3011{
3012 int i;
3013
3014 BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3015
3016 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3017 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3018
3019 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3020 return 0;
3021 }
3022 if (offset == RX_CPU_BASE) {
3023 for (i = 0; i < 10000; i++) {
3024 tw32(offset + CPU_STATE, 0xffffffff);
3025 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3026 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3027 break;
3028 }
3029
3030 tw32(offset + CPU_STATE, 0xffffffff);
3031 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3032 udelay(10);
3033 } else {
3034 for (i = 0; i < 10000; i++) {
3035 tw32(offset + CPU_STATE, 0xffffffff);
3036 tw32(offset + CPU_MODE, CPU_MODE_HALT);
3037 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3038 break;
3039 }
3040 }
3041
3042 if (i >= 10000) {
3043 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3044 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3045 return -ENODEV;
3046 }
3047
3048 /* Clear firmware's nvram arbitration. */
3049 if (tg3_flag(tp, NVRAM))
3050 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3051 return 0;
3052}
3053
3054struct fw_info {
3055 unsigned int fw_base;
3056 unsigned int fw_len;
3057 const __be32 *fw_data;
3058};
3059
3060/* tp->lock is held. */
3061static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3062 u32 cpu_scratch_base, int cpu_scratch_size,
3063 struct fw_info *info)
3064{
3065 int err, lock_err, i;
3066 void (*write_op)(struct tg3 *, u32, u32);
3067
3068 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3069 netdev_err(tp->dev,
3070 "%s: Trying to load TX cpu firmware which is 5705\n",
3071 __func__);
3072 return -EINVAL;
3073 }
3074
3075 if (tg3_flag(tp, 5705_PLUS))
3076 write_op = tg3_write_mem;
3077 else
3078 write_op = tg3_write_indirect_reg32;
3079
3080 /* It is possible that bootcode is still loading at this point.
3081 * Get the nvram lock first before halting the cpu.
3082 */
3083 lock_err = tg3_nvram_lock(tp);
3084 err = tg3_halt_cpu(tp, cpu_base);
3085 if (!lock_err)
3086 tg3_nvram_unlock(tp);
3087 if (err)
3088 goto out;
3089
3090 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3091 write_op(tp, cpu_scratch_base + i, 0);
3092 tw32(cpu_base + CPU_STATE, 0xffffffff);
3093 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3094 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3095 write_op(tp, (cpu_scratch_base +
3096 (info->fw_base & 0xffff) +
3097 (i * sizeof(u32))),
3098 be32_to_cpu(info->fw_data[i]));
3099
3100 err = 0;
3101
3102out:
3103 return err;
3104}
3105
3106/* tp->lock is held. */
3107static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3108{
3109 struct fw_info info;
3110 const __be32 *fw_data;
3111 int err, i;
3112
3113 fw_data = (void *)tp->fw->data;
3114
3115 /* Firmware blob starts with version numbers, followed by
3116 start address and length. We are setting complete length.
3117 length = end_address_of_bss - start_address_of_text.
3118 Remainder is the blob to be loaded contiguously
3119 from start address. */
3120
3121 info.fw_base = be32_to_cpu(fw_data[1]);
3122 info.fw_len = tp->fw->size - 12;
3123 info.fw_data = &fw_data[3];
3124
3125 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3126 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3127 &info);
3128 if (err)
3129 return err;
3130
3131 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3132 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3133 &info);
3134 if (err)
3135 return err;
3136
3137 /* Now startup only the RX cpu. */
3138 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3139 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3140
3141 for (i = 0; i < 5; i++) {
3142 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3143 break;
3144 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3145 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3146 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3147 udelay(1000);
3148 }
3149 if (i >= 5) {
3150 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3151 "should be %08x\n", __func__,
3152 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3153 return -ENODEV;
3154 }
3155 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3156 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3157
3158 return 0;
3159}
3160
3161/* tp->lock is held. */
3162static int tg3_load_tso_firmware(struct tg3 *tp)
3163{
3164 struct fw_info info;
3165 const __be32 *fw_data;
3166 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3167 int err, i;
3168
3169 if (tg3_flag(tp, HW_TSO_1) ||
3170 tg3_flag(tp, HW_TSO_2) ||
3171 tg3_flag(tp, HW_TSO_3))
3172 return 0;
3173
3174 fw_data = (void *)tp->fw->data;
3175
3176 /* Firmware blob starts with version numbers, followed by
3177 start address and length. We are setting complete length.
3178 length = end_address_of_bss - start_address_of_text.
3179 Remainder is the blob to be loaded contiguously
3180 from start address. */
3181
3182 info.fw_base = be32_to_cpu(fw_data[1]);
3183 cpu_scratch_size = tp->fw_len;
3184 info.fw_len = tp->fw->size - 12;
3185 info.fw_data = &fw_data[3];
3186
3187 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3188 cpu_base = RX_CPU_BASE;
3189 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3190 } else {
3191 cpu_base = TX_CPU_BASE;
3192 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3193 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3194 }
3195
3196 err = tg3_load_firmware_cpu(tp, cpu_base,
3197 cpu_scratch_base, cpu_scratch_size,
3198 &info);
3199 if (err)
3200 return err;
3201
3202 /* Now startup the cpu. */
3203 tw32(cpu_base + CPU_STATE, 0xffffffff);
3204 tw32_f(cpu_base + CPU_PC, info.fw_base);
3205
3206 for (i = 0; i < 5; i++) {
3207 if (tr32(cpu_base + CPU_PC) == info.fw_base)
3208 break;
3209 tw32(cpu_base + CPU_STATE, 0xffffffff);
3210 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3211 tw32_f(cpu_base + CPU_PC, info.fw_base);
3212 udelay(1000);
3213 }
3214 if (i >= 5) {
3215 netdev_err(tp->dev,
3216 "%s fails to set CPU PC, is %08x should be %08x\n",
3217 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3218 return -ENODEV;
3219 }
3220 tw32(cpu_base + CPU_STATE, 0xffffffff);
3221 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3222 return 0;
3223}
3224
3225
Matt Carlsonffbcfed2009-02-25 14:24:28 +00003226/* tp->lock is held. */
Matt Carlson3f007892008-11-03 16:51:36 -08003227static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3228{
3229 u32 addr_high, addr_low;
3230 int i;
3231
3232 addr_high = ((tp->dev->dev_addr[0] << 8) |
3233 tp->dev->dev_addr[1]);
3234 addr_low = ((tp->dev->dev_addr[2] << 24) |
3235 (tp->dev->dev_addr[3] << 16) |
3236 (tp->dev->dev_addr[4] << 8) |
3237 (tp->dev->dev_addr[5] << 0));
3238 for (i = 0; i < 4; i++) {
3239 if (i == 1 && skip_mac_1)
3240 continue;
3241 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3242 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3243 }
3244
3245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3246 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
3247 for (i = 0; i < 12; i++) {
3248 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3249 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3250 }
3251 }
3252
3253 addr_high = (tp->dev->dev_addr[0] +
3254 tp->dev->dev_addr[1] +
3255 tp->dev->dev_addr[2] +
3256 tp->dev->dev_addr[3] +
3257 tp->dev->dev_addr[4] +
3258 tp->dev->dev_addr[5]) &
3259 TX_BACKOFF_SEED_MASK;
3260 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3261}
3262
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003263static void tg3_enable_register_access(struct tg3 *tp)
3264{
3265 /*
3266 * Make sure register accesses (indirect or otherwise) will function
3267 * correctly.
3268 */
3269 pci_write_config_dword(tp->pdev,
3270 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3271}
3272
3273static int tg3_power_up(struct tg3 *tp)
3274{
Matt Carlsonbed98292011-07-13 09:27:29 +00003275 int err;
3276
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003277 tg3_enable_register_access(tp);
3278
Matt Carlsonbed98292011-07-13 09:27:29 +00003279 err = pci_set_power_state(tp->pdev, PCI_D0);
3280 if (!err) {
3281 /* Switch out of Vaux if it is a NIC */
3282 tg3_pwrsrc_switch_to_vmain(tp);
3283 } else {
3284 netdev_err(tp->dev, "Transition to D0 failed\n");
3285 }
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003286
Matt Carlsonbed98292011-07-13 09:27:29 +00003287 return err;
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003288}
3289
3290static int tg3_power_down_prepare(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003291{
3292 u32 misc_host_ctrl;
Matt Carlson0a459aa2008-11-03 16:54:15 -08003293 bool device_should_wake, do_low_power;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003294
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003295 tg3_enable_register_access(tp);
Matt Carlson5e7dfd02008-11-21 17:18:16 -08003296
3297 /* Restore the CLKREQ setting. */
Joe Perches63c3a662011-04-26 08:12:10 +00003298 if (tg3_flag(tp, CLKREQ_BUG)) {
Matt Carlson5e7dfd02008-11-21 17:18:16 -08003299 u16 lnkctl;
3300
3301 pci_read_config_word(tp->pdev,
Jon Mason708ebb32011-06-27 12:56:50 +00003302 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
Matt Carlson5e7dfd02008-11-21 17:18:16 -08003303 &lnkctl);
3304 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3305 pci_write_config_word(tp->pdev,
Jon Mason708ebb32011-06-27 12:56:50 +00003306 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
Matt Carlson5e7dfd02008-11-21 17:18:16 -08003307 lnkctl);
3308 }
3309
Linus Torvalds1da177e2005-04-16 15:20:36 -07003310 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3311 tw32(TG3PCI_MISC_HOST_CTRL,
3312 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3313
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003314 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
Joe Perches63c3a662011-04-26 08:12:10 +00003315 tg3_flag(tp, WOL_ENABLE);
Matt Carlson05ac4cb2008-11-03 16:53:46 -08003316
Joe Perches63c3a662011-04-26 08:12:10 +00003317 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson0a459aa2008-11-03 16:54:15 -08003318 do_low_power = false;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003319 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
Matt Carlson80096062010-08-02 11:26:06 +00003320 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003321 struct phy_device *phydev;
Matt Carlson0a459aa2008-11-03 16:54:15 -08003322 u32 phyid, advertising;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003323
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00003324 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003325
Matt Carlson80096062010-08-02 11:26:06 +00003326 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003327
3328 tp->link_config.orig_speed = phydev->speed;
3329 tp->link_config.orig_duplex = phydev->duplex;
3330 tp->link_config.orig_autoneg = phydev->autoneg;
3331 tp->link_config.orig_advertising = phydev->advertising;
3332
3333 advertising = ADVERTISED_TP |
3334 ADVERTISED_Pause |
3335 ADVERTISED_Autoneg |
3336 ADVERTISED_10baseT_Half;
3337
Joe Perches63c3a662011-04-26 08:12:10 +00003338 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3339 if (tg3_flag(tp, WOL_SPEED_100MB))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003340 advertising |=
3341 ADVERTISED_100baseT_Half |
3342 ADVERTISED_100baseT_Full |
3343 ADVERTISED_10baseT_Full;
3344 else
3345 advertising |= ADVERTISED_10baseT_Full;
3346 }
3347
3348 phydev->advertising = advertising;
3349
3350 phy_start_aneg(phydev);
Matt Carlson0a459aa2008-11-03 16:54:15 -08003351
3352 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
Matt Carlson6a443a02010-02-17 15:17:04 +00003353 if (phyid != PHY_ID_BCMAC131) {
3354 phyid &= PHY_BCM_OUI_MASK;
3355 if (phyid == PHY_BCM_OUI_1 ||
3356 phyid == PHY_BCM_OUI_2 ||
3357 phyid == PHY_BCM_OUI_3)
Matt Carlson0a459aa2008-11-03 16:54:15 -08003358 do_low_power = true;
3359 }
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07003360 }
Matt Carlsondd477002008-05-25 23:45:58 -07003361 } else {
Matt Carlson20232762008-12-21 20:18:56 -08003362 do_low_power = true;
Matt Carlson0a459aa2008-11-03 16:54:15 -08003363
Matt Carlson80096062010-08-02 11:26:06 +00003364 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3365 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsondd477002008-05-25 23:45:58 -07003366 tp->link_config.orig_speed = tp->link_config.speed;
3367 tp->link_config.orig_duplex = tp->link_config.duplex;
3368 tp->link_config.orig_autoneg = tp->link_config.autoneg;
3369 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003370
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003371 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
Matt Carlsondd477002008-05-25 23:45:58 -07003372 tp->link_config.speed = SPEED_10;
3373 tp->link_config.duplex = DUPLEX_HALF;
3374 tp->link_config.autoneg = AUTONEG_ENABLE;
3375 tg3_setup_phy(tp, 0);
3376 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003377 }
3378
Michael Chanb5d37722006-09-27 16:06:21 -07003379 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
3380 u32 val;
3381
3382 val = tr32(GRC_VCPU_EXT_CTRL);
3383 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
Joe Perches63c3a662011-04-26 08:12:10 +00003384 } else if (!tg3_flag(tp, ENABLE_ASF)) {
Michael Chan6921d202005-12-13 21:15:53 -08003385 int i;
3386 u32 val;
3387
3388 for (i = 0; i < 200; i++) {
3389 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3390 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3391 break;
3392 msleep(1);
3393 }
3394 }
Joe Perches63c3a662011-04-26 08:12:10 +00003395 if (tg3_flag(tp, WOL_CAP))
Gary Zambranoa85feb82007-05-05 11:52:19 -07003396 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3397 WOL_DRV_STATE_SHUTDOWN |
3398 WOL_DRV_WOL |
3399 WOL_SET_MAGIC_PKT);
Michael Chan6921d202005-12-13 21:15:53 -08003400
Matt Carlson05ac4cb2008-11-03 16:53:46 -08003401 if (device_should_wake) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003402 u32 mac_mode;
3403
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003404 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
Matt Carlsonb4bd2922011-04-20 07:57:41 +00003405 if (do_low_power &&
3406 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3407 tg3_phy_auxctl_write(tp,
3408 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
3409 MII_TG3_AUXCTL_PCTL_WOL_EN |
3410 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3411 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
Matt Carlsondd477002008-05-25 23:45:58 -07003412 udelay(40);
3413 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003414
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003415 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
Michael Chan3f7045c2006-09-27 16:02:29 -07003416 mac_mode = MAC_MODE_PORT_MODE_GMII;
3417 else
3418 mac_mode = MAC_MODE_PORT_MODE_MII;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003419
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07003420 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3421 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3422 ASIC_REV_5700) {
Joe Perches63c3a662011-04-26 08:12:10 +00003423 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07003424 SPEED_100 : SPEED_10;
3425 if (tg3_5700_link_polarity(tp, speed))
3426 mac_mode |= MAC_MODE_LINK_POLARITY;
3427 else
3428 mac_mode &= ~MAC_MODE_LINK_POLARITY;
3429 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003430 } else {
3431 mac_mode = MAC_MODE_PORT_MODE_TBI;
3432 }
3433
Joe Perches63c3a662011-04-26 08:12:10 +00003434 if (!tg3_flag(tp, 5750_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003435 tw32(MAC_LED_CTRL, tp->led_ctrl);
3436
Matt Carlson05ac4cb2008-11-03 16:53:46 -08003437 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
Joe Perches63c3a662011-04-26 08:12:10 +00003438 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3439 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
Matt Carlson05ac4cb2008-11-03 16:53:46 -08003440 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003441
Joe Perches63c3a662011-04-26 08:12:10 +00003442 if (tg3_flag(tp, ENABLE_APE))
Matt Carlsond2394e6b2010-11-24 08:31:47 +00003443 mac_mode |= MAC_MODE_APE_TX_EN |
3444 MAC_MODE_APE_RX_EN |
3445 MAC_MODE_TDE_ENABLE;
Matt Carlson3bda1252008-08-15 14:08:22 -07003446
Linus Torvalds1da177e2005-04-16 15:20:36 -07003447 tw32_f(MAC_MODE, mac_mode);
3448 udelay(100);
3449
3450 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
3451 udelay(10);
3452 }
3453
Joe Perches63c3a662011-04-26 08:12:10 +00003454 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07003455 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3456 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
3457 u32 base_val;
3458
3459 base_val = tp->pci_clock_ctrl;
3460 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3461 CLOCK_CTRL_TXCLK_DISABLE);
3462
Michael Chanb401e9e2005-12-19 16:27:04 -08003463 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
3464 CLOCK_CTRL_PWRDOWN_PLL133, 40);
Joe Perches63c3a662011-04-26 08:12:10 +00003465 } else if (tg3_flag(tp, 5780_CLASS) ||
3466 tg3_flag(tp, CPMU_PRESENT) ||
Matt Carlson6ff6f812011-05-19 12:12:54 +00003467 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan4cf78e42005-07-25 12:29:19 -07003468 /* do nothing */
Joe Perches63c3a662011-04-26 08:12:10 +00003469 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003470 u32 newbits1, newbits2;
3471
3472 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3473 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3474 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3475 CLOCK_CTRL_TXCLK_DISABLE |
3476 CLOCK_CTRL_ALTCLK);
3477 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
Joe Perches63c3a662011-04-26 08:12:10 +00003478 } else if (tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003479 newbits1 = CLOCK_CTRL_625_CORE;
3480 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3481 } else {
3482 newbits1 = CLOCK_CTRL_ALTCLK;
3483 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3484 }
3485
Michael Chanb401e9e2005-12-19 16:27:04 -08003486 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
3487 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003488
Michael Chanb401e9e2005-12-19 16:27:04 -08003489 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
3490 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003491
Joe Perches63c3a662011-04-26 08:12:10 +00003492 if (!tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003493 u32 newbits3;
3494
3495 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3496 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3497 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3498 CLOCK_CTRL_TXCLK_DISABLE |
3499 CLOCK_CTRL_44MHZ_CORE);
3500 } else {
3501 newbits3 = CLOCK_CTRL_44MHZ_CORE;
3502 }
3503
Michael Chanb401e9e2005-12-19 16:27:04 -08003504 tw32_wait_f(TG3PCI_CLOCK_CTRL,
3505 tp->pci_clock_ctrl | newbits3, 40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003506 }
3507 }
3508
Joe Perches63c3a662011-04-26 08:12:10 +00003509 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
Matt Carlson0a459aa2008-11-03 16:54:15 -08003510 tg3_power_down_phy(tp, do_low_power);
Michael Chan6921d202005-12-13 21:15:53 -08003511
Matt Carlsoncd0d7222011-07-13 09:27:33 +00003512 tg3_frob_aux_power(tp, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003513
3514 /* Workaround for unstable PLL clock */
3515 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
3516 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
3517 u32 val = tr32(0x7d00);
3518
3519 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3520 tw32(0x7d00, val);
Joe Perches63c3a662011-04-26 08:12:10 +00003521 if (!tg3_flag(tp, ENABLE_ASF)) {
Michael Chanec41c7d2006-01-17 02:40:55 -08003522 int err;
3523
3524 err = tg3_nvram_lock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003525 tg3_halt_cpu(tp, RX_CPU_BASE);
Michael Chanec41c7d2006-01-17 02:40:55 -08003526 if (!err)
3527 tg3_nvram_unlock(tp);
Michael Chan6921d202005-12-13 21:15:53 -08003528 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003529 }
3530
Michael Chanbbadf502006-04-06 21:46:34 -07003531 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3532
Linus Torvalds1da177e2005-04-16 15:20:36 -07003533 return 0;
3534}
3535
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003536static void tg3_power_down(struct tg3 *tp)
3537{
3538 tg3_power_down_prepare(tp);
3539
Joe Perches63c3a662011-04-26 08:12:10 +00003540 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00003541 pci_set_power_state(tp->pdev, PCI_D3hot);
3542}
3543
Linus Torvalds1da177e2005-04-16 15:20:36 -07003544static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3545{
3546 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3547 case MII_TG3_AUX_STAT_10HALF:
3548 *speed = SPEED_10;
3549 *duplex = DUPLEX_HALF;
3550 break;
3551
3552 case MII_TG3_AUX_STAT_10FULL:
3553 *speed = SPEED_10;
3554 *duplex = DUPLEX_FULL;
3555 break;
3556
3557 case MII_TG3_AUX_STAT_100HALF:
3558 *speed = SPEED_100;
3559 *duplex = DUPLEX_HALF;
3560 break;
3561
3562 case MII_TG3_AUX_STAT_100FULL:
3563 *speed = SPEED_100;
3564 *duplex = DUPLEX_FULL;
3565 break;
3566
3567 case MII_TG3_AUX_STAT_1000HALF:
3568 *speed = SPEED_1000;
3569 *duplex = DUPLEX_HALF;
3570 break;
3571
3572 case MII_TG3_AUX_STAT_1000FULL:
3573 *speed = SPEED_1000;
3574 *duplex = DUPLEX_FULL;
3575 break;
3576
3577 default:
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003578 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
Michael Chan715116a2006-09-27 16:09:25 -07003579 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3580 SPEED_10;
3581 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3582 DUPLEX_HALF;
3583 break;
3584 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003585 *speed = SPEED_INVALID;
3586 *duplex = DUPLEX_INVALID;
3587 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07003588 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003589}
3590
Matt Carlson42b64a42011-05-19 12:12:49 +00003591static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003592{
Matt Carlson42b64a42011-05-19 12:12:49 +00003593 int err = 0;
3594 u32 val, new_adv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003595
Matt Carlson42b64a42011-05-19 12:12:49 +00003596 new_adv = ADVERTISE_CSMA;
3597 if (advertise & ADVERTISED_10baseT_Half)
3598 new_adv |= ADVERTISE_10HALF;
3599 if (advertise & ADVERTISED_10baseT_Full)
3600 new_adv |= ADVERTISE_10FULL;
3601 if (advertise & ADVERTISED_100baseT_Half)
3602 new_adv |= ADVERTISE_100HALF;
3603 if (advertise & ADVERTISED_100baseT_Full)
3604 new_adv |= ADVERTISE_100FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003605
Matt Carlson42b64a42011-05-19 12:12:49 +00003606 new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003607
Matt Carlson42b64a42011-05-19 12:12:49 +00003608 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3609 if (err)
3610 goto done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003611
Matt Carlson42b64a42011-05-19 12:12:49 +00003612 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3613 goto done;
Matt Carlsonba4d07a2007-12-20 20:08:00 -08003614
Matt Carlson42b64a42011-05-19 12:12:49 +00003615 new_adv = 0;
3616 if (advertise & ADVERTISED_1000baseT_Half)
Matt Carlson221c5632011-06-13 13:39:01 +00003617 new_adv |= ADVERTISE_1000HALF;
Matt Carlson42b64a42011-05-19 12:12:49 +00003618 if (advertise & ADVERTISED_1000baseT_Full)
Matt Carlson221c5632011-06-13 13:39:01 +00003619 new_adv |= ADVERTISE_1000FULL;
Matt Carlsonba4d07a2007-12-20 20:08:00 -08003620
Matt Carlson42b64a42011-05-19 12:12:49 +00003621 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3622 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
Matt Carlson221c5632011-06-13 13:39:01 +00003623 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003624
Matt Carlson221c5632011-06-13 13:39:01 +00003625 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
Matt Carlson42b64a42011-05-19 12:12:49 +00003626 if (err)
3627 goto done;
Matt Carlsonba4d07a2007-12-20 20:08:00 -08003628
Matt Carlson42b64a42011-05-19 12:12:49 +00003629 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3630 goto done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003631
Matt Carlson42b64a42011-05-19 12:12:49 +00003632 tw32(TG3_CPMU_EEE_MODE,
3633 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
Matt Carlsonba4d07a2007-12-20 20:08:00 -08003634
Matt Carlson42b64a42011-05-19 12:12:49 +00003635 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3636 if (!err) {
3637 u32 err2;
Matt Carlson52b02d02010-10-14 10:37:41 +00003638
Matt Carlsona6b68da2010-12-06 08:28:52 +00003639 val = 0;
Matt Carlson42b64a42011-05-19 12:12:49 +00003640 /* Advertise 100-BaseTX EEE ability */
3641 if (advertise & ADVERTISED_100baseT_Full)
3642 val |= MDIO_AN_EEE_ADV_100TX;
3643 /* Advertise 1000-BaseT EEE ability */
3644 if (advertise & ADVERTISED_1000baseT_Full)
3645 val |= MDIO_AN_EEE_ADV_1000T;
3646 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
Matt Carlsonb715ce92011-07-20 10:20:52 +00003647 if (err)
3648 val = 0;
3649
3650 switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3651 case ASIC_REV_5717:
3652 case ASIC_REV_57765:
3653 case ASIC_REV_5719:
3654 /* If we advertised any eee advertisements above... */
3655 if (val)
3656 val = MII_TG3_DSP_TAP26_ALNOKO |
3657 MII_TG3_DSP_TAP26_RMRXSTO |
3658 MII_TG3_DSP_TAP26_OPCSINPT;
3659 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3660 /* Fall through */
3661 case ASIC_REV_5720:
3662 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3663 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3664 MII_TG3_DSP_CH34TP2_HIBW01);
3665 }
Matt Carlson52b02d02010-10-14 10:37:41 +00003666
Matt Carlson42b64a42011-05-19 12:12:49 +00003667 err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3668 if (!err)
3669 err = err2;
3670 }
3671
3672done:
3673 return err;
3674}
3675
3676static void tg3_phy_copper_begin(struct tg3 *tp)
3677{
3678 u32 new_adv;
3679 int i;
3680
3681 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
3682 new_adv = ADVERTISED_10baseT_Half |
3683 ADVERTISED_10baseT_Full;
3684 if (tg3_flag(tp, WOL_SPEED_100MB))
3685 new_adv |= ADVERTISED_100baseT_Half |
3686 ADVERTISED_100baseT_Full;
3687
3688 tg3_phy_autoneg_cfg(tp, new_adv,
3689 FLOW_CTRL_TX | FLOW_CTRL_RX);
3690 } else if (tp->link_config.speed == SPEED_INVALID) {
3691 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
3692 tp->link_config.advertising &=
3693 ~(ADVERTISED_1000baseT_Half |
3694 ADVERTISED_1000baseT_Full);
3695
3696 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
3697 tp->link_config.flowctrl);
3698 } else {
3699 /* Asking for a specific link mode. */
3700 if (tp->link_config.speed == SPEED_1000) {
3701 if (tp->link_config.duplex == DUPLEX_FULL)
3702 new_adv = ADVERTISED_1000baseT_Full;
3703 else
3704 new_adv = ADVERTISED_1000baseT_Half;
3705 } else if (tp->link_config.speed == SPEED_100) {
3706 if (tp->link_config.duplex == DUPLEX_FULL)
3707 new_adv = ADVERTISED_100baseT_Full;
3708 else
3709 new_adv = ADVERTISED_100baseT_Half;
3710 } else {
3711 if (tp->link_config.duplex == DUPLEX_FULL)
3712 new_adv = ADVERTISED_10baseT_Full;
3713 else
3714 new_adv = ADVERTISED_10baseT_Half;
3715 }
3716
3717 tg3_phy_autoneg_cfg(tp, new_adv,
3718 tp->link_config.flowctrl);
Matt Carlson52b02d02010-10-14 10:37:41 +00003719 }
3720
Linus Torvalds1da177e2005-04-16 15:20:36 -07003721 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3722 tp->link_config.speed != SPEED_INVALID) {
3723 u32 bmcr, orig_bmcr;
3724
3725 tp->link_config.active_speed = tp->link_config.speed;
3726 tp->link_config.active_duplex = tp->link_config.duplex;
3727
3728 bmcr = 0;
3729 switch (tp->link_config.speed) {
3730 default:
3731 case SPEED_10:
3732 break;
3733
3734 case SPEED_100:
3735 bmcr |= BMCR_SPEED100;
3736 break;
3737
3738 case SPEED_1000:
Matt Carlson221c5632011-06-13 13:39:01 +00003739 bmcr |= BMCR_SPEED1000;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003740 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07003741 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003742
3743 if (tp->link_config.duplex == DUPLEX_FULL)
3744 bmcr |= BMCR_FULLDPLX;
3745
3746 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3747 (bmcr != orig_bmcr)) {
3748 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3749 for (i = 0; i < 1500; i++) {
3750 u32 tmp;
3751
3752 udelay(10);
3753 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3754 tg3_readphy(tp, MII_BMSR, &tmp))
3755 continue;
3756 if (!(tmp & BMSR_LSTATUS)) {
3757 udelay(40);
3758 break;
3759 }
3760 }
3761 tg3_writephy(tp, MII_BMCR, bmcr);
3762 udelay(40);
3763 }
3764 } else {
3765 tg3_writephy(tp, MII_BMCR,
3766 BMCR_ANENABLE | BMCR_ANRESTART);
3767 }
3768}
3769
3770static int tg3_init_5401phy_dsp(struct tg3 *tp)
3771{
3772 int err;
3773
3774 /* Turn off tap power management. */
3775 /* Set Extended packet length bit */
Matt Carlsonb4bd2922011-04-20 07:57:41 +00003776 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003777
Matt Carlson6ee7c0a2010-08-02 11:26:04 +00003778 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3779 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3780 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3781 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3782 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003783
3784 udelay(40);
3785
3786 return err;
3787}
3788
Michael Chan3600d912006-12-07 00:21:48 -08003789static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003790{
Michael Chan3600d912006-12-07 00:21:48 -08003791 u32 adv_reg, all_mask = 0;
3792
3793 if (mask & ADVERTISED_10baseT_Half)
3794 all_mask |= ADVERTISE_10HALF;
3795 if (mask & ADVERTISED_10baseT_Full)
3796 all_mask |= ADVERTISE_10FULL;
3797 if (mask & ADVERTISED_100baseT_Half)
3798 all_mask |= ADVERTISE_100HALF;
3799 if (mask & ADVERTISED_100baseT_Full)
3800 all_mask |= ADVERTISE_100FULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003801
3802 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3803 return 0;
3804
Matt Carlsonb99d2a52011-08-31 11:44:47 +00003805 if ((adv_reg & ADVERTISE_ALL) != all_mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003806 return 0;
Matt Carlsonb99d2a52011-08-31 11:44:47 +00003807
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003808 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003809 u32 tg3_ctrl;
3810
Michael Chan3600d912006-12-07 00:21:48 -08003811 all_mask = 0;
3812 if (mask & ADVERTISED_1000baseT_Half)
3813 all_mask |= ADVERTISE_1000HALF;
3814 if (mask & ADVERTISED_1000baseT_Full)
3815 all_mask |= ADVERTISE_1000FULL;
3816
Matt Carlson221c5632011-06-13 13:39:01 +00003817 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003818 return 0;
3819
Matt Carlsonb99d2a52011-08-31 11:44:47 +00003820 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
3821 if (tg3_ctrl != all_mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003822 return 0;
3823 }
Matt Carlson93a700a2011-08-31 11:44:54 +00003824
Linus Torvalds1da177e2005-04-16 15:20:36 -07003825 return 1;
3826}
3827
Matt Carlsonef167e22007-12-20 20:10:01 -08003828static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3829{
3830 u32 curadv, reqadv;
3831
3832 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3833 return 1;
3834
3835 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3836 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3837
3838 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3839 if (curadv != reqadv)
3840 return 0;
3841
Joe Perches63c3a662011-04-26 08:12:10 +00003842 if (tg3_flag(tp, PAUSE_AUTONEG))
Matt Carlsonef167e22007-12-20 20:10:01 -08003843 tg3_readphy(tp, MII_LPA, rmtadv);
3844 } else {
3845 /* Reprogram the advertisement register, even if it
3846 * does not affect the current link. If the link
3847 * gets renegotiated in the future, we can save an
3848 * additional renegotiation cycle by advertising
3849 * it correctly in the first place.
3850 */
3851 if (curadv != reqadv) {
3852 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3853 ADVERTISE_PAUSE_ASYM);
3854 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3855 }
3856 }
3857
3858 return 1;
3859}
3860
Linus Torvalds1da177e2005-04-16 15:20:36 -07003861static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3862{
3863 int current_link_up;
Matt Carlsonf833c4c2010-09-15 09:00:01 +00003864 u32 bmsr, val;
Matt Carlsonef167e22007-12-20 20:10:01 -08003865 u32 lcl_adv, rmt_adv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003866 u16 current_speed;
3867 u8 current_duplex;
3868 int i, err;
3869
3870 tw32(MAC_EVENT, 0);
3871
3872 tw32_f(MAC_STATUS,
3873 (MAC_STATUS_SYNC_CHANGED |
3874 MAC_STATUS_CFG_CHANGED |
3875 MAC_STATUS_MI_COMPLETION |
3876 MAC_STATUS_LNKSTATE_CHANGED));
3877 udelay(40);
3878
Matt Carlson8ef21422008-05-02 16:47:53 -07003879 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3880 tw32_f(MAC_MI_MODE,
3881 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3882 udelay(80);
3883 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003884
Matt Carlsonb4bd2922011-04-20 07:57:41 +00003885 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003886
3887 /* Some third-party PHYs need to be reset on link going
3888 * down.
3889 */
3890 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3891 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3892 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3893 netif_carrier_ok(tp->dev)) {
3894 tg3_readphy(tp, MII_BMSR, &bmsr);
3895 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3896 !(bmsr & BMSR_LSTATUS))
3897 force_reset = 1;
3898 }
3899 if (force_reset)
3900 tg3_phy_reset(tp);
3901
Matt Carlson79eb6902010-02-17 15:17:03 +00003902 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003903 tg3_readphy(tp, MII_BMSR, &bmsr);
3904 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
Joe Perches63c3a662011-04-26 08:12:10 +00003905 !tg3_flag(tp, INIT_COMPLETE))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003906 bmsr = 0;
3907
3908 if (!(bmsr & BMSR_LSTATUS)) {
3909 err = tg3_init_5401phy_dsp(tp);
3910 if (err)
3911 return err;
3912
3913 tg3_readphy(tp, MII_BMSR, &bmsr);
3914 for (i = 0; i < 1000; i++) {
3915 udelay(10);
3916 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3917 (bmsr & BMSR_LSTATUS)) {
3918 udelay(40);
3919 break;
3920 }
3921 }
3922
Matt Carlson79eb6902010-02-17 15:17:03 +00003923 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3924 TG3_PHY_REV_BCM5401_B0 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07003925 !(bmsr & BMSR_LSTATUS) &&
3926 tp->link_config.active_speed == SPEED_1000) {
3927 err = tg3_phy_reset(tp);
3928 if (!err)
3929 err = tg3_init_5401phy_dsp(tp);
3930 if (err)
3931 return err;
3932 }
3933 }
3934 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3935 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3936 /* 5701 {A0,B0} CRC bug workaround */
3937 tg3_writephy(tp, 0x15, 0x0a75);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00003938 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3939 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3940 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003941 }
3942
3943 /* Clear pending interrupts... */
Matt Carlsonf833c4c2010-09-15 09:00:01 +00003944 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3945 tg3_readphy(tp, MII_TG3_ISTAT, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003946
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003947 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003948 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003949 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003950 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3951
3952 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3954 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3955 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3956 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3957 else
3958 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3959 }
3960
3961 current_link_up = 0;
3962 current_speed = SPEED_INVALID;
3963 current_duplex = DUPLEX_INVALID;
3964
Matt Carlsonf07e9af2010-08-02 11:26:07 +00003965 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
Matt Carlson15ee95c2011-04-20 07:57:40 +00003966 err = tg3_phy_auxctl_read(tp,
3967 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3968 &val);
3969 if (!err && !(val & (1 << 10))) {
Matt Carlsonb4bd2922011-04-20 07:57:41 +00003970 tg3_phy_auxctl_write(tp,
3971 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
3972 val | (1 << 10));
Linus Torvalds1da177e2005-04-16 15:20:36 -07003973 goto relink;
3974 }
3975 }
3976
3977 bmsr = 0;
3978 for (i = 0; i < 100; i++) {
3979 tg3_readphy(tp, MII_BMSR, &bmsr);
3980 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3981 (bmsr & BMSR_LSTATUS))
3982 break;
3983 udelay(40);
3984 }
3985
3986 if (bmsr & BMSR_LSTATUS) {
3987 u32 aux_stat, bmcr;
3988
3989 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3990 for (i = 0; i < 2000; i++) {
3991 udelay(10);
3992 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3993 aux_stat)
3994 break;
3995 }
3996
3997 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3998 &current_speed,
3999 &current_duplex);
4000
4001 bmcr = 0;
4002 for (i = 0; i < 200; i++) {
4003 tg3_readphy(tp, MII_BMCR, &bmcr);
4004 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4005 continue;
4006 if (bmcr && bmcr != 0x7fff)
4007 break;
4008 udelay(10);
4009 }
4010
Matt Carlsonef167e22007-12-20 20:10:01 -08004011 lcl_adv = 0;
4012 rmt_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004013
Matt Carlsonef167e22007-12-20 20:10:01 -08004014 tp->link_config.active_speed = current_speed;
4015 tp->link_config.active_duplex = current_duplex;
4016
4017 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4018 if ((bmcr & BMCR_ANENABLE) &&
4019 tg3_copper_is_advertising_all(tp,
4020 tp->link_config.advertising)) {
4021 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
4022 &rmt_adv))
4023 current_link_up = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004024 }
4025 } else {
4026 if (!(bmcr & BMCR_ANENABLE) &&
4027 tp->link_config.speed == current_speed &&
Matt Carlsonef167e22007-12-20 20:10:01 -08004028 tp->link_config.duplex == current_duplex &&
4029 tp->link_config.flowctrl ==
4030 tp->link_config.active_flowctrl) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004031 current_link_up = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004032 }
4033 }
4034
Matt Carlsonef167e22007-12-20 20:10:01 -08004035 if (current_link_up == 1 &&
4036 tp->link_config.active_duplex == DUPLEX_FULL)
4037 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004038 }
4039
Linus Torvalds1da177e2005-04-16 15:20:36 -07004040relink:
Matt Carlson80096062010-08-02 11:26:06 +00004041 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004042 tg3_phy_copper_begin(tp);
4043
Matt Carlsonf833c4c2010-09-15 09:00:01 +00004044 tg3_readphy(tp, MII_BMSR, &bmsr);
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00004045 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4046 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004047 current_link_up = 1;
4048 }
4049
4050 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4051 if (current_link_up == 1) {
4052 if (tp->link_config.active_speed == SPEED_100 ||
4053 tp->link_config.active_speed == SPEED_10)
4054 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4055 else
4056 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004057 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
Matt Carlson7f97a4b2009-08-25 10:10:03 +00004058 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4059 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07004060 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4061
4062 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4063 if (tp->link_config.active_duplex == DUPLEX_HALF)
4064 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4065
Linus Torvalds1da177e2005-04-16 15:20:36 -07004066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07004067 if (current_link_up == 1 &&
4068 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004069 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07004070 else
4071 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004072 }
4073
4074 /* ??? Without this setting Netgear GA302T PHY does not
4075 * ??? send/receive packets...
4076 */
Matt Carlson79eb6902010-02-17 15:17:03 +00004077 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07004078 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
4079 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
4080 tw32_f(MAC_MI_MODE, tp->mi_mode);
4081 udelay(80);
4082 }
4083
4084 tw32_f(MAC_MODE, tp->mac_mode);
4085 udelay(40);
4086
Matt Carlson52b02d02010-10-14 10:37:41 +00004087 tg3_phy_eee_adjust(tp, current_link_up);
4088
Joe Perches63c3a662011-04-26 08:12:10 +00004089 if (tg3_flag(tp, USE_LINKCHG_REG)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004090 /* Polled via timer. */
4091 tw32_f(MAC_EVENT, 0);
4092 } else {
4093 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4094 }
4095 udelay(40);
4096
4097 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
4098 current_link_up == 1 &&
4099 tp->link_config.active_speed == SPEED_1000 &&
Joe Perches63c3a662011-04-26 08:12:10 +00004100 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004101 udelay(120);
4102 tw32_f(MAC_STATUS,
4103 (MAC_STATUS_SYNC_CHANGED |
4104 MAC_STATUS_CFG_CHANGED));
4105 udelay(40);
4106 tg3_write_mem(tp,
4107 NIC_SRAM_FIRMWARE_MBOX,
4108 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
4109 }
4110
Matt Carlson5e7dfd02008-11-21 17:18:16 -08004111 /* Prevent send BD corruption. */
Joe Perches63c3a662011-04-26 08:12:10 +00004112 if (tg3_flag(tp, CLKREQ_BUG)) {
Matt Carlson5e7dfd02008-11-21 17:18:16 -08004113 u16 oldlnkctl, newlnkctl;
4114
4115 pci_read_config_word(tp->pdev,
Jon Mason708ebb32011-06-27 12:56:50 +00004116 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
Matt Carlson5e7dfd02008-11-21 17:18:16 -08004117 &oldlnkctl);
4118 if (tp->link_config.active_speed == SPEED_100 ||
4119 tp->link_config.active_speed == SPEED_10)
4120 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
4121 else
4122 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
4123 if (newlnkctl != oldlnkctl)
4124 pci_write_config_word(tp->pdev,
Matt Carlson93a700a2011-08-31 11:44:54 +00004125 pci_pcie_cap(tp->pdev) +
4126 PCI_EXP_LNKCTL, newlnkctl);
Matt Carlson5e7dfd02008-11-21 17:18:16 -08004127 }
4128
Linus Torvalds1da177e2005-04-16 15:20:36 -07004129 if (current_link_up != netif_carrier_ok(tp->dev)) {
4130 if (current_link_up)
4131 netif_carrier_on(tp->dev);
4132 else
4133 netif_carrier_off(tp->dev);
4134 tg3_link_report(tp);
4135 }
4136
4137 return 0;
4138}
4139
4140struct tg3_fiber_aneginfo {
4141 int state;
4142#define ANEG_STATE_UNKNOWN 0
4143#define ANEG_STATE_AN_ENABLE 1
4144#define ANEG_STATE_RESTART_INIT 2
4145#define ANEG_STATE_RESTART 3
4146#define ANEG_STATE_DISABLE_LINK_OK 4
4147#define ANEG_STATE_ABILITY_DETECT_INIT 5
4148#define ANEG_STATE_ABILITY_DETECT 6
4149#define ANEG_STATE_ACK_DETECT_INIT 7
4150#define ANEG_STATE_ACK_DETECT 8
4151#define ANEG_STATE_COMPLETE_ACK_INIT 9
4152#define ANEG_STATE_COMPLETE_ACK 10
4153#define ANEG_STATE_IDLE_DETECT_INIT 11
4154#define ANEG_STATE_IDLE_DETECT 12
4155#define ANEG_STATE_LINK_OK 13
4156#define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4157#define ANEG_STATE_NEXT_PAGE_WAIT 15
4158
4159 u32 flags;
4160#define MR_AN_ENABLE 0x00000001
4161#define MR_RESTART_AN 0x00000002
4162#define MR_AN_COMPLETE 0x00000004
4163#define MR_PAGE_RX 0x00000008
4164#define MR_NP_LOADED 0x00000010
4165#define MR_TOGGLE_TX 0x00000020
4166#define MR_LP_ADV_FULL_DUPLEX 0x00000040
4167#define MR_LP_ADV_HALF_DUPLEX 0x00000080
4168#define MR_LP_ADV_SYM_PAUSE 0x00000100
4169#define MR_LP_ADV_ASYM_PAUSE 0x00000200
4170#define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4171#define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4172#define MR_LP_ADV_NEXT_PAGE 0x00001000
4173#define MR_TOGGLE_RX 0x00002000
4174#define MR_NP_RX 0x00004000
4175
4176#define MR_LINK_OK 0x80000000
4177
4178 unsigned long link_time, cur_time;
4179
4180 u32 ability_match_cfg;
4181 int ability_match_count;
4182
4183 char ability_match, idle_match, ack_match;
4184
4185 u32 txconfig, rxconfig;
4186#define ANEG_CFG_NP 0x00000080
4187#define ANEG_CFG_ACK 0x00000040
4188#define ANEG_CFG_RF2 0x00000020
4189#define ANEG_CFG_RF1 0x00000010
4190#define ANEG_CFG_PS2 0x00000001
4191#define ANEG_CFG_PS1 0x00008000
4192#define ANEG_CFG_HD 0x00004000
4193#define ANEG_CFG_FD 0x00002000
4194#define ANEG_CFG_INVAL 0x00001f06
4195
4196};
4197#define ANEG_OK 0
4198#define ANEG_DONE 1
4199#define ANEG_TIMER_ENAB 2
4200#define ANEG_FAILED -1
4201
4202#define ANEG_STATE_SETTLE_TIME 10000
4203
4204static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4205 struct tg3_fiber_aneginfo *ap)
4206{
Matt Carlson5be73b42007-12-20 20:09:29 -08004207 u16 flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004208 unsigned long delta;
4209 u32 rx_cfg_reg;
4210 int ret;
4211
4212 if (ap->state == ANEG_STATE_UNKNOWN) {
4213 ap->rxconfig = 0;
4214 ap->link_time = 0;
4215 ap->cur_time = 0;
4216 ap->ability_match_cfg = 0;
4217 ap->ability_match_count = 0;
4218 ap->ability_match = 0;
4219 ap->idle_match = 0;
4220 ap->ack_match = 0;
4221 }
4222 ap->cur_time++;
4223
4224 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
4225 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4226
4227 if (rx_cfg_reg != ap->ability_match_cfg) {
4228 ap->ability_match_cfg = rx_cfg_reg;
4229 ap->ability_match = 0;
4230 ap->ability_match_count = 0;
4231 } else {
4232 if (++ap->ability_match_count > 1) {
4233 ap->ability_match = 1;
4234 ap->ability_match_cfg = rx_cfg_reg;
4235 }
4236 }
4237 if (rx_cfg_reg & ANEG_CFG_ACK)
4238 ap->ack_match = 1;
4239 else
4240 ap->ack_match = 0;
4241
4242 ap->idle_match = 0;
4243 } else {
4244 ap->idle_match = 1;
4245 ap->ability_match_cfg = 0;
4246 ap->ability_match_count = 0;
4247 ap->ability_match = 0;
4248 ap->ack_match = 0;
4249
4250 rx_cfg_reg = 0;
4251 }
4252
4253 ap->rxconfig = rx_cfg_reg;
4254 ret = ANEG_OK;
4255
Matt Carlson33f401a2010-04-05 10:19:27 +00004256 switch (ap->state) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004257 case ANEG_STATE_UNKNOWN:
4258 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4259 ap->state = ANEG_STATE_AN_ENABLE;
4260
4261 /* fallthru */
4262 case ANEG_STATE_AN_ENABLE:
4263 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4264 if (ap->flags & MR_AN_ENABLE) {
4265 ap->link_time = 0;
4266 ap->cur_time = 0;
4267 ap->ability_match_cfg = 0;
4268 ap->ability_match_count = 0;
4269 ap->ability_match = 0;
4270 ap->idle_match = 0;
4271 ap->ack_match = 0;
4272
4273 ap->state = ANEG_STATE_RESTART_INIT;
4274 } else {
4275 ap->state = ANEG_STATE_DISABLE_LINK_OK;
4276 }
4277 break;
4278
4279 case ANEG_STATE_RESTART_INIT:
4280 ap->link_time = ap->cur_time;
4281 ap->flags &= ~(MR_NP_LOADED);
4282 ap->txconfig = 0;
4283 tw32(MAC_TX_AUTO_NEG, 0);
4284 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4285 tw32_f(MAC_MODE, tp->mac_mode);
4286 udelay(40);
4287
4288 ret = ANEG_TIMER_ENAB;
4289 ap->state = ANEG_STATE_RESTART;
4290
4291 /* fallthru */
4292 case ANEG_STATE_RESTART:
4293 delta = ap->cur_time - ap->link_time;
Matt Carlson859a5882010-04-05 10:19:28 +00004294 if (delta > ANEG_STATE_SETTLE_TIME)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004295 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
Matt Carlson859a5882010-04-05 10:19:28 +00004296 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07004297 ret = ANEG_TIMER_ENAB;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004298 break;
4299
4300 case ANEG_STATE_DISABLE_LINK_OK:
4301 ret = ANEG_DONE;
4302 break;
4303
4304 case ANEG_STATE_ABILITY_DETECT_INIT:
4305 ap->flags &= ~(MR_TOGGLE_TX);
Matt Carlson5be73b42007-12-20 20:09:29 -08004306 ap->txconfig = ANEG_CFG_FD;
4307 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4308 if (flowctrl & ADVERTISE_1000XPAUSE)
4309 ap->txconfig |= ANEG_CFG_PS1;
4310 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4311 ap->txconfig |= ANEG_CFG_PS2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004312 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4313 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4314 tw32_f(MAC_MODE, tp->mac_mode);
4315 udelay(40);
4316
4317 ap->state = ANEG_STATE_ABILITY_DETECT;
4318 break;
4319
4320 case ANEG_STATE_ABILITY_DETECT:
Matt Carlson859a5882010-04-05 10:19:28 +00004321 if (ap->ability_match != 0 && ap->rxconfig != 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004322 ap->state = ANEG_STATE_ACK_DETECT_INIT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004323 break;
4324
4325 case ANEG_STATE_ACK_DETECT_INIT:
4326 ap->txconfig |= ANEG_CFG_ACK;
4327 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
4328 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
4329 tw32_f(MAC_MODE, tp->mac_mode);
4330 udelay(40);
4331
4332 ap->state = ANEG_STATE_ACK_DETECT;
4333
4334 /* fallthru */
4335 case ANEG_STATE_ACK_DETECT:
4336 if (ap->ack_match != 0) {
4337 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4338 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4339 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
4340 } else {
4341 ap->state = ANEG_STATE_AN_ENABLE;
4342 }
4343 } else if (ap->ability_match != 0 &&
4344 ap->rxconfig == 0) {
4345 ap->state = ANEG_STATE_AN_ENABLE;
4346 }
4347 break;
4348
4349 case ANEG_STATE_COMPLETE_ACK_INIT:
4350 if (ap->rxconfig & ANEG_CFG_INVAL) {
4351 ret = ANEG_FAILED;
4352 break;
4353 }
4354 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4355 MR_LP_ADV_HALF_DUPLEX |
4356 MR_LP_ADV_SYM_PAUSE |
4357 MR_LP_ADV_ASYM_PAUSE |
4358 MR_LP_ADV_REMOTE_FAULT1 |
4359 MR_LP_ADV_REMOTE_FAULT2 |
4360 MR_LP_ADV_NEXT_PAGE |
4361 MR_TOGGLE_RX |
4362 MR_NP_RX);
4363 if (ap->rxconfig & ANEG_CFG_FD)
4364 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
4365 if (ap->rxconfig & ANEG_CFG_HD)
4366 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
4367 if (ap->rxconfig & ANEG_CFG_PS1)
4368 ap->flags |= MR_LP_ADV_SYM_PAUSE;
4369 if (ap->rxconfig & ANEG_CFG_PS2)
4370 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4371 if (ap->rxconfig & ANEG_CFG_RF1)
4372 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
4373 if (ap->rxconfig & ANEG_CFG_RF2)
4374 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
4375 if (ap->rxconfig & ANEG_CFG_NP)
4376 ap->flags |= MR_LP_ADV_NEXT_PAGE;
4377
4378 ap->link_time = ap->cur_time;
4379
4380 ap->flags ^= (MR_TOGGLE_TX);
4381 if (ap->rxconfig & 0x0008)
4382 ap->flags |= MR_TOGGLE_RX;
4383 if (ap->rxconfig & ANEG_CFG_NP)
4384 ap->flags |= MR_NP_RX;
4385 ap->flags |= MR_PAGE_RX;
4386
4387 ap->state = ANEG_STATE_COMPLETE_ACK;
4388 ret = ANEG_TIMER_ENAB;
4389 break;
4390
4391 case ANEG_STATE_COMPLETE_ACK:
4392 if (ap->ability_match != 0 &&
4393 ap->rxconfig == 0) {
4394 ap->state = ANEG_STATE_AN_ENABLE;
4395 break;
4396 }
4397 delta = ap->cur_time - ap->link_time;
4398 if (delta > ANEG_STATE_SETTLE_TIME) {
4399 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4400 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4401 } else {
4402 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4403 !(ap->flags & MR_NP_RX)) {
4404 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
4405 } else {
4406 ret = ANEG_FAILED;
4407 }
4408 }
4409 }
4410 break;
4411
4412 case ANEG_STATE_IDLE_DETECT_INIT:
4413 ap->link_time = ap->cur_time;
4414 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4415 tw32_f(MAC_MODE, tp->mac_mode);
4416 udelay(40);
4417
4418 ap->state = ANEG_STATE_IDLE_DETECT;
4419 ret = ANEG_TIMER_ENAB;
4420 break;
4421
4422 case ANEG_STATE_IDLE_DETECT:
4423 if (ap->ability_match != 0 &&
4424 ap->rxconfig == 0) {
4425 ap->state = ANEG_STATE_AN_ENABLE;
4426 break;
4427 }
4428 delta = ap->cur_time - ap->link_time;
4429 if (delta > ANEG_STATE_SETTLE_TIME) {
4430 /* XXX another gem from the Broadcom driver :( */
4431 ap->state = ANEG_STATE_LINK_OK;
4432 }
4433 break;
4434
4435 case ANEG_STATE_LINK_OK:
4436 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4437 ret = ANEG_DONE;
4438 break;
4439
4440 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
4441 /* ??? unimplemented */
4442 break;
4443
4444 case ANEG_STATE_NEXT_PAGE_WAIT:
4445 /* ??? unimplemented */
4446 break;
4447
4448 default:
4449 ret = ANEG_FAILED;
4450 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07004451 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004452
4453 return ret;
4454}
4455
Matt Carlson5be73b42007-12-20 20:09:29 -08004456static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004457{
4458 int res = 0;
4459 struct tg3_fiber_aneginfo aninfo;
4460 int status = ANEG_FAILED;
4461 unsigned int tick;
4462 u32 tmp;
4463
4464 tw32_f(MAC_TX_AUTO_NEG, 0);
4465
4466 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4467 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
4468 udelay(40);
4469
4470 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
4471 udelay(40);
4472
4473 memset(&aninfo, 0, sizeof(aninfo));
4474 aninfo.flags |= MR_AN_ENABLE;
4475 aninfo.state = ANEG_STATE_UNKNOWN;
4476 aninfo.cur_time = 0;
4477 tick = 0;
4478 while (++tick < 195000) {
4479 status = tg3_fiber_aneg_smachine(tp, &aninfo);
4480 if (status == ANEG_DONE || status == ANEG_FAILED)
4481 break;
4482
4483 udelay(1);
4484 }
4485
4486 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
4487 tw32_f(MAC_MODE, tp->mac_mode);
4488 udelay(40);
4489
Matt Carlson5be73b42007-12-20 20:09:29 -08004490 *txflags = aninfo.txconfig;
4491 *rxflags = aninfo.flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004492
4493 if (status == ANEG_DONE &&
4494 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4495 MR_LP_ADV_FULL_DUPLEX)))
4496 res = 1;
4497
4498 return res;
4499}
4500
4501static void tg3_init_bcm8002(struct tg3 *tp)
4502{
4503 u32 mac_status = tr32(MAC_STATUS);
4504 int i;
4505
4506 /* Reset when initting first time or we have a link. */
Joe Perches63c3a662011-04-26 08:12:10 +00004507 if (tg3_flag(tp, INIT_COMPLETE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07004508 !(mac_status & MAC_STATUS_PCS_SYNCED))
4509 return;
4510
4511 /* Set PLL lock range. */
4512 tg3_writephy(tp, 0x16, 0x8007);
4513
4514 /* SW reset */
4515 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4516
4517 /* Wait for reset to complete. */
4518 /* XXX schedule_timeout() ... */
4519 for (i = 0; i < 500; i++)
4520 udelay(10);
4521
4522 /* Config mode; select PMA/Ch 1 regs. */
4523 tg3_writephy(tp, 0x10, 0x8411);
4524
4525 /* Enable auto-lock and comdet, select txclk for tx. */
4526 tg3_writephy(tp, 0x11, 0x0a10);
4527
4528 tg3_writephy(tp, 0x18, 0x00a0);
4529 tg3_writephy(tp, 0x16, 0x41ff);
4530
4531 /* Assert and deassert POR. */
4532 tg3_writephy(tp, 0x13, 0x0400);
4533 udelay(40);
4534 tg3_writephy(tp, 0x13, 0x0000);
4535
4536 tg3_writephy(tp, 0x11, 0x0a50);
4537 udelay(40);
4538 tg3_writephy(tp, 0x11, 0x0a10);
4539
4540 /* Wait for signal to stabilize */
4541 /* XXX schedule_timeout() ... */
4542 for (i = 0; i < 15000; i++)
4543 udelay(10);
4544
4545 /* Deselect the channel register so we can read the PHYID
4546 * later.
4547 */
4548 tg3_writephy(tp, 0x10, 0x8011);
4549}
4550
4551static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4552{
Matt Carlson82cd3d12007-12-20 20:09:00 -08004553 u16 flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004554 u32 sg_dig_ctrl, sg_dig_status;
4555 u32 serdes_cfg, expected_sg_dig_ctrl;
4556 int workaround, port_a;
4557 int current_link_up;
4558
4559 serdes_cfg = 0;
4560 expected_sg_dig_ctrl = 0;
4561 workaround = 0;
4562 port_a = 1;
4563 current_link_up = 0;
4564
4565 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4566 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
4567 workaround = 1;
4568 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
4569 port_a = 0;
4570
4571 /* preserve bits 0-11,13,14 for signal pre-emphasis */
4572 /* preserve bits 20-23 for voltage regulator */
4573 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4574 }
4575
4576 sg_dig_ctrl = tr32(SG_DIG_CTRL);
4577
4578 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004579 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004580 if (workaround) {
4581 u32 val = serdes_cfg;
4582
4583 if (port_a)
4584 val |= 0xc010000;
4585 else
4586 val |= 0x4010000;
4587 tw32_f(MAC_SERDES_CFG, val);
4588 }
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004589
4590 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004591 }
4592 if (mac_status & MAC_STATUS_PCS_SYNCED) {
4593 tg3_setup_flow_control(tp, 0, 0);
4594 current_link_up = 1;
4595 }
4596 goto out;
4597 }
4598
4599 /* Want auto-negotiation. */
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004600 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004601
Matt Carlson82cd3d12007-12-20 20:09:00 -08004602 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4603 if (flowctrl & ADVERTISE_1000XPAUSE)
4604 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4605 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4606 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004607
4608 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004609 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
Michael Chan3d3ebe72006-09-27 15:59:15 -07004610 tp->serdes_counter &&
4611 ((mac_status & (MAC_STATUS_PCS_SYNCED |
4612 MAC_STATUS_RCVD_CFG)) ==
4613 MAC_STATUS_PCS_SYNCED)) {
4614 tp->serdes_counter--;
4615 current_link_up = 1;
4616 goto out;
4617 }
4618restart_autoneg:
Linus Torvalds1da177e2005-04-16 15:20:36 -07004619 if (workaround)
4620 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004621 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004622 udelay(5);
4623 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4624
Michael Chan3d3ebe72006-09-27 15:59:15 -07004625 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004626 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004627 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4628 MAC_STATUS_SIGNAL_DET)) {
Michael Chan3d3ebe72006-09-27 15:59:15 -07004629 sg_dig_status = tr32(SG_DIG_STATUS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004630 mac_status = tr32(MAC_STATUS);
4631
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004632 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07004633 (mac_status & MAC_STATUS_PCS_SYNCED)) {
Matt Carlson82cd3d12007-12-20 20:09:00 -08004634 u32 local_adv = 0, remote_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004635
Matt Carlson82cd3d12007-12-20 20:09:00 -08004636 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4637 local_adv |= ADVERTISE_1000XPAUSE;
4638 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4639 local_adv |= ADVERTISE_1000XPSE_ASYM;
4640
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004641 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
Matt Carlson82cd3d12007-12-20 20:09:00 -08004642 remote_adv |= LPA_1000XPAUSE;
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004643 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
Matt Carlson82cd3d12007-12-20 20:09:00 -08004644 remote_adv |= LPA_1000XPAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004645
4646 tg3_setup_flow_control(tp, local_adv, remote_adv);
4647 current_link_up = 1;
Michael Chan3d3ebe72006-09-27 15:59:15 -07004648 tp->serdes_counter = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004649 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004650 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
Michael Chan3d3ebe72006-09-27 15:59:15 -07004651 if (tp->serdes_counter)
4652 tp->serdes_counter--;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004653 else {
4654 if (workaround) {
4655 u32 val = serdes_cfg;
4656
4657 if (port_a)
4658 val |= 0xc010000;
4659 else
4660 val |= 0x4010000;
4661
4662 tw32_f(MAC_SERDES_CFG, val);
4663 }
4664
Matt Carlsonc98f6e32007-12-20 20:08:32 -08004665 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004666 udelay(40);
4667
4668 /* Link parallel detection - link is up */
4669 /* only if we have PCS_SYNC and not */
4670 /* receiving config code words */
4671 mac_status = tr32(MAC_STATUS);
4672 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4673 !(mac_status & MAC_STATUS_RCVD_CFG)) {
4674 tg3_setup_flow_control(tp, 0, 0);
4675 current_link_up = 1;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004676 tp->phy_flags |=
4677 TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan3d3ebe72006-09-27 15:59:15 -07004678 tp->serdes_counter =
4679 SERDES_PARALLEL_DET_TIMEOUT;
4680 } else
4681 goto restart_autoneg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004682 }
4683 }
Michael Chan3d3ebe72006-09-27 15:59:15 -07004684 } else {
4685 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004686 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004687 }
4688
4689out:
4690 return current_link_up;
4691}
4692
4693static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
4694{
4695 int current_link_up = 0;
4696
Michael Chan5cf64b82007-05-05 12:11:21 -07004697 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004698 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004699
4700 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
Matt Carlson5be73b42007-12-20 20:09:29 -08004701 u32 txflags, rxflags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004702 int i;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004703
Matt Carlson5be73b42007-12-20 20:09:29 -08004704 if (fiber_autoneg(tp, &txflags, &rxflags)) {
4705 u32 local_adv = 0, remote_adv = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004706
Matt Carlson5be73b42007-12-20 20:09:29 -08004707 if (txflags & ANEG_CFG_PS1)
4708 local_adv |= ADVERTISE_1000XPAUSE;
4709 if (txflags & ANEG_CFG_PS2)
4710 local_adv |= ADVERTISE_1000XPSE_ASYM;
4711
4712 if (rxflags & MR_LP_ADV_SYM_PAUSE)
4713 remote_adv |= LPA_1000XPAUSE;
4714 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
4715 remote_adv |= LPA_1000XPAUSE_ASYM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004716
4717 tg3_setup_flow_control(tp, local_adv, remote_adv);
4718
Linus Torvalds1da177e2005-04-16 15:20:36 -07004719 current_link_up = 1;
4720 }
4721 for (i = 0; i < 30; i++) {
4722 udelay(20);
4723 tw32_f(MAC_STATUS,
4724 (MAC_STATUS_SYNC_CHANGED |
4725 MAC_STATUS_CFG_CHANGED));
4726 udelay(40);
4727 if ((tr32(MAC_STATUS) &
4728 (MAC_STATUS_SYNC_CHANGED |
4729 MAC_STATUS_CFG_CHANGED)) == 0)
4730 break;
4731 }
4732
4733 mac_status = tr32(MAC_STATUS);
4734 if (current_link_up == 0 &&
4735 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4736 !(mac_status & MAC_STATUS_RCVD_CFG))
4737 current_link_up = 1;
4738 } else {
Matt Carlson5be73b42007-12-20 20:09:29 -08004739 tg3_setup_flow_control(tp, 0, 0);
4740
Linus Torvalds1da177e2005-04-16 15:20:36 -07004741 /* Forcing 1000FD link up. */
4742 current_link_up = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004743
4744 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4745 udelay(40);
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07004746
4747 tw32_f(MAC_MODE, tp->mac_mode);
4748 udelay(40);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004749 }
4750
4751out:
4752 return current_link_up;
4753}
4754
4755static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4756{
4757 u32 orig_pause_cfg;
4758 u16 orig_active_speed;
4759 u8 orig_active_duplex;
4760 u32 mac_status;
4761 int current_link_up;
4762 int i;
4763
Matt Carlson8d018622007-12-20 20:05:44 -08004764 orig_pause_cfg = tp->link_config.active_flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004765 orig_active_speed = tp->link_config.active_speed;
4766 orig_active_duplex = tp->link_config.active_duplex;
4767
Joe Perches63c3a662011-04-26 08:12:10 +00004768 if (!tg3_flag(tp, HW_AUTONEG) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07004769 netif_carrier_ok(tp->dev) &&
Joe Perches63c3a662011-04-26 08:12:10 +00004770 tg3_flag(tp, INIT_COMPLETE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004771 mac_status = tr32(MAC_STATUS);
4772 mac_status &= (MAC_STATUS_PCS_SYNCED |
4773 MAC_STATUS_SIGNAL_DET |
4774 MAC_STATUS_CFG_CHANGED |
4775 MAC_STATUS_RCVD_CFG);
4776 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4777 MAC_STATUS_SIGNAL_DET)) {
4778 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4779 MAC_STATUS_CFG_CHANGED));
4780 return 0;
4781 }
4782 }
4783
4784 tw32_f(MAC_TX_AUTO_NEG, 0);
4785
4786 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4787 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4788 tw32_f(MAC_MODE, tp->mac_mode);
4789 udelay(40);
4790
Matt Carlson79eb6902010-02-17 15:17:03 +00004791 if (tp->phy_id == TG3_PHY_ID_BCM8002)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004792 tg3_init_bcm8002(tp);
4793
4794 /* Enable link change event even when serdes polling. */
4795 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4796 udelay(40);
4797
4798 current_link_up = 0;
4799 mac_status = tr32(MAC_STATUS);
4800
Joe Perches63c3a662011-04-26 08:12:10 +00004801 if (tg3_flag(tp, HW_AUTONEG))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004802 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4803 else
4804 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4805
Matt Carlson898a56f2009-08-28 14:02:40 +00004806 tp->napi[0].hw_status->status =
Linus Torvalds1da177e2005-04-16 15:20:36 -07004807 (SD_STATUS_UPDATED |
Matt Carlson898a56f2009-08-28 14:02:40 +00004808 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004809
4810 for (i = 0; i < 100; i++) {
4811 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4812 MAC_STATUS_CFG_CHANGED));
4813 udelay(5);
4814 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
Michael Chan3d3ebe72006-09-27 15:59:15 -07004815 MAC_STATUS_CFG_CHANGED |
4816 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004817 break;
4818 }
4819
4820 mac_status = tr32(MAC_STATUS);
4821 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4822 current_link_up = 0;
Michael Chan3d3ebe72006-09-27 15:59:15 -07004823 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4824 tp->serdes_counter == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004825 tw32_f(MAC_MODE, (tp->mac_mode |
4826 MAC_MODE_SEND_CONFIGS));
4827 udelay(1);
4828 tw32_f(MAC_MODE, tp->mac_mode);
4829 }
4830 }
4831
4832 if (current_link_up == 1) {
4833 tp->link_config.active_speed = SPEED_1000;
4834 tp->link_config.active_duplex = DUPLEX_FULL;
4835 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4836 LED_CTRL_LNKLED_OVERRIDE |
4837 LED_CTRL_1000MBPS_ON));
4838 } else {
4839 tp->link_config.active_speed = SPEED_INVALID;
4840 tp->link_config.active_duplex = DUPLEX_INVALID;
4841 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4842 LED_CTRL_LNKLED_OVERRIDE |
4843 LED_CTRL_TRAFFIC_OVERRIDE));
4844 }
4845
4846 if (current_link_up != netif_carrier_ok(tp->dev)) {
4847 if (current_link_up)
4848 netif_carrier_on(tp->dev);
4849 else
4850 netif_carrier_off(tp->dev);
4851 tg3_link_report(tp);
4852 } else {
Matt Carlson8d018622007-12-20 20:05:44 -08004853 u32 now_pause_cfg = tp->link_config.active_flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004854 if (orig_pause_cfg != now_pause_cfg ||
4855 orig_active_speed != tp->link_config.active_speed ||
4856 orig_active_duplex != tp->link_config.active_duplex)
4857 tg3_link_report(tp);
4858 }
4859
4860 return 0;
4861}
4862
Michael Chan747e8f82005-07-25 12:33:22 -07004863static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4864{
4865 int current_link_up, err = 0;
4866 u32 bmsr, bmcr;
4867 u16 current_speed;
4868 u8 current_duplex;
Matt Carlsonef167e22007-12-20 20:10:01 -08004869 u32 local_adv, remote_adv;
Michael Chan747e8f82005-07-25 12:33:22 -07004870
4871 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4872 tw32_f(MAC_MODE, tp->mac_mode);
4873 udelay(40);
4874
4875 tw32(MAC_EVENT, 0);
4876
4877 tw32_f(MAC_STATUS,
4878 (MAC_STATUS_SYNC_CHANGED |
4879 MAC_STATUS_CFG_CHANGED |
4880 MAC_STATUS_MI_COMPLETION |
4881 MAC_STATUS_LNKSTATE_CHANGED));
4882 udelay(40);
4883
4884 if (force_reset)
4885 tg3_phy_reset(tp);
4886
4887 current_link_up = 0;
4888 current_speed = SPEED_INVALID;
4889 current_duplex = DUPLEX_INVALID;
4890
4891 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4892 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
Michael Chand4d2c552006-03-20 17:47:20 -08004893 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4894 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4895 bmsr |= BMSR_LSTATUS;
4896 else
4897 bmsr &= ~BMSR_LSTATUS;
4898 }
Michael Chan747e8f82005-07-25 12:33:22 -07004899
4900 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4901
4902 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004903 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
Michael Chan747e8f82005-07-25 12:33:22 -07004904 /* do nothing, just check for link up at the end */
4905 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4906 u32 adv, new_adv;
4907
4908 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4909 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4910 ADVERTISE_1000XPAUSE |
4911 ADVERTISE_1000XPSE_ASYM |
4912 ADVERTISE_SLCT);
4913
Matt Carlsonba4d07a2007-12-20 20:08:00 -08004914 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
Michael Chan747e8f82005-07-25 12:33:22 -07004915
4916 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4917 new_adv |= ADVERTISE_1000XHALF;
4918 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4919 new_adv |= ADVERTISE_1000XFULL;
4920
4921 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4922 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4923 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4924 tg3_writephy(tp, MII_BMCR, bmcr);
4925
4926 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
Michael Chan3d3ebe72006-09-27 15:59:15 -07004927 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004928 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07004929
4930 return err;
4931 }
4932 } else {
4933 u32 new_bmcr;
4934
4935 bmcr &= ~BMCR_SPEED1000;
4936 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4937
4938 if (tp->link_config.duplex == DUPLEX_FULL)
4939 new_bmcr |= BMCR_FULLDPLX;
4940
4941 if (new_bmcr != bmcr) {
4942 /* BMCR_SPEED1000 is a reserved bit that needs
4943 * to be set on write.
4944 */
4945 new_bmcr |= BMCR_SPEED1000;
4946
4947 /* Force a linkdown */
4948 if (netif_carrier_ok(tp->dev)) {
4949 u32 adv;
4950
4951 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4952 adv &= ~(ADVERTISE_1000XFULL |
4953 ADVERTISE_1000XHALF |
4954 ADVERTISE_SLCT);
4955 tg3_writephy(tp, MII_ADVERTISE, adv);
4956 tg3_writephy(tp, MII_BMCR, bmcr |
4957 BMCR_ANRESTART |
4958 BMCR_ANENABLE);
4959 udelay(10);
4960 netif_carrier_off(tp->dev);
4961 }
4962 tg3_writephy(tp, MII_BMCR, new_bmcr);
4963 bmcr = new_bmcr;
4964 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4965 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
Michael Chand4d2c552006-03-20 17:47:20 -08004966 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4967 ASIC_REV_5714) {
4968 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4969 bmsr |= BMSR_LSTATUS;
4970 else
4971 bmsr &= ~BMSR_LSTATUS;
4972 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00004973 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07004974 }
4975 }
4976
4977 if (bmsr & BMSR_LSTATUS) {
4978 current_speed = SPEED_1000;
4979 current_link_up = 1;
4980 if (bmcr & BMCR_FULLDPLX)
4981 current_duplex = DUPLEX_FULL;
4982 else
4983 current_duplex = DUPLEX_HALF;
4984
Matt Carlsonef167e22007-12-20 20:10:01 -08004985 local_adv = 0;
4986 remote_adv = 0;
4987
Michael Chan747e8f82005-07-25 12:33:22 -07004988 if (bmcr & BMCR_ANENABLE) {
Matt Carlsonef167e22007-12-20 20:10:01 -08004989 u32 common;
Michael Chan747e8f82005-07-25 12:33:22 -07004990
4991 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4992 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4993 common = local_adv & remote_adv;
4994 if (common & (ADVERTISE_1000XHALF |
4995 ADVERTISE_1000XFULL)) {
4996 if (common & ADVERTISE_1000XFULL)
4997 current_duplex = DUPLEX_FULL;
4998 else
4999 current_duplex = DUPLEX_HALF;
Joe Perches63c3a662011-04-26 08:12:10 +00005000 } else if (!tg3_flag(tp, 5780_CLASS)) {
Matt Carlson57d8b882010-06-05 17:24:35 +00005001 /* Link is up via parallel detect */
Matt Carlson859a5882010-04-05 10:19:28 +00005002 } else {
Michael Chan747e8f82005-07-25 12:33:22 -07005003 current_link_up = 0;
Matt Carlson859a5882010-04-05 10:19:28 +00005004 }
Michael Chan747e8f82005-07-25 12:33:22 -07005005 }
5006 }
5007
Matt Carlsonef167e22007-12-20 20:10:01 -08005008 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5009 tg3_setup_flow_control(tp, local_adv, remote_adv);
5010
Michael Chan747e8f82005-07-25 12:33:22 -07005011 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5012 if (tp->link_config.active_duplex == DUPLEX_HALF)
5013 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5014
5015 tw32_f(MAC_MODE, tp->mac_mode);
5016 udelay(40);
5017
5018 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5019
5020 tp->link_config.active_speed = current_speed;
5021 tp->link_config.active_duplex = current_duplex;
5022
5023 if (current_link_up != netif_carrier_ok(tp->dev)) {
5024 if (current_link_up)
5025 netif_carrier_on(tp->dev);
5026 else {
5027 netif_carrier_off(tp->dev);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005028 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07005029 }
5030 tg3_link_report(tp);
5031 }
5032 return err;
5033}
5034
5035static void tg3_serdes_parallel_detect(struct tg3 *tp)
5036{
Michael Chan3d3ebe72006-09-27 15:59:15 -07005037 if (tp->serdes_counter) {
Michael Chan747e8f82005-07-25 12:33:22 -07005038 /* Give autoneg time to complete. */
Michael Chan3d3ebe72006-09-27 15:59:15 -07005039 tp->serdes_counter--;
Michael Chan747e8f82005-07-25 12:33:22 -07005040 return;
5041 }
Matt Carlsonc6cdf432010-04-05 10:19:26 +00005042
Michael Chan747e8f82005-07-25 12:33:22 -07005043 if (!netif_carrier_ok(tp->dev) &&
5044 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5045 u32 bmcr;
5046
5047 tg3_readphy(tp, MII_BMCR, &bmcr);
5048 if (bmcr & BMCR_ANENABLE) {
5049 u32 phy1, phy2;
5050
5051 /* Select shadow register 0x1f */
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00005052 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5053 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
Michael Chan747e8f82005-07-25 12:33:22 -07005054
5055 /* Select expansion interrupt status register */
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00005056 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5057 MII_TG3_DSP_EXP1_INT_STAT);
5058 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5059 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
Michael Chan747e8f82005-07-25 12:33:22 -07005060
5061 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5062 /* We have signal detect and not receiving
5063 * config code words, link is up by parallel
5064 * detection.
5065 */
5066
5067 bmcr &= ~BMCR_ANENABLE;
5068 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5069 tg3_writephy(tp, MII_BMCR, bmcr);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005070 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07005071 }
5072 }
Matt Carlson859a5882010-04-05 10:19:28 +00005073 } else if (netif_carrier_ok(tp->dev) &&
5074 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005075 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
Michael Chan747e8f82005-07-25 12:33:22 -07005076 u32 phy2;
5077
5078 /* Select expansion interrupt status register */
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00005079 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5080 MII_TG3_DSP_EXP1_INT_STAT);
5081 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
Michael Chan747e8f82005-07-25 12:33:22 -07005082 if (phy2 & 0x20) {
5083 u32 bmcr;
5084
5085 /* Config code words received, turn on autoneg. */
5086 tg3_readphy(tp, MII_BMCR, &bmcr);
5087 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5088
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005089 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chan747e8f82005-07-25 12:33:22 -07005090
5091 }
5092 }
5093}
5094
Linus Torvalds1da177e2005-04-16 15:20:36 -07005095static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5096{
Matt Carlsonf2096f92011-04-05 14:22:48 +00005097 u32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005098 int err;
5099
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005100 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005101 err = tg3_setup_fiber_phy(tp, force_reset);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00005102 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
Michael Chan747e8f82005-07-25 12:33:22 -07005103 err = tg3_setup_fiber_mii_phy(tp, force_reset);
Matt Carlson859a5882010-04-05 10:19:28 +00005104 else
Linus Torvalds1da177e2005-04-16 15:20:36 -07005105 err = tg3_setup_copper_phy(tp, force_reset);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005106
Matt Carlsonbcb37f62008-11-03 16:52:09 -08005107 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
Matt Carlsonf2096f92011-04-05 14:22:48 +00005108 u32 scale;
Matt Carlsonaa6c91f2007-11-12 21:18:04 -08005109
5110 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
5111 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5112 scale = 65;
5113 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5114 scale = 6;
5115 else
5116 scale = 12;
5117
5118 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
5119 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5120 tw32(GRC_MISC_CFG, val);
5121 }
5122
Matt Carlsonf2096f92011-04-05 14:22:48 +00005123 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5124 (6 << TX_LENGTHS_IPG_SHIFT);
5125 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
5126 val |= tr32(MAC_TX_LENGTHS) &
5127 (TX_LENGTHS_JMB_FRM_LEN_MSK |
5128 TX_LENGTHS_CNT_DWN_VAL_MSK);
5129
Linus Torvalds1da177e2005-04-16 15:20:36 -07005130 if (tp->link_config.active_speed == SPEED_1000 &&
5131 tp->link_config.active_duplex == DUPLEX_HALF)
Matt Carlsonf2096f92011-04-05 14:22:48 +00005132 tw32(MAC_TX_LENGTHS, val |
5133 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005134 else
Matt Carlsonf2096f92011-04-05 14:22:48 +00005135 tw32(MAC_TX_LENGTHS, val |
5136 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005137
Joe Perches63c3a662011-04-26 08:12:10 +00005138 if (!tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005139 if (netif_carrier_ok(tp->dev)) {
5140 tw32(HOSTCC_STAT_COAL_TICKS,
David S. Miller15f98502005-05-18 22:49:26 -07005141 tp->coal.stats_block_coalesce_usecs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005142 } else {
5143 tw32(HOSTCC_STAT_COAL_TICKS, 0);
5144 }
5145 }
5146
Joe Perches63c3a662011-04-26 08:12:10 +00005147 if (tg3_flag(tp, ASPM_WORKAROUND)) {
Matt Carlsonf2096f92011-04-05 14:22:48 +00005148 val = tr32(PCIE_PWR_MGMT_THRESH);
Matt Carlson8ed5d972007-05-07 00:25:49 -07005149 if (!netif_carrier_ok(tp->dev))
5150 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5151 tp->pwrmgmt_thresh;
5152 else
5153 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
5154 tw32(PCIE_PWR_MGMT_THRESH, val);
5155 }
5156
Linus Torvalds1da177e2005-04-16 15:20:36 -07005157 return err;
5158}
5159
Matt Carlson66cfd1b2010-09-30 10:34:30 +00005160static inline int tg3_irq_sync(struct tg3 *tp)
5161{
5162 return tp->irq_sync;
5163}
5164
Matt Carlson97bd8e42011-04-13 11:05:04 +00005165static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5166{
5167 int i;
5168
5169 dst = (u32 *)((u8 *)dst + off);
5170 for (i = 0; i < len; i += sizeof(u32))
5171 *dst++ = tr32(off + i);
5172}
5173
5174static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5175{
5176 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5177 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5178 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5179 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5180 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5181 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5182 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5183 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5184 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5185 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5186 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5187 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5188 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5189 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5190 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5191 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5192 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5193 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5194 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5195
Joe Perches63c3a662011-04-26 08:12:10 +00005196 if (tg3_flag(tp, SUPPORT_MSIX))
Matt Carlson97bd8e42011-04-13 11:05:04 +00005197 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5198
5199 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5200 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5201 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5202 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5203 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5204 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5205 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5206 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5207
Joe Perches63c3a662011-04-26 08:12:10 +00005208 if (!tg3_flag(tp, 5705_PLUS)) {
Matt Carlson97bd8e42011-04-13 11:05:04 +00005209 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5210 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5211 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5212 }
5213
5214 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5215 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5216 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5217 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5218 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5219
Joe Perches63c3a662011-04-26 08:12:10 +00005220 if (tg3_flag(tp, NVRAM))
Matt Carlson97bd8e42011-04-13 11:05:04 +00005221 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5222}
5223
5224static void tg3_dump_state(struct tg3 *tp)
5225{
5226 int i;
5227 u32 *regs;
5228
5229 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5230 if (!regs) {
5231 netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5232 return;
5233 }
5234
Joe Perches63c3a662011-04-26 08:12:10 +00005235 if (tg3_flag(tp, PCI_EXPRESS)) {
Matt Carlson97bd8e42011-04-13 11:05:04 +00005236 /* Read up to but not including private PCI registers */
5237 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5238 regs[i / sizeof(u32)] = tr32(i);
5239 } else
5240 tg3_dump_legacy_regs(tp, regs);
5241
5242 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5243 if (!regs[i + 0] && !regs[i + 1] &&
5244 !regs[i + 2] && !regs[i + 3])
5245 continue;
5246
5247 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5248 i * 4,
5249 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5250 }
5251
5252 kfree(regs);
5253
5254 for (i = 0; i < tp->irq_cnt; i++) {
5255 struct tg3_napi *tnapi = &tp->napi[i];
5256
5257 /* SW status block */
5258 netdev_err(tp->dev,
5259 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5260 i,
5261 tnapi->hw_status->status,
5262 tnapi->hw_status->status_tag,
5263 tnapi->hw_status->rx_jumbo_consumer,
5264 tnapi->hw_status->rx_consumer,
5265 tnapi->hw_status->rx_mini_consumer,
5266 tnapi->hw_status->idx[0].rx_producer,
5267 tnapi->hw_status->idx[0].tx_consumer);
5268
5269 netdev_err(tp->dev,
5270 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
5271 i,
5272 tnapi->last_tag, tnapi->last_irq_tag,
5273 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
5274 tnapi->rx_rcb_ptr,
5275 tnapi->prodring.rx_std_prod_idx,
5276 tnapi->prodring.rx_std_cons_idx,
5277 tnapi->prodring.rx_jmb_prod_idx,
5278 tnapi->prodring.rx_jmb_cons_idx);
5279 }
5280}
5281
Michael Chandf3e6542006-05-26 17:48:07 -07005282/* This is called whenever we suspect that the system chipset is re-
5283 * ordering the sequence of MMIO to the tx send mailbox. The symptom
5284 * is bogus tx completions. We try to recover by setting the
5285 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
5286 * in the workqueue.
5287 */
5288static void tg3_tx_recover(struct tg3 *tp)
5289{
Joe Perches63c3a662011-04-26 08:12:10 +00005290 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
Michael Chandf3e6542006-05-26 17:48:07 -07005291 tp->write32_tx_mbox == tg3_write_indirect_mbox);
5292
Matt Carlson5129c3a2010-04-05 10:19:23 +00005293 netdev_warn(tp->dev,
5294 "The system may be re-ordering memory-mapped I/O "
5295 "cycles to the network device, attempting to recover. "
5296 "Please report the problem to the driver maintainer "
5297 "and include system chipset information.\n");
Michael Chandf3e6542006-05-26 17:48:07 -07005298
5299 spin_lock(&tp->lock);
Joe Perches63c3a662011-04-26 08:12:10 +00005300 tg3_flag_set(tp, TX_RECOVERY_PENDING);
Michael Chandf3e6542006-05-26 17:48:07 -07005301 spin_unlock(&tp->lock);
5302}
5303
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005304static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
Michael Chan1b2a7202006-08-07 21:46:02 -07005305{
Matt Carlsonf65aac12010-08-02 11:26:03 +00005306 /* Tell compiler to fetch tx indices from memory. */
5307 barrier();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005308 return tnapi->tx_pending -
5309 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
Michael Chan1b2a7202006-08-07 21:46:02 -07005310}
5311
Linus Torvalds1da177e2005-04-16 15:20:36 -07005312/* Tigon3 never reports partial packet sends. So we do not
5313 * need special logic to handle SKBs that have not had all
5314 * of their frags sent yet, like SunGEM does.
5315 */
Matt Carlson17375d22009-08-28 14:02:18 +00005316static void tg3_tx(struct tg3_napi *tnapi)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005317{
Matt Carlson17375d22009-08-28 14:02:18 +00005318 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00005319 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005320 u32 sw_idx = tnapi->tx_cons;
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005321 struct netdev_queue *txq;
5322 int index = tnapi - tp->napi;
5323
Joe Perches63c3a662011-04-26 08:12:10 +00005324 if (tg3_flag(tp, ENABLE_TSS))
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005325 index--;
5326
5327 txq = netdev_get_tx_queue(tp->dev, index);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005328
5329 while (sw_idx != hw_idx) {
Matt Carlsondf8944c2011-07-27 14:20:46 +00005330 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07005331 struct sk_buff *skb = ri->skb;
Michael Chandf3e6542006-05-26 17:48:07 -07005332 int i, tx_bug = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005333
Michael Chandf3e6542006-05-26 17:48:07 -07005334 if (unlikely(skb == NULL)) {
5335 tg3_tx_recover(tp);
5336 return;
5337 }
5338
Alexander Duyckf4188d82009-12-02 16:48:38 +00005339 pci_unmap_single(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005340 dma_unmap_addr(ri, mapping),
Alexander Duyckf4188d82009-12-02 16:48:38 +00005341 skb_headlen(skb),
5342 PCI_DMA_TODEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005343
5344 ri->skb = NULL;
5345
Matt Carlsone01ee142011-07-27 14:20:50 +00005346 while (ri->fragmented) {
5347 ri->fragmented = false;
5348 sw_idx = NEXT_TX(sw_idx);
5349 ri = &tnapi->tx_buffers[sw_idx];
5350 }
5351
Linus Torvalds1da177e2005-04-16 15:20:36 -07005352 sw_idx = NEXT_TX(sw_idx);
5353
5354 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005355 ri = &tnapi->tx_buffers[sw_idx];
Michael Chandf3e6542006-05-26 17:48:07 -07005356 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
5357 tx_bug = 1;
Alexander Duyckf4188d82009-12-02 16:48:38 +00005358
5359 pci_unmap_page(tp->pdev,
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005360 dma_unmap_addr(ri, mapping),
Eric Dumazet9e903e02011-10-18 21:00:24 +00005361 skb_frag_size(&skb_shinfo(skb)->frags[i]),
Alexander Duyckf4188d82009-12-02 16:48:38 +00005362 PCI_DMA_TODEVICE);
Matt Carlsone01ee142011-07-27 14:20:50 +00005363
5364 while (ri->fragmented) {
5365 ri->fragmented = false;
5366 sw_idx = NEXT_TX(sw_idx);
5367 ri = &tnapi->tx_buffers[sw_idx];
5368 }
5369
Linus Torvalds1da177e2005-04-16 15:20:36 -07005370 sw_idx = NEXT_TX(sw_idx);
5371 }
5372
David S. Millerf47c11e2005-06-24 20:18:35 -07005373 dev_kfree_skb(skb);
Michael Chandf3e6542006-05-26 17:48:07 -07005374
5375 if (unlikely(tx_bug)) {
5376 tg3_tx_recover(tp);
5377 return;
5378 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005379 }
5380
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005381 tnapi->tx_cons = sw_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005382
Michael Chan1b2a7202006-08-07 21:46:02 -07005383 /* Need to make the tx_cons update visible to tg3_start_xmit()
5384 * before checking for netif_queue_stopped(). Without the
5385 * memory barrier, there is a small possibility that tg3_start_xmit()
5386 * will miss it and cause the queue to be stopped forever.
5387 */
5388 smp_mb();
5389
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005390 if (unlikely(netif_tx_queue_stopped(txq) &&
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005391 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005392 __netif_tx_lock(txq, smp_processor_id());
5393 if (netif_tx_queue_stopped(txq) &&
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005394 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
Matt Carlsonfe5f5782009-09-01 13:09:39 +00005395 netif_tx_wake_queue(txq);
5396 __netif_tx_unlock(txq);
Michael Chan51b91462005-09-01 17:41:28 -07005397 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005398}
5399
Matt Carlson2b2cdb62009-11-13 13:03:48 +00005400static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
5401{
5402 if (!ri->skb)
5403 return;
5404
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005405 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
Matt Carlson2b2cdb62009-11-13 13:03:48 +00005406 map_sz, PCI_DMA_FROMDEVICE);
5407 dev_kfree_skb_any(ri->skb);
5408 ri->skb = NULL;
5409}
5410
Linus Torvalds1da177e2005-04-16 15:20:36 -07005411/* Returns size of skb allocated or < 0 on error.
5412 *
5413 * We only need to fill in the address because the other members
5414 * of the RX descriptor are invariant, see tg3_init_rings.
5415 *
5416 * Note the purposeful assymetry of cpu vs. chip accesses. For
5417 * posting buffers we only dirty the first cache line of the RX
5418 * descriptor (containing the address). Whereas for the RX status
5419 * buffers the cpu only reads the last cacheline of the RX descriptor
5420 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
5421 */
Matt Carlson86b21e52009-11-13 13:03:45 +00005422static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
Matt Carlsona3896162009-11-13 13:03:44 +00005423 u32 opaque_key, u32 dest_idx_unmasked)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005424{
5425 struct tg3_rx_buffer_desc *desc;
Matt Carlsonf94e2902010-10-14 10:37:42 +00005426 struct ring_info *map;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005427 struct sk_buff *skb;
5428 dma_addr_t mapping;
5429 int skb_size, dest_idx;
5430
Linus Torvalds1da177e2005-04-16 15:20:36 -07005431 switch (opaque_key) {
5432 case RXD_OPAQUE_RING_STD:
Matt Carlson2c49a442010-09-30 10:34:35 +00005433 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
Matt Carlson21f581a2009-08-28 14:00:25 +00005434 desc = &tpr->rx_std[dest_idx];
5435 map = &tpr->rx_std_buffers[dest_idx];
Matt Carlson287be122009-08-28 13:58:46 +00005436 skb_size = tp->rx_pkt_map_sz;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005437 break;
5438
5439 case RXD_OPAQUE_RING_JUMBO:
Matt Carlson2c49a442010-09-30 10:34:35 +00005440 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
Matt Carlson79ed5ac2009-08-28 14:00:55 +00005441 desc = &tpr->rx_jmb[dest_idx].std;
Matt Carlson21f581a2009-08-28 14:00:25 +00005442 map = &tpr->rx_jmb_buffers[dest_idx];
Matt Carlson287be122009-08-28 13:58:46 +00005443 skb_size = TG3_RX_JMB_MAP_SZ;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005444 break;
5445
5446 default:
5447 return -EINVAL;
Stephen Hemminger855e1112008-04-16 16:37:28 -07005448 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005449
5450 /* Do not overwrite any of the map or rp information
5451 * until we are sure we can commit to a new buffer.
5452 *
5453 * Callers depend upon this behavior and assume that
5454 * we leave everything unchanged if we fail.
5455 */
Matt Carlson81389f52011-08-31 11:44:49 +00005456 skb = netdev_alloc_skb(tp->dev, skb_size + TG3_RX_OFFSET(tp));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005457 if (skb == NULL)
5458 return -ENOMEM;
5459
Matt Carlson81389f52011-08-31 11:44:49 +00005460 skb_reserve(skb, TG3_RX_OFFSET(tp));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005461
Matt Carlson287be122009-08-28 13:58:46 +00005462 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005463 PCI_DMA_FROMDEVICE);
Matt Carlsona21771d2009-11-02 14:25:31 +00005464 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5465 dev_kfree_skb(skb);
5466 return -EIO;
5467 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005468
5469 map->skb = skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005470 dma_unmap_addr_set(map, mapping, mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005471
Linus Torvalds1da177e2005-04-16 15:20:36 -07005472 desc->addr_hi = ((u64)mapping >> 32);
5473 desc->addr_lo = ((u64)mapping & 0xffffffff);
5474
5475 return skb_size;
5476}
5477
5478/* We only need to move over in the address because the other
5479 * members of the RX descriptor are invariant. See notes above
5480 * tg3_alloc_rx_skb for full details.
5481 */
Matt Carlsona3896162009-11-13 13:03:44 +00005482static void tg3_recycle_rx(struct tg3_napi *tnapi,
5483 struct tg3_rx_prodring_set *dpr,
5484 u32 opaque_key, int src_idx,
5485 u32 dest_idx_unmasked)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005486{
Matt Carlson17375d22009-08-28 14:02:18 +00005487 struct tg3 *tp = tnapi->tp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005488 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
5489 struct ring_info *src_map, *dest_map;
Matt Carlson8fea32b2010-09-15 08:59:58 +00005490 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
Matt Carlsonc6cdf432010-04-05 10:19:26 +00005491 int dest_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005492
5493 switch (opaque_key) {
5494 case RXD_OPAQUE_RING_STD:
Matt Carlson2c49a442010-09-30 10:34:35 +00005495 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
Matt Carlsona3896162009-11-13 13:03:44 +00005496 dest_desc = &dpr->rx_std[dest_idx];
5497 dest_map = &dpr->rx_std_buffers[dest_idx];
5498 src_desc = &spr->rx_std[src_idx];
5499 src_map = &spr->rx_std_buffers[src_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07005500 break;
5501
5502 case RXD_OPAQUE_RING_JUMBO:
Matt Carlson2c49a442010-09-30 10:34:35 +00005503 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
Matt Carlsona3896162009-11-13 13:03:44 +00005504 dest_desc = &dpr->rx_jmb[dest_idx].std;
5505 dest_map = &dpr->rx_jmb_buffers[dest_idx];
5506 src_desc = &spr->rx_jmb[src_idx].std;
5507 src_map = &spr->rx_jmb_buffers[src_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07005508 break;
5509
5510 default:
5511 return;
Stephen Hemminger855e1112008-04-16 16:37:28 -07005512 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005513
5514 dest_map->skb = src_map->skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005515 dma_unmap_addr_set(dest_map, mapping,
5516 dma_unmap_addr(src_map, mapping));
Linus Torvalds1da177e2005-04-16 15:20:36 -07005517 dest_desc->addr_hi = src_desc->addr_hi;
5518 dest_desc->addr_lo = src_desc->addr_lo;
Matt Carlsone92967b2010-02-12 14:47:06 +00005519
5520 /* Ensure that the update to the skb happens after the physical
5521 * addresses have been transferred to the new BD location.
5522 */
5523 smp_wmb();
5524
Linus Torvalds1da177e2005-04-16 15:20:36 -07005525 src_map->skb = NULL;
5526}
5527
Linus Torvalds1da177e2005-04-16 15:20:36 -07005528/* The RX ring scheme is composed of multiple rings which post fresh
5529 * buffers to the chip, and one special ring the chip uses to report
5530 * status back to the host.
5531 *
5532 * The special ring reports the status of received packets to the
5533 * host. The chip does not write into the original descriptor the
5534 * RX buffer was obtained from. The chip simply takes the original
5535 * descriptor as provided by the host, updates the status and length
5536 * field, then writes this into the next status ring entry.
5537 *
5538 * Each ring the host uses to post buffers to the chip is described
5539 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
5540 * it is first placed into the on-chip ram. When the packet's length
5541 * is known, it walks down the TG3_BDINFO entries to select the ring.
5542 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
5543 * which is within the range of the new packet's length is chosen.
5544 *
5545 * The "separate ring for rx status" scheme may sound queer, but it makes
5546 * sense from a cache coherency perspective. If only the host writes
5547 * to the buffer post rings, and only the chip writes to the rx status
5548 * rings, then cache lines never move beyond shared-modified state.
5549 * If both the host and chip were to write into the same ring, cache line
5550 * eviction could occur since both entities want it in an exclusive state.
5551 */
Matt Carlson17375d22009-08-28 14:02:18 +00005552static int tg3_rx(struct tg3_napi *tnapi, int budget)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005553{
Matt Carlson17375d22009-08-28 14:02:18 +00005554 struct tg3 *tp = tnapi->tp;
Michael Chanf92905d2006-06-29 20:14:29 -07005555 u32 work_mask, rx_std_posted = 0;
Matt Carlson43619352009-11-13 13:03:47 +00005556 u32 std_prod_idx, jmb_prod_idx;
Matt Carlson72334482009-08-28 14:03:01 +00005557 u32 sw_idx = tnapi->rx_rcb_ptr;
Michael Chan483ba502005-04-25 15:14:03 -07005558 u16 hw_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005559 int received;
Matt Carlson8fea32b2010-09-15 08:59:58 +00005560 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005561
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00005562 hw_idx = *(tnapi->rx_rcb_prod_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005563 /*
5564 * We need to order the read of hw_idx and the read of
5565 * the opaque cookie.
5566 */
5567 rmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07005568 work_mask = 0;
5569 received = 0;
Matt Carlson43619352009-11-13 13:03:47 +00005570 std_prod_idx = tpr->rx_std_prod_idx;
5571 jmb_prod_idx = tpr->rx_jmb_prod_idx;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005572 while (sw_idx != hw_idx && budget > 0) {
Matt Carlsonafc081f2009-11-13 13:03:43 +00005573 struct ring_info *ri;
Matt Carlson72334482009-08-28 14:03:01 +00005574 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
Linus Torvalds1da177e2005-04-16 15:20:36 -07005575 unsigned int len;
5576 struct sk_buff *skb;
5577 dma_addr_t dma_addr;
5578 u32 opaque_key, desc_idx, *post_ptr;
5579
5580 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
5581 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
5582 if (opaque_key == RXD_OPAQUE_RING_STD) {
Matt Carlson8fea32b2010-09-15 08:59:58 +00005583 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005584 dma_addr = dma_unmap_addr(ri, mapping);
Matt Carlson21f581a2009-08-28 14:00:25 +00005585 skb = ri->skb;
Matt Carlson43619352009-11-13 13:03:47 +00005586 post_ptr = &std_prod_idx;
Michael Chanf92905d2006-06-29 20:14:29 -07005587 rx_std_posted++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005588 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
Matt Carlson8fea32b2010-09-15 08:59:58 +00005589 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00005590 dma_addr = dma_unmap_addr(ri, mapping);
Matt Carlson21f581a2009-08-28 14:00:25 +00005591 skb = ri->skb;
Matt Carlson43619352009-11-13 13:03:47 +00005592 post_ptr = &jmb_prod_idx;
Matt Carlson21f581a2009-08-28 14:00:25 +00005593 } else
Linus Torvalds1da177e2005-04-16 15:20:36 -07005594 goto next_pkt_nopost;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005595
5596 work_mask |= opaque_key;
5597
5598 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
5599 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
5600 drop_it:
Matt Carlsona3896162009-11-13 13:03:44 +00005601 tg3_recycle_rx(tnapi, tpr, opaque_key,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005602 desc_idx, *post_ptr);
5603 drop_it_no_recycle:
5604 /* Other statistics kept track of by card. */
Eric Dumazetb0057c52010-10-10 19:55:52 +00005605 tp->rx_dropped++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005606 goto next_pkt;
5607 }
5608
Matt Carlsonad829262008-11-21 17:16:16 -08005609 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
5610 ETH_FCS_LEN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005611
Matt Carlsond2757fc2010-04-12 06:58:27 +00005612 if (len > TG3_RX_COPY_THRESH(tp)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005613 int skb_size;
5614
Matt Carlson86b21e52009-11-13 13:03:45 +00005615 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
Matt Carlsonafc081f2009-11-13 13:03:43 +00005616 *post_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005617 if (skb_size < 0)
5618 goto drop_it;
5619
Matt Carlson287be122009-08-28 13:58:46 +00005620 pci_unmap_single(tp->pdev, dma_addr, skb_size,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005621 PCI_DMA_FROMDEVICE);
5622
Matt Carlson61e800c2010-02-17 15:16:54 +00005623 /* Ensure that the update to the skb happens
5624 * after the usage of the old DMA mapping.
5625 */
5626 smp_wmb();
5627
5628 ri->skb = NULL;
5629
Linus Torvalds1da177e2005-04-16 15:20:36 -07005630 skb_put(skb, len);
5631 } else {
5632 struct sk_buff *copy_skb;
5633
Matt Carlsona3896162009-11-13 13:03:44 +00005634 tg3_recycle_rx(tnapi, tpr, opaque_key,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005635 desc_idx, *post_ptr);
5636
Matt Carlsonbf933c82011-01-25 15:58:49 +00005637 copy_skb = netdev_alloc_skb(tp->dev, len +
Matt Carlson9dc7a112010-04-12 06:58:28 +00005638 TG3_RAW_IP_ALIGN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005639 if (copy_skb == NULL)
5640 goto drop_it_no_recycle;
5641
Matt Carlsonbf933c82011-01-25 15:58:49 +00005642 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005643 skb_put(copy_skb, len);
5644 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
Arnaldo Carvalho de Melod626f622007-03-27 18:55:52 -03005645 skb_copy_from_linear_data(skb, copy_skb->data, len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005646 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
5647
5648 /* We'll reuse the original ring buffer. */
5649 skb = copy_skb;
5650 }
5651
Michał Mirosławdc668912011-04-07 03:35:07 +00005652 if ((tp->dev->features & NETIF_F_RXCSUM) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07005653 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
5654 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
5655 >> RXD_TCPCSUM_SHIFT) == 0xffff))
5656 skb->ip_summed = CHECKSUM_UNNECESSARY;
5657 else
Eric Dumazetbc8acf22010-09-02 13:07:41 -07005658 skb_checksum_none_assert(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005659
5660 skb->protocol = eth_type_trans(skb, tp->dev);
Matt Carlsonf7b493e2009-02-25 14:21:52 +00005661
5662 if (len > (tp->dev->mtu + ETH_HLEN) &&
5663 skb->protocol != htons(ETH_P_8021Q)) {
5664 dev_kfree_skb(skb);
Eric Dumazetb0057c52010-10-10 19:55:52 +00005665 goto drop_it_no_recycle;
Matt Carlsonf7b493e2009-02-25 14:21:52 +00005666 }
5667
Matt Carlson9dc7a112010-04-12 06:58:28 +00005668 if (desc->type_flags & RXD_FLAG_VLAN &&
Matt Carlsonbf933c82011-01-25 15:58:49 +00005669 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
5670 __vlan_hwaccel_put_tag(skb,
5671 desc->err_vlan & RXD_VLAN_MASK);
Matt Carlson9dc7a112010-04-12 06:58:28 +00005672
Matt Carlsonbf933c82011-01-25 15:58:49 +00005673 napi_gro_receive(&tnapi->napi, skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005674
Linus Torvalds1da177e2005-04-16 15:20:36 -07005675 received++;
5676 budget--;
5677
5678next_pkt:
5679 (*post_ptr)++;
Michael Chanf92905d2006-06-29 20:14:29 -07005680
5681 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
Matt Carlson2c49a442010-09-30 10:34:35 +00005682 tpr->rx_std_prod_idx = std_prod_idx &
5683 tp->rx_std_ring_mask;
Matt Carlson86cfe4f2010-01-12 10:11:37 +00005684 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5685 tpr->rx_std_prod_idx);
Michael Chanf92905d2006-06-29 20:14:29 -07005686 work_mask &= ~RXD_OPAQUE_RING_STD;
5687 rx_std_posted = 0;
5688 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005689next_pkt_nopost:
Michael Chan483ba502005-04-25 15:14:03 -07005690 sw_idx++;
Matt Carlson7cb32cf2010-09-30 10:34:36 +00005691 sw_idx &= tp->rx_ret_ring_mask;
Michael Chan52f6d692005-04-25 15:14:32 -07005692
5693 /* Refresh hw_idx to see if there is new work */
5694 if (sw_idx == hw_idx) {
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00005695 hw_idx = *(tnapi->rx_rcb_prod_idx);
Michael Chan52f6d692005-04-25 15:14:32 -07005696 rmb();
5697 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005698 }
5699
5700 /* ACK the status ring. */
Matt Carlson72334482009-08-28 14:03:01 +00005701 tnapi->rx_rcb_ptr = sw_idx;
5702 tw32_rx_mbox(tnapi->consmbox, sw_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005703
5704 /* Refill RX ring(s). */
Joe Perches63c3a662011-04-26 08:12:10 +00005705 if (!tg3_flag(tp, ENABLE_RSS)) {
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005706 if (work_mask & RXD_OPAQUE_RING_STD) {
Matt Carlson2c49a442010-09-30 10:34:35 +00005707 tpr->rx_std_prod_idx = std_prod_idx &
5708 tp->rx_std_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005709 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5710 tpr->rx_std_prod_idx);
5711 }
5712 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
Matt Carlson2c49a442010-09-30 10:34:35 +00005713 tpr->rx_jmb_prod_idx = jmb_prod_idx &
5714 tp->rx_jmb_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005715 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5716 tpr->rx_jmb_prod_idx);
5717 }
5718 mmiowb();
5719 } else if (work_mask) {
5720 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
5721 * updated before the producer indices can be updated.
5722 */
5723 smp_wmb();
5724
Matt Carlson2c49a442010-09-30 10:34:35 +00005725 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
5726 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005727
Matt Carlsone4af1af2010-02-12 14:47:05 +00005728 if (tnapi != &tp->napi[1])
5729 napi_schedule(&tp->napi[1].napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005730 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005731
5732 return received;
5733}
5734
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005735static void tg3_poll_link(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005736{
Linus Torvalds1da177e2005-04-16 15:20:36 -07005737 /* handle link change and other phy events */
Joe Perches63c3a662011-04-26 08:12:10 +00005738 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005739 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
5740
Linus Torvalds1da177e2005-04-16 15:20:36 -07005741 if (sblk->status & SD_STATUS_LINK_CHG) {
5742 sblk->status = SD_STATUS_UPDATED |
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005743 (sblk->status & ~SD_STATUS_LINK_CHG);
David S. Millerf47c11e2005-06-24 20:18:35 -07005744 spin_lock(&tp->lock);
Joe Perches63c3a662011-04-26 08:12:10 +00005745 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlsondd477002008-05-25 23:45:58 -07005746 tw32_f(MAC_STATUS,
5747 (MAC_STATUS_SYNC_CHANGED |
5748 MAC_STATUS_CFG_CHANGED |
5749 MAC_STATUS_MI_COMPLETION |
5750 MAC_STATUS_LNKSTATE_CHANGED));
5751 udelay(40);
5752 } else
5753 tg3_setup_phy(tp, 0);
David S. Millerf47c11e2005-06-24 20:18:35 -07005754 spin_unlock(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005755 }
5756 }
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005757}
5758
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005759static int tg3_rx_prodring_xfer(struct tg3 *tp,
5760 struct tg3_rx_prodring_set *dpr,
5761 struct tg3_rx_prodring_set *spr)
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005762{
5763 u32 si, di, cpycnt, src_prod_idx;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005764 int i, err = 0;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005765
5766 while (1) {
5767 src_prod_idx = spr->rx_std_prod_idx;
5768
5769 /* Make sure updates to the rx_std_buffers[] entries and the
5770 * standard producer index are seen in the correct order.
5771 */
5772 smp_rmb();
5773
5774 if (spr->rx_std_cons_idx == src_prod_idx)
5775 break;
5776
5777 if (spr->rx_std_cons_idx < src_prod_idx)
5778 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
5779 else
Matt Carlson2c49a442010-09-30 10:34:35 +00005780 cpycnt = tp->rx_std_ring_mask + 1 -
5781 spr->rx_std_cons_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005782
Matt Carlson2c49a442010-09-30 10:34:35 +00005783 cpycnt = min(cpycnt,
5784 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005785
5786 si = spr->rx_std_cons_idx;
5787 di = dpr->rx_std_prod_idx;
5788
Matt Carlsone92967b2010-02-12 14:47:06 +00005789 for (i = di; i < di + cpycnt; i++) {
5790 if (dpr->rx_std_buffers[i].skb) {
5791 cpycnt = i - di;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005792 err = -ENOSPC;
Matt Carlsone92967b2010-02-12 14:47:06 +00005793 break;
5794 }
5795 }
5796
5797 if (!cpycnt)
5798 break;
5799
5800 /* Ensure that updates to the rx_std_buffers ring and the
5801 * shadowed hardware producer ring from tg3_recycle_skb() are
5802 * ordered correctly WRT the skb check above.
5803 */
5804 smp_rmb();
5805
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005806 memcpy(&dpr->rx_std_buffers[di],
5807 &spr->rx_std_buffers[si],
5808 cpycnt * sizeof(struct ring_info));
5809
5810 for (i = 0; i < cpycnt; i++, di++, si++) {
5811 struct tg3_rx_buffer_desc *sbd, *dbd;
5812 sbd = &spr->rx_std[si];
5813 dbd = &dpr->rx_std[di];
5814 dbd->addr_hi = sbd->addr_hi;
5815 dbd->addr_lo = sbd->addr_lo;
5816 }
5817
Matt Carlson2c49a442010-09-30 10:34:35 +00005818 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
5819 tp->rx_std_ring_mask;
5820 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
5821 tp->rx_std_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005822 }
5823
5824 while (1) {
5825 src_prod_idx = spr->rx_jmb_prod_idx;
5826
5827 /* Make sure updates to the rx_jmb_buffers[] entries and
5828 * the jumbo producer index are seen in the correct order.
5829 */
5830 smp_rmb();
5831
5832 if (spr->rx_jmb_cons_idx == src_prod_idx)
5833 break;
5834
5835 if (spr->rx_jmb_cons_idx < src_prod_idx)
5836 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5837 else
Matt Carlson2c49a442010-09-30 10:34:35 +00005838 cpycnt = tp->rx_jmb_ring_mask + 1 -
5839 spr->rx_jmb_cons_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005840
5841 cpycnt = min(cpycnt,
Matt Carlson2c49a442010-09-30 10:34:35 +00005842 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005843
5844 si = spr->rx_jmb_cons_idx;
5845 di = dpr->rx_jmb_prod_idx;
5846
Matt Carlsone92967b2010-02-12 14:47:06 +00005847 for (i = di; i < di + cpycnt; i++) {
5848 if (dpr->rx_jmb_buffers[i].skb) {
5849 cpycnt = i - di;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005850 err = -ENOSPC;
Matt Carlsone92967b2010-02-12 14:47:06 +00005851 break;
5852 }
5853 }
5854
5855 if (!cpycnt)
5856 break;
5857
5858 /* Ensure that updates to the rx_jmb_buffers ring and the
5859 * shadowed hardware producer ring from tg3_recycle_skb() are
5860 * ordered correctly WRT the skb check above.
5861 */
5862 smp_rmb();
5863
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005864 memcpy(&dpr->rx_jmb_buffers[di],
5865 &spr->rx_jmb_buffers[si],
5866 cpycnt * sizeof(struct ring_info));
5867
5868 for (i = 0; i < cpycnt; i++, di++, si++) {
5869 struct tg3_rx_buffer_desc *sbd, *dbd;
5870 sbd = &spr->rx_jmb[si].std;
5871 dbd = &dpr->rx_jmb[di].std;
5872 dbd->addr_hi = sbd->addr_hi;
5873 dbd->addr_lo = sbd->addr_lo;
5874 }
5875
Matt Carlson2c49a442010-09-30 10:34:35 +00005876 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5877 tp->rx_jmb_ring_mask;
5878 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5879 tp->rx_jmb_ring_mask;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005880 }
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005881
5882 return err;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005883}
5884
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005885static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5886{
5887 struct tg3 *tp = tnapi->tp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005888
5889 /* run TX completion thread */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00005890 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
Matt Carlson17375d22009-08-28 14:02:18 +00005891 tg3_tx(tnapi);
Joe Perches63c3a662011-04-26 08:12:10 +00005892 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
Michael Chan4fd7ab52007-10-12 01:39:50 -07005893 return work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005894 }
5895
Linus Torvalds1da177e2005-04-16 15:20:36 -07005896 /* run RX thread, within the bounds set by NAPI.
5897 * All RX "locking" is done by ensuring outside
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005898 * code synchronizes with tg3->napi.poll()
Linus Torvalds1da177e2005-04-16 15:20:36 -07005899 */
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00005900 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
Matt Carlson17375d22009-08-28 14:02:18 +00005901 work_done += tg3_rx(tnapi, budget - work_done);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005902
Joe Perches63c3a662011-04-26 08:12:10 +00005903 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
Matt Carlson8fea32b2010-09-15 08:59:58 +00005904 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005905 int i, err = 0;
Matt Carlsone4af1af2010-02-12 14:47:05 +00005906 u32 std_prod_idx = dpr->rx_std_prod_idx;
5907 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005908
Matt Carlsone4af1af2010-02-12 14:47:05 +00005909 for (i = 1; i < tp->irq_cnt; i++)
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005910 err |= tg3_rx_prodring_xfer(tp, dpr,
Matt Carlson8fea32b2010-09-15 08:59:58 +00005911 &tp->napi[i].prodring);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005912
5913 wmb();
5914
Matt Carlsone4af1af2010-02-12 14:47:05 +00005915 if (std_prod_idx != dpr->rx_std_prod_idx)
5916 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5917 dpr->rx_std_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005918
Matt Carlsone4af1af2010-02-12 14:47:05 +00005919 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5920 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5921 dpr->rx_jmb_prod_idx);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005922
5923 mmiowb();
Matt Carlsonf89f38b2010-02-12 14:47:07 +00005924
5925 if (err)
5926 tw32_f(HOSTCC_MODE, tp->coal_now);
Matt Carlsonb196c7e2009-11-13 13:03:50 +00005927 }
5928
David S. Miller6f535762007-10-11 18:08:29 -07005929 return work_done;
5930}
David S. Millerf7383c22005-05-18 22:50:53 -07005931
Matt Carlsondb219972011-11-04 09:15:03 +00005932static inline void tg3_reset_task_schedule(struct tg3 *tp)
5933{
5934 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
5935 schedule_work(&tp->reset_task);
5936}
5937
5938static inline void tg3_reset_task_cancel(struct tg3 *tp)
5939{
5940 cancel_work_sync(&tp->reset_task);
5941 tg3_flag_clear(tp, RESET_TASK_PENDING);
5942}
5943
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005944static int tg3_poll_msix(struct napi_struct *napi, int budget)
5945{
5946 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5947 struct tg3 *tp = tnapi->tp;
5948 int work_done = 0;
5949 struct tg3_hw_status *sblk = tnapi->hw_status;
5950
5951 while (1) {
5952 work_done = tg3_poll_work(tnapi, work_done, budget);
5953
Joe Perches63c3a662011-04-26 08:12:10 +00005954 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005955 goto tx_recovery;
5956
5957 if (unlikely(work_done >= budget))
5958 break;
5959
Matt Carlsonc6cdf432010-04-05 10:19:26 +00005960 /* tp->last_tag is used in tg3_int_reenable() below
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005961 * to tell the hw how much work has been processed,
5962 * so we must read it before checking for more work.
5963 */
5964 tnapi->last_tag = sblk->status_tag;
5965 tnapi->last_irq_tag = tnapi->last_tag;
5966 rmb();
5967
5968 /* check for RX/TX work to do */
Matt Carlson6d40db72010-04-05 10:19:20 +00005969 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5970 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005971 napi_complete(napi);
5972 /* Reenable interrupts. */
5973 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5974 mmiowb();
5975 break;
5976 }
5977 }
5978
5979 return work_done;
5980
5981tx_recovery:
5982 /* work_done is guaranteed to be less than budget. */
5983 napi_complete(napi);
Matt Carlsondb219972011-11-04 09:15:03 +00005984 tg3_reset_task_schedule(tp);
Matt Carlson35f2d7d2009-11-13 13:03:41 +00005985 return work_done;
5986}
5987
Matt Carlsone64de4e2011-04-13 11:05:05 +00005988static void tg3_process_error(struct tg3 *tp)
5989{
5990 u32 val;
5991 bool real_error = false;
5992
Joe Perches63c3a662011-04-26 08:12:10 +00005993 if (tg3_flag(tp, ERROR_PROCESSED))
Matt Carlsone64de4e2011-04-13 11:05:05 +00005994 return;
5995
5996 /* Check Flow Attention register */
5997 val = tr32(HOSTCC_FLOW_ATTN);
5998 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
5999 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
6000 real_error = true;
6001 }
6002
6003 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
6004 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
6005 real_error = true;
6006 }
6007
6008 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
6009 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
6010 real_error = true;
6011 }
6012
6013 if (!real_error)
6014 return;
6015
6016 tg3_dump_state(tp);
6017
Joe Perches63c3a662011-04-26 08:12:10 +00006018 tg3_flag_set(tp, ERROR_PROCESSED);
Matt Carlsondb219972011-11-04 09:15:03 +00006019 tg3_reset_task_schedule(tp);
Matt Carlsone64de4e2011-04-13 11:05:05 +00006020}
6021
David S. Miller6f535762007-10-11 18:08:29 -07006022static int tg3_poll(struct napi_struct *napi, int budget)
6023{
Matt Carlson8ef04422009-08-28 14:01:37 +00006024 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
6025 struct tg3 *tp = tnapi->tp;
David S. Miller6f535762007-10-11 18:08:29 -07006026 int work_done = 0;
Matt Carlson898a56f2009-08-28 14:02:40 +00006027 struct tg3_hw_status *sblk = tnapi->hw_status;
David S. Miller6f535762007-10-11 18:08:29 -07006028
6029 while (1) {
Matt Carlsone64de4e2011-04-13 11:05:05 +00006030 if (sblk->status & SD_STATUS_ERROR)
6031 tg3_process_error(tp);
6032
Matt Carlson35f2d7d2009-11-13 13:03:41 +00006033 tg3_poll_link(tp);
6034
Matt Carlson17375d22009-08-28 14:02:18 +00006035 work_done = tg3_poll_work(tnapi, work_done, budget);
David S. Miller6f535762007-10-11 18:08:29 -07006036
Joe Perches63c3a662011-04-26 08:12:10 +00006037 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
David S. Miller6f535762007-10-11 18:08:29 -07006038 goto tx_recovery;
6039
6040 if (unlikely(work_done >= budget))
6041 break;
6042
Joe Perches63c3a662011-04-26 08:12:10 +00006043 if (tg3_flag(tp, TAGGED_STATUS)) {
Matt Carlson17375d22009-08-28 14:02:18 +00006044 /* tp->last_tag is used in tg3_int_reenable() below
Michael Chan4fd7ab52007-10-12 01:39:50 -07006045 * to tell the hw how much work has been processed,
6046 * so we must read it before checking for more work.
6047 */
Matt Carlson898a56f2009-08-28 14:02:40 +00006048 tnapi->last_tag = sblk->status_tag;
6049 tnapi->last_irq_tag = tnapi->last_tag;
Michael Chan4fd7ab52007-10-12 01:39:50 -07006050 rmb();
6051 } else
6052 sblk->status &= ~SD_STATUS_UPDATED;
6053
Matt Carlson17375d22009-08-28 14:02:18 +00006054 if (likely(!tg3_has_work(tnapi))) {
Ben Hutchings288379f2009-01-19 16:43:59 -08006055 napi_complete(napi);
Matt Carlson17375d22009-08-28 14:02:18 +00006056 tg3_int_reenable(tnapi);
David S. Miller6f535762007-10-11 18:08:29 -07006057 break;
6058 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006059 }
6060
Stephen Hemmingerbea33482007-10-03 16:41:36 -07006061 return work_done;
David S. Miller6f535762007-10-11 18:08:29 -07006062
6063tx_recovery:
Michael Chan4fd7ab52007-10-12 01:39:50 -07006064 /* work_done is guaranteed to be less than budget. */
Ben Hutchings288379f2009-01-19 16:43:59 -08006065 napi_complete(napi);
Matt Carlsondb219972011-11-04 09:15:03 +00006066 tg3_reset_task_schedule(tp);
Michael Chan4fd7ab52007-10-12 01:39:50 -07006067 return work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006068}
6069
Matt Carlson66cfd1b2010-09-30 10:34:30 +00006070static void tg3_napi_disable(struct tg3 *tp)
6071{
6072 int i;
6073
6074 for (i = tp->irq_cnt - 1; i >= 0; i--)
6075 napi_disable(&tp->napi[i].napi);
6076}
6077
6078static void tg3_napi_enable(struct tg3 *tp)
6079{
6080 int i;
6081
6082 for (i = 0; i < tp->irq_cnt; i++)
6083 napi_enable(&tp->napi[i].napi);
6084}
6085
6086static void tg3_napi_init(struct tg3 *tp)
6087{
6088 int i;
6089
6090 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
6091 for (i = 1; i < tp->irq_cnt; i++)
6092 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
6093}
6094
6095static void tg3_napi_fini(struct tg3 *tp)
6096{
6097 int i;
6098
6099 for (i = 0; i < tp->irq_cnt; i++)
6100 netif_napi_del(&tp->napi[i].napi);
6101}
6102
6103static inline void tg3_netif_stop(struct tg3 *tp)
6104{
6105 tp->dev->trans_start = jiffies; /* prevent tx timeout */
6106 tg3_napi_disable(tp);
6107 netif_tx_disable(tp->dev);
6108}
6109
6110static inline void tg3_netif_start(struct tg3 *tp)
6111{
6112 /* NOTE: unconditional netif_tx_wake_all_queues is only
6113 * appropriate so long as all callers are assured to
6114 * have free tx slots (such as after tg3_init_hw)
6115 */
6116 netif_tx_wake_all_queues(tp->dev);
6117
6118 tg3_napi_enable(tp);
6119 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
6120 tg3_enable_ints(tp);
6121}
6122
David S. Millerf47c11e2005-06-24 20:18:35 -07006123static void tg3_irq_quiesce(struct tg3 *tp)
6124{
Matt Carlson4f125f42009-09-01 12:55:02 +00006125 int i;
6126
David S. Millerf47c11e2005-06-24 20:18:35 -07006127 BUG_ON(tp->irq_sync);
6128
6129 tp->irq_sync = 1;
6130 smp_mb();
6131
Matt Carlson4f125f42009-09-01 12:55:02 +00006132 for (i = 0; i < tp->irq_cnt; i++)
6133 synchronize_irq(tp->napi[i].irq_vec);
David S. Millerf47c11e2005-06-24 20:18:35 -07006134}
6135
David S. Millerf47c11e2005-06-24 20:18:35 -07006136/* Fully shutdown all tg3 driver activity elsewhere in the system.
6137 * If irq_sync is non-zero, then the IRQ handler must be synchronized
6138 * with as well. Most of the time, this is not necessary except when
6139 * shutting down the device.
6140 */
6141static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
6142{
Michael Chan46966542007-07-11 19:47:19 -07006143 spin_lock_bh(&tp->lock);
David S. Millerf47c11e2005-06-24 20:18:35 -07006144 if (irq_sync)
6145 tg3_irq_quiesce(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -07006146}
6147
6148static inline void tg3_full_unlock(struct tg3 *tp)
6149{
David S. Millerf47c11e2005-06-24 20:18:35 -07006150 spin_unlock_bh(&tp->lock);
6151}
6152
Michael Chanfcfa0a32006-03-20 22:28:41 -08006153/* One-shot MSI handler - Chip automatically disables interrupt
6154 * after sending MSI so driver doesn't have to do it.
6155 */
David Howells7d12e782006-10-05 14:55:46 +01006156static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
Michael Chanfcfa0a32006-03-20 22:28:41 -08006157{
Matt Carlson09943a12009-08-28 14:01:57 +00006158 struct tg3_napi *tnapi = dev_id;
6159 struct tg3 *tp = tnapi->tp;
Michael Chanfcfa0a32006-03-20 22:28:41 -08006160
Matt Carlson898a56f2009-08-28 14:02:40 +00006161 prefetch(tnapi->hw_status);
Matt Carlson0c1d0e22009-09-01 13:16:33 +00006162 if (tnapi->rx_rcb)
6163 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Michael Chanfcfa0a32006-03-20 22:28:41 -08006164
6165 if (likely(!tg3_irq_sync(tp)))
Matt Carlson09943a12009-08-28 14:01:57 +00006166 napi_schedule(&tnapi->napi);
Michael Chanfcfa0a32006-03-20 22:28:41 -08006167
6168 return IRQ_HANDLED;
6169}
6170
Michael Chan88b06bc2005-04-21 17:13:25 -07006171/* MSI ISR - No need to check for interrupt sharing and no need to
6172 * flush status block and interrupt mailbox. PCI ordering rules
6173 * guarantee that MSI will arrive after the status block.
6174 */
David Howells7d12e782006-10-05 14:55:46 +01006175static irqreturn_t tg3_msi(int irq, void *dev_id)
Michael Chan88b06bc2005-04-21 17:13:25 -07006176{
Matt Carlson09943a12009-08-28 14:01:57 +00006177 struct tg3_napi *tnapi = dev_id;
6178 struct tg3 *tp = tnapi->tp;
Michael Chan88b06bc2005-04-21 17:13:25 -07006179
Matt Carlson898a56f2009-08-28 14:02:40 +00006180 prefetch(tnapi->hw_status);
Matt Carlson0c1d0e22009-09-01 13:16:33 +00006181 if (tnapi->rx_rcb)
6182 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Michael Chan88b06bc2005-04-21 17:13:25 -07006183 /*
David S. Millerfac9b832005-05-18 22:46:34 -07006184 * Writing any value to intr-mbox-0 clears PCI INTA# and
Michael Chan88b06bc2005-04-21 17:13:25 -07006185 * chip-internal interrupt pending events.
David S. Millerfac9b832005-05-18 22:46:34 -07006186 * Writing non-zero to intr-mbox-0 additional tells the
Michael Chan88b06bc2005-04-21 17:13:25 -07006187 * NIC to stop sending us irqs, engaging "in-intr-handler"
6188 * event coalescing.
6189 */
Matt Carlson5b39de92011-08-31 11:44:50 +00006190 tw32_mailbox(tnapi->int_mbox, 0x00000001);
Michael Chan61487482005-09-05 17:53:19 -07006191 if (likely(!tg3_irq_sync(tp)))
Matt Carlson09943a12009-08-28 14:01:57 +00006192 napi_schedule(&tnapi->napi);
Michael Chan61487482005-09-05 17:53:19 -07006193
Michael Chan88b06bc2005-04-21 17:13:25 -07006194 return IRQ_RETVAL(1);
6195}
6196
David Howells7d12e782006-10-05 14:55:46 +01006197static irqreturn_t tg3_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006198{
Matt Carlson09943a12009-08-28 14:01:57 +00006199 struct tg3_napi *tnapi = dev_id;
6200 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00006201 struct tg3_hw_status *sblk = tnapi->hw_status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006202 unsigned int handled = 1;
6203
Linus Torvalds1da177e2005-04-16 15:20:36 -07006204 /* In INTx mode, it is possible for the interrupt to arrive at
6205 * the CPU before the status block posted prior to the interrupt.
6206 * Reading the PCI State register will confirm whether the
6207 * interrupt is ours and will flush the status block.
6208 */
Michael Chand18edcb2007-03-24 20:57:11 -07006209 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
Joe Perches63c3a662011-04-26 08:12:10 +00006210 if (tg3_flag(tp, CHIP_RESETTING) ||
Michael Chand18edcb2007-03-24 20:57:11 -07006211 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6212 handled = 0;
David S. Millerf47c11e2005-06-24 20:18:35 -07006213 goto out;
David S. Millerfac9b832005-05-18 22:46:34 -07006214 }
Michael Chand18edcb2007-03-24 20:57:11 -07006215 }
6216
6217 /*
6218 * Writing any value to intr-mbox-0 clears PCI INTA# and
6219 * chip-internal interrupt pending events.
6220 * Writing non-zero to intr-mbox-0 additional tells the
6221 * NIC to stop sending us irqs, engaging "in-intr-handler"
6222 * event coalescing.
Michael Chanc04cb342007-05-07 00:26:15 -07006223 *
6224 * Flush the mailbox to de-assert the IRQ immediately to prevent
6225 * spurious interrupts. The flush impacts performance but
6226 * excessive spurious interrupts can be worse in some cases.
Michael Chand18edcb2007-03-24 20:57:11 -07006227 */
Michael Chanc04cb342007-05-07 00:26:15 -07006228 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
Michael Chand18edcb2007-03-24 20:57:11 -07006229 if (tg3_irq_sync(tp))
6230 goto out;
6231 sblk->status &= ~SD_STATUS_UPDATED;
Matt Carlson17375d22009-08-28 14:02:18 +00006232 if (likely(tg3_has_work(tnapi))) {
Matt Carlson72334482009-08-28 14:03:01 +00006233 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Matt Carlson09943a12009-08-28 14:01:57 +00006234 napi_schedule(&tnapi->napi);
Michael Chand18edcb2007-03-24 20:57:11 -07006235 } else {
6236 /* No work, shared interrupt perhaps? re-enable
6237 * interrupts, and flush that PCI write
6238 */
6239 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
6240 0x00000000);
David S. Millerfac9b832005-05-18 22:46:34 -07006241 }
David S. Millerf47c11e2005-06-24 20:18:35 -07006242out:
David S. Millerfac9b832005-05-18 22:46:34 -07006243 return IRQ_RETVAL(handled);
6244}
6245
David Howells7d12e782006-10-05 14:55:46 +01006246static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
David S. Millerfac9b832005-05-18 22:46:34 -07006247{
Matt Carlson09943a12009-08-28 14:01:57 +00006248 struct tg3_napi *tnapi = dev_id;
6249 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00006250 struct tg3_hw_status *sblk = tnapi->hw_status;
David S. Millerfac9b832005-05-18 22:46:34 -07006251 unsigned int handled = 1;
6252
David S. Millerfac9b832005-05-18 22:46:34 -07006253 /* In INTx mode, it is possible for the interrupt to arrive at
6254 * the CPU before the status block posted prior to the interrupt.
6255 * Reading the PCI State register will confirm whether the
6256 * interrupt is ours and will flush the status block.
6257 */
Matt Carlson898a56f2009-08-28 14:02:40 +00006258 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
Joe Perches63c3a662011-04-26 08:12:10 +00006259 if (tg3_flag(tp, CHIP_RESETTING) ||
Michael Chand18edcb2007-03-24 20:57:11 -07006260 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
6261 handled = 0;
David S. Millerf47c11e2005-06-24 20:18:35 -07006262 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006263 }
Michael Chand18edcb2007-03-24 20:57:11 -07006264 }
6265
6266 /*
6267 * writing any value to intr-mbox-0 clears PCI INTA# and
6268 * chip-internal interrupt pending events.
6269 * writing non-zero to intr-mbox-0 additional tells the
6270 * NIC to stop sending us irqs, engaging "in-intr-handler"
6271 * event coalescing.
Michael Chanc04cb342007-05-07 00:26:15 -07006272 *
6273 * Flush the mailbox to de-assert the IRQ immediately to prevent
6274 * spurious interrupts. The flush impacts performance but
6275 * excessive spurious interrupts can be worse in some cases.
Michael Chand18edcb2007-03-24 20:57:11 -07006276 */
Michael Chanc04cb342007-05-07 00:26:15 -07006277 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
Matt Carlson624f8e52009-04-20 06:55:01 +00006278
6279 /*
6280 * In a shared interrupt configuration, sometimes other devices'
6281 * interrupts will scream. We record the current status tag here
6282 * so that the above check can report that the screaming interrupts
6283 * are unhandled. Eventually they will be silenced.
6284 */
Matt Carlson898a56f2009-08-28 14:02:40 +00006285 tnapi->last_irq_tag = sblk->status_tag;
Matt Carlson624f8e52009-04-20 06:55:01 +00006286
Michael Chand18edcb2007-03-24 20:57:11 -07006287 if (tg3_irq_sync(tp))
6288 goto out;
Matt Carlson624f8e52009-04-20 06:55:01 +00006289
Matt Carlson72334482009-08-28 14:03:01 +00006290 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
Matt Carlson624f8e52009-04-20 06:55:01 +00006291
Matt Carlson09943a12009-08-28 14:01:57 +00006292 napi_schedule(&tnapi->napi);
Matt Carlson624f8e52009-04-20 06:55:01 +00006293
David S. Millerf47c11e2005-06-24 20:18:35 -07006294out:
Linus Torvalds1da177e2005-04-16 15:20:36 -07006295 return IRQ_RETVAL(handled);
6296}
6297
Michael Chan79381092005-04-21 17:13:59 -07006298/* ISR for interrupt test */
David Howells7d12e782006-10-05 14:55:46 +01006299static irqreturn_t tg3_test_isr(int irq, void *dev_id)
Michael Chan79381092005-04-21 17:13:59 -07006300{
Matt Carlson09943a12009-08-28 14:01:57 +00006301 struct tg3_napi *tnapi = dev_id;
6302 struct tg3 *tp = tnapi->tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00006303 struct tg3_hw_status *sblk = tnapi->hw_status;
Michael Chan79381092005-04-21 17:13:59 -07006304
Michael Chanf9804dd2005-09-27 12:13:10 -07006305 if ((sblk->status & SD_STATUS_UPDATED) ||
6306 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
Michael Chanb16250e2006-09-27 16:10:14 -07006307 tg3_disable_ints(tp);
Michael Chan79381092005-04-21 17:13:59 -07006308 return IRQ_RETVAL(1);
6309 }
6310 return IRQ_RETVAL(0);
6311}
6312
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07006313static int tg3_init_hw(struct tg3 *, int);
Michael Chan944d9802005-05-29 14:57:48 -07006314static int tg3_halt(struct tg3 *, int, int);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006315
Michael Chanb9ec6c12006-07-25 16:37:27 -07006316/* Restart hardware after configuration changes, self-test, etc.
6317 * Invoked with tp->lock held.
6318 */
6319static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
Eric Dumazet78c61462008-04-24 23:33:06 -07006320 __releases(tp->lock)
6321 __acquires(tp->lock)
Michael Chanb9ec6c12006-07-25 16:37:27 -07006322{
6323 int err;
6324
6325 err = tg3_init_hw(tp, reset_phy);
6326 if (err) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00006327 netdev_err(tp->dev,
6328 "Failed to re-initialize device, aborting\n");
Michael Chanb9ec6c12006-07-25 16:37:27 -07006329 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6330 tg3_full_unlock(tp);
6331 del_timer_sync(&tp->timer);
6332 tp->irq_sync = 0;
Matt Carlsonfed97812009-09-01 13:10:19 +00006333 tg3_napi_enable(tp);
Michael Chanb9ec6c12006-07-25 16:37:27 -07006334 dev_close(tp->dev);
6335 tg3_full_lock(tp, 0);
6336 }
6337 return err;
6338}
6339
Linus Torvalds1da177e2005-04-16 15:20:36 -07006340#ifdef CONFIG_NET_POLL_CONTROLLER
6341static void tg3_poll_controller(struct net_device *dev)
6342{
Matt Carlson4f125f42009-09-01 12:55:02 +00006343 int i;
Michael Chan88b06bc2005-04-21 17:13:25 -07006344 struct tg3 *tp = netdev_priv(dev);
6345
Matt Carlson4f125f42009-09-01 12:55:02 +00006346 for (i = 0; i < tp->irq_cnt; i++)
Louis Rillingfe234f02010-03-09 06:14:41 +00006347 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006348}
6349#endif
6350
David Howellsc4028952006-11-22 14:57:56 +00006351static void tg3_reset_task(struct work_struct *work)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006352{
David Howellsc4028952006-11-22 14:57:56 +00006353 struct tg3 *tp = container_of(work, struct tg3, reset_task);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07006354 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006355 unsigned int restart_timer;
6356
Michael Chan7faa0062006-02-02 17:29:28 -08006357 tg3_full_lock(tp, 0);
Michael Chan7faa0062006-02-02 17:29:28 -08006358
6359 if (!netif_running(tp->dev)) {
Matt Carlsondb219972011-11-04 09:15:03 +00006360 tg3_flag_clear(tp, RESET_TASK_PENDING);
Michael Chan7faa0062006-02-02 17:29:28 -08006361 tg3_full_unlock(tp);
6362 return;
6363 }
6364
6365 tg3_full_unlock(tp);
6366
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07006367 tg3_phy_stop(tp);
6368
Linus Torvalds1da177e2005-04-16 15:20:36 -07006369 tg3_netif_stop(tp);
6370
David S. Millerf47c11e2005-06-24 20:18:35 -07006371 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006372
Joe Perches63c3a662011-04-26 08:12:10 +00006373 restart_timer = tg3_flag(tp, RESTART_TIMER);
6374 tg3_flag_clear(tp, RESTART_TIMER);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006375
Joe Perches63c3a662011-04-26 08:12:10 +00006376 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
Michael Chandf3e6542006-05-26 17:48:07 -07006377 tp->write32_tx_mbox = tg3_write32_tx_mbox;
6378 tp->write32_rx_mbox = tg3_write_flush_reg32;
Joe Perches63c3a662011-04-26 08:12:10 +00006379 tg3_flag_set(tp, MBOX_WRITE_REORDER);
6380 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
Michael Chandf3e6542006-05-26 17:48:07 -07006381 }
6382
Michael Chan944d9802005-05-29 14:57:48 -07006383 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07006384 err = tg3_init_hw(tp, 1);
6385 if (err)
Michael Chanb9ec6c12006-07-25 16:37:27 -07006386 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006387
6388 tg3_netif_start(tp);
6389
Linus Torvalds1da177e2005-04-16 15:20:36 -07006390 if (restart_timer)
6391 mod_timer(&tp->timer, jiffies + 1);
Michael Chan7faa0062006-02-02 17:29:28 -08006392
Michael Chanb9ec6c12006-07-25 16:37:27 -07006393out:
Michael Chan7faa0062006-02-02 17:29:28 -08006394 tg3_full_unlock(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07006395
6396 if (!err)
6397 tg3_phy_start(tp);
Matt Carlsondb219972011-11-04 09:15:03 +00006398
6399 tg3_flag_clear(tp, RESET_TASK_PENDING);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006400}
6401
6402static void tg3_tx_timeout(struct net_device *dev)
6403{
6404 struct tg3 *tp = netdev_priv(dev);
6405
Michael Chanb0408752007-02-13 12:18:30 -08006406 if (netif_msg_tx_err(tp)) {
Joe Perches05dbe002010-02-17 19:44:19 +00006407 netdev_err(dev, "transmit timed out, resetting\n");
Matt Carlson97bd8e42011-04-13 11:05:04 +00006408 tg3_dump_state(tp);
Michael Chanb0408752007-02-13 12:18:30 -08006409 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006410
Matt Carlsondb219972011-11-04 09:15:03 +00006411 tg3_reset_task_schedule(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006412}
6413
Michael Chanc58ec932005-09-17 00:46:27 -07006414/* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
6415static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
6416{
6417 u32 base = (u32) mapping & 0xffffffff;
6418
Eric Dumazet807540b2010-09-23 05:40:09 +00006419 return (base > 0xffffdcc0) && (base + len + 8 < base);
Michael Chanc58ec932005-09-17 00:46:27 -07006420}
6421
Michael Chan72f2afb2006-03-06 19:28:35 -08006422/* Test for DMA addresses > 40-bit */
6423static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
6424 int len)
6425{
6426#if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
Joe Perches63c3a662011-04-26 08:12:10 +00006427 if (tg3_flag(tp, 40BIT_DMA_BUG))
Eric Dumazet807540b2010-09-23 05:40:09 +00006428 return ((u64) mapping + len) > DMA_BIT_MASK(40);
Michael Chan72f2afb2006-03-06 19:28:35 -08006429 return 0;
6430#else
6431 return 0;
6432#endif
6433}
6434
Matt Carlsond1a3b732011-07-27 14:20:51 +00006435static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
Matt Carlson92cd3a12011-07-27 14:20:47 +00006436 dma_addr_t mapping, u32 len, u32 flags,
6437 u32 mss, u32 vlan)
Matt Carlson2ffcc982011-05-19 12:12:44 +00006438{
Matt Carlson92cd3a12011-07-27 14:20:47 +00006439 txbd->addr_hi = ((u64) mapping >> 32);
6440 txbd->addr_lo = ((u64) mapping & 0xffffffff);
6441 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
6442 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
Matt Carlson2ffcc982011-05-19 12:12:44 +00006443}
Linus Torvalds1da177e2005-04-16 15:20:36 -07006444
Matt Carlson84b67b22011-07-27 14:20:52 +00006445static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
Matt Carlsond1a3b732011-07-27 14:20:51 +00006446 dma_addr_t map, u32 len, u32 flags,
6447 u32 mss, u32 vlan)
6448{
6449 struct tg3 *tp = tnapi->tp;
6450 bool hwbug = false;
6451
6452 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
6453 hwbug = 1;
6454
6455 if (tg3_4g_overflow_test(map, len))
6456 hwbug = 1;
6457
6458 if (tg3_40bit_overflow_test(tp, map, len))
6459 hwbug = 1;
6460
Matt Carlsone31aa982011-07-27 14:20:53 +00006461 if (tg3_flag(tp, 4K_FIFO_LIMIT)) {
Matt Carlsonb9e45482011-11-04 09:14:59 +00006462 u32 prvidx = *entry;
Matt Carlsone31aa982011-07-27 14:20:53 +00006463 u32 tmp_flag = flags & ~TXD_FLAG_END;
Matt Carlsonb9e45482011-11-04 09:14:59 +00006464 while (len > TG3_TX_BD_DMA_MAX && *budget) {
Matt Carlsone31aa982011-07-27 14:20:53 +00006465 u32 frag_len = TG3_TX_BD_DMA_MAX;
6466 len -= TG3_TX_BD_DMA_MAX;
6467
Matt Carlsonb9e45482011-11-04 09:14:59 +00006468 /* Avoid the 8byte DMA problem */
6469 if (len <= 8) {
6470 len += TG3_TX_BD_DMA_MAX / 2;
6471 frag_len = TG3_TX_BD_DMA_MAX / 2;
Matt Carlsone31aa982011-07-27 14:20:53 +00006472 }
6473
Matt Carlsonb9e45482011-11-04 09:14:59 +00006474 tnapi->tx_buffers[*entry].fragmented = true;
6475
6476 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6477 frag_len, tmp_flag, mss, vlan);
6478 *budget -= 1;
6479 prvidx = *entry;
6480 *entry = NEXT_TX(*entry);
6481
Matt Carlsone31aa982011-07-27 14:20:53 +00006482 map += frag_len;
6483 }
6484
6485 if (len) {
6486 if (*budget) {
6487 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6488 len, flags, mss, vlan);
Matt Carlsonb9e45482011-11-04 09:14:59 +00006489 *budget -= 1;
Matt Carlsone31aa982011-07-27 14:20:53 +00006490 *entry = NEXT_TX(*entry);
6491 } else {
6492 hwbug = 1;
Matt Carlsonb9e45482011-11-04 09:14:59 +00006493 tnapi->tx_buffers[prvidx].fragmented = false;
Matt Carlsone31aa982011-07-27 14:20:53 +00006494 }
6495 }
6496 } else {
Matt Carlson84b67b22011-07-27 14:20:52 +00006497 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
6498 len, flags, mss, vlan);
Matt Carlsone31aa982011-07-27 14:20:53 +00006499 *entry = NEXT_TX(*entry);
6500 }
Matt Carlsond1a3b732011-07-27 14:20:51 +00006501
6502 return hwbug;
6503}
6504
Matt Carlson0d681b22011-07-27 14:20:49 +00006505static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
Matt Carlson432aa7e2011-05-19 12:12:45 +00006506{
6507 int i;
Matt Carlson0d681b22011-07-27 14:20:49 +00006508 struct sk_buff *skb;
Matt Carlsondf8944c2011-07-27 14:20:46 +00006509 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
Matt Carlson432aa7e2011-05-19 12:12:45 +00006510
Matt Carlson0d681b22011-07-27 14:20:49 +00006511 skb = txb->skb;
6512 txb->skb = NULL;
6513
Matt Carlson432aa7e2011-05-19 12:12:45 +00006514 pci_unmap_single(tnapi->tp->pdev,
6515 dma_unmap_addr(txb, mapping),
6516 skb_headlen(skb),
6517 PCI_DMA_TODEVICE);
Matt Carlsone01ee142011-07-27 14:20:50 +00006518
6519 while (txb->fragmented) {
6520 txb->fragmented = false;
6521 entry = NEXT_TX(entry);
6522 txb = &tnapi->tx_buffers[entry];
6523 }
6524
Matt Carlsonba1142e2011-11-04 09:15:00 +00006525 for (i = 0; i <= last; i++) {
Eric Dumazet9e903e02011-10-18 21:00:24 +00006526 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
Matt Carlson432aa7e2011-05-19 12:12:45 +00006527
6528 entry = NEXT_TX(entry);
6529 txb = &tnapi->tx_buffers[entry];
6530
6531 pci_unmap_page(tnapi->tp->pdev,
6532 dma_unmap_addr(txb, mapping),
Eric Dumazet9e903e02011-10-18 21:00:24 +00006533 skb_frag_size(frag), PCI_DMA_TODEVICE);
Matt Carlsone01ee142011-07-27 14:20:50 +00006534
6535 while (txb->fragmented) {
6536 txb->fragmented = false;
6537 entry = NEXT_TX(entry);
6538 txb = &tnapi->tx_buffers[entry];
6539 }
Matt Carlson432aa7e2011-05-19 12:12:45 +00006540 }
6541}
6542
Michael Chan72f2afb2006-03-06 19:28:35 -08006543/* Workaround 4GB and 40-bit hardware DMA bugs. */
Matt Carlson24f4efd2009-11-13 13:03:35 +00006544static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
David S. Miller1805b2f2011-10-24 18:18:09 -04006545 struct sk_buff **pskb,
Matt Carlson84b67b22011-07-27 14:20:52 +00006546 u32 *entry, u32 *budget,
Matt Carlson92cd3a12011-07-27 14:20:47 +00006547 u32 base_flags, u32 mss, u32 vlan)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006548{
Matt Carlson24f4efd2009-11-13 13:03:35 +00006549 struct tg3 *tp = tnapi->tp;
David S. Miller1805b2f2011-10-24 18:18:09 -04006550 struct sk_buff *new_skb, *skb = *pskb;
Michael Chanc58ec932005-09-17 00:46:27 -07006551 dma_addr_t new_addr = 0;
Matt Carlson432aa7e2011-05-19 12:12:45 +00006552 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006553
Matt Carlson41588ba2008-04-19 18:12:33 -07006554 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
6555 new_skb = skb_copy(skb, GFP_ATOMIC);
6556 else {
6557 int more_headroom = 4 - ((unsigned long)skb->data & 3);
6558
6559 new_skb = skb_copy_expand(skb,
6560 skb_headroom(skb) + more_headroom,
6561 skb_tailroom(skb), GFP_ATOMIC);
6562 }
6563
Linus Torvalds1da177e2005-04-16 15:20:36 -07006564 if (!new_skb) {
Michael Chanc58ec932005-09-17 00:46:27 -07006565 ret = -1;
6566 } else {
6567 /* New SKB is guaranteed to be linear. */
Alexander Duyckf4188d82009-12-02 16:48:38 +00006568 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
6569 PCI_DMA_TODEVICE);
6570 /* Make sure the mapping succeeded */
6571 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
Alexander Duyckf4188d82009-12-02 16:48:38 +00006572 dev_kfree_skb(new_skb);
Michael Chanc58ec932005-09-17 00:46:27 -07006573 ret = -1;
Michael Chanc58ec932005-09-17 00:46:27 -07006574 } else {
Matt Carlsonb9e45482011-11-04 09:14:59 +00006575 u32 save_entry = *entry;
6576
Matt Carlson92cd3a12011-07-27 14:20:47 +00006577 base_flags |= TXD_FLAG_END;
6578
Matt Carlson84b67b22011-07-27 14:20:52 +00006579 tnapi->tx_buffers[*entry].skb = new_skb;
6580 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
Matt Carlson432aa7e2011-05-19 12:12:45 +00006581 mapping, new_addr);
6582
Matt Carlson84b67b22011-07-27 14:20:52 +00006583 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
Matt Carlsond1a3b732011-07-27 14:20:51 +00006584 new_skb->len, base_flags,
6585 mss, vlan)) {
Matt Carlsonba1142e2011-11-04 09:15:00 +00006586 tg3_tx_skb_unmap(tnapi, save_entry, -1);
Matt Carlsond1a3b732011-07-27 14:20:51 +00006587 dev_kfree_skb(new_skb);
6588 ret = -1;
6589 }
Michael Chanc58ec932005-09-17 00:46:27 -07006590 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006591 }
6592
Linus Torvalds1da177e2005-04-16 15:20:36 -07006593 dev_kfree_skb(skb);
David S. Miller1805b2f2011-10-24 18:18:09 -04006594 *pskb = new_skb;
Michael Chanc58ec932005-09-17 00:46:27 -07006595 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006596}
6597
Matt Carlson2ffcc982011-05-19 12:12:44 +00006598static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
Michael Chan52c0fd82006-06-29 20:15:54 -07006599
6600/* Use GSO to workaround a rare TSO bug that may be triggered when the
6601 * TSO header is greater than 80 bytes.
6602 */
6603static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
6604{
6605 struct sk_buff *segs, *nskb;
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006606 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
Michael Chan52c0fd82006-06-29 20:15:54 -07006607
6608 /* Estimate the number of fragments in the worst case */
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006609 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
Michael Chan52c0fd82006-06-29 20:15:54 -07006610 netif_stop_queue(tp->dev);
Matt Carlsonf65aac12010-08-02 11:26:03 +00006611
6612 /* netif_tx_stop_queue() must be done before checking
6613 * checking tx index in tg3_tx_avail() below, because in
6614 * tg3_tx(), we update tx index before checking for
6615 * netif_tx_queue_stopped().
6616 */
6617 smp_mb();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006618 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
Michael Chan7f62ad52007-02-20 23:25:40 -08006619 return NETDEV_TX_BUSY;
6620
6621 netif_wake_queue(tp->dev);
Michael Chan52c0fd82006-06-29 20:15:54 -07006622 }
6623
6624 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
Hirofumi Nakagawa801678c2008-04-29 01:03:09 -07006625 if (IS_ERR(segs))
Michael Chan52c0fd82006-06-29 20:15:54 -07006626 goto tg3_tso_bug_end;
6627
6628 do {
6629 nskb = segs;
6630 segs = segs->next;
6631 nskb->next = NULL;
Matt Carlson2ffcc982011-05-19 12:12:44 +00006632 tg3_start_xmit(nskb, tp->dev);
Michael Chan52c0fd82006-06-29 20:15:54 -07006633 } while (segs);
6634
6635tg3_tso_bug_end:
6636 dev_kfree_skb(skb);
6637
6638 return NETDEV_TX_OK;
6639}
Michael Chan52c0fd82006-06-29 20:15:54 -07006640
Michael Chan5a6f3072006-03-20 22:28:05 -08006641/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
Joe Perches63c3a662011-04-26 08:12:10 +00006642 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
Michael Chan5a6f3072006-03-20 22:28:05 -08006643 */
Matt Carlson2ffcc982011-05-19 12:12:44 +00006644static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
Michael Chan5a6f3072006-03-20 22:28:05 -08006645{
6646 struct tg3 *tp = netdev_priv(dev);
Matt Carlson92cd3a12011-07-27 14:20:47 +00006647 u32 len, entry, base_flags, mss, vlan = 0;
Matt Carlson84b67b22011-07-27 14:20:52 +00006648 u32 budget;
Matt Carlson432aa7e2011-05-19 12:12:45 +00006649 int i = -1, would_hit_hwbug;
David S. Miller90079ce2008-09-11 04:52:51 -07006650 dma_addr_t mapping;
Matt Carlson24f4efd2009-11-13 13:03:35 +00006651 struct tg3_napi *tnapi;
6652 struct netdev_queue *txq;
Matt Carlson432aa7e2011-05-19 12:12:45 +00006653 unsigned int last;
Alexander Duyckf4188d82009-12-02 16:48:38 +00006654
Matt Carlson24f4efd2009-11-13 13:03:35 +00006655 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
6656 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
Joe Perches63c3a662011-04-26 08:12:10 +00006657 if (tg3_flag(tp, ENABLE_TSS))
Matt Carlson24f4efd2009-11-13 13:03:35 +00006658 tnapi++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006659
Matt Carlson84b67b22011-07-27 14:20:52 +00006660 budget = tg3_tx_avail(tnapi);
6661
Michael Chan00b70502006-06-17 21:58:45 -07006662 /* We are running in BH disabled context with netif_tx_lock
Stephen Hemmingerbea33482007-10-03 16:41:36 -07006663 * and TX reclaim runs via tp->napi.poll inside of a software
David S. Millerf47c11e2005-06-24 20:18:35 -07006664 * interrupt. Furthermore, IRQ processing runs lockless so we have
6665 * no IRQ context deadlocks to worry about either. Rejoice!
Linus Torvalds1da177e2005-04-16 15:20:36 -07006666 */
Matt Carlson84b67b22011-07-27 14:20:52 +00006667 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
Matt Carlson24f4efd2009-11-13 13:03:35 +00006668 if (!netif_tx_queue_stopped(txq)) {
6669 netif_tx_stop_queue(txq);
Stephen Hemminger1f064a82005-12-06 17:36:44 -08006670
6671 /* This is a hard error, log it. */
Matt Carlson5129c3a2010-04-05 10:19:23 +00006672 netdev_err(dev,
6673 "BUG! Tx Ring full when queue awake!\n");
Stephen Hemminger1f064a82005-12-06 17:36:44 -08006674 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006675 return NETDEV_TX_BUSY;
6676 }
6677
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006678 entry = tnapi->tx_prod;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006679 base_flags = 0;
Patrick McHardy84fa7932006-08-29 16:44:56 -07006680 if (skb->ip_summed == CHECKSUM_PARTIAL)
Linus Torvalds1da177e2005-04-16 15:20:36 -07006681 base_flags |= TXD_FLAG_TCPUDP_CSUM;
Matt Carlson24f4efd2009-11-13 13:03:35 +00006682
Matt Carlsonbe98da62010-07-11 09:31:46 +00006683 mss = skb_shinfo(skb)->gso_size;
6684 if (mss) {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006685 struct iphdr *iph;
Matt Carlson34195c32010-07-11 09:31:42 +00006686 u32 tcp_opt_len, hdr_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006687
6688 if (skb_header_cloned(skb) &&
Eric Dumazet48855432011-10-24 07:53:03 +00006689 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6690 goto drop;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006691
Matt Carlson34195c32010-07-11 09:31:42 +00006692 iph = ip_hdr(skb);
Arnaldo Carvalho de Meloab6a5bb2007-03-18 17:43:48 -07006693 tcp_opt_len = tcp_optlen(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006694
Matt Carlson02e96082010-09-15 08:59:59 +00006695 if (skb_is_gso_v6(skb)) {
Matt Carlson34195c32010-07-11 09:31:42 +00006696 hdr_len = skb_headlen(skb) - ETH_HLEN;
6697 } else {
6698 u32 ip_tcp_len;
6699
6700 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6701 hdr_len = ip_tcp_len + tcp_opt_len;
6702
6703 iph->check = 0;
6704 iph->tot_len = htons(mss + hdr_len);
6705 }
6706
Michael Chan52c0fd82006-06-29 20:15:54 -07006707 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
Joe Perches63c3a662011-04-26 08:12:10 +00006708 tg3_flag(tp, TSO_BUG))
Matt Carlsonde6f31e2010-04-12 06:58:30 +00006709 return tg3_tso_bug(tp, skb);
Michael Chan52c0fd82006-06-29 20:15:54 -07006710
Linus Torvalds1da177e2005-04-16 15:20:36 -07006711 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
6712 TXD_FLAG_CPU_POST_DMA);
6713
Joe Perches63c3a662011-04-26 08:12:10 +00006714 if (tg3_flag(tp, HW_TSO_1) ||
6715 tg3_flag(tp, HW_TSO_2) ||
6716 tg3_flag(tp, HW_TSO_3)) {
Arnaldo Carvalho de Meloaa8223c2007-04-10 21:04:22 -07006717 tcp_hdr(skb)->check = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006718 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
Arnaldo Carvalho de Meloaa8223c2007-04-10 21:04:22 -07006719 } else
6720 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6721 iph->daddr, 0,
6722 IPPROTO_TCP,
6723 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006724
Joe Perches63c3a662011-04-26 08:12:10 +00006725 if (tg3_flag(tp, HW_TSO_3)) {
Matt Carlson615774f2009-11-13 13:03:39 +00006726 mss |= (hdr_len & 0xc) << 12;
6727 if (hdr_len & 0x10)
6728 base_flags |= 0x00000010;
6729 base_flags |= (hdr_len & 0x3e0) << 5;
Joe Perches63c3a662011-04-26 08:12:10 +00006730 } else if (tg3_flag(tp, HW_TSO_2))
Matt Carlson92c6b8d2009-11-02 14:23:27 +00006731 mss |= hdr_len << 9;
Joe Perches63c3a662011-04-26 08:12:10 +00006732 else if (tg3_flag(tp, HW_TSO_1) ||
Matt Carlson92c6b8d2009-11-02 14:23:27 +00006733 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006734 if (tcp_opt_len || iph->ihl > 5) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07006735 int tsflags;
6736
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006737 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006738 mss |= (tsflags << 11);
6739 }
6740 } else {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006741 if (tcp_opt_len || iph->ihl > 5) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07006742 int tsflags;
6743
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006744 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006745 base_flags |= tsflags << 12;
6746 }
6747 }
6748 }
Matt Carlsonbf933c82011-01-25 15:58:49 +00006749
Matt Carlson93a700a2011-08-31 11:44:54 +00006750 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
6751 !mss && skb->len > VLAN_ETH_FRAME_LEN)
6752 base_flags |= TXD_FLAG_JMB_PKT;
6753
Matt Carlson92cd3a12011-07-27 14:20:47 +00006754 if (vlan_tx_tag_present(skb)) {
6755 base_flags |= TXD_FLAG_VLAN;
6756 vlan = vlan_tx_tag_get(skb);
6757 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006758
Alexander Duyckf4188d82009-12-02 16:48:38 +00006759 len = skb_headlen(skb);
6760
6761 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
Eric Dumazet48855432011-10-24 07:53:03 +00006762 if (pci_dma_mapping_error(tp->pdev, mapping))
6763 goto drop;
6764
David S. Miller90079ce2008-09-11 04:52:51 -07006765
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006766 tnapi->tx_buffers[entry].skb = skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00006767 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006768
6769 would_hit_hwbug = 0;
6770
Joe Perches63c3a662011-04-26 08:12:10 +00006771 if (tg3_flag(tp, 5701_DMA_BUG))
Michael Chanc58ec932005-09-17 00:46:27 -07006772 would_hit_hwbug = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006773
Matt Carlson84b67b22011-07-27 14:20:52 +00006774 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
Matt Carlsond1a3b732011-07-27 14:20:51 +00006775 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
Matt Carlsonba1142e2011-11-04 09:15:00 +00006776 mss, vlan)) {
Matt Carlsond1a3b732011-07-27 14:20:51 +00006777 would_hit_hwbug = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006778 /* Now loop through additional data fragments, and queue them. */
Matt Carlsonba1142e2011-11-04 09:15:00 +00006779 } else if (skb_shinfo(skb)->nr_frags > 0) {
Matt Carlson92cd3a12011-07-27 14:20:47 +00006780 u32 tmp_mss = mss;
6781
6782 if (!tg3_flag(tp, HW_TSO_1) &&
6783 !tg3_flag(tp, HW_TSO_2) &&
6784 !tg3_flag(tp, HW_TSO_3))
6785 tmp_mss = 0;
6786
Linus Torvalds1da177e2005-04-16 15:20:36 -07006787 last = skb_shinfo(skb)->nr_frags - 1;
6788 for (i = 0; i <= last; i++) {
6789 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6790
Eric Dumazet9e903e02011-10-18 21:00:24 +00006791 len = skb_frag_size(frag);
Ian Campbelldc234d02011-08-24 22:28:11 +00006792 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
Ian Campbell5d6bcdf2011-10-06 11:10:48 +01006793 len, DMA_TO_DEVICE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006794
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006795 tnapi->tx_buffers[entry].skb = NULL;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00006796 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
Alexander Duyckf4188d82009-12-02 16:48:38 +00006797 mapping);
Ian Campbell5d6bcdf2011-10-06 11:10:48 +01006798 if (dma_mapping_error(&tp->pdev->dev, mapping))
Alexander Duyckf4188d82009-12-02 16:48:38 +00006799 goto dma_error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006800
Matt Carlsonb9e45482011-11-04 09:14:59 +00006801 if (!budget ||
6802 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
Matt Carlson84b67b22011-07-27 14:20:52 +00006803 len, base_flags |
6804 ((i == last) ? TXD_FLAG_END : 0),
Matt Carlsonb9e45482011-11-04 09:14:59 +00006805 tmp_mss, vlan)) {
Matt Carlson92c6b8d2009-11-02 14:23:27 +00006806 would_hit_hwbug = 1;
Matt Carlsonb9e45482011-11-04 09:14:59 +00006807 break;
6808 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006809 }
6810 }
6811
6812 if (would_hit_hwbug) {
Matt Carlson0d681b22011-07-27 14:20:49 +00006813 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006814
6815 /* If the workaround fails due to memory/mapping
6816 * failure, silently drop this packet.
6817 */
Matt Carlson84b67b22011-07-27 14:20:52 +00006818 entry = tnapi->tx_prod;
6819 budget = tg3_tx_avail(tnapi);
David S. Miller1805b2f2011-10-24 18:18:09 -04006820 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
Matt Carlson84b67b22011-07-27 14:20:52 +00006821 base_flags, mss, vlan))
Eric Dumazet48855432011-10-24 07:53:03 +00006822 goto drop_nofree;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006823 }
6824
Richard Cochrand515b452011-06-19 03:31:41 +00006825 skb_tx_timestamp(skb);
6826
Linus Torvalds1da177e2005-04-16 15:20:36 -07006827 /* Packets are ready, update Tx producer idx local and on card. */
Matt Carlson24f4efd2009-11-13 13:03:35 +00006828 tw32_tx_mbox(tnapi->prodmbox, entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07006829
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006830 tnapi->tx_prod = entry;
6831 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
Matt Carlson24f4efd2009-11-13 13:03:35 +00006832 netif_tx_stop_queue(txq);
Matt Carlsonf65aac12010-08-02 11:26:03 +00006833
6834 /* netif_tx_stop_queue() must be done before checking
6835 * checking tx index in tg3_tx_avail() below, because in
6836 * tg3_tx(), we update tx index before checking for
6837 * netif_tx_queue_stopped().
6838 */
6839 smp_mb();
Matt Carlsonf3f3f272009-08-28 14:03:21 +00006840 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
Matt Carlson24f4efd2009-11-13 13:03:35 +00006841 netif_tx_wake_queue(txq);
Michael Chan51b91462005-09-01 17:41:28 -07006842 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07006843
Eric Dumazetcdd0db02009-05-28 00:00:41 +00006844 mmiowb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07006845 return NETDEV_TX_OK;
Alexander Duyckf4188d82009-12-02 16:48:38 +00006846
6847dma_error:
Matt Carlsonba1142e2011-11-04 09:15:00 +00006848 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
Matt Carlson432aa7e2011-05-19 12:12:45 +00006849 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
Eric Dumazet48855432011-10-24 07:53:03 +00006850drop:
6851 dev_kfree_skb(skb);
6852drop_nofree:
6853 tp->tx_dropped++;
Alexander Duyckf4188d82009-12-02 16:48:38 +00006854 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07006855}
6856
Matt Carlson6e01b202011-08-19 13:58:20 +00006857static void tg3_mac_loopback(struct tg3 *tp, bool enable)
6858{
6859 if (enable) {
6860 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
6861 MAC_MODE_PORT_MODE_MASK);
6862
6863 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
6864
6865 if (!tg3_flag(tp, 5705_PLUS))
6866 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6867
6868 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
6869 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
6870 else
6871 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
6872 } else {
6873 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
6874
6875 if (tg3_flag(tp, 5705_PLUS) ||
6876 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
6877 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
6878 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
6879 }
6880
6881 tw32(MAC_MODE, tp->mac_mode);
6882 udelay(40);
6883}
6884
Matt Carlson941ec902011-08-19 13:58:23 +00006885static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
Matt Carlson5e5a7f32011-08-19 13:58:21 +00006886{
Matt Carlson941ec902011-08-19 13:58:23 +00006887 u32 val, bmcr, mac_mode, ptest = 0;
Matt Carlson5e5a7f32011-08-19 13:58:21 +00006888
6889 tg3_phy_toggle_apd(tp, false);
6890 tg3_phy_toggle_automdix(tp, 0);
6891
Matt Carlson941ec902011-08-19 13:58:23 +00006892 if (extlpbk && tg3_phy_set_extloopbk(tp))
6893 return -EIO;
6894
6895 bmcr = BMCR_FULLDPLX;
Matt Carlson5e5a7f32011-08-19 13:58:21 +00006896 switch (speed) {
6897 case SPEED_10:
6898 break;
6899 case SPEED_100:
6900 bmcr |= BMCR_SPEED100;
6901 break;
6902 case SPEED_1000:
6903 default:
6904 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
6905 speed = SPEED_100;
6906 bmcr |= BMCR_SPEED100;
6907 } else {
6908 speed = SPEED_1000;
6909 bmcr |= BMCR_SPEED1000;
6910 }
6911 }
6912
Matt Carlson941ec902011-08-19 13:58:23 +00006913 if (extlpbk) {
6914 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
6915 tg3_readphy(tp, MII_CTRL1000, &val);
6916 val |= CTL1000_AS_MASTER |
6917 CTL1000_ENABLE_MASTER;
6918 tg3_writephy(tp, MII_CTRL1000, val);
6919 } else {
6920 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
6921 MII_TG3_FET_PTEST_TRIM_2;
6922 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
6923 }
6924 } else
6925 bmcr |= BMCR_LOOPBACK;
6926
Matt Carlson5e5a7f32011-08-19 13:58:21 +00006927 tg3_writephy(tp, MII_BMCR, bmcr);
6928
6929 /* The write needs to be flushed for the FETs */
6930 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
6931 tg3_readphy(tp, MII_BMCR, &bmcr);
6932
6933 udelay(40);
6934
6935 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
6936 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
Matt Carlson941ec902011-08-19 13:58:23 +00006937 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
Matt Carlson5e5a7f32011-08-19 13:58:21 +00006938 MII_TG3_FET_PTEST_FRC_TX_LINK |
6939 MII_TG3_FET_PTEST_FRC_TX_LOCK);
6940
6941 /* The write needs to be flushed for the AC131 */
6942 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
6943 }
6944
6945 /* Reset to prevent losing 1st rx packet intermittently */
6946 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
6947 tg3_flag(tp, 5780_CLASS)) {
6948 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6949 udelay(10);
6950 tw32_f(MAC_RX_MODE, tp->rx_mode);
6951 }
6952
6953 mac_mode = tp->mac_mode &
6954 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
6955 if (speed == SPEED_1000)
6956 mac_mode |= MAC_MODE_PORT_MODE_GMII;
6957 else
6958 mac_mode |= MAC_MODE_PORT_MODE_MII;
6959
6960 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
6961 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
6962
6963 if (masked_phy_id == TG3_PHY_ID_BCM5401)
6964 mac_mode &= ~MAC_MODE_LINK_POLARITY;
6965 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
6966 mac_mode |= MAC_MODE_LINK_POLARITY;
6967
6968 tg3_writephy(tp, MII_TG3_EXT_CTRL,
6969 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
6970 }
6971
6972 tw32(MAC_MODE, mac_mode);
6973 udelay(40);
Matt Carlson941ec902011-08-19 13:58:23 +00006974
6975 return 0;
Matt Carlson5e5a7f32011-08-19 13:58:21 +00006976}
6977
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00006978static void tg3_set_loopback(struct net_device *dev, u32 features)
6979{
6980 struct tg3 *tp = netdev_priv(dev);
6981
6982 if (features & NETIF_F_LOOPBACK) {
6983 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
6984 return;
6985
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00006986 spin_lock_bh(&tp->lock);
Matt Carlson6e01b202011-08-19 13:58:20 +00006987 tg3_mac_loopback(tp, true);
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00006988 netif_carrier_on(tp->dev);
6989 spin_unlock_bh(&tp->lock);
6990 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
6991 } else {
6992 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
6993 return;
6994
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00006995 spin_lock_bh(&tp->lock);
Matt Carlson6e01b202011-08-19 13:58:20 +00006996 tg3_mac_loopback(tp, false);
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00006997 /* Force link status check */
6998 tg3_setup_phy(tp, 1);
6999 spin_unlock_bh(&tp->lock);
7000 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
7001 }
7002}
7003
Michał Mirosławdc668912011-04-07 03:35:07 +00007004static u32 tg3_fix_features(struct net_device *dev, u32 features)
7005{
7006 struct tg3 *tp = netdev_priv(dev);
7007
Joe Perches63c3a662011-04-26 08:12:10 +00007008 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
Michał Mirosławdc668912011-04-07 03:35:07 +00007009 features &= ~NETIF_F_ALL_TSO;
7010
7011 return features;
7012}
7013
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00007014static int tg3_set_features(struct net_device *dev, u32 features)
7015{
7016 u32 changed = dev->features ^ features;
7017
7018 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
7019 tg3_set_loopback(dev, features);
7020
7021 return 0;
7022}
7023
Linus Torvalds1da177e2005-04-16 15:20:36 -07007024static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
7025 int new_mtu)
7026{
7027 dev->mtu = new_mtu;
7028
Michael Chanef7f5ec2005-07-25 12:32:25 -07007029 if (new_mtu > ETH_DATA_LEN) {
Joe Perches63c3a662011-04-26 08:12:10 +00007030 if (tg3_flag(tp, 5780_CLASS)) {
Michał Mirosławdc668912011-04-07 03:35:07 +00007031 netdev_update_features(dev);
Joe Perches63c3a662011-04-26 08:12:10 +00007032 tg3_flag_clear(tp, TSO_CAPABLE);
Matt Carlson859a5882010-04-05 10:19:28 +00007033 } else {
Joe Perches63c3a662011-04-26 08:12:10 +00007034 tg3_flag_set(tp, JUMBO_RING_ENABLE);
Matt Carlson859a5882010-04-05 10:19:28 +00007035 }
Michael Chanef7f5ec2005-07-25 12:32:25 -07007036 } else {
Joe Perches63c3a662011-04-26 08:12:10 +00007037 if (tg3_flag(tp, 5780_CLASS)) {
7038 tg3_flag_set(tp, TSO_CAPABLE);
Michał Mirosławdc668912011-04-07 03:35:07 +00007039 netdev_update_features(dev);
7040 }
Joe Perches63c3a662011-04-26 08:12:10 +00007041 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
Michael Chanef7f5ec2005-07-25 12:32:25 -07007042 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007043}
7044
7045static int tg3_change_mtu(struct net_device *dev, int new_mtu)
7046{
7047 struct tg3 *tp = netdev_priv(dev);
Michael Chanb9ec6c12006-07-25 16:37:27 -07007048 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007049
7050 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
7051 return -EINVAL;
7052
7053 if (!netif_running(dev)) {
7054 /* We'll just catch it later when the
7055 * device is up'd.
7056 */
7057 tg3_set_mtu(dev, tp, new_mtu);
7058 return 0;
7059 }
7060
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07007061 tg3_phy_stop(tp);
7062
Linus Torvalds1da177e2005-04-16 15:20:36 -07007063 tg3_netif_stop(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -07007064
7065 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007066
Michael Chan944d9802005-05-29 14:57:48 -07007067 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007068
7069 tg3_set_mtu(dev, tp, new_mtu);
7070
Michael Chanb9ec6c12006-07-25 16:37:27 -07007071 err = tg3_restart_hw(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007072
Michael Chanb9ec6c12006-07-25 16:37:27 -07007073 if (!err)
7074 tg3_netif_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007075
David S. Millerf47c11e2005-06-24 20:18:35 -07007076 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007077
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07007078 if (!err)
7079 tg3_phy_start(tp);
7080
Michael Chanb9ec6c12006-07-25 16:37:27 -07007081 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007082}
7083
Matt Carlson21f581a2009-08-28 14:00:25 +00007084static void tg3_rx_prodring_free(struct tg3 *tp,
7085 struct tg3_rx_prodring_set *tpr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007086{
Linus Torvalds1da177e2005-04-16 15:20:36 -07007087 int i;
7088
Matt Carlson8fea32b2010-09-15 08:59:58 +00007089 if (tpr != &tp->napi[0].prodring) {
Matt Carlsonb196c7e2009-11-13 13:03:50 +00007090 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
Matt Carlson2c49a442010-09-30 10:34:35 +00007091 i = (i + 1) & tp->rx_std_ring_mask)
Matt Carlsonb196c7e2009-11-13 13:03:50 +00007092 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
7093 tp->rx_pkt_map_sz);
7094
Joe Perches63c3a662011-04-26 08:12:10 +00007095 if (tg3_flag(tp, JUMBO_CAPABLE)) {
Matt Carlsonb196c7e2009-11-13 13:03:50 +00007096 for (i = tpr->rx_jmb_cons_idx;
7097 i != tpr->rx_jmb_prod_idx;
Matt Carlson2c49a442010-09-30 10:34:35 +00007098 i = (i + 1) & tp->rx_jmb_ring_mask) {
Matt Carlsonb196c7e2009-11-13 13:03:50 +00007099 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
7100 TG3_RX_JMB_MAP_SZ);
7101 }
7102 }
7103
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007104 return;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00007105 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007106
Matt Carlson2c49a442010-09-30 10:34:35 +00007107 for (i = 0; i <= tp->rx_std_ring_mask; i++)
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007108 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
7109 tp->rx_pkt_map_sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007110
Joe Perches63c3a662011-04-26 08:12:10 +00007111 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
Matt Carlson2c49a442010-09-30 10:34:35 +00007112 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007113 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
7114 TG3_RX_JMB_MAP_SZ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007115 }
7116}
7117
Matt Carlsonc6cdf432010-04-05 10:19:26 +00007118/* Initialize rx rings for packet processing.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007119 *
7120 * The chip has been shut down and the driver detached from
7121 * the networking, so no interrupts or new tx packets will
7122 * end up in the driver. tp->{tx,}lock are held and thus
7123 * we may not sleep.
7124 */
Matt Carlson21f581a2009-08-28 14:00:25 +00007125static int tg3_rx_prodring_alloc(struct tg3 *tp,
7126 struct tg3_rx_prodring_set *tpr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007127{
Matt Carlson287be122009-08-28 13:58:46 +00007128 u32 i, rx_pkt_dma_sz;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007129
Matt Carlsonb196c7e2009-11-13 13:03:50 +00007130 tpr->rx_std_cons_idx = 0;
7131 tpr->rx_std_prod_idx = 0;
7132 tpr->rx_jmb_cons_idx = 0;
7133 tpr->rx_jmb_prod_idx = 0;
7134
Matt Carlson8fea32b2010-09-15 08:59:58 +00007135 if (tpr != &tp->napi[0].prodring) {
Matt Carlson2c49a442010-09-30 10:34:35 +00007136 memset(&tpr->rx_std_buffers[0], 0,
7137 TG3_RX_STD_BUFF_RING_SIZE(tp));
Matt Carlson48035722010-10-14 10:37:43 +00007138 if (tpr->rx_jmb_buffers)
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007139 memset(&tpr->rx_jmb_buffers[0], 0,
Matt Carlson2c49a442010-09-30 10:34:35 +00007140 TG3_RX_JMB_BUFF_RING_SIZE(tp));
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007141 goto done;
7142 }
7143
Linus Torvalds1da177e2005-04-16 15:20:36 -07007144 /* Zero out all descriptors. */
Matt Carlson2c49a442010-09-30 10:34:35 +00007145 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
Linus Torvalds1da177e2005-04-16 15:20:36 -07007146
Matt Carlson287be122009-08-28 13:58:46 +00007147 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
Joe Perches63c3a662011-04-26 08:12:10 +00007148 if (tg3_flag(tp, 5780_CLASS) &&
Matt Carlson287be122009-08-28 13:58:46 +00007149 tp->dev->mtu > ETH_DATA_LEN)
7150 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
7151 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
Michael Chan7e72aad2005-07-25 12:31:17 -07007152
Linus Torvalds1da177e2005-04-16 15:20:36 -07007153 /* Initialize invariants of the rings, we only set this
7154 * stuff once. This works because the card does not
7155 * write into the rx buffer posting rings.
7156 */
Matt Carlson2c49a442010-09-30 10:34:35 +00007157 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007158 struct tg3_rx_buffer_desc *rxd;
7159
Matt Carlson21f581a2009-08-28 14:00:25 +00007160 rxd = &tpr->rx_std[i];
Matt Carlson287be122009-08-28 13:58:46 +00007161 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007162 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
7163 rxd->opaque = (RXD_OPAQUE_RING_STD |
7164 (i << RXD_OPAQUE_INDEX_SHIFT));
7165 }
7166
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007167 /* Now allocate fresh SKBs for each rx ring. */
7168 for (i = 0; i < tp->rx_pending; i++) {
Matt Carlson86b21e52009-11-13 13:03:45 +00007169 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00007170 netdev_warn(tp->dev,
7171 "Using a smaller RX standard ring. Only "
7172 "%d out of %d buffers were allocated "
7173 "successfully\n", i, tp->rx_pending);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007174 if (i == 0)
7175 goto initfail;
7176 tp->rx_pending = i;
7177 break;
7178 }
7179 }
7180
Joe Perches63c3a662011-04-26 08:12:10 +00007181 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007182 goto done;
7183
Matt Carlson2c49a442010-09-30 10:34:35 +00007184 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007185
Joe Perches63c3a662011-04-26 08:12:10 +00007186 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
Matt Carlson0d86df82010-02-17 15:17:00 +00007187 goto done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007188
Matt Carlson2c49a442010-09-30 10:34:35 +00007189 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
Matt Carlson0d86df82010-02-17 15:17:00 +00007190 struct tg3_rx_buffer_desc *rxd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007191
Matt Carlson0d86df82010-02-17 15:17:00 +00007192 rxd = &tpr->rx_jmb[i].std;
7193 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
7194 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
7195 RXD_FLAG_JUMBO;
7196 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
7197 (i << RXD_OPAQUE_INDEX_SHIFT));
7198 }
7199
7200 for (i = 0; i < tp->rx_jumbo_pending; i++) {
7201 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
Matt Carlson5129c3a2010-04-05 10:19:23 +00007202 netdev_warn(tp->dev,
7203 "Using a smaller RX jumbo ring. Only %d "
7204 "out of %d buffers were allocated "
7205 "successfully\n", i, tp->rx_jumbo_pending);
Matt Carlson0d86df82010-02-17 15:17:00 +00007206 if (i == 0)
7207 goto initfail;
7208 tp->rx_jumbo_pending = i;
7209 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007210 }
7211 }
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007212
7213done:
Michael Chan32d8c572006-07-25 16:38:29 -07007214 return 0;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007215
7216initfail:
Matt Carlson21f581a2009-08-28 14:00:25 +00007217 tg3_rx_prodring_free(tp, tpr);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007218 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007219}
7220
Matt Carlson21f581a2009-08-28 14:00:25 +00007221static void tg3_rx_prodring_fini(struct tg3 *tp,
7222 struct tg3_rx_prodring_set *tpr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007223{
Matt Carlson21f581a2009-08-28 14:00:25 +00007224 kfree(tpr->rx_std_buffers);
7225 tpr->rx_std_buffers = NULL;
7226 kfree(tpr->rx_jmb_buffers);
7227 tpr->rx_jmb_buffers = NULL;
7228 if (tpr->rx_std) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00007229 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
7230 tpr->rx_std, tpr->rx_std_mapping);
Matt Carlson21f581a2009-08-28 14:00:25 +00007231 tpr->rx_std = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007232 }
Matt Carlson21f581a2009-08-28 14:00:25 +00007233 if (tpr->rx_jmb) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00007234 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
7235 tpr->rx_jmb, tpr->rx_jmb_mapping);
Matt Carlson21f581a2009-08-28 14:00:25 +00007236 tpr->rx_jmb = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007237 }
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007238}
7239
Matt Carlson21f581a2009-08-28 14:00:25 +00007240static int tg3_rx_prodring_init(struct tg3 *tp,
7241 struct tg3_rx_prodring_set *tpr)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007242{
Matt Carlson2c49a442010-09-30 10:34:35 +00007243 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
7244 GFP_KERNEL);
Matt Carlson21f581a2009-08-28 14:00:25 +00007245 if (!tpr->rx_std_buffers)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007246 return -ENOMEM;
7247
Matt Carlson4bae65c2010-11-24 08:31:52 +00007248 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
7249 TG3_RX_STD_RING_BYTES(tp),
7250 &tpr->rx_std_mapping,
7251 GFP_KERNEL);
Matt Carlson21f581a2009-08-28 14:00:25 +00007252 if (!tpr->rx_std)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007253 goto err_out;
7254
Joe Perches63c3a662011-04-26 08:12:10 +00007255 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
Matt Carlson2c49a442010-09-30 10:34:35 +00007256 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
Matt Carlson21f581a2009-08-28 14:00:25 +00007257 GFP_KERNEL);
7258 if (!tpr->rx_jmb_buffers)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007259 goto err_out;
7260
Matt Carlson4bae65c2010-11-24 08:31:52 +00007261 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
7262 TG3_RX_JMB_RING_BYTES(tp),
7263 &tpr->rx_jmb_mapping,
7264 GFP_KERNEL);
Matt Carlson21f581a2009-08-28 14:00:25 +00007265 if (!tpr->rx_jmb)
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007266 goto err_out;
7267 }
7268
7269 return 0;
7270
7271err_out:
Matt Carlson21f581a2009-08-28 14:00:25 +00007272 tg3_rx_prodring_fini(tp, tpr);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007273 return -ENOMEM;
7274}
7275
7276/* Free up pending packets in all rx/tx rings.
7277 *
7278 * The chip has been shut down and the driver detached from
7279 * the networking, so no interrupts or new tx packets will
7280 * end up in the driver. tp->{tx,}lock is not held and we are not
7281 * in an interrupt context and thus may sleep.
7282 */
7283static void tg3_free_rings(struct tg3 *tp)
7284{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007285 int i, j;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007286
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007287 for (j = 0; j < tp->irq_cnt; j++) {
7288 struct tg3_napi *tnapi = &tp->napi[j];
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007289
Matt Carlson8fea32b2010-09-15 08:59:58 +00007290 tg3_rx_prodring_free(tp, &tnapi->prodring);
Matt Carlsonb28f6422010-06-05 17:24:32 +00007291
Matt Carlson0c1d0e22009-09-01 13:16:33 +00007292 if (!tnapi->tx_buffers)
7293 continue;
7294
Matt Carlson0d681b22011-07-27 14:20:49 +00007295 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
7296 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007297
Matt Carlson0d681b22011-07-27 14:20:49 +00007298 if (!skb)
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007299 continue;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007300
Matt Carlsonba1142e2011-11-04 09:15:00 +00007301 tg3_tx_skb_unmap(tnapi, i,
7302 skb_shinfo(skb)->nr_frags - 1);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007303
7304 dev_kfree_skb_any(skb);
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007305 }
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007306 }
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007307}
7308
7309/* Initialize tx/rx rings for packet processing.
7310 *
7311 * The chip has been shut down and the driver detached from
7312 * the networking, so no interrupts or new tx packets will
7313 * end up in the driver. tp->{tx,}lock are held and thus
7314 * we may not sleep.
7315 */
7316static int tg3_init_rings(struct tg3 *tp)
7317{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007318 int i;
Matt Carlson72334482009-08-28 14:03:01 +00007319
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007320 /* Free up all the SKBs. */
7321 tg3_free_rings(tp);
7322
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007323 for (i = 0; i < tp->irq_cnt; i++) {
7324 struct tg3_napi *tnapi = &tp->napi[i];
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007325
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007326 tnapi->last_tag = 0;
7327 tnapi->last_irq_tag = 0;
7328 tnapi->hw_status->status = 0;
7329 tnapi->hw_status->status_tag = 0;
7330 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7331
7332 tnapi->tx_prod = 0;
7333 tnapi->tx_cons = 0;
Matt Carlson0c1d0e22009-09-01 13:16:33 +00007334 if (tnapi->tx_ring)
7335 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007336
7337 tnapi->rx_rcb_ptr = 0;
Matt Carlson0c1d0e22009-09-01 13:16:33 +00007338 if (tnapi->rx_rcb)
7339 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007340
Matt Carlson8fea32b2010-09-15 08:59:58 +00007341 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
Matt Carlsone4af1af2010-02-12 14:47:05 +00007342 tg3_free_rings(tp);
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007343 return -ENOMEM;
Matt Carlsone4af1af2010-02-12 14:47:05 +00007344 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007345 }
Matt Carlson72334482009-08-28 14:03:01 +00007346
Matt Carlson2b2cdb62009-11-13 13:03:48 +00007347 return 0;
Matt Carlsoncf7a7292009-08-28 13:59:57 +00007348}
7349
7350/*
7351 * Must not be invoked with interrupt sources disabled and
7352 * the hardware shutdown down.
7353 */
7354static void tg3_free_consistent(struct tg3 *tp)
7355{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007356 int i;
Matt Carlson898a56f2009-08-28 14:02:40 +00007357
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007358 for (i = 0; i < tp->irq_cnt; i++) {
7359 struct tg3_napi *tnapi = &tp->napi[i];
7360
7361 if (tnapi->tx_ring) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00007362 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007363 tnapi->tx_ring, tnapi->tx_desc_mapping);
7364 tnapi->tx_ring = NULL;
7365 }
7366
7367 kfree(tnapi->tx_buffers);
7368 tnapi->tx_buffers = NULL;
7369
7370 if (tnapi->rx_rcb) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00007371 dma_free_coherent(&tp->pdev->dev,
7372 TG3_RX_RCB_RING_BYTES(tp),
7373 tnapi->rx_rcb,
7374 tnapi->rx_rcb_mapping);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007375 tnapi->rx_rcb = NULL;
7376 }
7377
Matt Carlson8fea32b2010-09-15 08:59:58 +00007378 tg3_rx_prodring_fini(tp, &tnapi->prodring);
7379
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007380 if (tnapi->hw_status) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00007381 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
7382 tnapi->hw_status,
7383 tnapi->status_mapping);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007384 tnapi->hw_status = NULL;
7385 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007386 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007387
Linus Torvalds1da177e2005-04-16 15:20:36 -07007388 if (tp->hw_stats) {
Matt Carlson4bae65c2010-11-24 08:31:52 +00007389 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
7390 tp->hw_stats, tp->stats_mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007391 tp->hw_stats = NULL;
7392 }
7393}
7394
7395/*
7396 * Must not be invoked with interrupt sources disabled and
7397 * the hardware shutdown down. Can sleep.
7398 */
7399static int tg3_alloc_consistent(struct tg3 *tp)
7400{
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007401 int i;
Matt Carlson898a56f2009-08-28 14:02:40 +00007402
Matt Carlson4bae65c2010-11-24 08:31:52 +00007403 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
7404 sizeof(struct tg3_hw_stats),
7405 &tp->stats_mapping,
7406 GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007407 if (!tp->hw_stats)
7408 goto err_out;
7409
Linus Torvalds1da177e2005-04-16 15:20:36 -07007410 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7411
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007412 for (i = 0; i < tp->irq_cnt; i++) {
7413 struct tg3_napi *tnapi = &tp->napi[i];
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00007414 struct tg3_hw_status *sblk;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007415
Matt Carlson4bae65c2010-11-24 08:31:52 +00007416 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
7417 TG3_HW_STATUS_SIZE,
7418 &tnapi->status_mapping,
7419 GFP_KERNEL);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007420 if (!tnapi->hw_status)
7421 goto err_out;
7422
7423 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00007424 sblk = tnapi->hw_status;
7425
Matt Carlson8fea32b2010-09-15 08:59:58 +00007426 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
7427 goto err_out;
7428
Matt Carlson19cfaec2009-12-03 08:36:20 +00007429 /* If multivector TSS is enabled, vector 0 does not handle
7430 * tx interrupts. Don't allocate any resources for it.
7431 */
Joe Perches63c3a662011-04-26 08:12:10 +00007432 if ((!i && !tg3_flag(tp, ENABLE_TSS)) ||
7433 (i && tg3_flag(tp, ENABLE_TSS))) {
Matt Carlsondf8944c2011-07-27 14:20:46 +00007434 tnapi->tx_buffers = kzalloc(
7435 sizeof(struct tg3_tx_ring_info) *
7436 TG3_TX_RING_SIZE, GFP_KERNEL);
Matt Carlson19cfaec2009-12-03 08:36:20 +00007437 if (!tnapi->tx_buffers)
7438 goto err_out;
7439
Matt Carlson4bae65c2010-11-24 08:31:52 +00007440 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
7441 TG3_TX_RING_BYTES,
7442 &tnapi->tx_desc_mapping,
7443 GFP_KERNEL);
Matt Carlson19cfaec2009-12-03 08:36:20 +00007444 if (!tnapi->tx_ring)
7445 goto err_out;
7446 }
7447
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00007448 /*
7449 * When RSS is enabled, the status block format changes
7450 * slightly. The "rx_jumbo_consumer", "reserved",
7451 * and "rx_mini_consumer" members get mapped to the
7452 * other three rx return ring producer indexes.
7453 */
7454 switch (i) {
7455 default:
7456 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
7457 break;
7458 case 2:
7459 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
7460 break;
7461 case 3:
7462 tnapi->rx_rcb_prod_idx = &sblk->reserved;
7463 break;
7464 case 4:
7465 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
7466 break;
7467 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007468
Matt Carlson0c1d0e22009-09-01 13:16:33 +00007469 /*
7470 * If multivector RSS is enabled, vector 0 does not handle
7471 * rx or tx interrupts. Don't allocate any resources for it.
7472 */
Joe Perches63c3a662011-04-26 08:12:10 +00007473 if (!i && tg3_flag(tp, ENABLE_RSS))
Matt Carlson0c1d0e22009-09-01 13:16:33 +00007474 continue;
7475
Matt Carlson4bae65c2010-11-24 08:31:52 +00007476 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
7477 TG3_RX_RCB_RING_BYTES(tp),
7478 &tnapi->rx_rcb_mapping,
7479 GFP_KERNEL);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007480 if (!tnapi->rx_rcb)
7481 goto err_out;
7482
7483 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007484 }
7485
Linus Torvalds1da177e2005-04-16 15:20:36 -07007486 return 0;
7487
7488err_out:
7489 tg3_free_consistent(tp);
7490 return -ENOMEM;
7491}
7492
7493#define MAX_WAIT_CNT 1000
7494
7495/* To stop a block, clear the enable bit and poll till it
7496 * clears. tp->lock is held.
7497 */
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007498static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007499{
7500 unsigned int i;
7501 u32 val;
7502
Joe Perches63c3a662011-04-26 08:12:10 +00007503 if (tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07007504 switch (ofs) {
7505 case RCVLSC_MODE:
7506 case DMAC_MODE:
7507 case MBFREE_MODE:
7508 case BUFMGR_MODE:
7509 case MEMARB_MODE:
7510 /* We can't enable/disable these bits of the
7511 * 5705/5750, just say success.
7512 */
7513 return 0;
7514
7515 default:
7516 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07007517 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007518 }
7519
7520 val = tr32(ofs);
7521 val &= ~enable_bit;
7522 tw32_f(ofs, val);
7523
7524 for (i = 0; i < MAX_WAIT_CNT; i++) {
7525 udelay(100);
7526 val = tr32(ofs);
7527 if ((val & enable_bit) == 0)
7528 break;
7529 }
7530
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007531 if (i == MAX_WAIT_CNT && !silent) {
Matt Carlson2445e462010-04-05 10:19:21 +00007532 dev_err(&tp->pdev->dev,
7533 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
7534 ofs, enable_bit);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007535 return -ENODEV;
7536 }
7537
7538 return 0;
7539}
7540
7541/* tp->lock is held. */
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007542static int tg3_abort_hw(struct tg3 *tp, int silent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007543{
7544 int i, err;
7545
7546 tg3_disable_ints(tp);
7547
7548 tp->rx_mode &= ~RX_MODE_ENABLE;
7549 tw32_f(MAC_RX_MODE, tp->rx_mode);
7550 udelay(10);
7551
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007552 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
7553 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
7554 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
7555 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
7556 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
7557 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007558
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007559 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
7560 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
7561 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
7562 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
7563 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
7564 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
7565 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007566
7567 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
7568 tw32_f(MAC_MODE, tp->mac_mode);
7569 udelay(40);
7570
7571 tp->tx_mode &= ~TX_MODE_ENABLE;
7572 tw32_f(MAC_TX_MODE, tp->tx_mode);
7573
7574 for (i = 0; i < MAX_WAIT_CNT; i++) {
7575 udelay(100);
7576 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
7577 break;
7578 }
7579 if (i >= MAX_WAIT_CNT) {
Matt Carlsonab96b242010-04-05 10:19:22 +00007580 dev_err(&tp->pdev->dev,
7581 "%s timed out, TX_MODE_ENABLE will not clear "
7582 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
Michael Chane6de8ad2005-05-05 14:42:41 -07007583 err |= -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007584 }
7585
Michael Chane6de8ad2005-05-05 14:42:41 -07007586 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007587 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
7588 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007589
7590 tw32(FTQ_RESET, 0xffffffff);
7591 tw32(FTQ_RESET, 0x00000000);
7592
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007593 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
7594 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007595
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007596 for (i = 0; i < tp->irq_cnt; i++) {
7597 struct tg3_napi *tnapi = &tp->napi[i];
7598 if (tnapi->hw_status)
7599 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7600 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07007601 if (tp->hw_stats)
7602 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
7603
Linus Torvalds1da177e2005-04-16 15:20:36 -07007604 return err;
7605}
7606
Michael Chanee6a99b2007-07-18 21:49:10 -07007607/* Save PCI command register before chip reset */
7608static void tg3_save_pci_state(struct tg3 *tp)
7609{
Matt Carlson8a6eac92007-10-21 16:17:55 -07007610 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
Michael Chanee6a99b2007-07-18 21:49:10 -07007611}
7612
7613/* Restore PCI state after chip reset */
7614static void tg3_restore_pci_state(struct tg3 *tp)
7615{
7616 u32 val;
7617
7618 /* Re-enable indirect register accesses. */
7619 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
7620 tp->misc_host_ctrl);
7621
7622 /* Set MAX PCI retry to zero. */
7623 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
7624 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
Joe Perches63c3a662011-04-26 08:12:10 +00007625 tg3_flag(tp, PCIX_MODE))
Michael Chanee6a99b2007-07-18 21:49:10 -07007626 val |= PCISTATE_RETRY_SAME_DMA;
Matt Carlson0d3031d2007-10-10 18:02:43 -07007627 /* Allow reads and writes to the APE register and memory space. */
Joe Perches63c3a662011-04-26 08:12:10 +00007628 if (tg3_flag(tp, ENABLE_APE))
Matt Carlson0d3031d2007-10-10 18:02:43 -07007629 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
Matt Carlsonf92d9dc12010-06-05 17:24:30 +00007630 PCISTATE_ALLOW_APE_SHMEM_WR |
7631 PCISTATE_ALLOW_APE_PSPACE_WR;
Michael Chanee6a99b2007-07-18 21:49:10 -07007632 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
7633
Matt Carlson8a6eac92007-10-21 16:17:55 -07007634 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
Michael Chanee6a99b2007-07-18 21:49:10 -07007635
Matt Carlsonfcb389d2008-11-03 16:55:44 -08007636 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
Joe Perches63c3a662011-04-26 08:12:10 +00007637 if (tg3_flag(tp, PCI_EXPRESS))
Matt Carlsoncf790032010-11-24 08:31:48 +00007638 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
Matt Carlsonfcb389d2008-11-03 16:55:44 -08007639 else {
7640 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
7641 tp->pci_cacheline_sz);
7642 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7643 tp->pci_lat_timer);
7644 }
Michael Chan114342f2007-10-15 02:12:26 -07007645 }
Matt Carlson5f5c51e2007-11-12 21:19:37 -08007646
Michael Chanee6a99b2007-07-18 21:49:10 -07007647 /* Make sure PCI-X relaxed ordering bit is clear. */
Joe Perches63c3a662011-04-26 08:12:10 +00007648 if (tg3_flag(tp, PCIX_MODE)) {
Matt Carlson9974a352007-10-07 23:27:28 -07007649 u16 pcix_cmd;
7650
7651 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7652 &pcix_cmd);
7653 pcix_cmd &= ~PCI_X_CMD_ERO;
7654 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7655 pcix_cmd);
7656 }
Michael Chanee6a99b2007-07-18 21:49:10 -07007657
Joe Perches63c3a662011-04-26 08:12:10 +00007658 if (tg3_flag(tp, 5780_CLASS)) {
Michael Chanee6a99b2007-07-18 21:49:10 -07007659
7660 /* Chip reset on 5780 will reset MSI enable bit,
7661 * so need to restore it.
7662 */
Joe Perches63c3a662011-04-26 08:12:10 +00007663 if (tg3_flag(tp, USING_MSI)) {
Michael Chanee6a99b2007-07-18 21:49:10 -07007664 u16 ctrl;
7665
7666 pci_read_config_word(tp->pdev,
7667 tp->msi_cap + PCI_MSI_FLAGS,
7668 &ctrl);
7669 pci_write_config_word(tp->pdev,
7670 tp->msi_cap + PCI_MSI_FLAGS,
7671 ctrl | PCI_MSI_FLAGS_ENABLE);
7672 val = tr32(MSGINT_MODE);
7673 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7674 }
7675 }
7676}
7677
Linus Torvalds1da177e2005-04-16 15:20:36 -07007678/* tp->lock is held. */
7679static int tg3_chip_reset(struct tg3 *tp)
7680{
7681 u32 val;
Michael Chan1ee582d2005-08-09 20:16:46 -07007682 void (*write_op)(struct tg3 *, u32, u32);
Matt Carlson4f125f42009-09-01 12:55:02 +00007683 int i, err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007684
David S. Millerf49639e2006-06-09 11:58:36 -07007685 tg3_nvram_lock(tp);
7686
Matt Carlson77b483f2008-08-15 14:07:24 -07007687 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7688
David S. Millerf49639e2006-06-09 11:58:36 -07007689 /* No matching tg3_nvram_unlock() after this because
7690 * chip reset below will undo the nvram lock.
7691 */
7692 tp->nvram_lock_cnt = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007693
Michael Chanee6a99b2007-07-18 21:49:10 -07007694 /* GRC_MISC_CFG core clock reset will clear the memory
7695 * enable bit in PCI register 4 and the MSI enable bit
7696 * on some chips, so we save relevant registers here.
7697 */
7698 tg3_save_pci_state(tp);
7699
Michael Chand9ab5ad2006-03-20 22:27:35 -08007700 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
Joe Perches63c3a662011-04-26 08:12:10 +00007701 tg3_flag(tp, 5755_PLUS))
Michael Chand9ab5ad2006-03-20 22:27:35 -08007702 tw32(GRC_FASTBOOT_PC, 0);
7703
Linus Torvalds1da177e2005-04-16 15:20:36 -07007704 /*
7705 * We must avoid the readl() that normally takes place.
7706 * It locks machines, causes machine checks, and other
7707 * fun things. So, temporarily disable the 5701
7708 * hardware workaround, while we do the reset.
7709 */
Michael Chan1ee582d2005-08-09 20:16:46 -07007710 write_op = tp->write32;
7711 if (write_op == tg3_write_flush_reg32)
7712 tp->write32 = tg3_write32;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007713
Michael Chand18edcb2007-03-24 20:57:11 -07007714 /* Prevent the irq handler from reading or writing PCI registers
7715 * during chip reset when the memory enable bit in the PCI command
7716 * register may be cleared. The chip does not generate interrupt
7717 * at this time, but the irq handler may still be called due to irq
7718 * sharing or irqpoll.
7719 */
Joe Perches63c3a662011-04-26 08:12:10 +00007720 tg3_flag_set(tp, CHIP_RESETTING);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00007721 for (i = 0; i < tp->irq_cnt; i++) {
7722 struct tg3_napi *tnapi = &tp->napi[i];
7723 if (tnapi->hw_status) {
7724 tnapi->hw_status->status = 0;
7725 tnapi->hw_status->status_tag = 0;
7726 }
7727 tnapi->last_tag = 0;
7728 tnapi->last_irq_tag = 0;
Michael Chanb8fa2f32007-04-06 17:35:37 -07007729 }
Michael Chand18edcb2007-03-24 20:57:11 -07007730 smp_mb();
Matt Carlson4f125f42009-09-01 12:55:02 +00007731
7732 for (i = 0; i < tp->irq_cnt; i++)
7733 synchronize_irq(tp->napi[i].irq_vec);
Michael Chand18edcb2007-03-24 20:57:11 -07007734
Matt Carlson255ca312009-08-25 10:07:27 +00007735 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7736 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7737 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7738 }
7739
Linus Torvalds1da177e2005-04-16 15:20:36 -07007740 /* do the reset */
7741 val = GRC_MISC_CFG_CORECLK_RESET;
7742
Joe Perches63c3a662011-04-26 08:12:10 +00007743 if (tg3_flag(tp, PCI_EXPRESS)) {
Matt Carlson88075d92010-08-02 11:25:58 +00007744 /* Force PCIe 1.0a mode */
7745 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Joe Perches63c3a662011-04-26 08:12:10 +00007746 !tg3_flag(tp, 57765_PLUS) &&
Matt Carlson88075d92010-08-02 11:25:58 +00007747 tr32(TG3_PCIE_PHY_TSTCTL) ==
7748 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7749 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7750
Linus Torvalds1da177e2005-04-16 15:20:36 -07007751 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7752 tw32(GRC_MISC_CFG, (1 << 29));
7753 val |= (1 << 29);
7754 }
7755 }
7756
Michael Chanb5d37722006-09-27 16:06:21 -07007757 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7758 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7759 tw32(GRC_VCPU_EXT_CTRL,
7760 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7761 }
7762
Matt Carlsonf37500d2010-08-02 11:25:59 +00007763 /* Manage gphy power for all CPMU absent PCIe devices. */
Joe Perches63c3a662011-04-26 08:12:10 +00007764 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
Linus Torvalds1da177e2005-04-16 15:20:36 -07007765 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
Matt Carlsonf37500d2010-08-02 11:25:59 +00007766
Linus Torvalds1da177e2005-04-16 15:20:36 -07007767 tw32(GRC_MISC_CFG, val);
7768
Michael Chan1ee582d2005-08-09 20:16:46 -07007769 /* restore 5701 hardware bug workaround write method */
7770 tp->write32 = write_op;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007771
7772 /* Unfortunately, we have to delay before the PCI read back.
7773 * Some 575X chips even will not respond to a PCI cfg access
7774 * when the reset command is given to the chip.
7775 *
7776 * How do these hardware designers expect things to work
7777 * properly if the PCI write is posted for a long period
7778 * of time? It is always necessary to have some method by
7779 * which a register read back can occur to push the write
7780 * out which does the reset.
7781 *
7782 * For most tg3 variants the trick below was working.
7783 * Ho hum...
7784 */
7785 udelay(120);
7786
7787 /* Flush PCI posted writes. The normal MMIO registers
7788 * are inaccessible at this time so this is the only
7789 * way to make this reliably (actually, this is no longer
7790 * the case, see above). I tried to use indirect
7791 * register read/write but this upset some 5701 variants.
7792 */
7793 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7794
7795 udelay(120);
7796
Jon Mason708ebb32011-06-27 12:56:50 +00007797 if (tg3_flag(tp, PCI_EXPRESS) && pci_pcie_cap(tp->pdev)) {
Matt Carlsone7126992009-08-25 10:08:16 +00007798 u16 val16;
7799
Linus Torvalds1da177e2005-04-16 15:20:36 -07007800 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7801 int i;
7802 u32 cfg_val;
7803
7804 /* Wait for link training to complete. */
7805 for (i = 0; i < 5000; i++)
7806 udelay(100);
7807
7808 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7809 pci_write_config_dword(tp->pdev, 0xc4,
7810 cfg_val | (1 << 15));
7811 }
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007812
Matt Carlsone7126992009-08-25 10:08:16 +00007813 /* Clear the "no snoop" and "relaxed ordering" bits. */
7814 pci_read_config_word(tp->pdev,
Jon Mason708ebb32011-06-27 12:56:50 +00007815 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
Matt Carlsone7126992009-08-25 10:08:16 +00007816 &val16);
7817 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7818 PCI_EXP_DEVCTL_NOSNOOP_EN);
7819 /*
7820 * Older PCIe devices only support the 128 byte
7821 * MPS setting. Enforce the restriction.
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007822 */
Joe Perches63c3a662011-04-26 08:12:10 +00007823 if (!tg3_flag(tp, CPMU_PRESENT))
Matt Carlsone7126992009-08-25 10:08:16 +00007824 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007825 pci_write_config_word(tp->pdev,
Jon Mason708ebb32011-06-27 12:56:50 +00007826 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVCTL,
Matt Carlsone7126992009-08-25 10:08:16 +00007827 val16);
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007828
Matt Carlsoncf790032010-11-24 08:31:48 +00007829 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007830
7831 /* Clear error status */
7832 pci_write_config_word(tp->pdev,
Jon Mason708ebb32011-06-27 12:56:50 +00007833 pci_pcie_cap(tp->pdev) + PCI_EXP_DEVSTA,
Matt Carlson5e7dfd02008-11-21 17:18:16 -08007834 PCI_EXP_DEVSTA_CED |
7835 PCI_EXP_DEVSTA_NFED |
7836 PCI_EXP_DEVSTA_FED |
7837 PCI_EXP_DEVSTA_URD);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007838 }
7839
Michael Chanee6a99b2007-07-18 21:49:10 -07007840 tg3_restore_pci_state(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007841
Joe Perches63c3a662011-04-26 08:12:10 +00007842 tg3_flag_clear(tp, CHIP_RESETTING);
7843 tg3_flag_clear(tp, ERROR_PROCESSED);
Michael Chand18edcb2007-03-24 20:57:11 -07007844
Michael Chanee6a99b2007-07-18 21:49:10 -07007845 val = 0;
Joe Perches63c3a662011-04-26 08:12:10 +00007846 if (tg3_flag(tp, 5780_CLASS))
Michael Chan4cf78e42005-07-25 12:29:19 -07007847 val = tr32(MEMARB_MODE);
Michael Chanee6a99b2007-07-18 21:49:10 -07007848 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007849
7850 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7851 tg3_stop_fw(tp);
7852 tw32(0x5000, 0x400);
7853 }
7854
7855 tw32(GRC_MODE, tp->grc_mode);
7856
7857 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
Andy Gospodarekab0049b2007-09-06 20:42:14 +01007858 val = tr32(0xc4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007859
7860 tw32(0xc4, val | (1 << 15));
7861 }
7862
7863 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7864 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7865 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7866 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7867 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7868 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7869 }
7870
Matt Carlsonf07e9af2010-08-02 11:26:07 +00007871 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Matt Carlson9e975cc2011-07-20 10:20:50 +00007872 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
Matt Carlsond2394e6b2010-11-24 08:31:47 +00007873 val = tp->mac_mode;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00007874 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
Matt Carlson9e975cc2011-07-20 10:20:50 +00007875 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
Matt Carlsond2394e6b2010-11-24 08:31:47 +00007876 val = tp->mac_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007877 } else
Matt Carlsond2394e6b2010-11-24 08:31:47 +00007878 val = 0;
7879
7880 tw32_f(MAC_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007881 udelay(40);
7882
Matt Carlson77b483f2008-08-15 14:07:24 -07007883 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7884
Michael Chan7a6f4362006-09-27 16:03:31 -07007885 err = tg3_poll_fw(tp);
7886 if (err)
7887 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007888
Matt Carlson0a9140c2009-08-28 12:27:50 +00007889 tg3_mdio_start(tp);
7890
Joe Perches63c3a662011-04-26 08:12:10 +00007891 if (tg3_flag(tp, PCI_EXPRESS) &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00007892 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7893 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Joe Perches63c3a662011-04-26 08:12:10 +00007894 !tg3_flag(tp, 57765_PLUS)) {
Andy Gospodarekab0049b2007-09-06 20:42:14 +01007895 val = tr32(0x7c00);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007896
7897 tw32(0x7c00, val | (1 << 25));
7898 }
7899
Matt Carlsond78b59f2011-04-05 14:22:46 +00007900 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
7901 val = tr32(TG3_CPMU_CLCK_ORIDE);
7902 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
7903 }
7904
Linus Torvalds1da177e2005-04-16 15:20:36 -07007905 /* Reprobe ASF enable state. */
Joe Perches63c3a662011-04-26 08:12:10 +00007906 tg3_flag_clear(tp, ENABLE_ASF);
7907 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007908 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7909 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7910 u32 nic_cfg;
7911
7912 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7913 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
Joe Perches63c3a662011-04-26 08:12:10 +00007914 tg3_flag_set(tp, ENABLE_ASF);
Matt Carlson4ba526c2008-08-15 14:10:04 -07007915 tp->last_event_jiffies = jiffies;
Joe Perches63c3a662011-04-26 08:12:10 +00007916 if (tg3_flag(tp, 5750_PLUS))
7917 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007918 }
7919 }
7920
7921 return 0;
7922}
7923
7924/* tp->lock is held. */
Michael Chan944d9802005-05-29 14:57:48 -07007925static int tg3_halt(struct tg3 *tp, int kind, int silent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007926{
7927 int err;
7928
7929 tg3_stop_fw(tp);
7930
Michael Chan944d9802005-05-29 14:57:48 -07007931 tg3_write_sig_pre_reset(tp, kind);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007932
David S. Millerb3b7d6b2005-05-05 14:40:20 -07007933 tg3_abort_hw(tp, silent);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007934 err = tg3_chip_reset(tp);
7935
Matt Carlsondaba2a62009-04-20 06:58:52 +00007936 __tg3_set_mac_addr(tp, 0);
7937
Michael Chan944d9802005-05-29 14:57:48 -07007938 tg3_write_sig_legacy(tp, kind);
7939 tg3_write_sig_post_reset(tp, kind);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007940
7941 if (err)
7942 return err;
7943
7944 return 0;
7945}
7946
Linus Torvalds1da177e2005-04-16 15:20:36 -07007947static int tg3_set_mac_addr(struct net_device *dev, void *p)
7948{
7949 struct tg3 *tp = netdev_priv(dev);
7950 struct sockaddr *addr = p;
Michael Chan986e0ae2007-05-05 12:10:20 -07007951 int err = 0, skip_mac_1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007952
Michael Chanf9804dd2005-09-27 12:13:10 -07007953 if (!is_valid_ether_addr(addr->sa_data))
7954 return -EINVAL;
7955
Linus Torvalds1da177e2005-04-16 15:20:36 -07007956 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7957
Michael Chane75f7c92006-03-20 21:33:26 -08007958 if (!netif_running(dev))
7959 return 0;
7960
Joe Perches63c3a662011-04-26 08:12:10 +00007961 if (tg3_flag(tp, ENABLE_ASF)) {
Michael Chan986e0ae2007-05-05 12:10:20 -07007962 u32 addr0_high, addr0_low, addr1_high, addr1_low;
Michael Chan58712ef2006-04-29 18:58:01 -07007963
Michael Chan986e0ae2007-05-05 12:10:20 -07007964 addr0_high = tr32(MAC_ADDR_0_HIGH);
7965 addr0_low = tr32(MAC_ADDR_0_LOW);
7966 addr1_high = tr32(MAC_ADDR_1_HIGH);
7967 addr1_low = tr32(MAC_ADDR_1_LOW);
7968
7969 /* Skip MAC addr 1 if ASF is using it. */
7970 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7971 !(addr1_high == 0 && addr1_low == 0))
7972 skip_mac_1 = 1;
Michael Chan58712ef2006-04-29 18:58:01 -07007973 }
Michael Chan986e0ae2007-05-05 12:10:20 -07007974 spin_lock_bh(&tp->lock);
7975 __tg3_set_mac_addr(tp, skip_mac_1);
7976 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07007977
Michael Chanb9ec6c12006-07-25 16:37:27 -07007978 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07007979}
7980
7981/* tp->lock is held. */
7982static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7983 dma_addr_t mapping, u32 maxlen_flags,
7984 u32 nic_addr)
7985{
7986 tg3_write_mem(tp,
7987 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7988 ((u64) mapping >> 32));
7989 tg3_write_mem(tp,
7990 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7991 ((u64) mapping & 0xffffffff));
7992 tg3_write_mem(tp,
7993 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7994 maxlen_flags);
7995
Joe Perches63c3a662011-04-26 08:12:10 +00007996 if (!tg3_flag(tp, 5705_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07007997 tg3_write_mem(tp,
7998 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7999 nic_addr);
8000}
8001
8002static void __tg3_set_rx_mode(struct net_device *);
Michael Chand244c892005-07-05 14:42:33 -07008003static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
David S. Miller15f98502005-05-18 22:49:26 -07008004{
Matt Carlsonb6080e12009-09-01 13:12:00 +00008005 int i;
8006
Joe Perches63c3a662011-04-26 08:12:10 +00008007 if (!tg3_flag(tp, ENABLE_TSS)) {
Matt Carlsonb6080e12009-09-01 13:12:00 +00008008 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
8009 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
8010 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
Matt Carlsonb6080e12009-09-01 13:12:00 +00008011 } else {
8012 tw32(HOSTCC_TXCOL_TICKS, 0);
8013 tw32(HOSTCC_TXMAX_FRAMES, 0);
8014 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
Matt Carlson19cfaec2009-12-03 08:36:20 +00008015 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00008016
Joe Perches63c3a662011-04-26 08:12:10 +00008017 if (!tg3_flag(tp, ENABLE_RSS)) {
Matt Carlson19cfaec2009-12-03 08:36:20 +00008018 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
8019 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
8020 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
8021 } else {
Matt Carlsonb6080e12009-09-01 13:12:00 +00008022 tw32(HOSTCC_RXCOL_TICKS, 0);
8023 tw32(HOSTCC_RXMAX_FRAMES, 0);
8024 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
David S. Miller15f98502005-05-18 22:49:26 -07008025 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00008026
Joe Perches63c3a662011-04-26 08:12:10 +00008027 if (!tg3_flag(tp, 5705_PLUS)) {
David S. Miller15f98502005-05-18 22:49:26 -07008028 u32 val = ec->stats_block_coalesce_usecs;
8029
Matt Carlsonb6080e12009-09-01 13:12:00 +00008030 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
8031 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
8032
David S. Miller15f98502005-05-18 22:49:26 -07008033 if (!netif_carrier_ok(tp->dev))
8034 val = 0;
8035
8036 tw32(HOSTCC_STAT_COAL_TICKS, val);
8037 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00008038
8039 for (i = 0; i < tp->irq_cnt - 1; i++) {
8040 u32 reg;
8041
8042 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
8043 tw32(reg, ec->rx_coalesce_usecs);
Matt Carlsonb6080e12009-09-01 13:12:00 +00008044 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
8045 tw32(reg, ec->rx_max_coalesced_frames);
Matt Carlsonb6080e12009-09-01 13:12:00 +00008046 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
8047 tw32(reg, ec->rx_max_coalesced_frames_irq);
Matt Carlson19cfaec2009-12-03 08:36:20 +00008048
Joe Perches63c3a662011-04-26 08:12:10 +00008049 if (tg3_flag(tp, ENABLE_TSS)) {
Matt Carlson19cfaec2009-12-03 08:36:20 +00008050 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
8051 tw32(reg, ec->tx_coalesce_usecs);
8052 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
8053 tw32(reg, ec->tx_max_coalesced_frames);
8054 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
8055 tw32(reg, ec->tx_max_coalesced_frames_irq);
8056 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00008057 }
8058
8059 for (; i < tp->irq_max - 1; i++) {
8060 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
Matt Carlsonb6080e12009-09-01 13:12:00 +00008061 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
Matt Carlsonb6080e12009-09-01 13:12:00 +00008062 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
Matt Carlson19cfaec2009-12-03 08:36:20 +00008063
Joe Perches63c3a662011-04-26 08:12:10 +00008064 if (tg3_flag(tp, ENABLE_TSS)) {
Matt Carlson19cfaec2009-12-03 08:36:20 +00008065 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
8066 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
8067 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
8068 }
Matt Carlsonb6080e12009-09-01 13:12:00 +00008069 }
David S. Miller15f98502005-05-18 22:49:26 -07008070}
Linus Torvalds1da177e2005-04-16 15:20:36 -07008071
8072/* tp->lock is held. */
Matt Carlson2d31eca2009-09-01 12:53:31 +00008073static void tg3_rings_reset(struct tg3 *tp)
8074{
8075 int i;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008076 u32 stblk, txrcb, rxrcb, limit;
Matt Carlson2d31eca2009-09-01 12:53:31 +00008077 struct tg3_napi *tnapi = &tp->napi[0];
8078
8079 /* Disable all transmit rings but the first. */
Joe Perches63c3a662011-04-26 08:12:10 +00008080 if (!tg3_flag(tp, 5705_PLUS))
Matt Carlson2d31eca2009-09-01 12:53:31 +00008081 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
Joe Perches63c3a662011-04-26 08:12:10 +00008082 else if (tg3_flag(tp, 5717_PLUS))
Matt Carlson3d377282010-10-14 10:37:39 +00008083 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
Matt Carlsonb703df62009-12-03 08:36:21 +00008084 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8085 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
Matt Carlson2d31eca2009-09-01 12:53:31 +00008086 else
8087 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8088
8089 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
8090 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
8091 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
8092 BDINFO_FLAGS_DISABLED);
8093
8094
8095 /* Disable all receive return rings but the first. */
Joe Perches63c3a662011-04-26 08:12:10 +00008096 if (tg3_flag(tp, 5717_PLUS))
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00008097 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
Joe Perches63c3a662011-04-26 08:12:10 +00008098 else if (!tg3_flag(tp, 5705_PLUS))
Matt Carlson2d31eca2009-09-01 12:53:31 +00008099 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
Matt Carlsonb703df62009-12-03 08:36:21 +00008100 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8101 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Matt Carlson2d31eca2009-09-01 12:53:31 +00008102 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
8103 else
8104 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8105
8106 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
8107 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
8108 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
8109 BDINFO_FLAGS_DISABLED);
8110
8111 /* Disable interrupts */
8112 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
Matt Carlson0e6cf6a2011-06-13 13:38:55 +00008113 tp->napi[0].chk_msi_cnt = 0;
8114 tp->napi[0].last_rx_cons = 0;
8115 tp->napi[0].last_tx_cons = 0;
Matt Carlson2d31eca2009-09-01 12:53:31 +00008116
8117 /* Zero mailbox registers. */
Joe Perches63c3a662011-04-26 08:12:10 +00008118 if (tg3_flag(tp, SUPPORT_MSIX)) {
Matt Carlson6fd45cb2010-09-15 08:59:57 +00008119 for (i = 1; i < tp->irq_max; i++) {
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008120 tp->napi[i].tx_prod = 0;
8121 tp->napi[i].tx_cons = 0;
Joe Perches63c3a662011-04-26 08:12:10 +00008122 if (tg3_flag(tp, ENABLE_TSS))
Matt Carlsonc2353a32010-01-20 16:58:08 +00008123 tw32_mailbox(tp->napi[i].prodmbox, 0);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008124 tw32_rx_mbox(tp->napi[i].consmbox, 0);
8125 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
Matt Carlson7f230732011-08-31 11:44:48 +00008126 tp->napi[i].chk_msi_cnt = 0;
Matt Carlson0e6cf6a2011-06-13 13:38:55 +00008127 tp->napi[i].last_rx_cons = 0;
8128 tp->napi[i].last_tx_cons = 0;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008129 }
Joe Perches63c3a662011-04-26 08:12:10 +00008130 if (!tg3_flag(tp, ENABLE_TSS))
Matt Carlsonc2353a32010-01-20 16:58:08 +00008131 tw32_mailbox(tp->napi[0].prodmbox, 0);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008132 } else {
8133 tp->napi[0].tx_prod = 0;
8134 tp->napi[0].tx_cons = 0;
8135 tw32_mailbox(tp->napi[0].prodmbox, 0);
8136 tw32_rx_mbox(tp->napi[0].consmbox, 0);
8137 }
Matt Carlson2d31eca2009-09-01 12:53:31 +00008138
8139 /* Make sure the NIC-based send BD rings are disabled. */
Joe Perches63c3a662011-04-26 08:12:10 +00008140 if (!tg3_flag(tp, 5705_PLUS)) {
Matt Carlson2d31eca2009-09-01 12:53:31 +00008141 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
8142 for (i = 0; i < 16; i++)
8143 tw32_tx_mbox(mbox + i * 8, 0);
8144 }
8145
8146 txrcb = NIC_SRAM_SEND_RCB;
8147 rxrcb = NIC_SRAM_RCV_RET_RCB;
8148
8149 /* Clear status block in ram. */
8150 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8151
8152 /* Set status block DMA address */
8153 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8154 ((u64) tnapi->status_mapping >> 32));
8155 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8156 ((u64) tnapi->status_mapping & 0xffffffff));
8157
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008158 if (tnapi->tx_ring) {
8159 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8160 (TG3_TX_RING_SIZE <<
8161 BDINFO_FLAGS_MAXLEN_SHIFT),
8162 NIC_SRAM_TX_BUFFER_DESC);
8163 txrcb += TG3_BDINFO_SIZE;
8164 }
Matt Carlson2d31eca2009-09-01 12:53:31 +00008165
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008166 if (tnapi->rx_rcb) {
8167 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008168 (tp->rx_ret_ring_mask + 1) <<
8169 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008170 rxrcb += TG3_BDINFO_SIZE;
8171 }
8172
8173 stblk = HOSTCC_STATBLCK_RING1;
8174
8175 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
8176 u64 mapping = (u64)tnapi->status_mapping;
8177 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
8178 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
8179
8180 /* Clear status block in ram. */
8181 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8182
Matt Carlson19cfaec2009-12-03 08:36:20 +00008183 if (tnapi->tx_ring) {
8184 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
8185 (TG3_TX_RING_SIZE <<
8186 BDINFO_FLAGS_MAXLEN_SHIFT),
8187 NIC_SRAM_TX_BUFFER_DESC);
8188 txrcb += TG3_BDINFO_SIZE;
8189 }
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008190
8191 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008192 ((tp->rx_ret_ring_mask + 1) <<
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008193 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
8194
8195 stblk += 8;
Matt Carlsonf77a6a82009-09-01 13:04:37 +00008196 rxrcb += TG3_BDINFO_SIZE;
8197 }
Matt Carlson2d31eca2009-09-01 12:53:31 +00008198}
8199
Matt Carlsoneb07a942011-04-20 07:57:36 +00008200static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
8201{
8202 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
8203
Joe Perches63c3a662011-04-26 08:12:10 +00008204 if (!tg3_flag(tp, 5750_PLUS) ||
8205 tg3_flag(tp, 5780_CLASS) ||
Matt Carlsoneb07a942011-04-20 07:57:36 +00008206 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8207 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8208 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
8209 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8210 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8211 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
8212 else
8213 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
8214
8215 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
8216 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
8217
8218 val = min(nic_rep_thresh, host_rep_thresh);
8219 tw32(RCVBDI_STD_THRESH, val);
8220
Joe Perches63c3a662011-04-26 08:12:10 +00008221 if (tg3_flag(tp, 57765_PLUS))
Matt Carlsoneb07a942011-04-20 07:57:36 +00008222 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
8223
Joe Perches63c3a662011-04-26 08:12:10 +00008224 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
Matt Carlsoneb07a942011-04-20 07:57:36 +00008225 return;
8226
Joe Perches63c3a662011-04-26 08:12:10 +00008227 if (!tg3_flag(tp, 5705_PLUS))
Matt Carlsoneb07a942011-04-20 07:57:36 +00008228 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
8229 else
8230 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717;
8231
8232 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
8233
8234 val = min(bdcache_maxcnt / 2, host_rep_thresh);
8235 tw32(RCVBDI_JUMBO_THRESH, val);
8236
Joe Perches63c3a662011-04-26 08:12:10 +00008237 if (tg3_flag(tp, 57765_PLUS))
Matt Carlsoneb07a942011-04-20 07:57:36 +00008238 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
8239}
8240
Matt Carlson2d31eca2009-09-01 12:53:31 +00008241/* tp->lock is held. */
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07008242static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
Linus Torvalds1da177e2005-04-16 15:20:36 -07008243{
8244 u32 val, rdmac_mode;
8245 int i, err, limit;
Matt Carlson8fea32b2010-09-15 08:59:58 +00008246 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008247
8248 tg3_disable_ints(tp);
8249
8250 tg3_stop_fw(tp);
8251
8252 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
8253
Joe Perches63c3a662011-04-26 08:12:10 +00008254 if (tg3_flag(tp, INIT_COMPLETE))
Michael Chane6de8ad2005-05-05 14:42:41 -07008255 tg3_abort_hw(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008256
Matt Carlson699c0192010-12-06 08:28:51 +00008257 /* Enable MAC control of LPI */
8258 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
8259 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
8260 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
8261 TG3_CPMU_EEE_LNKIDL_UART_IDL);
8262
8263 tw32_f(TG3_CPMU_EEE_CTRL,
8264 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
8265
Matt Carlsona386b902010-12-06 08:28:53 +00008266 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
8267 TG3_CPMU_EEEMD_LPI_IN_TX |
8268 TG3_CPMU_EEEMD_LPI_IN_RX |
8269 TG3_CPMU_EEEMD_EEE_ENABLE;
8270
8271 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8272 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
8273
Joe Perches63c3a662011-04-26 08:12:10 +00008274 if (tg3_flag(tp, ENABLE_APE))
Matt Carlsona386b902010-12-06 08:28:53 +00008275 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
8276
8277 tw32_f(TG3_CPMU_EEE_MODE, val);
8278
8279 tw32_f(TG3_CPMU_EEE_DBTMR1,
8280 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
8281 TG3_CPMU_DBTMR1_LNKIDLE_2047US);
8282
8283 tw32_f(TG3_CPMU_EEE_DBTMR2,
Matt Carlsond7f2ab22011-01-25 15:58:56 +00008284 TG3_CPMU_DBTMR2_APE_TX_2047US |
Matt Carlsona386b902010-12-06 08:28:53 +00008285 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
Matt Carlson699c0192010-12-06 08:28:51 +00008286 }
8287
Matt Carlson603f1172010-02-12 14:47:10 +00008288 if (reset_phy)
Michael Chand4d2c552006-03-20 17:47:20 -08008289 tg3_phy_reset(tp);
8290
Linus Torvalds1da177e2005-04-16 15:20:36 -07008291 err = tg3_chip_reset(tp);
8292 if (err)
8293 return err;
8294
8295 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
8296
Matt Carlsonbcb37f62008-11-03 16:52:09 -08008297 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
Matt Carlsond30cdd22007-10-07 23:28:35 -07008298 val = tr32(TG3_CPMU_CTRL);
8299 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
8300 tw32(TG3_CPMU_CTRL, val);
Matt Carlson9acb9612007-11-12 21:10:06 -08008301
8302 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8303 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8304 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8305 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
8306
8307 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
8308 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
8309 val |= CPMU_LNK_AWARE_MACCLK_6_25;
8310 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
8311
8312 val = tr32(TG3_CPMU_HST_ACC);
8313 val &= ~CPMU_HST_ACC_MACCLK_MASK;
8314 val |= CPMU_HST_ACC_MACCLK_6_25;
8315 tw32(TG3_CPMU_HST_ACC, val);
Matt Carlsond30cdd22007-10-07 23:28:35 -07008316 }
8317
Matt Carlson33466d92009-04-20 06:57:41 +00008318 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
8319 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
8320 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
8321 PCIE_PWR_MGMT_L1_THRESH_4MS;
8322 tw32(PCIE_PWR_MGMT_THRESH, val);
Matt Carlson521e6b92009-08-25 10:06:01 +00008323
8324 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
8325 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
8326
8327 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
Matt Carlson33466d92009-04-20 06:57:41 +00008328
Matt Carlsonf40386c2009-11-02 14:24:02 +00008329 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8330 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
Matt Carlson255ca312009-08-25 10:07:27 +00008331 }
8332
Joe Perches63c3a662011-04-26 08:12:10 +00008333 if (tg3_flag(tp, L1PLLPD_EN)) {
Matt Carlson614b0592010-01-20 16:58:02 +00008334 u32 grc_mode = tr32(GRC_MODE);
8335
8336 /* Access the lower 1K of PL PCIE block registers. */
8337 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8338 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
8339
8340 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
8341 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
8342 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
8343
8344 tw32(GRC_MODE, grc_mode);
8345 }
8346
Matt Carlson5093eed2010-11-24 08:31:45 +00008347 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
8348 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
8349 u32 grc_mode = tr32(GRC_MODE);
Matt Carlsoncea46462010-04-12 06:58:24 +00008350
Matt Carlson5093eed2010-11-24 08:31:45 +00008351 /* Access the lower 1K of PL PCIE block registers. */
8352 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8353 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
Matt Carlsoncea46462010-04-12 06:58:24 +00008354
Matt Carlson5093eed2010-11-24 08:31:45 +00008355 val = tr32(TG3_PCIE_TLDLPL_PORT +
8356 TG3_PCIE_PL_LO_PHYCTL5);
8357 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
8358 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
Matt Carlsoncea46462010-04-12 06:58:24 +00008359
Matt Carlson5093eed2010-11-24 08:31:45 +00008360 tw32(GRC_MODE, grc_mode);
8361 }
Matt Carlsona977dbe2010-04-12 06:58:26 +00008362
Matt Carlson1ff30a52011-05-19 12:12:46 +00008363 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
8364 u32 grc_mode = tr32(GRC_MODE);
8365
8366 /* Access the lower 1K of DL PCIE block registers. */
8367 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
8368 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
8369
8370 val = tr32(TG3_PCIE_TLDLPL_PORT +
8371 TG3_PCIE_DL_LO_FTSMAX);
8372 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
8373 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
8374 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
8375
8376 tw32(GRC_MODE, grc_mode);
8377 }
8378
Matt Carlsona977dbe2010-04-12 06:58:26 +00008379 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
8380 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
8381 val |= CPMU_LSPD_10MB_MACCLK_6_25;
8382 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
Matt Carlsoncea46462010-04-12 06:58:24 +00008383 }
8384
Linus Torvalds1da177e2005-04-16 15:20:36 -07008385 /* This works around an issue with Athlon chipsets on
8386 * B3 tigon3 silicon. This bit has no effect on any
8387 * other revision. But do not set this on PCI Express
Matt Carlson795d01c2007-10-07 23:28:17 -07008388 * chips and don't even touch the clocks if the CPMU is present.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008389 */
Joe Perches63c3a662011-04-26 08:12:10 +00008390 if (!tg3_flag(tp, CPMU_PRESENT)) {
8391 if (!tg3_flag(tp, PCI_EXPRESS))
Matt Carlson795d01c2007-10-07 23:28:17 -07008392 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
8393 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
8394 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008395
8396 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
Joe Perches63c3a662011-04-26 08:12:10 +00008397 tg3_flag(tp, PCIX_MODE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008398 val = tr32(TG3PCI_PCISTATE);
8399 val |= PCISTATE_RETRY_SAME_DMA;
8400 tw32(TG3PCI_PCISTATE, val);
8401 }
8402
Joe Perches63c3a662011-04-26 08:12:10 +00008403 if (tg3_flag(tp, ENABLE_APE)) {
Matt Carlson0d3031d2007-10-10 18:02:43 -07008404 /* Allow reads and writes to the
8405 * APE register and memory space.
8406 */
8407 val = tr32(TG3PCI_PCISTATE);
8408 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
Matt Carlsonf92d9dc12010-06-05 17:24:30 +00008409 PCISTATE_ALLOW_APE_SHMEM_WR |
8410 PCISTATE_ALLOW_APE_PSPACE_WR;
Matt Carlson0d3031d2007-10-10 18:02:43 -07008411 tw32(TG3PCI_PCISTATE, val);
8412 }
8413
Linus Torvalds1da177e2005-04-16 15:20:36 -07008414 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
8415 /* Enable some hw fixes. */
8416 val = tr32(TG3PCI_MSI_DATA);
8417 val |= (1 << 26) | (1 << 28) | (1 << 29);
8418 tw32(TG3PCI_MSI_DATA, val);
8419 }
8420
8421 /* Descriptor ring init may make accesses to the
8422 * NIC SRAM area to setup the TX descriptors, so we
8423 * can only do this after the hardware has been
8424 * successfully reset.
8425 */
Michael Chan32d8c572006-07-25 16:38:29 -07008426 err = tg3_init_rings(tp);
8427 if (err)
8428 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008429
Joe Perches63c3a662011-04-26 08:12:10 +00008430 if (tg3_flag(tp, 57765_PLUS)) {
Matt Carlsoncbf9ca62009-11-13 13:03:40 +00008431 val = tr32(TG3PCI_DMA_RW_CTRL) &
8432 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
Matt Carlson1a319022010-04-12 06:58:25 +00008433 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
8434 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
Matt Carlson0aebff42011-04-25 12:42:45 +00008435 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8436 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
8437 val |= DMA_RWCTRL_TAGGED_STAT_WA;
Matt Carlsoncbf9ca62009-11-13 13:03:40 +00008438 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
8439 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
8440 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
Matt Carlsond30cdd22007-10-07 23:28:35 -07008441 /* This value is determined during the probe time DMA
8442 * engine test, tg3_test_dma.
8443 */
8444 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
8445 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008446
8447 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
8448 GRC_MODE_4X_NIC_SEND_RINGS |
8449 GRC_MODE_NO_TX_PHDR_CSUM |
8450 GRC_MODE_NO_RX_PHDR_CSUM);
8451 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
Michael Chand2d746f2006-04-06 21:45:39 -07008452
8453 /* Pseudo-header checksum is done by hardware logic and not
8454 * the offload processers, so make the chip do the pseudo-
8455 * header checksums on receive. For transmit it is more
8456 * convenient to do the pseudo-header checksum in software
8457 * as Linux does that on transmit for us in all cases.
8458 */
8459 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008460
8461 tw32(GRC_MODE,
8462 tp->grc_mode |
8463 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
8464
8465 /* Setup the timer prescalar register. Clock is always 66Mhz. */
8466 val = tr32(GRC_MISC_CFG);
8467 val &= ~0xff;
8468 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
8469 tw32(GRC_MISC_CFG, val);
8470
8471 /* Initialize MBUF/DESC pool. */
Joe Perches63c3a662011-04-26 08:12:10 +00008472 if (tg3_flag(tp, 5750_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008473 /* Do nothing. */
8474 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
8475 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
8476 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
8477 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
8478 else
8479 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8480 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8481 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
Joe Perches63c3a662011-04-26 08:12:10 +00008482 } else if (tg3_flag(tp, TSO_CAPABLE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008483 int fw_len;
8484
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08008485 fw_len = tp->fw_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008486 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8487 tw32(BUFMGR_MB_POOL_ADDR,
8488 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8489 tw32(BUFMGR_MB_POOL_SIZE,
8490 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8491 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008492
Michael Chan0f893dc2005-07-25 12:30:38 -07008493 if (tp->dev->mtu <= ETH_DATA_LEN) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008494 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8495 tp->bufmgr_config.mbuf_read_dma_low_water);
8496 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8497 tp->bufmgr_config.mbuf_mac_rx_low_water);
8498 tw32(BUFMGR_MB_HIGH_WATER,
8499 tp->bufmgr_config.mbuf_high_water);
8500 } else {
8501 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8502 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8503 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8504 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8505 tw32(BUFMGR_MB_HIGH_WATER,
8506 tp->bufmgr_config.mbuf_high_water_jumbo);
8507 }
8508 tw32(BUFMGR_DMA_LOW_WATER,
8509 tp->bufmgr_config.dma_low_water);
8510 tw32(BUFMGR_DMA_HIGH_WATER,
8511 tp->bufmgr_config.dma_high_water);
8512
Matt Carlsond309a462010-09-30 10:34:31 +00008513 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8515 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
Matt Carlson4d958472011-04-20 07:57:35 +00008516 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8517 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
8518 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0)
8519 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
Matt Carlsond309a462010-09-30 10:34:31 +00008520 tw32(BUFMGR_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008521 for (i = 0; i < 2000; i++) {
8522 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8523 break;
8524 udelay(10);
8525 }
8526 if (i >= 2000) {
Joe Perches05dbe002010-02-17 19:44:19 +00008527 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008528 return -ENODEV;
8529 }
8530
Matt Carlsoneb07a942011-04-20 07:57:36 +00008531 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8532 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
Michael Chanb5d37722006-09-27 16:06:21 -07008533
Matt Carlsoneb07a942011-04-20 07:57:36 +00008534 tg3_setup_rxbd_thresholds(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008535
8536 /* Initialize TG3_BDINFO's at:
8537 * RCVDBDI_STD_BD: standard eth size rx ring
8538 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8539 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8540 *
8541 * like so:
8542 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8543 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8544 * ring attribute flags
8545 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8546 *
8547 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8548 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8549 *
8550 * The size of each ring is fixed in the firmware, but the location is
8551 * configurable.
8552 */
8553 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
Matt Carlson21f581a2009-08-28 14:00:25 +00008554 ((u64) tpr->rx_std_mapping >> 32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07008555 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
Matt Carlson21f581a2009-08-28 14:00:25 +00008556 ((u64) tpr->rx_std_mapping & 0xffffffff));
Joe Perches63c3a662011-04-26 08:12:10 +00008557 if (!tg3_flag(tp, 5717_PLUS))
Matt Carlson87668d32009-11-13 13:03:34 +00008558 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8559 NIC_SRAM_RX_BUFFER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008560
Matt Carlsonfdb72b32009-08-28 13:57:12 +00008561 /* Disable the mini ring */
Joe Perches63c3a662011-04-26 08:12:10 +00008562 if (!tg3_flag(tp, 5705_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07008563 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8564 BDINFO_FLAGS_DISABLED);
8565
Matt Carlsonfdb72b32009-08-28 13:57:12 +00008566 /* Program the jumbo buffer descriptor ring control
8567 * blocks on those devices that have them.
8568 */
Matt Carlsona0512942011-07-27 14:20:54 +00008569 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
Joe Perches63c3a662011-04-26 08:12:10 +00008570 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008571
Joe Perches63c3a662011-04-26 08:12:10 +00008572 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008573 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
Matt Carlson21f581a2009-08-28 14:00:25 +00008574 ((u64) tpr->rx_jmb_mapping >> 32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07008575 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
Matt Carlson21f581a2009-08-28 14:00:25 +00008576 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
Matt Carlsonde9f5232011-04-05 14:22:43 +00008577 val = TG3_RX_JMB_RING_SIZE(tp) <<
8578 BDINFO_FLAGS_MAXLEN_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008579 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
Matt Carlsonde9f5232011-04-05 14:22:43 +00008580 val | BDINFO_FLAGS_USE_EXT_RECV);
Joe Perches63c3a662011-04-26 08:12:10 +00008581 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
Matt Carlsona50d0792010-06-05 17:24:37 +00008582 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Matt Carlson87668d32009-11-13 13:03:34 +00008583 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8584 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008585 } else {
8586 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8587 BDINFO_FLAGS_DISABLED);
8588 }
8589
Joe Perches63c3a662011-04-26 08:12:10 +00008590 if (tg3_flag(tp, 57765_PLUS)) {
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008591 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Matt Carlsonde9f5232011-04-05 14:22:43 +00008592 val = TG3_RX_STD_MAX_SIZE_5700;
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008593 else
Matt Carlsonde9f5232011-04-05 14:22:43 +00008594 val = TG3_RX_STD_MAX_SIZE_5717;
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008595 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8596 val |= (TG3_RX_STD_DMA_SZ << 2);
8597 } else
Matt Carlson04380d42010-04-12 06:58:29 +00008598 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
Matt Carlsonfdb72b32009-08-28 13:57:12 +00008599 } else
Matt Carlsonde9f5232011-04-05 14:22:43 +00008600 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
Matt Carlsonfdb72b32009-08-28 13:57:12 +00008601
8602 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008603
Matt Carlson411da642009-11-13 13:03:46 +00008604 tpr->rx_std_prod_idx = tp->rx_pending;
Matt Carlson66711e62009-11-13 13:03:49 +00008605 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008606
Joe Perches63c3a662011-04-26 08:12:10 +00008607 tpr->rx_jmb_prod_idx =
8608 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
Matt Carlson66711e62009-11-13 13:03:49 +00008609 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008610
Matt Carlson2d31eca2009-09-01 12:53:31 +00008611 tg3_rings_reset(tp);
8612
Linus Torvalds1da177e2005-04-16 15:20:36 -07008613 /* Initialize MAC address and backoff seed. */
Michael Chan986e0ae2007-05-05 12:10:20 -07008614 __tg3_set_mac_addr(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008615
8616 /* MTU + ethernet header + FCS + optional VLAN tag */
Matt Carlsonf7b493e2009-02-25 14:21:52 +00008617 tw32(MAC_RX_MTU_SIZE,
8618 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008619
8620 /* The slot time is changed by tg3_setup_phy if we
8621 * run at gigabit with half duplex.
8622 */
Matt Carlsonf2096f92011-04-05 14:22:48 +00008623 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8624 (6 << TX_LENGTHS_IPG_SHIFT) |
8625 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
8626
8627 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8628 val |= tr32(MAC_TX_LENGTHS) &
8629 (TX_LENGTHS_JMB_FRM_LEN_MSK |
8630 TX_LENGTHS_CNT_DWN_VAL_MSK);
8631
8632 tw32(MAC_TX_LENGTHS, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008633
8634 /* Receive rules. */
8635 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8636 tw32(RCVLPC_CONFIG, 0x0181);
8637
8638 /* Calculate RDMAC_MODE setting early, we need it to determine
8639 * the RCVLPC_STATE_ENABLE mask.
8640 */
8641 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8642 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8643 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8644 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8645 RDMAC_MODE_LNGREAD_ENAB);
Michael Chan85e94ce2005-04-21 17:05:28 -07008646
Matt Carlsondeabaac2010-11-24 08:31:50 +00008647 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
Matt Carlson0339e4e2010-02-12 14:47:09 +00008648 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8649
Matt Carlson57e69832008-05-25 23:48:31 -07008650 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson321d32a2008-11-21 17:22:19 -08008651 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8652 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
Matt Carlsond30cdd22007-10-07 23:28:35 -07008653 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8654 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8655 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8656
Matt Carlsonc5908932011-03-09 16:58:25 +00008657 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8658 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
Joe Perches63c3a662011-04-26 08:12:10 +00008659 if (tg3_flag(tp, TSO_CAPABLE) &&
Matt Carlsonc13e3712007-05-05 11:50:04 -07008660 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008661 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8662 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
Joe Perches63c3a662011-04-26 08:12:10 +00008663 !tg3_flag(tp, IS_5788)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008664 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8665 }
8666 }
8667
Joe Perches63c3a662011-04-26 08:12:10 +00008668 if (tg3_flag(tp, PCI_EXPRESS))
Michael Chan85e94ce2005-04-21 17:05:28 -07008669 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8670
Joe Perches63c3a662011-04-26 08:12:10 +00008671 if (tg3_flag(tp, HW_TSO_1) ||
8672 tg3_flag(tp, HW_TSO_2) ||
8673 tg3_flag(tp, HW_TSO_3))
Matt Carlson027455a2008-12-21 20:19:30 -08008674 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8675
Matt Carlson108a6c12011-05-19 12:12:47 +00008676 if (tg3_flag(tp, 57765_PLUS) ||
Matt Carlsone849cdc2009-11-13 13:03:38 +00008677 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Matt Carlson027455a2008-12-21 20:19:30 -08008678 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8679 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008680
Matt Carlsonf2096f92011-04-05 14:22:48 +00008681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
8682 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
8683
Matt Carlson41a8a7e2010-09-15 08:59:53 +00008684 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8685 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8686 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8687 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
Joe Perches63c3a662011-04-26 08:12:10 +00008688 tg3_flag(tp, 57765_PLUS)) {
Matt Carlson41a8a7e2010-09-15 08:59:53 +00008689 val = tr32(TG3_RDMA_RSRVCTRL_REG);
Matt Carlsond78b59f2011-04-05 14:22:46 +00008690 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8691 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
Matt Carlsonb4495ed2011-01-25 15:58:47 +00008692 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
8693 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
8694 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
8695 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
8696 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
8697 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
Matt Carlsonb75cc0e2010-11-24 08:31:46 +00008698 }
Matt Carlson41a8a7e2010-09-15 08:59:53 +00008699 tw32(TG3_RDMA_RSRVCTRL_REG,
8700 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8701 }
8702
Matt Carlsond78b59f2011-04-05 14:22:46 +00008703 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
8704 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
Matt Carlsond309a462010-09-30 10:34:31 +00008705 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8706 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8707 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8708 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8709 }
8710
Linus Torvalds1da177e2005-04-16 15:20:36 -07008711 /* Receive/send statistics. */
Joe Perches63c3a662011-04-26 08:12:10 +00008712 if (tg3_flag(tp, 5750_PLUS)) {
Michael Chan16613942006-06-29 20:15:13 -07008713 val = tr32(RCVLPC_STATS_ENABLE);
8714 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8715 tw32(RCVLPC_STATS_ENABLE, val);
8716 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
Joe Perches63c3a662011-04-26 08:12:10 +00008717 tg3_flag(tp, TSO_CAPABLE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008718 val = tr32(RCVLPC_STATS_ENABLE);
8719 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8720 tw32(RCVLPC_STATS_ENABLE, val);
8721 } else {
8722 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8723 }
8724 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8725 tw32(SNDDATAI_STATSENAB, 0xffffff);
8726 tw32(SNDDATAI_STATSCTRL,
8727 (SNDDATAI_SCTRL_ENABLE |
8728 SNDDATAI_SCTRL_FASTUPD));
8729
8730 /* Setup host coalescing engine. */
8731 tw32(HOSTCC_MODE, 0);
8732 for (i = 0; i < 2000; i++) {
8733 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8734 break;
8735 udelay(10);
8736 }
8737
Michael Chand244c892005-07-05 14:42:33 -07008738 __tg3_set_coalesce(tp, &tp->coal);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008739
Joe Perches63c3a662011-04-26 08:12:10 +00008740 if (!tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008741 /* Status/statistics block address. See tg3_timer,
8742 * the tg3_periodic_fetch_stats call there, and
8743 * tg3_get_stats to see how this works for 5705/5750 chips.
8744 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07008745 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8746 ((u64) tp->stats_mapping >> 32));
8747 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8748 ((u64) tp->stats_mapping & 0xffffffff));
8749 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
Matt Carlson2d31eca2009-09-01 12:53:31 +00008750
Linus Torvalds1da177e2005-04-16 15:20:36 -07008751 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
Matt Carlson2d31eca2009-09-01 12:53:31 +00008752
8753 /* Clear statistics and status block memory areas */
8754 for (i = NIC_SRAM_STATS_BLK;
8755 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8756 i += sizeof(u32)) {
8757 tg3_write_mem(tp, i, 0);
8758 udelay(40);
8759 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008760 }
8761
8762 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8763
8764 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8765 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
Joe Perches63c3a662011-04-26 08:12:10 +00008766 if (!tg3_flag(tp, 5705_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07008767 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8768
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008769 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8770 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
Michael Chanc94e3942005-09-27 12:12:42 -07008771 /* reset to prevent losing 1st rx packet intermittently */
8772 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8773 udelay(10);
8774 }
8775
Matt Carlson3bda1252008-08-15 14:08:22 -07008776 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
Matt Carlson9e975cc2011-07-20 10:20:50 +00008777 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
8778 MAC_MODE_FHDE_ENABLE;
8779 if (tg3_flag(tp, ENABLE_APE))
8780 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
Joe Perches63c3a662011-04-26 08:12:10 +00008781 if (!tg3_flag(tp, 5705_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008782 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
Matt Carlsone8f3f6c2007-07-11 19:47:55 -07008783 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8784 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008785 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8786 udelay(40);
8787
Michael Chan314fba32005-04-21 17:07:04 -07008788 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
Joe Perches63c3a662011-04-26 08:12:10 +00008789 * If TG3_FLAG_IS_NIC is zero, we should read the
Michael Chan314fba32005-04-21 17:07:04 -07008790 * register to preserve the GPIO settings for LOMs. The GPIOs,
8791 * whether used as inputs or outputs, are set by boot code after
8792 * reset.
8793 */
Joe Perches63c3a662011-04-26 08:12:10 +00008794 if (!tg3_flag(tp, IS_NIC)) {
Michael Chan314fba32005-04-21 17:07:04 -07008795 u32 gpio_mask;
8796
Michael Chan9d26e212006-12-07 00:21:14 -08008797 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8798 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8799 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
Michael Chan3e7d83b2005-04-21 17:10:36 -07008800
8801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8802 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8803 GRC_LCLCTRL_GPIO_OUTPUT3;
8804
Michael Chanaf36e6b2006-03-23 01:28:06 -08008805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8806 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8807
Gary Zambranoaaf84462007-05-05 11:51:45 -07008808 tp->grc_local_ctrl &= ~gpio_mask;
Michael Chan314fba32005-04-21 17:07:04 -07008809 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8810
8811 /* GPIO1 must be driven high for eeprom write protect */
Joe Perches63c3a662011-04-26 08:12:10 +00008812 if (tg3_flag(tp, EEPROM_WRITE_PROT))
Michael Chan9d26e212006-12-07 00:21:14 -08008813 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8814 GRC_LCLCTRL_GPIO_OUTPUT1);
Michael Chan314fba32005-04-21 17:07:04 -07008815 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008816 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8817 udelay(100);
8818
Joe Perches63c3a662011-04-26 08:12:10 +00008819 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) {
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008820 val = tr32(MSGINT_MODE);
8821 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
Matt Carlson5b39de92011-08-31 11:44:50 +00008822 if (!tg3_flag(tp, 1SHOT_MSI))
8823 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008824 tw32(MSGINT_MODE, val);
8825 }
8826
Joe Perches63c3a662011-04-26 08:12:10 +00008827 if (!tg3_flag(tp, 5705_PLUS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008828 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8829 udelay(40);
8830 }
8831
8832 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8833 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8834 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8835 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8836 WDMAC_MODE_LNGREAD_ENAB);
8837
Matt Carlsonc5908932011-03-09 16:58:25 +00008838 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8839 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
Joe Perches63c3a662011-04-26 08:12:10 +00008840 if (tg3_flag(tp, TSO_CAPABLE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07008841 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8842 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8843 /* nothing */
8844 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
Joe Perches63c3a662011-04-26 08:12:10 +00008845 !tg3_flag(tp, IS_5788)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008846 val |= WDMAC_MODE_RX_ACCEL;
8847 }
8848 }
8849
Michael Chand9ab5ad2006-03-20 22:27:35 -08008850 /* Enable host coalescing bug fix */
Joe Perches63c3a662011-04-26 08:12:10 +00008851 if (tg3_flag(tp, 5755_PLUS))
Matt Carlsonf51f3562008-05-25 23:45:08 -07008852 val |= WDMAC_MODE_STATUS_TAG_FIX;
Michael Chand9ab5ad2006-03-20 22:27:35 -08008853
Matt Carlson788a0352009-11-02 14:26:03 +00008854 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8855 val |= WDMAC_MODE_BURST_ALL_DATA;
8856
Linus Torvalds1da177e2005-04-16 15:20:36 -07008857 tw32_f(WDMAC_MODE, val);
8858 udelay(40);
8859
Joe Perches63c3a662011-04-26 08:12:10 +00008860 if (tg3_flag(tp, PCIX_MODE)) {
Matt Carlson9974a352007-10-07 23:27:28 -07008861 u16 pcix_cmd;
8862
8863 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8864 &pcix_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008865 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
Matt Carlson9974a352007-10-07 23:27:28 -07008866 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8867 pcix_cmd |= PCI_X_CMD_READ_2K;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008868 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
Matt Carlson9974a352007-10-07 23:27:28 -07008869 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8870 pcix_cmd |= PCI_X_CMD_READ_2K;
Linus Torvalds1da177e2005-04-16 15:20:36 -07008871 }
Matt Carlson9974a352007-10-07 23:27:28 -07008872 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8873 pcix_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008874 }
8875
8876 tw32_f(RDMAC_MODE, rdmac_mode);
8877 udelay(40);
8878
8879 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
Joe Perches63c3a662011-04-26 08:12:10 +00008880 if (!tg3_flag(tp, 5705_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07008881 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
Matt Carlson9936bcf2007-10-10 18:03:07 -07008882
8883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8884 tw32(SNDDATAC_MODE,
8885 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8886 else
8887 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8888
Linus Torvalds1da177e2005-04-16 15:20:36 -07008889 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8890 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008891 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
Joe Perches63c3a662011-04-26 08:12:10 +00008892 if (tg3_flag(tp, LRG_PROD_RING_CAP))
Matt Carlson7cb32cf2010-09-30 10:34:36 +00008893 val |= RCVDBDI_MODE_LRG_RING_SZ;
8894 tw32(RCVDBDI_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008895 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
Joe Perches63c3a662011-04-26 08:12:10 +00008896 if (tg3_flag(tp, HW_TSO_1) ||
8897 tg3_flag(tp, HW_TSO_2) ||
8898 tg3_flag(tp, HW_TSO_3))
Linus Torvalds1da177e2005-04-16 15:20:36 -07008899 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008900 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
Joe Perches63c3a662011-04-26 08:12:10 +00008901 if (tg3_flag(tp, ENABLE_TSS))
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008902 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8903 tw32(SNDBDI_MODE, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07008904 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8905
8906 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8907 err = tg3_load_5701_a0_firmware_fix(tp);
8908 if (err)
8909 return err;
8910 }
8911
Joe Perches63c3a662011-04-26 08:12:10 +00008912 if (tg3_flag(tp, TSO_CAPABLE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008913 err = tg3_load_tso_firmware(tp);
8914 if (err)
8915 return err;
8916 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07008917
8918 tp->tx_mode = TX_MODE_ENABLE;
Matt Carlsonf2096f92011-04-05 14:22:48 +00008919
Joe Perches63c3a662011-04-26 08:12:10 +00008920 if (tg3_flag(tp, 5755_PLUS) ||
Matt Carlsonb1d05212010-06-05 17:24:31 +00008921 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8922 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
Matt Carlsonf2096f92011-04-05 14:22:48 +00008923
8924 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
8925 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
8926 tp->tx_mode &= ~val;
8927 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
8928 }
8929
Linus Torvalds1da177e2005-04-16 15:20:36 -07008930 tw32_f(MAC_TX_MODE, tp->tx_mode);
8931 udelay(100);
8932
Joe Perches63c3a662011-04-26 08:12:10 +00008933 if (tg3_flag(tp, ENABLE_RSS)) {
Matt Carlson9d53fa12011-07-20 10:20:54 +00008934 int i = 0;
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008935 u32 reg = MAC_RSS_INDIR_TBL_0;
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008936
Matt Carlson9d53fa12011-07-20 10:20:54 +00008937 if (tp->irq_cnt == 2) {
8938 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i += 8) {
8939 tw32(reg, 0x0);
8940 reg += 4;
8941 }
8942 } else {
8943 u32 val;
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008944
Matt Carlson9d53fa12011-07-20 10:20:54 +00008945 while (i < TG3_RSS_INDIR_TBL_SIZE) {
8946 val = i % (tp->irq_cnt - 1);
8947 i++;
8948 for (; i % 8; i++) {
8949 val <<= 4;
8950 val |= (i % (tp->irq_cnt - 1));
8951 }
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008952 tw32(reg, val);
8953 reg += 4;
8954 }
8955 }
8956
8957 /* Setup the "secret" hash key. */
8958 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8959 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8960 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8961 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8962 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8963 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8964 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8965 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8966 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8967 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8968 }
8969
Linus Torvalds1da177e2005-04-16 15:20:36 -07008970 tp->rx_mode = RX_MODE_ENABLE;
Joe Perches63c3a662011-04-26 08:12:10 +00008971 if (tg3_flag(tp, 5755_PLUS))
Michael Chanaf36e6b2006-03-23 01:28:06 -08008972 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8973
Joe Perches63c3a662011-04-26 08:12:10 +00008974 if (tg3_flag(tp, ENABLE_RSS))
Matt Carlsonbaf8a942009-09-01 13:13:00 +00008975 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8976 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8977 RX_MODE_RSS_IPV6_HASH_EN |
8978 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8979 RX_MODE_RSS_IPV4_HASH_EN |
8980 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8981
Linus Torvalds1da177e2005-04-16 15:20:36 -07008982 tw32_f(MAC_RX_MODE, tp->rx_mode);
8983 udelay(10);
8984
Linus Torvalds1da177e2005-04-16 15:20:36 -07008985 tw32(MAC_LED_CTRL, tp->led_ctrl);
8986
8987 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008988 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008989 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8990 udelay(10);
8991 }
8992 tw32_f(MAC_RX_MODE, tp->rx_mode);
8993 udelay(10);
8994
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008995 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008996 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00008997 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07008998 /* Set drive transmission level to 1.2V */
8999 /* only if the signal pre-emphasis bit is not set */
9000 val = tr32(MAC_SERDES_CFG);
9001 val &= 0xfffff000;
9002 val |= 0x880;
9003 tw32(MAC_SERDES_CFG, val);
9004 }
9005 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
9006 tw32(MAC_SERDES_CFG, 0x616000);
9007 }
9008
9009 /* Prevent chip from dropping frames when flow control
9010 * is enabled.
9011 */
Matt Carlson666bc832010-01-20 16:58:03 +00009012 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
9013 val = 1;
9014 else
9015 val = 2;
9016 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009017
9018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009019 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009020 /* Use hardware link auto-negotiation */
Joe Perches63c3a662011-04-26 08:12:10 +00009021 tg3_flag_set(tp, HW_AUTONEG);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009022 }
9023
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009024 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
Matt Carlson6ff6f812011-05-19 12:12:54 +00009025 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
Michael Chand4d2c552006-03-20 17:47:20 -08009026 u32 tmp;
9027
9028 tmp = tr32(SERDES_RX_CTRL);
9029 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
9030 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
9031 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
9032 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9033 }
9034
Joe Perches63c3a662011-04-26 08:12:10 +00009035 if (!tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson80096062010-08-02 11:26:06 +00009036 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
9037 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
Matt Carlsondd477002008-05-25 23:45:58 -07009038 tp->link_config.speed = tp->link_config.orig_speed;
9039 tp->link_config.duplex = tp->link_config.orig_duplex;
9040 tp->link_config.autoneg = tp->link_config.orig_autoneg;
9041 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009042
Matt Carlsondd477002008-05-25 23:45:58 -07009043 err = tg3_setup_phy(tp, 0);
9044 if (err)
9045 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009046
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009047 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9048 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
Matt Carlsondd477002008-05-25 23:45:58 -07009049 u32 tmp;
9050
9051 /* Clear CRC stats. */
9052 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
9053 tg3_writephy(tp, MII_TG3_TEST1,
9054 tmp | MII_TG3_TEST1_CRC_EN);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00009055 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
Matt Carlsondd477002008-05-25 23:45:58 -07009056 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009057 }
9058 }
9059
9060 __tg3_set_rx_mode(tp->dev);
9061
9062 /* Initialize receive rules. */
9063 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
9064 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
9065 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
9066 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
9067
Joe Perches63c3a662011-04-26 08:12:10 +00009068 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
Linus Torvalds1da177e2005-04-16 15:20:36 -07009069 limit = 8;
9070 else
9071 limit = 16;
Joe Perches63c3a662011-04-26 08:12:10 +00009072 if (tg3_flag(tp, ENABLE_ASF))
Linus Torvalds1da177e2005-04-16 15:20:36 -07009073 limit -= 4;
9074 switch (limit) {
9075 case 16:
9076 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
9077 case 15:
9078 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
9079 case 14:
9080 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
9081 case 13:
9082 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
9083 case 12:
9084 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
9085 case 11:
9086 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
9087 case 10:
9088 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
9089 case 9:
9090 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
9091 case 8:
9092 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
9093 case 7:
9094 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
9095 case 6:
9096 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
9097 case 5:
9098 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
9099 case 4:
9100 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
9101 case 3:
9102 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
9103 case 2:
9104 case 1:
9105
9106 default:
9107 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -07009108 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009109
Joe Perches63c3a662011-04-26 08:12:10 +00009110 if (tg3_flag(tp, ENABLE_APE))
Matt Carlson9ce768e2007-10-11 19:49:11 -07009111 /* Write our heartbeat update interval to APE. */
9112 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
9113 APE_HOST_HEARTBEAT_INT_DISABLE);
Matt Carlson0d3031d2007-10-10 18:02:43 -07009114
Linus Torvalds1da177e2005-04-16 15:20:36 -07009115 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
9116
Linus Torvalds1da177e2005-04-16 15:20:36 -07009117 return 0;
9118}
9119
9120/* Called at device open time to get the chip ready for
9121 * packet processing. Invoked with tp->lock held.
9122 */
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07009123static int tg3_init_hw(struct tg3 *tp, int reset_phy)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009124{
Linus Torvalds1da177e2005-04-16 15:20:36 -07009125 tg3_switch_clocks(tp);
9126
9127 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9128
Matt Carlson2f751b62008-08-04 23:17:34 -07009129 return tg3_reset_hw(tp, reset_phy);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009130}
9131
9132#define TG3_STAT_ADD32(PSTAT, REG) \
9133do { u32 __val = tr32(REG); \
9134 (PSTAT)->low += __val; \
9135 if ((PSTAT)->low < __val) \
9136 (PSTAT)->high += 1; \
9137} while (0)
9138
9139static void tg3_periodic_fetch_stats(struct tg3 *tp)
9140{
9141 struct tg3_hw_stats *sp = tp->hw_stats;
9142
9143 if (!netif_carrier_ok(tp->dev))
9144 return;
9145
9146 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
9147 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
9148 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
9149 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
9150 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
9151 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
9152 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
9153 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
9154 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
9155 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
9156 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
9157 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
9158 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
9159
9160 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
9161 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
9162 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
9163 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
9164 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
9165 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
9166 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
9167 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
9168 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
9169 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
9170 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
9171 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
9172 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
9173 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
Michael Chan463d3052006-05-22 16:36:27 -07009174
9175 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
Matt Carlson310050f2011-05-19 12:12:55 +00009176 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9177 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0 &&
9178 tp->pci_chip_rev_id != CHIPREV_ID_5720_A0) {
Matt Carlson4d958472011-04-20 07:57:35 +00009179 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
9180 } else {
9181 u32 val = tr32(HOSTCC_FLOW_ATTN);
9182 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
9183 if (val) {
9184 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
9185 sp->rx_discards.low += val;
9186 if (sp->rx_discards.low < val)
9187 sp->rx_discards.high += 1;
9188 }
9189 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
9190 }
Michael Chan463d3052006-05-22 16:36:27 -07009191 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009192}
9193
Matt Carlson0e6cf6a2011-06-13 13:38:55 +00009194static void tg3_chk_missed_msi(struct tg3 *tp)
9195{
9196 u32 i;
9197
9198 for (i = 0; i < tp->irq_cnt; i++) {
9199 struct tg3_napi *tnapi = &tp->napi[i];
9200
9201 if (tg3_has_work(tnapi)) {
9202 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
9203 tnapi->last_tx_cons == tnapi->tx_cons) {
9204 if (tnapi->chk_msi_cnt < 1) {
9205 tnapi->chk_msi_cnt++;
9206 return;
9207 }
Matt Carlson7f230732011-08-31 11:44:48 +00009208 tg3_msi(0, tnapi);
Matt Carlson0e6cf6a2011-06-13 13:38:55 +00009209 }
9210 }
9211 tnapi->chk_msi_cnt = 0;
9212 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
9213 tnapi->last_tx_cons = tnapi->tx_cons;
9214 }
9215}
9216
Linus Torvalds1da177e2005-04-16 15:20:36 -07009217static void tg3_timer(unsigned long __opaque)
9218{
9219 struct tg3 *tp = (struct tg3 *) __opaque;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009220
Michael Chanf475f162006-03-27 23:20:14 -08009221 if (tp->irq_sync)
9222 goto restart_timer;
9223
David S. Millerf47c11e2005-06-24 20:18:35 -07009224 spin_lock(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009225
Matt Carlson0e6cf6a2011-06-13 13:38:55 +00009226 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
9227 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
9228 tg3_chk_missed_msi(tp);
9229
Joe Perches63c3a662011-04-26 08:12:10 +00009230 if (!tg3_flag(tp, TAGGED_STATUS)) {
David S. Millerfac9b832005-05-18 22:46:34 -07009231 /* All of this garbage is because when using non-tagged
9232 * IRQ status the mailbox/status_block protocol the chip
9233 * uses with the cpu is race prone.
9234 */
Matt Carlson898a56f2009-08-28 14:02:40 +00009235 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
David S. Millerfac9b832005-05-18 22:46:34 -07009236 tw32(GRC_LOCAL_CTRL,
9237 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
9238 } else {
9239 tw32(HOSTCC_MODE, tp->coalesce_mode |
Matt Carlsonfd2ce372009-09-01 12:51:13 +00009240 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
David S. Millerfac9b832005-05-18 22:46:34 -07009241 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009242
David S. Millerfac9b832005-05-18 22:46:34 -07009243 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
Joe Perches63c3a662011-04-26 08:12:10 +00009244 tg3_flag_set(tp, RESTART_TIMER);
David S. Millerf47c11e2005-06-24 20:18:35 -07009245 spin_unlock(&tp->lock);
Matt Carlsondb219972011-11-04 09:15:03 +00009246 tg3_reset_task_schedule(tp);
David S. Millerfac9b832005-05-18 22:46:34 -07009247 return;
9248 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009249 }
9250
Linus Torvalds1da177e2005-04-16 15:20:36 -07009251 /* This part only runs once per second. */
9252 if (!--tp->timer_counter) {
Joe Perches63c3a662011-04-26 08:12:10 +00009253 if (tg3_flag(tp, 5705_PLUS))
David S. Millerfac9b832005-05-18 22:46:34 -07009254 tg3_periodic_fetch_stats(tp);
9255
Matt Carlsonb0c59432011-05-19 12:12:48 +00009256 if (tp->setlpicnt && !--tp->setlpicnt)
9257 tg3_phy_eee_enable(tp);
Matt Carlson52b02d02010-10-14 10:37:41 +00009258
Joe Perches63c3a662011-04-26 08:12:10 +00009259 if (tg3_flag(tp, USE_LINKCHG_REG)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009260 u32 mac_stat;
9261 int phy_event;
9262
9263 mac_stat = tr32(MAC_STATUS);
9264
9265 phy_event = 0;
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009266 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009267 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
9268 phy_event = 1;
9269 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
9270 phy_event = 1;
9271
9272 if (phy_event)
9273 tg3_setup_phy(tp, 0);
Joe Perches63c3a662011-04-26 08:12:10 +00009274 } else if (tg3_flag(tp, POLL_SERDES)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009275 u32 mac_stat = tr32(MAC_STATUS);
9276 int need_setup = 0;
9277
9278 if (netif_carrier_ok(tp->dev) &&
9279 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
9280 need_setup = 1;
9281 }
Matt Carlsonbe98da62010-07-11 09:31:46 +00009282 if (!netif_carrier_ok(tp->dev) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07009283 (mac_stat & (MAC_STATUS_PCS_SYNCED |
9284 MAC_STATUS_SIGNAL_DET))) {
9285 need_setup = 1;
9286 }
9287 if (need_setup) {
Michael Chan3d3ebe72006-09-27 15:59:15 -07009288 if (!tp->serdes_counter) {
9289 tw32_f(MAC_MODE,
9290 (tp->mac_mode &
9291 ~MAC_MODE_PORT_MODE_MASK));
9292 udelay(40);
9293 tw32_f(MAC_MODE, tp->mac_mode);
9294 udelay(40);
9295 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009296 tg3_setup_phy(tp, 0);
9297 }
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009298 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
Joe Perches63c3a662011-04-26 08:12:10 +00009299 tg3_flag(tp, 5780_CLASS)) {
Michael Chan747e8f82005-07-25 12:33:22 -07009300 tg3_serdes_parallel_detect(tp);
Matt Carlson57d8b882010-06-05 17:24:35 +00009301 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07009302
9303 tp->timer_counter = tp->timer_multiplier;
9304 }
9305
Michael Chan130b8e42006-09-27 16:00:40 -07009306 /* Heartbeat is only sent once every 2 seconds.
9307 *
9308 * The heartbeat is to tell the ASF firmware that the host
9309 * driver is still alive. In the event that the OS crashes,
9310 * ASF needs to reset the hardware to free up the FIFO space
9311 * that may be filled with rx packets destined for the host.
9312 * If the FIFO is full, ASF will no longer function properly.
9313 *
9314 * Unintended resets have been reported on real time kernels
9315 * where the timer doesn't run on time. Netpoll will also have
9316 * same problem.
9317 *
9318 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
9319 * to check the ring condition when the heartbeat is expiring
9320 * before doing the reset. This will prevent most unintended
9321 * resets.
9322 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07009323 if (!--tp->asf_counter) {
Joe Perches63c3a662011-04-26 08:12:10 +00009324 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
Matt Carlson7c5026a2008-05-02 16:49:29 -07009325 tg3_wait_for_event_ack(tp);
9326
Michael Chanbbadf502006-04-06 21:46:34 -07009327 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
Michael Chan130b8e42006-09-27 16:00:40 -07009328 FWCMD_NICDRV_ALIVE3);
Michael Chanbbadf502006-04-06 21:46:34 -07009329 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
Matt Carlsonc6cdf432010-04-05 10:19:26 +00009330 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
9331 TG3_FW_UPDATE_TIMEOUT_SEC);
Matt Carlson4ba526c2008-08-15 14:10:04 -07009332
9333 tg3_generate_fw_event(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009334 }
9335 tp->asf_counter = tp->asf_multiplier;
9336 }
9337
David S. Millerf47c11e2005-06-24 20:18:35 -07009338 spin_unlock(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009339
Michael Chanf475f162006-03-27 23:20:14 -08009340restart_timer:
Linus Torvalds1da177e2005-04-16 15:20:36 -07009341 tp->timer.expires = jiffies + tp->timer_offset;
9342 add_timer(&tp->timer);
9343}
9344
Matt Carlson4f125f42009-09-01 12:55:02 +00009345static int tg3_request_irq(struct tg3 *tp, int irq_num)
Michael Chanfcfa0a32006-03-20 22:28:41 -08009346{
David Howells7d12e782006-10-05 14:55:46 +01009347 irq_handler_t fn;
Michael Chanfcfa0a32006-03-20 22:28:41 -08009348 unsigned long flags;
Matt Carlson4f125f42009-09-01 12:55:02 +00009349 char *name;
9350 struct tg3_napi *tnapi = &tp->napi[irq_num];
9351
9352 if (tp->irq_cnt == 1)
9353 name = tp->dev->name;
9354 else {
9355 name = &tnapi->irq_lbl[0];
9356 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
9357 name[IFNAMSIZ-1] = 0;
9358 }
Michael Chanfcfa0a32006-03-20 22:28:41 -08009359
Joe Perches63c3a662011-04-26 08:12:10 +00009360 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
Michael Chanfcfa0a32006-03-20 22:28:41 -08009361 fn = tg3_msi;
Joe Perches63c3a662011-04-26 08:12:10 +00009362 if (tg3_flag(tp, 1SHOT_MSI))
Michael Chanfcfa0a32006-03-20 22:28:41 -08009363 fn = tg3_msi_1shot;
Javier Martinez Canillasab392d22011-03-28 16:27:31 +00009364 flags = 0;
Michael Chanfcfa0a32006-03-20 22:28:41 -08009365 } else {
9366 fn = tg3_interrupt;
Joe Perches63c3a662011-04-26 08:12:10 +00009367 if (tg3_flag(tp, TAGGED_STATUS))
Michael Chanfcfa0a32006-03-20 22:28:41 -08009368 fn = tg3_interrupt_tagged;
Javier Martinez Canillasab392d22011-03-28 16:27:31 +00009369 flags = IRQF_SHARED;
Michael Chanfcfa0a32006-03-20 22:28:41 -08009370 }
Matt Carlson4f125f42009-09-01 12:55:02 +00009371
9372 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
Michael Chanfcfa0a32006-03-20 22:28:41 -08009373}
9374
Michael Chan79381092005-04-21 17:13:59 -07009375static int tg3_test_interrupt(struct tg3 *tp)
9376{
Matt Carlson09943a12009-08-28 14:01:57 +00009377 struct tg3_napi *tnapi = &tp->napi[0];
Michael Chan79381092005-04-21 17:13:59 -07009378 struct net_device *dev = tp->dev;
Michael Chanb16250e2006-09-27 16:10:14 -07009379 int err, i, intr_ok = 0;
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009380 u32 val;
Michael Chan79381092005-04-21 17:13:59 -07009381
Michael Chand4bc3922005-05-29 14:59:20 -07009382 if (!netif_running(dev))
9383 return -ENODEV;
9384
Michael Chan79381092005-04-21 17:13:59 -07009385 tg3_disable_ints(tp);
9386
Matt Carlson4f125f42009-09-01 12:55:02 +00009387 free_irq(tnapi->irq_vec, tnapi);
Michael Chan79381092005-04-21 17:13:59 -07009388
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009389 /*
9390 * Turn off MSI one shot mode. Otherwise this test has no
9391 * observable way to know whether the interrupt was delivered.
9392 */
Matt Carlson3aa1cdf2011-07-20 10:20:55 +00009393 if (tg3_flag(tp, 57765_PLUS)) {
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009394 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
9395 tw32(MSGINT_MODE, val);
9396 }
9397
Matt Carlson4f125f42009-09-01 12:55:02 +00009398 err = request_irq(tnapi->irq_vec, tg3_test_isr,
Matt Carlson09943a12009-08-28 14:01:57 +00009399 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
Michael Chan79381092005-04-21 17:13:59 -07009400 if (err)
9401 return err;
9402
Matt Carlson898a56f2009-08-28 14:02:40 +00009403 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
Michael Chan79381092005-04-21 17:13:59 -07009404 tg3_enable_ints(tp);
9405
9406 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
Matt Carlsonfd2ce372009-09-01 12:51:13 +00009407 tnapi->coal_now);
Michael Chan79381092005-04-21 17:13:59 -07009408
9409 for (i = 0; i < 5; i++) {
Michael Chanb16250e2006-09-27 16:10:14 -07009410 u32 int_mbox, misc_host_ctrl;
9411
Matt Carlson898a56f2009-08-28 14:02:40 +00009412 int_mbox = tr32_mailbox(tnapi->int_mbox);
Michael Chanb16250e2006-09-27 16:10:14 -07009413 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
9414
9415 if ((int_mbox != 0) ||
9416 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
9417 intr_ok = 1;
Michael Chan79381092005-04-21 17:13:59 -07009418 break;
Michael Chanb16250e2006-09-27 16:10:14 -07009419 }
9420
Matt Carlson3aa1cdf2011-07-20 10:20:55 +00009421 if (tg3_flag(tp, 57765_PLUS) &&
9422 tnapi->hw_status->status_tag != tnapi->last_tag)
9423 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
9424
Michael Chan79381092005-04-21 17:13:59 -07009425 msleep(10);
9426 }
9427
9428 tg3_disable_ints(tp);
9429
Matt Carlson4f125f42009-09-01 12:55:02 +00009430 free_irq(tnapi->irq_vec, tnapi);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009431
Matt Carlson4f125f42009-09-01 12:55:02 +00009432 err = tg3_request_irq(tp, 0);
Michael Chan79381092005-04-21 17:13:59 -07009433
9434 if (err)
9435 return err;
9436
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009437 if (intr_ok) {
9438 /* Reenable MSI one shot mode. */
Matt Carlson5b39de92011-08-31 11:44:50 +00009439 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009440 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
9441 tw32(MSGINT_MODE, val);
9442 }
Michael Chan79381092005-04-21 17:13:59 -07009443 return 0;
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009444 }
Michael Chan79381092005-04-21 17:13:59 -07009445
9446 return -EIO;
9447}
9448
9449/* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
9450 * successfully restored
9451 */
9452static int tg3_test_msi(struct tg3 *tp)
9453{
Michael Chan79381092005-04-21 17:13:59 -07009454 int err;
9455 u16 pci_cmd;
9456
Joe Perches63c3a662011-04-26 08:12:10 +00009457 if (!tg3_flag(tp, USING_MSI))
Michael Chan79381092005-04-21 17:13:59 -07009458 return 0;
9459
9460 /* Turn off SERR reporting in case MSI terminates with Master
9461 * Abort.
9462 */
9463 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9464 pci_write_config_word(tp->pdev, PCI_COMMAND,
9465 pci_cmd & ~PCI_COMMAND_SERR);
9466
9467 err = tg3_test_interrupt(tp);
9468
9469 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9470
9471 if (!err)
9472 return 0;
9473
9474 /* other failures */
9475 if (err != -EIO)
9476 return err;
9477
9478 /* MSI test failed, go back to INTx mode */
Matt Carlson5129c3a2010-04-05 10:19:23 +00009479 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
9480 "to INTx mode. Please report this failure to the PCI "
9481 "maintainer and include system chipset information\n");
Michael Chan79381092005-04-21 17:13:59 -07009482
Matt Carlson4f125f42009-09-01 12:55:02 +00009483 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
Matt Carlson09943a12009-08-28 14:01:57 +00009484
Michael Chan79381092005-04-21 17:13:59 -07009485 pci_disable_msi(tp->pdev);
9486
Joe Perches63c3a662011-04-26 08:12:10 +00009487 tg3_flag_clear(tp, USING_MSI);
Andre Detschdc8bf1b2010-04-26 07:27:07 +00009488 tp->napi[0].irq_vec = tp->pdev->irq;
Michael Chan79381092005-04-21 17:13:59 -07009489
Matt Carlson4f125f42009-09-01 12:55:02 +00009490 err = tg3_request_irq(tp, 0);
Michael Chan79381092005-04-21 17:13:59 -07009491 if (err)
9492 return err;
9493
9494 /* Need to reset the chip because the MSI cycle may have terminated
9495 * with Master Abort.
9496 */
David S. Millerf47c11e2005-06-24 20:18:35 -07009497 tg3_full_lock(tp, 1);
Michael Chan79381092005-04-21 17:13:59 -07009498
Michael Chan944d9802005-05-29 14:57:48 -07009499 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07009500 err = tg3_init_hw(tp, 1);
Michael Chan79381092005-04-21 17:13:59 -07009501
David S. Millerf47c11e2005-06-24 20:18:35 -07009502 tg3_full_unlock(tp);
Michael Chan79381092005-04-21 17:13:59 -07009503
9504 if (err)
Matt Carlson4f125f42009-09-01 12:55:02 +00009505 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
Michael Chan79381092005-04-21 17:13:59 -07009506
9507 return err;
9508}
9509
Matt Carlson9e9fd122009-01-19 16:57:45 -08009510static int tg3_request_firmware(struct tg3 *tp)
9511{
9512 const __be32 *fw_data;
9513
9514 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
Joe Perches05dbe002010-02-17 19:44:19 +00009515 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
9516 tp->fw_needed);
Matt Carlson9e9fd122009-01-19 16:57:45 -08009517 return -ENOENT;
9518 }
9519
9520 fw_data = (void *)tp->fw->data;
9521
9522 /* Firmware blob starts with version numbers, followed by
9523 * start address and _full_ length including BSS sections
9524 * (which must be longer than the actual data, of course
9525 */
9526
9527 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
9528 if (tp->fw_len < (tp->fw->size - 12)) {
Joe Perches05dbe002010-02-17 19:44:19 +00009529 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
9530 tp->fw_len, tp->fw_needed);
Matt Carlson9e9fd122009-01-19 16:57:45 -08009531 release_firmware(tp->fw);
9532 tp->fw = NULL;
9533 return -EINVAL;
9534 }
9535
9536 /* We no longer need firmware; we have it. */
9537 tp->fw_needed = NULL;
9538 return 0;
9539}
9540
Matt Carlson679563f2009-09-01 12:55:46 +00009541static bool tg3_enable_msix(struct tg3 *tp)
9542{
9543 int i, rc, cpus = num_online_cpus();
9544 struct msix_entry msix_ent[tp->irq_max];
9545
9546 if (cpus == 1)
9547 /* Just fallback to the simpler MSI mode. */
9548 return false;
9549
9550 /*
9551 * We want as many rx rings enabled as there are cpus.
9552 * The first MSIX vector only deals with link interrupts, etc,
9553 * so we add one to the number of vectors we are requesting.
9554 */
9555 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9556
9557 for (i = 0; i < tp->irq_max; i++) {
9558 msix_ent[i].entry = i;
9559 msix_ent[i].vector = 0;
9560 }
9561
9562 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
Matt Carlson2430b032010-06-05 17:24:34 +00009563 if (rc < 0) {
9564 return false;
9565 } else if (rc != 0) {
Matt Carlson679563f2009-09-01 12:55:46 +00009566 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9567 return false;
Joe Perches05dbe002010-02-17 19:44:19 +00009568 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9569 tp->irq_cnt, rc);
Matt Carlson679563f2009-09-01 12:55:46 +00009570 tp->irq_cnt = rc;
9571 }
9572
9573 for (i = 0; i < tp->irq_max; i++)
9574 tp->napi[i].irq_vec = msix_ent[i].vector;
9575
Ben Hutchings2ddaad32010-09-27 22:11:51 -07009576 netif_set_real_num_tx_queues(tp->dev, 1);
9577 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9578 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9579 pci_disable_msix(tp->pdev);
9580 return false;
9581 }
Matt Carlsonb92b9042010-11-24 08:31:51 +00009582
9583 if (tp->irq_cnt > 1) {
Joe Perches63c3a662011-04-26 08:12:10 +00009584 tg3_flag_set(tp, ENABLE_RSS);
Matt Carlsond78b59f2011-04-05 14:22:46 +00009585
9586 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
9587 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
Joe Perches63c3a662011-04-26 08:12:10 +00009588 tg3_flag_set(tp, ENABLE_TSS);
Matt Carlsonb92b9042010-11-24 08:31:51 +00009589 netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9590 }
9591 }
Matt Carlson2430b032010-06-05 17:24:34 +00009592
Matt Carlson679563f2009-09-01 12:55:46 +00009593 return true;
9594}
9595
Matt Carlson07b01732009-08-28 14:01:15 +00009596static void tg3_ints_init(struct tg3 *tp)
9597{
Joe Perches63c3a662011-04-26 08:12:10 +00009598 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
9599 !tg3_flag(tp, TAGGED_STATUS)) {
Matt Carlson07b01732009-08-28 14:01:15 +00009600 /* All MSI supporting chips should support tagged
9601 * status. Assert that this is the case.
9602 */
Matt Carlson5129c3a2010-04-05 10:19:23 +00009603 netdev_warn(tp->dev,
9604 "MSI without TAGGED_STATUS? Not using MSI\n");
Matt Carlson679563f2009-09-01 12:55:46 +00009605 goto defcfg;
Matt Carlson07b01732009-08-28 14:01:15 +00009606 }
Matt Carlson4f125f42009-09-01 12:55:02 +00009607
Joe Perches63c3a662011-04-26 08:12:10 +00009608 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
9609 tg3_flag_set(tp, USING_MSIX);
9610 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
9611 tg3_flag_set(tp, USING_MSI);
Matt Carlson679563f2009-09-01 12:55:46 +00009612
Joe Perches63c3a662011-04-26 08:12:10 +00009613 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
Matt Carlson679563f2009-09-01 12:55:46 +00009614 u32 msi_mode = tr32(MSGINT_MODE);
Joe Perches63c3a662011-04-26 08:12:10 +00009615 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
Matt Carlsonbaf8a942009-09-01 13:13:00 +00009616 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
Matt Carlson5b39de92011-08-31 11:44:50 +00009617 if (!tg3_flag(tp, 1SHOT_MSI))
9618 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
Matt Carlson679563f2009-09-01 12:55:46 +00009619 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9620 }
9621defcfg:
Joe Perches63c3a662011-04-26 08:12:10 +00009622 if (!tg3_flag(tp, USING_MSIX)) {
Matt Carlson679563f2009-09-01 12:55:46 +00009623 tp->irq_cnt = 1;
9624 tp->napi[0].irq_vec = tp->pdev->irq;
Ben Hutchings2ddaad32010-09-27 22:11:51 -07009625 netif_set_real_num_tx_queues(tp->dev, 1);
Matt Carlson85407882010-10-06 13:40:58 -07009626 netif_set_real_num_rx_queues(tp->dev, 1);
Matt Carlson679563f2009-09-01 12:55:46 +00009627 }
Matt Carlson07b01732009-08-28 14:01:15 +00009628}
9629
9630static void tg3_ints_fini(struct tg3 *tp)
9631{
Joe Perches63c3a662011-04-26 08:12:10 +00009632 if (tg3_flag(tp, USING_MSIX))
Matt Carlson679563f2009-09-01 12:55:46 +00009633 pci_disable_msix(tp->pdev);
Joe Perches63c3a662011-04-26 08:12:10 +00009634 else if (tg3_flag(tp, USING_MSI))
Matt Carlson679563f2009-09-01 12:55:46 +00009635 pci_disable_msi(tp->pdev);
Joe Perches63c3a662011-04-26 08:12:10 +00009636 tg3_flag_clear(tp, USING_MSI);
9637 tg3_flag_clear(tp, USING_MSIX);
9638 tg3_flag_clear(tp, ENABLE_RSS);
9639 tg3_flag_clear(tp, ENABLE_TSS);
Matt Carlson07b01732009-08-28 14:01:15 +00009640}
9641
Linus Torvalds1da177e2005-04-16 15:20:36 -07009642static int tg3_open(struct net_device *dev)
9643{
9644 struct tg3 *tp = netdev_priv(dev);
Matt Carlson4f125f42009-09-01 12:55:02 +00009645 int i, err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009646
Matt Carlson9e9fd122009-01-19 16:57:45 -08009647 if (tp->fw_needed) {
9648 err = tg3_request_firmware(tp);
9649 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9650 if (err)
9651 return err;
9652 } else if (err) {
Joe Perches05dbe002010-02-17 19:44:19 +00009653 netdev_warn(tp->dev, "TSO capability disabled\n");
Joe Perches63c3a662011-04-26 08:12:10 +00009654 tg3_flag_clear(tp, TSO_CAPABLE);
9655 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
Joe Perches05dbe002010-02-17 19:44:19 +00009656 netdev_notice(tp->dev, "TSO capability restored\n");
Joe Perches63c3a662011-04-26 08:12:10 +00009657 tg3_flag_set(tp, TSO_CAPABLE);
Matt Carlson9e9fd122009-01-19 16:57:45 -08009658 }
9659 }
9660
Michael Chanc49a1562006-12-17 17:07:29 -08009661 netif_carrier_off(tp->dev);
9662
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00009663 err = tg3_power_up(tp);
Matt Carlson2f751b62008-08-04 23:17:34 -07009664 if (err)
Michael Chanbc1c7562006-03-20 17:48:03 -08009665 return err;
Matt Carlson2f751b62008-08-04 23:17:34 -07009666
9667 tg3_full_lock(tp, 0);
Michael Chanbc1c7562006-03-20 17:48:03 -08009668
Linus Torvalds1da177e2005-04-16 15:20:36 -07009669 tg3_disable_ints(tp);
Joe Perches63c3a662011-04-26 08:12:10 +00009670 tg3_flag_clear(tp, INIT_COMPLETE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009671
David S. Millerf47c11e2005-06-24 20:18:35 -07009672 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009673
Matt Carlson679563f2009-09-01 12:55:46 +00009674 /*
9675 * Setup interrupts first so we know how
9676 * many NAPI resources to allocate
9677 */
9678 tg3_ints_init(tp);
9679
Linus Torvalds1da177e2005-04-16 15:20:36 -07009680 /* The placement of this call is tied
9681 * to the setup and use of Host TX descriptors.
9682 */
9683 err = tg3_alloc_consistent(tp);
9684 if (err)
Matt Carlson679563f2009-09-01 12:55:46 +00009685 goto err_out1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009686
Matt Carlson66cfd1b2010-09-30 10:34:30 +00009687 tg3_napi_init(tp);
9688
Matt Carlsonfed97812009-09-01 13:10:19 +00009689 tg3_napi_enable(tp);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07009690
Matt Carlson4f125f42009-09-01 12:55:02 +00009691 for (i = 0; i < tp->irq_cnt; i++) {
9692 struct tg3_napi *tnapi = &tp->napi[i];
9693 err = tg3_request_irq(tp, i);
9694 if (err) {
Matt Carlson5bc09182011-11-04 09:15:01 +00009695 for (i--; i >= 0; i--) {
9696 tnapi = &tp->napi[i];
Matt Carlson4f125f42009-09-01 12:55:02 +00009697 free_irq(tnapi->irq_vec, tnapi);
Matt Carlson5bc09182011-11-04 09:15:01 +00009698 }
9699 goto err_out2;
Matt Carlson4f125f42009-09-01 12:55:02 +00009700 }
9701 }
Matt Carlson07b01732009-08-28 14:01:15 +00009702
David S. Millerf47c11e2005-06-24 20:18:35 -07009703 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009704
Gary Zambrano8e7a22e2006-04-29 18:59:13 -07009705 err = tg3_init_hw(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009706 if (err) {
Michael Chan944d9802005-05-29 14:57:48 -07009707 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009708 tg3_free_rings(tp);
9709 } else {
Matt Carlson0e6cf6a2011-06-13 13:38:55 +00009710 if (tg3_flag(tp, TAGGED_STATUS) &&
9711 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
9712 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765)
David S. Millerfac9b832005-05-18 22:46:34 -07009713 tp->timer_offset = HZ;
9714 else
9715 tp->timer_offset = HZ / 10;
9716
9717 BUG_ON(tp->timer_offset > HZ);
9718 tp->timer_counter = tp->timer_multiplier =
9719 (HZ / tp->timer_offset);
9720 tp->asf_counter = tp->asf_multiplier =
Michael Chan28fbef72005-10-26 15:48:35 -07009721 ((HZ / tp->timer_offset) * 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009722
9723 init_timer(&tp->timer);
9724 tp->timer.expires = jiffies + tp->timer_offset;
9725 tp->timer.data = (unsigned long) tp;
9726 tp->timer.function = tg3_timer;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009727 }
9728
David S. Millerf47c11e2005-06-24 20:18:35 -07009729 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009730
Matt Carlson07b01732009-08-28 14:01:15 +00009731 if (err)
Matt Carlson679563f2009-09-01 12:55:46 +00009732 goto err_out3;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009733
Joe Perches63c3a662011-04-26 08:12:10 +00009734 if (tg3_flag(tp, USING_MSI)) {
Michael Chan79381092005-04-21 17:13:59 -07009735 err = tg3_test_msi(tp);
David S. Millerfac9b832005-05-18 22:46:34 -07009736
Michael Chan79381092005-04-21 17:13:59 -07009737 if (err) {
David S. Millerf47c11e2005-06-24 20:18:35 -07009738 tg3_full_lock(tp, 0);
Michael Chan944d9802005-05-29 14:57:48 -07009739 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Michael Chan79381092005-04-21 17:13:59 -07009740 tg3_free_rings(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -07009741 tg3_full_unlock(tp);
Michael Chan79381092005-04-21 17:13:59 -07009742
Matt Carlson679563f2009-09-01 12:55:46 +00009743 goto err_out2;
Michael Chan79381092005-04-21 17:13:59 -07009744 }
Michael Chanfcfa0a32006-03-20 22:28:41 -08009745
Joe Perches63c3a662011-04-26 08:12:10 +00009746 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009747 u32 val = tr32(PCIE_TRANSACTION_CFG);
Michael Chanfcfa0a32006-03-20 22:28:41 -08009748
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00009749 tw32(PCIE_TRANSACTION_CFG,
9750 val | PCIE_TRANS_CFG_1SHOT_MSI);
Michael Chanfcfa0a32006-03-20 22:28:41 -08009751 }
Michael Chan79381092005-04-21 17:13:59 -07009752 }
9753
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07009754 tg3_phy_start(tp);
9755
David S. Millerf47c11e2005-06-24 20:18:35 -07009756 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009757
Michael Chan79381092005-04-21 17:13:59 -07009758 add_timer(&tp->timer);
Joe Perches63c3a662011-04-26 08:12:10 +00009759 tg3_flag_set(tp, INIT_COMPLETE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009760 tg3_enable_ints(tp);
9761
David S. Millerf47c11e2005-06-24 20:18:35 -07009762 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009763
Matt Carlsonfe5f5782009-09-01 13:09:39 +00009764 netif_tx_start_all_queues(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009765
Mahesh Bandewar06c03c02011-05-08 06:51:48 +00009766 /*
9767 * Reset loopback feature if it was turned on while the device was down
9768 * make sure that it's installed properly now.
9769 */
9770 if (dev->features & NETIF_F_LOOPBACK)
9771 tg3_set_loopback(dev, dev->features);
9772
Linus Torvalds1da177e2005-04-16 15:20:36 -07009773 return 0;
Matt Carlson07b01732009-08-28 14:01:15 +00009774
Matt Carlson679563f2009-09-01 12:55:46 +00009775err_out3:
Matt Carlson4f125f42009-09-01 12:55:02 +00009776 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9777 struct tg3_napi *tnapi = &tp->napi[i];
9778 free_irq(tnapi->irq_vec, tnapi);
9779 }
Matt Carlson07b01732009-08-28 14:01:15 +00009780
Matt Carlson679563f2009-09-01 12:55:46 +00009781err_out2:
Matt Carlsonfed97812009-09-01 13:10:19 +00009782 tg3_napi_disable(tp);
Matt Carlson66cfd1b2010-09-30 10:34:30 +00009783 tg3_napi_fini(tp);
Matt Carlson07b01732009-08-28 14:01:15 +00009784 tg3_free_consistent(tp);
Matt Carlson679563f2009-09-01 12:55:46 +00009785
9786err_out1:
9787 tg3_ints_fini(tp);
Matt Carlsoncd0d7222011-07-13 09:27:33 +00009788 tg3_frob_aux_power(tp, false);
9789 pci_set_power_state(tp->pdev, PCI_D3hot);
Matt Carlson07b01732009-08-28 14:01:15 +00009790 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009791}
9792
Eric Dumazet511d2222010-07-07 20:44:24 +00009793static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9794 struct rtnl_link_stats64 *);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009795static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9796
9797static int tg3_close(struct net_device *dev)
9798{
Matt Carlson4f125f42009-09-01 12:55:02 +00009799 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009800 struct tg3 *tp = netdev_priv(dev);
9801
Matt Carlsonfed97812009-09-01 13:10:19 +00009802 tg3_napi_disable(tp);
Matt Carlsondb219972011-11-04 09:15:03 +00009803 tg3_reset_task_cancel(tp);
Michael Chan7faa0062006-02-02 17:29:28 -08009804
Matt Carlsonfe5f5782009-09-01 13:09:39 +00009805 netif_tx_stop_all_queues(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009806
9807 del_timer_sync(&tp->timer);
9808
Matt Carlson24bb4fb2009-10-05 17:55:29 +00009809 tg3_phy_stop(tp);
9810
David S. Millerf47c11e2005-06-24 20:18:35 -07009811 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009812
9813 tg3_disable_ints(tp);
9814
Michael Chan944d9802005-05-29 14:57:48 -07009815 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009816 tg3_free_rings(tp);
Joe Perches63c3a662011-04-26 08:12:10 +00009817 tg3_flag_clear(tp, INIT_COMPLETE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009818
David S. Millerf47c11e2005-06-24 20:18:35 -07009819 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009820
Matt Carlson4f125f42009-09-01 12:55:02 +00009821 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9822 struct tg3_napi *tnapi = &tp->napi[i];
9823 free_irq(tnapi->irq_vec, tnapi);
9824 }
Matt Carlson07b01732009-08-28 14:01:15 +00009825
9826 tg3_ints_fini(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009827
Eric Dumazet511d2222010-07-07 20:44:24 +00009828 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9829
Linus Torvalds1da177e2005-04-16 15:20:36 -07009830 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9831 sizeof(tp->estats_prev));
9832
Matt Carlson66cfd1b2010-09-30 10:34:30 +00009833 tg3_napi_fini(tp);
9834
Linus Torvalds1da177e2005-04-16 15:20:36 -07009835 tg3_free_consistent(tp);
9836
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +00009837 tg3_power_down(tp);
Michael Chanbc1c7562006-03-20 17:48:03 -08009838
9839 netif_carrier_off(tp->dev);
9840
Linus Torvalds1da177e2005-04-16 15:20:36 -07009841 return 0;
9842}
9843
Eric Dumazet511d2222010-07-07 20:44:24 +00009844static inline u64 get_stat64(tg3_stat64_t *val)
Stefan Buehler816f8b82008-08-15 14:10:54 -07009845{
9846 return ((u64)val->high << 32) | ((u64)val->low);
9847}
9848
Eric Dumazet511d2222010-07-07 20:44:24 +00009849static u64 calc_crc_errors(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009850{
9851 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9852
Matt Carlsonf07e9af2010-08-02 11:26:07 +00009853 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07009854 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9855 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07009856 u32 val;
9857
David S. Millerf47c11e2005-06-24 20:18:35 -07009858 spin_lock_bh(&tp->lock);
Michael Chan569a5df2007-02-13 12:18:15 -08009859 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9860 tg3_writephy(tp, MII_TG3_TEST1,
9861 val | MII_TG3_TEST1_CRC_EN);
Matt Carlsonf08aa1a2010-08-02 11:26:05 +00009862 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009863 } else
9864 val = 0;
David S. Millerf47c11e2005-06-24 20:18:35 -07009865 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009866
9867 tp->phy_crc_errors += val;
9868
9869 return tp->phy_crc_errors;
9870 }
9871
9872 return get_stat64(&hw_stats->rx_fcs_errors);
9873}
9874
9875#define ESTAT_ADD(member) \
9876 estats->member = old_estats->member + \
Eric Dumazet511d2222010-07-07 20:44:24 +00009877 get_stat64(&hw_stats->member)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009878
9879static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9880{
9881 struct tg3_ethtool_stats *estats = &tp->estats;
9882 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9883 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9884
9885 if (!hw_stats)
9886 return old_estats;
9887
9888 ESTAT_ADD(rx_octets);
9889 ESTAT_ADD(rx_fragments);
9890 ESTAT_ADD(rx_ucast_packets);
9891 ESTAT_ADD(rx_mcast_packets);
9892 ESTAT_ADD(rx_bcast_packets);
9893 ESTAT_ADD(rx_fcs_errors);
9894 ESTAT_ADD(rx_align_errors);
9895 ESTAT_ADD(rx_xon_pause_rcvd);
9896 ESTAT_ADD(rx_xoff_pause_rcvd);
9897 ESTAT_ADD(rx_mac_ctrl_rcvd);
9898 ESTAT_ADD(rx_xoff_entered);
9899 ESTAT_ADD(rx_frame_too_long_errors);
9900 ESTAT_ADD(rx_jabbers);
9901 ESTAT_ADD(rx_undersize_packets);
9902 ESTAT_ADD(rx_in_length_errors);
9903 ESTAT_ADD(rx_out_length_errors);
9904 ESTAT_ADD(rx_64_or_less_octet_packets);
9905 ESTAT_ADD(rx_65_to_127_octet_packets);
9906 ESTAT_ADD(rx_128_to_255_octet_packets);
9907 ESTAT_ADD(rx_256_to_511_octet_packets);
9908 ESTAT_ADD(rx_512_to_1023_octet_packets);
9909 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9910 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9911 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9912 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9913 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9914
9915 ESTAT_ADD(tx_octets);
9916 ESTAT_ADD(tx_collisions);
9917 ESTAT_ADD(tx_xon_sent);
9918 ESTAT_ADD(tx_xoff_sent);
9919 ESTAT_ADD(tx_flow_control);
9920 ESTAT_ADD(tx_mac_errors);
9921 ESTAT_ADD(tx_single_collisions);
9922 ESTAT_ADD(tx_mult_collisions);
9923 ESTAT_ADD(tx_deferred);
9924 ESTAT_ADD(tx_excessive_collisions);
9925 ESTAT_ADD(tx_late_collisions);
9926 ESTAT_ADD(tx_collide_2times);
9927 ESTAT_ADD(tx_collide_3times);
9928 ESTAT_ADD(tx_collide_4times);
9929 ESTAT_ADD(tx_collide_5times);
9930 ESTAT_ADD(tx_collide_6times);
9931 ESTAT_ADD(tx_collide_7times);
9932 ESTAT_ADD(tx_collide_8times);
9933 ESTAT_ADD(tx_collide_9times);
9934 ESTAT_ADD(tx_collide_10times);
9935 ESTAT_ADD(tx_collide_11times);
9936 ESTAT_ADD(tx_collide_12times);
9937 ESTAT_ADD(tx_collide_13times);
9938 ESTAT_ADD(tx_collide_14times);
9939 ESTAT_ADD(tx_collide_15times);
9940 ESTAT_ADD(tx_ucast_packets);
9941 ESTAT_ADD(tx_mcast_packets);
9942 ESTAT_ADD(tx_bcast_packets);
9943 ESTAT_ADD(tx_carrier_sense_errors);
9944 ESTAT_ADD(tx_discards);
9945 ESTAT_ADD(tx_errors);
9946
9947 ESTAT_ADD(dma_writeq_full);
9948 ESTAT_ADD(dma_write_prioq_full);
9949 ESTAT_ADD(rxbds_empty);
9950 ESTAT_ADD(rx_discards);
9951 ESTAT_ADD(rx_errors);
9952 ESTAT_ADD(rx_threshold_hit);
9953
9954 ESTAT_ADD(dma_readq_full);
9955 ESTAT_ADD(dma_read_prioq_full);
9956 ESTAT_ADD(tx_comp_queue_full);
9957
9958 ESTAT_ADD(ring_set_send_prod_index);
9959 ESTAT_ADD(ring_status_update);
9960 ESTAT_ADD(nic_irqs);
9961 ESTAT_ADD(nic_avoided_irqs);
9962 ESTAT_ADD(nic_tx_threshold_hit);
9963
Matt Carlson4452d092011-05-19 12:12:51 +00009964 ESTAT_ADD(mbuf_lwm_thresh_hit);
9965
Linus Torvalds1da177e2005-04-16 15:20:36 -07009966 return estats;
9967}
9968
Eric Dumazet511d2222010-07-07 20:44:24 +00009969static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9970 struct rtnl_link_stats64 *stats)
Linus Torvalds1da177e2005-04-16 15:20:36 -07009971{
9972 struct tg3 *tp = netdev_priv(dev);
Eric Dumazet511d2222010-07-07 20:44:24 +00009973 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07009974 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9975
9976 if (!hw_stats)
9977 return old_stats;
9978
9979 stats->rx_packets = old_stats->rx_packets +
9980 get_stat64(&hw_stats->rx_ucast_packets) +
9981 get_stat64(&hw_stats->rx_mcast_packets) +
9982 get_stat64(&hw_stats->rx_bcast_packets);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04009983
Linus Torvalds1da177e2005-04-16 15:20:36 -07009984 stats->tx_packets = old_stats->tx_packets +
9985 get_stat64(&hw_stats->tx_ucast_packets) +
9986 get_stat64(&hw_stats->tx_mcast_packets) +
9987 get_stat64(&hw_stats->tx_bcast_packets);
9988
9989 stats->rx_bytes = old_stats->rx_bytes +
9990 get_stat64(&hw_stats->rx_octets);
9991 stats->tx_bytes = old_stats->tx_bytes +
9992 get_stat64(&hw_stats->tx_octets);
9993
9994 stats->rx_errors = old_stats->rx_errors +
John W. Linville4f63b872005-09-12 14:43:18 -07009995 get_stat64(&hw_stats->rx_errors);
Linus Torvalds1da177e2005-04-16 15:20:36 -07009996 stats->tx_errors = old_stats->tx_errors +
9997 get_stat64(&hw_stats->tx_errors) +
9998 get_stat64(&hw_stats->tx_mac_errors) +
9999 get_stat64(&hw_stats->tx_carrier_sense_errors) +
10000 get_stat64(&hw_stats->tx_discards);
10001
10002 stats->multicast = old_stats->multicast +
10003 get_stat64(&hw_stats->rx_mcast_packets);
10004 stats->collisions = old_stats->collisions +
10005 get_stat64(&hw_stats->tx_collisions);
10006
10007 stats->rx_length_errors = old_stats->rx_length_errors +
10008 get_stat64(&hw_stats->rx_frame_too_long_errors) +
10009 get_stat64(&hw_stats->rx_undersize_packets);
10010
10011 stats->rx_over_errors = old_stats->rx_over_errors +
10012 get_stat64(&hw_stats->rxbds_empty);
10013 stats->rx_frame_errors = old_stats->rx_frame_errors +
10014 get_stat64(&hw_stats->rx_align_errors);
10015 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
10016 get_stat64(&hw_stats->tx_discards);
10017 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
10018 get_stat64(&hw_stats->tx_carrier_sense_errors);
10019
10020 stats->rx_crc_errors = old_stats->rx_crc_errors +
10021 calc_crc_errors(tp);
10022
John W. Linville4f63b872005-09-12 14:43:18 -070010023 stats->rx_missed_errors = old_stats->rx_missed_errors +
10024 get_stat64(&hw_stats->rx_discards);
10025
Eric Dumazetb0057c52010-10-10 19:55:52 +000010026 stats->rx_dropped = tp->rx_dropped;
Eric Dumazet48855432011-10-24 07:53:03 +000010027 stats->tx_dropped = tp->tx_dropped;
Eric Dumazetb0057c52010-10-10 19:55:52 +000010028
Linus Torvalds1da177e2005-04-16 15:20:36 -070010029 return stats;
10030}
10031
10032static inline u32 calc_crc(unsigned char *buf, int len)
10033{
10034 u32 reg;
10035 u32 tmp;
10036 int j, k;
10037
10038 reg = 0xffffffff;
10039
10040 for (j = 0; j < len; j++) {
10041 reg ^= buf[j];
10042
10043 for (k = 0; k < 8; k++) {
10044 tmp = reg & 0x01;
10045
10046 reg >>= 1;
10047
Matt Carlson859a5882010-04-05 10:19:28 +000010048 if (tmp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010049 reg ^= 0xedb88320;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010050 }
10051 }
10052
10053 return ~reg;
10054}
10055
10056static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
10057{
10058 /* accept or reject all multicast frames */
10059 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
10060 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
10061 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
10062 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
10063}
10064
10065static void __tg3_set_rx_mode(struct net_device *dev)
10066{
10067 struct tg3 *tp = netdev_priv(dev);
10068 u32 rx_mode;
10069
10070 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
10071 RX_MODE_KEEP_VLAN_TAG);
10072
Matt Carlsonbf933c82011-01-25 15:58:49 +000010073#if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010074 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
10075 * flag clear.
10076 */
Joe Perches63c3a662011-04-26 08:12:10 +000010077 if (!tg3_flag(tp, ENABLE_ASF))
Linus Torvalds1da177e2005-04-16 15:20:36 -070010078 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
10079#endif
10080
10081 if (dev->flags & IFF_PROMISC) {
10082 /* Promiscuous mode. */
10083 rx_mode |= RX_MODE_PROMISC;
10084 } else if (dev->flags & IFF_ALLMULTI) {
10085 /* Accept all multicast. */
Matt Carlsonde6f31e2010-04-12 06:58:30 +000010086 tg3_set_multi(tp, 1);
Jiri Pirko4cd24ea2010-02-08 04:30:35 +000010087 } else if (netdev_mc_empty(dev)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070010088 /* Reject all multicast. */
Matt Carlsonde6f31e2010-04-12 06:58:30 +000010089 tg3_set_multi(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010090 } else {
10091 /* Accept one or more multicast(s). */
Jiri Pirko22bedad2010-04-01 21:22:57 +000010092 struct netdev_hw_addr *ha;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010093 u32 mc_filter[4] = { 0, };
10094 u32 regidx;
10095 u32 bit;
10096 u32 crc;
10097
Jiri Pirko22bedad2010-04-01 21:22:57 +000010098 netdev_for_each_mc_addr(ha, dev) {
10099 crc = calc_crc(ha->addr, ETH_ALEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010100 bit = ~crc & 0x7f;
10101 regidx = (bit & 0x60) >> 5;
10102 bit &= 0x1f;
10103 mc_filter[regidx] |= (1 << bit);
10104 }
10105
10106 tw32(MAC_HASH_REG_0, mc_filter[0]);
10107 tw32(MAC_HASH_REG_1, mc_filter[1]);
10108 tw32(MAC_HASH_REG_2, mc_filter[2]);
10109 tw32(MAC_HASH_REG_3, mc_filter[3]);
10110 }
10111
10112 if (rx_mode != tp->rx_mode) {
10113 tp->rx_mode = rx_mode;
10114 tw32_f(MAC_RX_MODE, rx_mode);
10115 udelay(10);
10116 }
10117}
10118
10119static void tg3_set_rx_mode(struct net_device *dev)
10120{
10121 struct tg3 *tp = netdev_priv(dev);
10122
Michael Chane75f7c92006-03-20 21:33:26 -080010123 if (!netif_running(dev))
10124 return;
10125
David S. Millerf47c11e2005-06-24 20:18:35 -070010126 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010127 __tg3_set_rx_mode(dev);
David S. Millerf47c11e2005-06-24 20:18:35 -070010128 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010129}
10130
Linus Torvalds1da177e2005-04-16 15:20:36 -070010131static int tg3_get_regs_len(struct net_device *dev)
10132{
Matt Carlson97bd8e42011-04-13 11:05:04 +000010133 return TG3_REG_BLK_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010134}
10135
10136static void tg3_get_regs(struct net_device *dev,
10137 struct ethtool_regs *regs, void *_p)
10138{
Linus Torvalds1da177e2005-04-16 15:20:36 -070010139 struct tg3 *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010140
10141 regs->version = 0;
10142
Matt Carlson97bd8e42011-04-13 11:05:04 +000010143 memset(_p, 0, TG3_REG_BLK_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010144
Matt Carlson80096062010-08-02 11:26:06 +000010145 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -080010146 return;
10147
David S. Millerf47c11e2005-06-24 20:18:35 -070010148 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010149
Matt Carlson97bd8e42011-04-13 11:05:04 +000010150 tg3_dump_legacy_regs(tp, (u32 *)_p);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010151
David S. Millerf47c11e2005-06-24 20:18:35 -070010152 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010153}
10154
10155static int tg3_get_eeprom_len(struct net_device *dev)
10156{
10157 struct tg3 *tp = netdev_priv(dev);
10158
10159 return tp->nvram_size;
10160}
10161
Linus Torvalds1da177e2005-04-16 15:20:36 -070010162static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10163{
10164 struct tg3 *tp = netdev_priv(dev);
10165 int ret;
10166 u8 *pd;
Al Virob9fc7dc2007-12-17 22:59:57 -080010167 u32 i, offset, len, b_offset, b_count;
Matt Carlsona9dc5292009-02-25 14:25:30 +000010168 __be32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010169
Joe Perches63c3a662011-04-26 08:12:10 +000010170 if (tg3_flag(tp, NO_NVRAM))
Matt Carlsondf259d82009-04-20 06:57:14 +000010171 return -EINVAL;
10172
Matt Carlson80096062010-08-02 11:26:06 +000010173 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -080010174 return -EAGAIN;
10175
Linus Torvalds1da177e2005-04-16 15:20:36 -070010176 offset = eeprom->offset;
10177 len = eeprom->len;
10178 eeprom->len = 0;
10179
10180 eeprom->magic = TG3_EEPROM_MAGIC;
10181
10182 if (offset & 3) {
10183 /* adjustments to start on required 4 byte boundary */
10184 b_offset = offset & 3;
10185 b_count = 4 - b_offset;
10186 if (b_count > len) {
10187 /* i.e. offset=1 len=2 */
10188 b_count = len;
10189 }
Matt Carlsona9dc5292009-02-25 14:25:30 +000010190 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010191 if (ret)
10192 return ret;
Matt Carlsonbe98da62010-07-11 09:31:46 +000010193 memcpy(data, ((char *)&val) + b_offset, b_count);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010194 len -= b_count;
10195 offset += b_count;
Matt Carlsonc6cdf432010-04-05 10:19:26 +000010196 eeprom->len += b_count;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010197 }
10198
Lucas De Marchi25985ed2011-03-30 22:57:33 -030010199 /* read bytes up to the last 4 byte boundary */
Linus Torvalds1da177e2005-04-16 15:20:36 -070010200 pd = &data[eeprom->len];
10201 for (i = 0; i < (len - (len & 3)); i += 4) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000010202 ret = tg3_nvram_read_be32(tp, offset + i, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010203 if (ret) {
10204 eeprom->len += i;
10205 return ret;
10206 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070010207 memcpy(pd + i, &val, 4);
10208 }
10209 eeprom->len += i;
10210
10211 if (len & 3) {
10212 /* read last bytes not ending on 4 byte boundary */
10213 pd = &data[eeprom->len];
10214 b_count = len & 3;
10215 b_offset = offset + len - b_count;
Matt Carlsona9dc5292009-02-25 14:25:30 +000010216 ret = tg3_nvram_read_be32(tp, b_offset, &val);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010217 if (ret)
10218 return ret;
Al Virob9fc7dc2007-12-17 22:59:57 -080010219 memcpy(pd, &val, b_count);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010220 eeprom->len += b_count;
10221 }
10222 return 0;
10223}
10224
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010225static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010226
10227static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
10228{
10229 struct tg3 *tp = netdev_priv(dev);
10230 int ret;
Al Virob9fc7dc2007-12-17 22:59:57 -080010231 u32 offset, len, b_offset, odd_len;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010232 u8 *buf;
Matt Carlsona9dc5292009-02-25 14:25:30 +000010233 __be32 start, end;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010234
Matt Carlson80096062010-08-02 11:26:06 +000010235 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Michael Chanbc1c7562006-03-20 17:48:03 -080010236 return -EAGAIN;
10237
Joe Perches63c3a662011-04-26 08:12:10 +000010238 if (tg3_flag(tp, NO_NVRAM) ||
Matt Carlsondf259d82009-04-20 06:57:14 +000010239 eeprom->magic != TG3_EEPROM_MAGIC)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010240 return -EINVAL;
10241
10242 offset = eeprom->offset;
10243 len = eeprom->len;
10244
10245 if ((b_offset = (offset & 3))) {
10246 /* adjustments to start on required 4 byte boundary */
Matt Carlsona9dc5292009-02-25 14:25:30 +000010247 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010248 if (ret)
10249 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010250 len += b_offset;
10251 offset &= ~3;
Michael Chan1c8594b2005-04-21 17:12:46 -070010252 if (len < 4)
10253 len = 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010254 }
10255
10256 odd_len = 0;
Michael Chan1c8594b2005-04-21 17:12:46 -070010257 if (len & 3) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070010258 /* adjustments to end on required 4 byte boundary */
10259 odd_len = 1;
10260 len = (len + 3) & ~3;
Matt Carlsona9dc5292009-02-25 14:25:30 +000010261 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010262 if (ret)
10263 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010264 }
10265
10266 buf = data;
10267 if (b_offset || odd_len) {
10268 buf = kmalloc(len, GFP_KERNEL);
Andy Gospodarekab0049b2007-09-06 20:42:14 +010010269 if (!buf)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010270 return -ENOMEM;
10271 if (b_offset)
10272 memcpy(buf, &start, 4);
10273 if (odd_len)
10274 memcpy(buf+len-4, &end, 4);
10275 memcpy(buf + b_offset, data, eeprom->len);
10276 }
10277
10278 ret = tg3_nvram_write_block(tp, offset, len, buf);
10279
10280 if (buf != data)
10281 kfree(buf);
10282
10283 return ret;
10284}
10285
10286static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10287{
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010288 struct tg3 *tp = netdev_priv(dev);
10289
Joe Perches63c3a662011-04-26 08:12:10 +000010290 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010291 struct phy_device *phydev;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010292 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010293 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010294 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10295 return phy_ethtool_gset(phydev, cmd);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010296 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010297
Linus Torvalds1da177e2005-04-16 15:20:36 -070010298 cmd->supported = (SUPPORTED_Autoneg);
10299
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010300 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
Linus Torvalds1da177e2005-04-16 15:20:36 -070010301 cmd->supported |= (SUPPORTED_1000baseT_Half |
10302 SUPPORTED_1000baseT_Full);
10303
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010304 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070010305 cmd->supported |= (SUPPORTED_100baseT_Half |
10306 SUPPORTED_100baseT_Full |
10307 SUPPORTED_10baseT_Half |
10308 SUPPORTED_10baseT_Full |
Matt Carlson3bebab52007-11-12 21:22:40 -080010309 SUPPORTED_TP);
Karsten Keilef348142006-05-12 12:49:08 -070010310 cmd->port = PORT_TP;
10311 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070010312 cmd->supported |= SUPPORTED_FIBRE;
Karsten Keilef348142006-05-12 12:49:08 -070010313 cmd->port = PORT_FIBRE;
10314 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010315
Linus Torvalds1da177e2005-04-16 15:20:36 -070010316 cmd->advertising = tp->link_config.advertising;
Matt Carlson5bb09772011-06-13 13:39:00 +000010317 if (tg3_flag(tp, PAUSE_AUTONEG)) {
10318 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
10319 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10320 cmd->advertising |= ADVERTISED_Pause;
10321 } else {
10322 cmd->advertising |= ADVERTISED_Pause |
10323 ADVERTISED_Asym_Pause;
10324 }
10325 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
10326 cmd->advertising |= ADVERTISED_Asym_Pause;
10327 }
10328 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070010329 if (netif_running(dev)) {
David Decotigny70739492011-04-27 18:32:40 +000010330 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010331 cmd->duplex = tp->link_config.active_duplex;
Matt Carlson64c22182010-10-14 10:37:44 +000010332 } else {
David Decotigny70739492011-04-27 18:32:40 +000010333 ethtool_cmd_speed_set(cmd, SPEED_INVALID);
Matt Carlson64c22182010-10-14 10:37:44 +000010334 cmd->duplex = DUPLEX_INVALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010335 }
Matt Carlson882e9792009-09-01 13:21:36 +000010336 cmd->phy_address = tp->phy_addr;
Matt Carlson7e5856b2009-02-25 14:23:01 +000010337 cmd->transceiver = XCVR_INTERNAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010338 cmd->autoneg = tp->link_config.autoneg;
10339 cmd->maxtxpkt = 0;
10340 cmd->maxrxpkt = 0;
10341 return 0;
10342}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010343
Linus Torvalds1da177e2005-04-16 15:20:36 -070010344static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10345{
10346 struct tg3 *tp = netdev_priv(dev);
David Decotigny25db0332011-04-27 18:32:39 +000010347 u32 speed = ethtool_cmd_speed(cmd);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010348
Joe Perches63c3a662011-04-26 08:12:10 +000010349 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010350 struct phy_device *phydev;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010351 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010352 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010353 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10354 return phy_ethtool_sset(phydev, cmd);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010355 }
10356
Matt Carlson7e5856b2009-02-25 14:23:01 +000010357 if (cmd->autoneg != AUTONEG_ENABLE &&
10358 cmd->autoneg != AUTONEG_DISABLE)
Michael Chan37ff2382005-10-26 15:49:51 -070010359 return -EINVAL;
Matt Carlson7e5856b2009-02-25 14:23:01 +000010360
10361 if (cmd->autoneg == AUTONEG_DISABLE &&
10362 cmd->duplex != DUPLEX_FULL &&
10363 cmd->duplex != DUPLEX_HALF)
Michael Chan37ff2382005-10-26 15:49:51 -070010364 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010365
Matt Carlson7e5856b2009-02-25 14:23:01 +000010366 if (cmd->autoneg == AUTONEG_ENABLE) {
10367 u32 mask = ADVERTISED_Autoneg |
10368 ADVERTISED_Pause |
10369 ADVERTISED_Asym_Pause;
10370
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010371 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
Matt Carlson7e5856b2009-02-25 14:23:01 +000010372 mask |= ADVERTISED_1000baseT_Half |
10373 ADVERTISED_1000baseT_Full;
10374
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010375 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
Matt Carlson7e5856b2009-02-25 14:23:01 +000010376 mask |= ADVERTISED_100baseT_Half |
10377 ADVERTISED_100baseT_Full |
10378 ADVERTISED_10baseT_Half |
10379 ADVERTISED_10baseT_Full |
10380 ADVERTISED_TP;
10381 else
10382 mask |= ADVERTISED_FIBRE;
10383
10384 if (cmd->advertising & ~mask)
10385 return -EINVAL;
10386
10387 mask &= (ADVERTISED_1000baseT_Half |
10388 ADVERTISED_1000baseT_Full |
10389 ADVERTISED_100baseT_Half |
10390 ADVERTISED_100baseT_Full |
10391 ADVERTISED_10baseT_Half |
10392 ADVERTISED_10baseT_Full);
10393
10394 cmd->advertising &= mask;
10395 } else {
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010396 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
David Decotigny25db0332011-04-27 18:32:39 +000010397 if (speed != SPEED_1000)
Matt Carlson7e5856b2009-02-25 14:23:01 +000010398 return -EINVAL;
10399
10400 if (cmd->duplex != DUPLEX_FULL)
10401 return -EINVAL;
10402 } else {
David Decotigny25db0332011-04-27 18:32:39 +000010403 if (speed != SPEED_100 &&
10404 speed != SPEED_10)
Matt Carlson7e5856b2009-02-25 14:23:01 +000010405 return -EINVAL;
10406 }
10407 }
10408
David S. Millerf47c11e2005-06-24 20:18:35 -070010409 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010410
10411 tp->link_config.autoneg = cmd->autoneg;
10412 if (cmd->autoneg == AUTONEG_ENABLE) {
Andy Gospodarek405d8e52007-10-08 01:08:47 -070010413 tp->link_config.advertising = (cmd->advertising |
10414 ADVERTISED_Autoneg);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010415 tp->link_config.speed = SPEED_INVALID;
10416 tp->link_config.duplex = DUPLEX_INVALID;
10417 } else {
10418 tp->link_config.advertising = 0;
David Decotigny25db0332011-04-27 18:32:39 +000010419 tp->link_config.speed = speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010420 tp->link_config.duplex = cmd->duplex;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010421 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010422
Michael Chan24fcad62006-12-17 17:06:46 -080010423 tp->link_config.orig_speed = tp->link_config.speed;
10424 tp->link_config.orig_duplex = tp->link_config.duplex;
10425 tp->link_config.orig_autoneg = tp->link_config.autoneg;
10426
Linus Torvalds1da177e2005-04-16 15:20:36 -070010427 if (netif_running(dev))
10428 tg3_setup_phy(tp, 1);
10429
David S. Millerf47c11e2005-06-24 20:18:35 -070010430 tg3_full_unlock(tp);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010431
Linus Torvalds1da177e2005-04-16 15:20:36 -070010432 return 0;
10433}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010434
Linus Torvalds1da177e2005-04-16 15:20:36 -070010435static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
10436{
10437 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010438
Linus Torvalds1da177e2005-04-16 15:20:36 -070010439 strcpy(info->driver, DRV_MODULE_NAME);
10440 strcpy(info->version, DRV_MODULE_VERSION);
Michael Chanc4e65752006-03-20 22:29:32 -080010441 strcpy(info->fw_version, tp->fw_ver);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010442 strcpy(info->bus_info, pci_name(tp->pdev));
10443}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010444
Linus Torvalds1da177e2005-04-16 15:20:36 -070010445static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10446{
10447 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010448
Joe Perches63c3a662011-04-26 08:12:10 +000010449 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
Gary Zambranoa85feb82007-05-05 11:52:19 -070010450 wol->supported = WAKE_MAGIC;
10451 else
10452 wol->supported = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010453 wol->wolopts = 0;
Joe Perches63c3a662011-04-26 08:12:10 +000010454 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
Linus Torvalds1da177e2005-04-16 15:20:36 -070010455 wol->wolopts = WAKE_MAGIC;
10456 memset(&wol->sopass, 0, sizeof(wol->sopass));
10457}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010458
Linus Torvalds1da177e2005-04-16 15:20:36 -070010459static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
10460{
10461 struct tg3 *tp = netdev_priv(dev);
Rafael J. Wysocki12dac072008-07-30 16:37:33 -070010462 struct device *dp = &tp->pdev->dev;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010463
Linus Torvalds1da177e2005-04-16 15:20:36 -070010464 if (wol->wolopts & ~WAKE_MAGIC)
10465 return -EINVAL;
10466 if ((wol->wolopts & WAKE_MAGIC) &&
Joe Perches63c3a662011-04-26 08:12:10 +000010467 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
Linus Torvalds1da177e2005-04-16 15:20:36 -070010468 return -EINVAL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010469
Rafael J. Wysockif2dc0d12010-10-25 13:01:55 +000010470 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
10471
David S. Millerf47c11e2005-06-24 20:18:35 -070010472 spin_lock_bh(&tp->lock);
Rafael J. Wysockif2dc0d12010-10-25 13:01:55 +000010473 if (device_may_wakeup(dp))
Joe Perches63c3a662011-04-26 08:12:10 +000010474 tg3_flag_set(tp, WOL_ENABLE);
Rafael J. Wysockif2dc0d12010-10-25 13:01:55 +000010475 else
Joe Perches63c3a662011-04-26 08:12:10 +000010476 tg3_flag_clear(tp, WOL_ENABLE);
David S. Millerf47c11e2005-06-24 20:18:35 -070010477 spin_unlock_bh(&tp->lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010478
Linus Torvalds1da177e2005-04-16 15:20:36 -070010479 return 0;
10480}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010481
Linus Torvalds1da177e2005-04-16 15:20:36 -070010482static u32 tg3_get_msglevel(struct net_device *dev)
10483{
10484 struct tg3 *tp = netdev_priv(dev);
10485 return tp->msg_enable;
10486}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010487
Linus Torvalds1da177e2005-04-16 15:20:36 -070010488static void tg3_set_msglevel(struct net_device *dev, u32 value)
10489{
10490 struct tg3 *tp = netdev_priv(dev);
10491 tp->msg_enable = value;
10492}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010493
Linus Torvalds1da177e2005-04-16 15:20:36 -070010494static int tg3_nway_reset(struct net_device *dev)
10495{
10496 struct tg3 *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010497 int r;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010498
Linus Torvalds1da177e2005-04-16 15:20:36 -070010499 if (!netif_running(dev))
10500 return -EAGAIN;
10501
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010502 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Michael Chanc94e3942005-09-27 12:12:42 -070010503 return -EINVAL;
10504
Joe Perches63c3a662011-04-26 08:12:10 +000010505 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010506 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010507 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000010508 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010509 } else {
10510 u32 bmcr;
10511
10512 spin_lock_bh(&tp->lock);
10513 r = -EINVAL;
10514 tg3_readphy(tp, MII_BMCR, &bmcr);
10515 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10516 ((bmcr & BMCR_ANENABLE) ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010517 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010518 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10519 BMCR_ANENABLE);
10520 r = 0;
10521 }
10522 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010523 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010524
Linus Torvalds1da177e2005-04-16 15:20:36 -070010525 return r;
10526}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010527
Linus Torvalds1da177e2005-04-16 15:20:36 -070010528static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10529{
10530 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010531
Matt Carlson2c49a442010-09-30 10:34:35 +000010532 ering->rx_max_pending = tp->rx_std_ring_mask;
Joe Perches63c3a662011-04-26 08:12:10 +000010533 if (tg3_flag(tp, JUMBO_RING_ENABLE))
Matt Carlson2c49a442010-09-30 10:34:35 +000010534 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
Michael Chan4f81c322006-03-20 21:33:42 -080010535 else
10536 ering->rx_jumbo_max_pending = 0;
10537
10538 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010539
10540 ering->rx_pending = tp->rx_pending;
Joe Perches63c3a662011-04-26 08:12:10 +000010541 if (tg3_flag(tp, JUMBO_RING_ENABLE))
Michael Chan4f81c322006-03-20 21:33:42 -080010542 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10543 else
10544 ering->rx_jumbo_pending = 0;
10545
Matt Carlsonf3f3f272009-08-28 14:03:21 +000010546 ering->tx_pending = tp->napi[0].tx_pending;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010547}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010548
Linus Torvalds1da177e2005-04-16 15:20:36 -070010549static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10550{
10551 struct tg3 *tp = netdev_priv(dev);
Matt Carlson646c9ed2009-09-01 12:58:41 +000010552 int i, irq_sync = 0, err = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010553
Matt Carlson2c49a442010-09-30 10:34:35 +000010554 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10555 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
Michael Chanbc3a9252006-10-18 20:55:18 -070010556 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10557 (ering->tx_pending <= MAX_SKB_FRAGS) ||
Joe Perches63c3a662011-04-26 08:12:10 +000010558 (tg3_flag(tp, TSO_BUG) &&
Michael Chanbc3a9252006-10-18 20:55:18 -070010559 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
Linus Torvalds1da177e2005-04-16 15:20:36 -070010560 return -EINVAL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010561
Michael Chanbbe832c2005-06-24 20:20:04 -070010562 if (netif_running(dev)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010563 tg3_phy_stop(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010564 tg3_netif_stop(tp);
Michael Chanbbe832c2005-06-24 20:20:04 -070010565 irq_sync = 1;
10566 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070010567
Michael Chanbbe832c2005-06-24 20:20:04 -070010568 tg3_full_lock(tp, irq_sync);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010569
Linus Torvalds1da177e2005-04-16 15:20:36 -070010570 tp->rx_pending = ering->rx_pending;
10571
Joe Perches63c3a662011-04-26 08:12:10 +000010572 if (tg3_flag(tp, MAX_RXPEND_64) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -070010573 tp->rx_pending > 63)
10574 tp->rx_pending = 63;
10575 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
Matt Carlson646c9ed2009-09-01 12:58:41 +000010576
Matt Carlson6fd45cb2010-09-15 08:59:57 +000010577 for (i = 0; i < tp->irq_max; i++)
Matt Carlson646c9ed2009-09-01 12:58:41 +000010578 tp->napi[i].tx_pending = ering->tx_pending;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010579
10580 if (netif_running(dev)) {
Michael Chan944d9802005-05-29 14:57:48 -070010581 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Michael Chanb9ec6c12006-07-25 16:37:27 -070010582 err = tg3_restart_hw(tp, 1);
10583 if (!err)
10584 tg3_netif_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070010585 }
10586
David S. Millerf47c11e2005-06-24 20:18:35 -070010587 tg3_full_unlock(tp);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010588
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010589 if (irq_sync && !err)
10590 tg3_phy_start(tp);
10591
Michael Chanb9ec6c12006-07-25 16:37:27 -070010592 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010593}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010594
Linus Torvalds1da177e2005-04-16 15:20:36 -070010595static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10596{
10597 struct tg3 *tp = netdev_priv(dev);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010598
Joe Perches63c3a662011-04-26 08:12:10 +000010599 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
Matt Carlson8d018622007-12-20 20:05:44 -080010600
Steve Glendinninge18ce342008-12-16 02:00:00 -080010601 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
Matt Carlson8d018622007-12-20 20:05:44 -080010602 epause->rx_pause = 1;
10603 else
10604 epause->rx_pause = 0;
10605
Steve Glendinninge18ce342008-12-16 02:00:00 -080010606 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
Matt Carlson8d018622007-12-20 20:05:44 -080010607 epause->tx_pause = 1;
10608 else
10609 epause->tx_pause = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010610}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010611
Linus Torvalds1da177e2005-04-16 15:20:36 -070010612static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10613{
10614 struct tg3 *tp = netdev_priv(dev);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010615 int err = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010616
Joe Perches63c3a662011-04-26 08:12:10 +000010617 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson27121682010-02-17 15:16:57 +000010618 u32 newadv;
10619 struct phy_device *phydev;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010620
Matt Carlson27121682010-02-17 15:16:57 +000010621 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010622
Matt Carlson27121682010-02-17 15:16:57 +000010623 if (!(phydev->supported & SUPPORTED_Pause) ||
10624 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
Nicolas Kaiser2259dca2010-10-07 23:29:27 +000010625 (epause->rx_pause != epause->tx_pause)))
Matt Carlson27121682010-02-17 15:16:57 +000010626 return -EINVAL;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010627
Matt Carlson27121682010-02-17 15:16:57 +000010628 tp->link_config.flowctrl = 0;
10629 if (epause->rx_pause) {
10630 tp->link_config.flowctrl |= FLOW_CTRL_RX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010631
Matt Carlson27121682010-02-17 15:16:57 +000010632 if (epause->tx_pause) {
Steve Glendinninge18ce342008-12-16 02:00:00 -080010633 tp->link_config.flowctrl |= FLOW_CTRL_TX;
Matt Carlson27121682010-02-17 15:16:57 +000010634 newadv = ADVERTISED_Pause;
10635 } else
10636 newadv = ADVERTISED_Pause |
10637 ADVERTISED_Asym_Pause;
10638 } else if (epause->tx_pause) {
10639 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10640 newadv = ADVERTISED_Asym_Pause;
10641 } else
10642 newadv = 0;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010643
Matt Carlson27121682010-02-17 15:16:57 +000010644 if (epause->autoneg)
Joe Perches63c3a662011-04-26 08:12:10 +000010645 tg3_flag_set(tp, PAUSE_AUTONEG);
Matt Carlson27121682010-02-17 15:16:57 +000010646 else
Joe Perches63c3a662011-04-26 08:12:10 +000010647 tg3_flag_clear(tp, PAUSE_AUTONEG);
Matt Carlson27121682010-02-17 15:16:57 +000010648
Matt Carlsonf07e9af2010-08-02 11:26:07 +000010649 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
Matt Carlson27121682010-02-17 15:16:57 +000010650 u32 oldadv = phydev->advertising &
10651 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10652 if (oldadv != newadv) {
10653 phydev->advertising &=
10654 ~(ADVERTISED_Pause |
10655 ADVERTISED_Asym_Pause);
10656 phydev->advertising |= newadv;
10657 if (phydev->autoneg) {
10658 /*
10659 * Always renegotiate the link to
10660 * inform our link partner of our
10661 * flow control settings, even if the
10662 * flow control is forced. Let
10663 * tg3_adjust_link() do the final
10664 * flow control setup.
10665 */
10666 return phy_start_aneg(phydev);
10667 }
10668 }
10669
10670 if (!epause->autoneg)
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010671 tg3_setup_flow_control(tp, 0, 0);
Matt Carlson27121682010-02-17 15:16:57 +000010672 } else {
10673 tp->link_config.orig_advertising &=
10674 ~(ADVERTISED_Pause |
10675 ADVERTISED_Asym_Pause);
10676 tp->link_config.orig_advertising |= newadv;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010677 }
10678 } else {
10679 int irq_sync = 0;
10680
10681 if (netif_running(dev)) {
10682 tg3_netif_stop(tp);
10683 irq_sync = 1;
10684 }
10685
10686 tg3_full_lock(tp, irq_sync);
10687
10688 if (epause->autoneg)
Joe Perches63c3a662011-04-26 08:12:10 +000010689 tg3_flag_set(tp, PAUSE_AUTONEG);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010690 else
Joe Perches63c3a662011-04-26 08:12:10 +000010691 tg3_flag_clear(tp, PAUSE_AUTONEG);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010692 if (epause->rx_pause)
Steve Glendinninge18ce342008-12-16 02:00:00 -080010693 tp->link_config.flowctrl |= FLOW_CTRL_RX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010694 else
Steve Glendinninge18ce342008-12-16 02:00:00 -080010695 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010696 if (epause->tx_pause)
Steve Glendinninge18ce342008-12-16 02:00:00 -080010697 tp->link_config.flowctrl |= FLOW_CTRL_TX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010698 else
Steve Glendinninge18ce342008-12-16 02:00:00 -080010699 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070010700
10701 if (netif_running(dev)) {
10702 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10703 err = tg3_restart_hw(tp, 1);
10704 if (!err)
10705 tg3_netif_start(tp);
10706 }
10707
10708 tg3_full_unlock(tp);
Michael Chanbbe832c2005-06-24 20:20:04 -070010709 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070010710
Michael Chanb9ec6c12006-07-25 16:37:27 -070010711 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010712}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010713
Matt Carlsonde6f31e2010-04-12 06:58:30 +000010714static int tg3_get_sset_count(struct net_device *dev, int sset)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010715{
Jeff Garzikb9f2c042007-10-03 18:07:32 -070010716 switch (sset) {
10717 case ETH_SS_TEST:
10718 return TG3_NUM_TEST;
10719 case ETH_SS_STATS:
10720 return TG3_NUM_STATS;
10721 default:
10722 return -EOPNOTSUPP;
10723 }
Michael Chan4cafd3f2005-05-29 14:56:34 -070010724}
10725
Matt Carlsonde6f31e2010-04-12 06:58:30 +000010726static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
Linus Torvalds1da177e2005-04-16 15:20:36 -070010727{
10728 switch (stringset) {
10729 case ETH_SS_STATS:
10730 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10731 break;
Michael Chan4cafd3f2005-05-29 14:56:34 -070010732 case ETH_SS_TEST:
10733 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10734 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -070010735 default:
10736 WARN_ON(1); /* we need a WARN() */
10737 break;
10738 }
10739}
10740
stephen hemminger81b87092011-04-04 08:43:50 +000010741static int tg3_set_phys_id(struct net_device *dev,
10742 enum ethtool_phys_id_state state)
Michael Chan4009a932005-09-05 17:52:54 -070010743{
10744 struct tg3 *tp = netdev_priv(dev);
Michael Chan4009a932005-09-05 17:52:54 -070010745
10746 if (!netif_running(tp->dev))
10747 return -EAGAIN;
10748
stephen hemminger81b87092011-04-04 08:43:50 +000010749 switch (state) {
10750 case ETHTOOL_ID_ACTIVE:
Allan, Bruce Wfce55922011-04-13 13:09:10 +000010751 return 1; /* cycle on/off once per second */
Michael Chan4009a932005-09-05 17:52:54 -070010752
stephen hemminger81b87092011-04-04 08:43:50 +000010753 case ETHTOOL_ID_ON:
10754 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10755 LED_CTRL_1000MBPS_ON |
10756 LED_CTRL_100MBPS_ON |
10757 LED_CTRL_10MBPS_ON |
10758 LED_CTRL_TRAFFIC_OVERRIDE |
10759 LED_CTRL_TRAFFIC_BLINK |
10760 LED_CTRL_TRAFFIC_LED);
10761 break;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040010762
stephen hemminger81b87092011-04-04 08:43:50 +000010763 case ETHTOOL_ID_OFF:
10764 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10765 LED_CTRL_TRAFFIC_OVERRIDE);
10766 break;
Michael Chan4009a932005-09-05 17:52:54 -070010767
stephen hemminger81b87092011-04-04 08:43:50 +000010768 case ETHTOOL_ID_INACTIVE:
10769 tw32(MAC_LED_CTRL, tp->led_ctrl);
10770 break;
Michael Chan4009a932005-09-05 17:52:54 -070010771 }
stephen hemminger81b87092011-04-04 08:43:50 +000010772
Michael Chan4009a932005-09-05 17:52:54 -070010773 return 0;
10774}
10775
Matt Carlsonde6f31e2010-04-12 06:58:30 +000010776static void tg3_get_ethtool_stats(struct net_device *dev,
Linus Torvalds1da177e2005-04-16 15:20:36 -070010777 struct ethtool_stats *estats, u64 *tmp_stats)
10778{
10779 struct tg3 *tp = netdev_priv(dev);
10780 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10781}
10782
Matt Carlson535a4902011-07-20 10:20:56 +000010783static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
Matt Carlsonc3e94502011-04-13 11:05:08 +000010784{
10785 int i;
10786 __be32 *buf;
10787 u32 offset = 0, len = 0;
10788 u32 magic, val;
10789
Joe Perches63c3a662011-04-26 08:12:10 +000010790 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
Matt Carlsonc3e94502011-04-13 11:05:08 +000010791 return NULL;
10792
10793 if (magic == TG3_EEPROM_MAGIC) {
10794 for (offset = TG3_NVM_DIR_START;
10795 offset < TG3_NVM_DIR_END;
10796 offset += TG3_NVM_DIRENT_SIZE) {
10797 if (tg3_nvram_read(tp, offset, &val))
10798 return NULL;
10799
10800 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
10801 TG3_NVM_DIRTYPE_EXTVPD)
10802 break;
10803 }
10804
10805 if (offset != TG3_NVM_DIR_END) {
10806 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
10807 if (tg3_nvram_read(tp, offset + 4, &offset))
10808 return NULL;
10809
10810 offset = tg3_nvram_logical_addr(tp, offset);
10811 }
10812 }
10813
10814 if (!offset || !len) {
10815 offset = TG3_NVM_VPD_OFF;
10816 len = TG3_NVM_VPD_LEN;
10817 }
10818
10819 buf = kmalloc(len, GFP_KERNEL);
10820 if (buf == NULL)
10821 return NULL;
10822
10823 if (magic == TG3_EEPROM_MAGIC) {
10824 for (i = 0; i < len; i += 4) {
10825 /* The data is in little-endian format in NVRAM.
10826 * Use the big-endian read routines to preserve
10827 * the byte order as it exists in NVRAM.
10828 */
10829 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
10830 goto error;
10831 }
10832 } else {
10833 u8 *ptr;
10834 ssize_t cnt;
10835 unsigned int pos = 0;
10836
10837 ptr = (u8 *)&buf[0];
10838 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
10839 cnt = pci_read_vpd(tp->pdev, pos,
10840 len - pos, ptr);
10841 if (cnt == -ETIMEDOUT || cnt == -EINTR)
10842 cnt = 0;
10843 else if (cnt < 0)
10844 goto error;
10845 }
10846 if (pos != len)
10847 goto error;
10848 }
10849
Matt Carlson535a4902011-07-20 10:20:56 +000010850 *vpdlen = len;
10851
Matt Carlsonc3e94502011-04-13 11:05:08 +000010852 return buf;
10853
10854error:
10855 kfree(buf);
10856 return NULL;
10857}
10858
Michael Chan566f86a2005-05-29 14:56:58 -070010859#define NVRAM_TEST_SIZE 0x100
Matt Carlsona5767de2007-11-12 21:10:58 -080010860#define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10861#define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10862#define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
Matt Carlson727a6d92011-06-13 13:38:58 +000010863#define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
10864#define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
Matt Carlsonbda18fa2011-07-20 10:20:57 +000010865#define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
Michael Chanb16250e2006-09-27 16:10:14 -070010866#define NVRAM_SELFBOOT_HW_SIZE 0x20
10867#define NVRAM_SELFBOOT_DATA_SIZE 0x1c
Michael Chan566f86a2005-05-29 14:56:58 -070010868
10869static int tg3_test_nvram(struct tg3 *tp)
10870{
Matt Carlson535a4902011-07-20 10:20:56 +000010871 u32 csum, magic, len;
Matt Carlsona9dc5292009-02-25 14:25:30 +000010872 __be32 *buf;
Andy Gospodarekab0049b2007-09-06 20:42:14 +010010873 int i, j, k, err = 0, size;
Michael Chan566f86a2005-05-29 14:56:58 -070010874
Joe Perches63c3a662011-04-26 08:12:10 +000010875 if (tg3_flag(tp, NO_NVRAM))
Matt Carlsondf259d82009-04-20 06:57:14 +000010876 return 0;
10877
Matt Carlsone4f34112009-02-25 14:25:00 +000010878 if (tg3_nvram_read(tp, 0, &magic) != 0)
Michael Chan1b277772006-03-20 22:27:48 -080010879 return -EIO;
10880
Michael Chan1b277772006-03-20 22:27:48 -080010881 if (magic == TG3_EEPROM_MAGIC)
10882 size = NVRAM_TEST_SIZE;
Michael Chanb16250e2006-09-27 16:10:14 -070010883 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
Matt Carlsona5767de2007-11-12 21:10:58 -080010884 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10885 TG3_EEPROM_SB_FORMAT_1) {
10886 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10887 case TG3_EEPROM_SB_REVISION_0:
10888 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10889 break;
10890 case TG3_EEPROM_SB_REVISION_2:
10891 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10892 break;
10893 case TG3_EEPROM_SB_REVISION_3:
10894 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10895 break;
Matt Carlson727a6d92011-06-13 13:38:58 +000010896 case TG3_EEPROM_SB_REVISION_4:
10897 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
10898 break;
10899 case TG3_EEPROM_SB_REVISION_5:
10900 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
10901 break;
10902 case TG3_EEPROM_SB_REVISION_6:
10903 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
10904 break;
Matt Carlsona5767de2007-11-12 21:10:58 -080010905 default:
Matt Carlson727a6d92011-06-13 13:38:58 +000010906 return -EIO;
Matt Carlsona5767de2007-11-12 21:10:58 -080010907 }
10908 } else
Michael Chan1b277772006-03-20 22:27:48 -080010909 return 0;
Michael Chanb16250e2006-09-27 16:10:14 -070010910 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10911 size = NVRAM_SELFBOOT_HW_SIZE;
10912 else
Michael Chan1b277772006-03-20 22:27:48 -080010913 return -EIO;
10914
10915 buf = kmalloc(size, GFP_KERNEL);
Michael Chan566f86a2005-05-29 14:56:58 -070010916 if (buf == NULL)
10917 return -ENOMEM;
10918
Michael Chan1b277772006-03-20 22:27:48 -080010919 err = -EIO;
10920 for (i = 0, j = 0; i < size; i += 4, j++) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000010921 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10922 if (err)
Michael Chan566f86a2005-05-29 14:56:58 -070010923 break;
Michael Chan566f86a2005-05-29 14:56:58 -070010924 }
Michael Chan1b277772006-03-20 22:27:48 -080010925 if (i < size)
Michael Chan566f86a2005-05-29 14:56:58 -070010926 goto out;
10927
Michael Chan1b277772006-03-20 22:27:48 -080010928 /* Selfboot format */
Matt Carlsona9dc5292009-02-25 14:25:30 +000010929 magic = be32_to_cpu(buf[0]);
Al Virob9fc7dc2007-12-17 22:59:57 -080010930 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
Michael Chanb16250e2006-09-27 16:10:14 -070010931 TG3_EEPROM_MAGIC_FW) {
Michael Chan1b277772006-03-20 22:27:48 -080010932 u8 *buf8 = (u8 *) buf, csum8 = 0;
10933
Al Virob9fc7dc2007-12-17 22:59:57 -080010934 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
Matt Carlsona5767de2007-11-12 21:10:58 -080010935 TG3_EEPROM_SB_REVISION_2) {
10936 /* For rev 2, the csum doesn't include the MBA. */
10937 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10938 csum8 += buf8[i];
10939 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10940 csum8 += buf8[i];
10941 } else {
10942 for (i = 0; i < size; i++)
10943 csum8 += buf8[i];
10944 }
Michael Chan1b277772006-03-20 22:27:48 -080010945
Adrian Bunkad96b482006-04-05 22:21:04 -070010946 if (csum8 == 0) {
10947 err = 0;
10948 goto out;
10949 }
10950
10951 err = -EIO;
10952 goto out;
Michael Chan1b277772006-03-20 22:27:48 -080010953 }
Michael Chan566f86a2005-05-29 14:56:58 -070010954
Al Virob9fc7dc2007-12-17 22:59:57 -080010955 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
Michael Chanb16250e2006-09-27 16:10:14 -070010956 TG3_EEPROM_MAGIC_HW) {
10957 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
Matt Carlsona9dc5292009-02-25 14:25:30 +000010958 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
Michael Chanb16250e2006-09-27 16:10:14 -070010959 u8 *buf8 = (u8 *) buf;
Michael Chanb16250e2006-09-27 16:10:14 -070010960
10961 /* Separate the parity bits and the data bytes. */
10962 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10963 if ((i == 0) || (i == 8)) {
10964 int l;
10965 u8 msk;
10966
10967 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10968 parity[k++] = buf8[i] & msk;
10969 i++;
Matt Carlson859a5882010-04-05 10:19:28 +000010970 } else if (i == 16) {
Michael Chanb16250e2006-09-27 16:10:14 -070010971 int l;
10972 u8 msk;
10973
10974 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10975 parity[k++] = buf8[i] & msk;
10976 i++;
10977
10978 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10979 parity[k++] = buf8[i] & msk;
10980 i++;
10981 }
10982 data[j++] = buf8[i];
10983 }
10984
10985 err = -EIO;
10986 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10987 u8 hw8 = hweight8(data[i]);
10988
10989 if ((hw8 & 0x1) && parity[i])
10990 goto out;
10991 else if (!(hw8 & 0x1) && !parity[i])
10992 goto out;
10993 }
10994 err = 0;
10995 goto out;
10996 }
10997
Matt Carlson01c3a392011-03-09 16:58:20 +000010998 err = -EIO;
10999
Michael Chan566f86a2005-05-29 14:56:58 -070011000 /* Bootstrap checksum at offset 0x10 */
11001 csum = calc_crc((unsigned char *) buf, 0x10);
Matt Carlson01c3a392011-03-09 16:58:20 +000011002 if (csum != le32_to_cpu(buf[0x10/4]))
Michael Chan566f86a2005-05-29 14:56:58 -070011003 goto out;
11004
11005 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
11006 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
Matt Carlson01c3a392011-03-09 16:58:20 +000011007 if (csum != le32_to_cpu(buf[0xfc/4]))
Matt Carlsona9dc5292009-02-25 14:25:30 +000011008 goto out;
Michael Chan566f86a2005-05-29 14:56:58 -070011009
Matt Carlsonc3e94502011-04-13 11:05:08 +000011010 kfree(buf);
11011
Matt Carlson535a4902011-07-20 10:20:56 +000011012 buf = tg3_vpd_readblock(tp, &len);
Matt Carlsonc3e94502011-04-13 11:05:08 +000011013 if (!buf)
11014 return -ENOMEM;
Matt Carlsond4894f32011-03-09 16:58:21 +000011015
Matt Carlson535a4902011-07-20 10:20:56 +000011016 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
Matt Carlsond4894f32011-03-09 16:58:21 +000011017 if (i > 0) {
11018 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
11019 if (j < 0)
11020 goto out;
11021
Matt Carlson535a4902011-07-20 10:20:56 +000011022 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
Matt Carlsond4894f32011-03-09 16:58:21 +000011023 goto out;
11024
11025 i += PCI_VPD_LRDT_TAG_SIZE;
11026 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
11027 PCI_VPD_RO_KEYWORD_CHKSUM);
11028 if (j > 0) {
11029 u8 csum8 = 0;
11030
11031 j += PCI_VPD_INFO_FLD_HDR_SIZE;
11032
11033 for (i = 0; i <= j; i++)
11034 csum8 += ((u8 *)buf)[i];
11035
11036 if (csum8)
11037 goto out;
11038 }
11039 }
11040
Michael Chan566f86a2005-05-29 14:56:58 -070011041 err = 0;
11042
11043out:
11044 kfree(buf);
11045 return err;
11046}
11047
Michael Chanca430072005-05-29 14:57:23 -070011048#define TG3_SERDES_TIMEOUT_SEC 2
11049#define TG3_COPPER_TIMEOUT_SEC 6
11050
11051static int tg3_test_link(struct tg3 *tp)
11052{
11053 int i, max;
11054
11055 if (!netif_running(tp->dev))
11056 return -ENODEV;
11057
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011058 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
Michael Chanca430072005-05-29 14:57:23 -070011059 max = TG3_SERDES_TIMEOUT_SEC;
11060 else
11061 max = TG3_COPPER_TIMEOUT_SEC;
11062
11063 for (i = 0; i < max; i++) {
11064 if (netif_carrier_ok(tp->dev))
11065 return 0;
11066
11067 if (msleep_interruptible(1000))
11068 break;
11069 }
11070
11071 return -EIO;
11072}
11073
Michael Chana71116d2005-05-29 14:58:11 -070011074/* Only test the commonly used registers */
David S. Miller30ca3e32006-03-20 23:02:36 -080011075static int tg3_test_registers(struct tg3 *tp)
Michael Chana71116d2005-05-29 14:58:11 -070011076{
Michael Chanb16250e2006-09-27 16:10:14 -070011077 int i, is_5705, is_5750;
Michael Chana71116d2005-05-29 14:58:11 -070011078 u32 offset, read_mask, write_mask, val, save_val, read_val;
11079 static struct {
11080 u16 offset;
11081 u16 flags;
11082#define TG3_FL_5705 0x1
11083#define TG3_FL_NOT_5705 0x2
11084#define TG3_FL_NOT_5788 0x4
Michael Chanb16250e2006-09-27 16:10:14 -070011085#define TG3_FL_NOT_5750 0x8
Michael Chana71116d2005-05-29 14:58:11 -070011086 u32 read_mask;
11087 u32 write_mask;
11088 } reg_tbl[] = {
11089 /* MAC Control Registers */
11090 { MAC_MODE, TG3_FL_NOT_5705,
11091 0x00000000, 0x00ef6f8c },
11092 { MAC_MODE, TG3_FL_5705,
11093 0x00000000, 0x01ef6b8c },
11094 { MAC_STATUS, TG3_FL_NOT_5705,
11095 0x03800107, 0x00000000 },
11096 { MAC_STATUS, TG3_FL_5705,
11097 0x03800100, 0x00000000 },
11098 { MAC_ADDR_0_HIGH, 0x0000,
11099 0x00000000, 0x0000ffff },
11100 { MAC_ADDR_0_LOW, 0x0000,
Matt Carlsonc6cdf432010-04-05 10:19:26 +000011101 0x00000000, 0xffffffff },
Michael Chana71116d2005-05-29 14:58:11 -070011102 { MAC_RX_MTU_SIZE, 0x0000,
11103 0x00000000, 0x0000ffff },
11104 { MAC_TX_MODE, 0x0000,
11105 0x00000000, 0x00000070 },
11106 { MAC_TX_LENGTHS, 0x0000,
11107 0x00000000, 0x00003fff },
11108 { MAC_RX_MODE, TG3_FL_NOT_5705,
11109 0x00000000, 0x000007fc },
11110 { MAC_RX_MODE, TG3_FL_5705,
11111 0x00000000, 0x000007dc },
11112 { MAC_HASH_REG_0, 0x0000,
11113 0x00000000, 0xffffffff },
11114 { MAC_HASH_REG_1, 0x0000,
11115 0x00000000, 0xffffffff },
11116 { MAC_HASH_REG_2, 0x0000,
11117 0x00000000, 0xffffffff },
11118 { MAC_HASH_REG_3, 0x0000,
11119 0x00000000, 0xffffffff },
11120
11121 /* Receive Data and Receive BD Initiator Control Registers. */
11122 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
11123 0x00000000, 0xffffffff },
11124 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
11125 0x00000000, 0xffffffff },
11126 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
11127 0x00000000, 0x00000003 },
11128 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
11129 0x00000000, 0xffffffff },
11130 { RCVDBDI_STD_BD+0, 0x0000,
11131 0x00000000, 0xffffffff },
11132 { RCVDBDI_STD_BD+4, 0x0000,
11133 0x00000000, 0xffffffff },
11134 { RCVDBDI_STD_BD+8, 0x0000,
11135 0x00000000, 0xffff0002 },
11136 { RCVDBDI_STD_BD+0xc, 0x0000,
11137 0x00000000, 0xffffffff },
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011138
Michael Chana71116d2005-05-29 14:58:11 -070011139 /* Receive BD Initiator Control Registers. */
11140 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
11141 0x00000000, 0xffffffff },
11142 { RCVBDI_STD_THRESH, TG3_FL_5705,
11143 0x00000000, 0x000003ff },
11144 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
11145 0x00000000, 0xffffffff },
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011146
Michael Chana71116d2005-05-29 14:58:11 -070011147 /* Host Coalescing Control Registers. */
11148 { HOSTCC_MODE, TG3_FL_NOT_5705,
11149 0x00000000, 0x00000004 },
11150 { HOSTCC_MODE, TG3_FL_5705,
11151 0x00000000, 0x000000f6 },
11152 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
11153 0x00000000, 0xffffffff },
11154 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
11155 0x00000000, 0x000003ff },
11156 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
11157 0x00000000, 0xffffffff },
11158 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
11159 0x00000000, 0x000003ff },
11160 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
11161 0x00000000, 0xffffffff },
11162 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11163 0x00000000, 0x000000ff },
11164 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
11165 0x00000000, 0xffffffff },
11166 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
11167 0x00000000, 0x000000ff },
11168 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
11169 0x00000000, 0xffffffff },
11170 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
11171 0x00000000, 0xffffffff },
11172 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11173 0x00000000, 0xffffffff },
11174 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11175 0x00000000, 0x000000ff },
11176 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
11177 0x00000000, 0xffffffff },
11178 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
11179 0x00000000, 0x000000ff },
11180 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
11181 0x00000000, 0xffffffff },
11182 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
11183 0x00000000, 0xffffffff },
11184 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
11185 0x00000000, 0xffffffff },
11186 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
11187 0x00000000, 0xffffffff },
11188 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
11189 0x00000000, 0xffffffff },
11190 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
11191 0xffffffff, 0x00000000 },
11192 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
11193 0xffffffff, 0x00000000 },
11194
11195 /* Buffer Manager Control Registers. */
Michael Chanb16250e2006-09-27 16:10:14 -070011196 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
Michael Chana71116d2005-05-29 14:58:11 -070011197 0x00000000, 0x007fff80 },
Michael Chanb16250e2006-09-27 16:10:14 -070011198 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
Michael Chana71116d2005-05-29 14:58:11 -070011199 0x00000000, 0x007fffff },
11200 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
11201 0x00000000, 0x0000003f },
11202 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
11203 0x00000000, 0x000001ff },
11204 { BUFMGR_MB_HIGH_WATER, 0x0000,
11205 0x00000000, 0x000001ff },
11206 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
11207 0xffffffff, 0x00000000 },
11208 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
11209 0xffffffff, 0x00000000 },
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011210
Michael Chana71116d2005-05-29 14:58:11 -070011211 /* Mailbox Registers */
11212 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
11213 0x00000000, 0x000001ff },
11214 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
11215 0x00000000, 0x000001ff },
11216 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
11217 0x00000000, 0x000007ff },
11218 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
11219 0x00000000, 0x000001ff },
11220
11221 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
11222 };
11223
Michael Chanb16250e2006-09-27 16:10:14 -070011224 is_5705 = is_5750 = 0;
Joe Perches63c3a662011-04-26 08:12:10 +000011225 if (tg3_flag(tp, 5705_PLUS)) {
Michael Chana71116d2005-05-29 14:58:11 -070011226 is_5705 = 1;
Joe Perches63c3a662011-04-26 08:12:10 +000011227 if (tg3_flag(tp, 5750_PLUS))
Michael Chanb16250e2006-09-27 16:10:14 -070011228 is_5750 = 1;
11229 }
Michael Chana71116d2005-05-29 14:58:11 -070011230
11231 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
11232 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
11233 continue;
11234
11235 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
11236 continue;
11237
Joe Perches63c3a662011-04-26 08:12:10 +000011238 if (tg3_flag(tp, IS_5788) &&
Michael Chana71116d2005-05-29 14:58:11 -070011239 (reg_tbl[i].flags & TG3_FL_NOT_5788))
11240 continue;
11241
Michael Chanb16250e2006-09-27 16:10:14 -070011242 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
11243 continue;
11244
Michael Chana71116d2005-05-29 14:58:11 -070011245 offset = (u32) reg_tbl[i].offset;
11246 read_mask = reg_tbl[i].read_mask;
11247 write_mask = reg_tbl[i].write_mask;
11248
11249 /* Save the original register content */
11250 save_val = tr32(offset);
11251
11252 /* Determine the read-only value. */
11253 read_val = save_val & read_mask;
11254
11255 /* Write zero to the register, then make sure the read-only bits
11256 * are not changed and the read/write bits are all zeros.
11257 */
11258 tw32(offset, 0);
11259
11260 val = tr32(offset);
11261
11262 /* Test the read-only and read/write bits. */
11263 if (((val & read_mask) != read_val) || (val & write_mask))
11264 goto out;
11265
11266 /* Write ones to all the bits defined by RdMask and WrMask, then
11267 * make sure the read-only bits are not changed and the
11268 * read/write bits are all ones.
11269 */
11270 tw32(offset, read_mask | write_mask);
11271
11272 val = tr32(offset);
11273
11274 /* Test the read-only bits. */
11275 if ((val & read_mask) != read_val)
11276 goto out;
11277
11278 /* Test the read/write bits. */
11279 if ((val & write_mask) != write_mask)
11280 goto out;
11281
11282 tw32(offset, save_val);
11283 }
11284
11285 return 0;
11286
11287out:
Michael Chan9f88f292006-12-07 00:22:54 -080011288 if (netif_msg_hw(tp))
Matt Carlson2445e462010-04-05 10:19:21 +000011289 netdev_err(tp->dev,
11290 "Register test failed at offset %x\n", offset);
Michael Chana71116d2005-05-29 14:58:11 -070011291 tw32(offset, save_val);
11292 return -EIO;
11293}
11294
Michael Chan7942e1d2005-05-29 14:58:36 -070011295static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
11296{
Arjan van de Venf71e1302006-03-03 21:33:57 -050011297 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
Michael Chan7942e1d2005-05-29 14:58:36 -070011298 int i;
11299 u32 j;
11300
Alejandro Martinez Ruize9edda62007-10-15 03:37:43 +020011301 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
Michael Chan7942e1d2005-05-29 14:58:36 -070011302 for (j = 0; j < len; j += 4) {
11303 u32 val;
11304
11305 tg3_write_mem(tp, offset + j, test_pattern[i]);
11306 tg3_read_mem(tp, offset + j, &val);
11307 if (val != test_pattern[i])
11308 return -EIO;
11309 }
11310 }
11311 return 0;
11312}
11313
11314static int tg3_test_memory(struct tg3 *tp)
11315{
11316 static struct mem_entry {
11317 u32 offset;
11318 u32 len;
11319 } mem_tbl_570x[] = {
Michael Chan38690192005-12-19 16:27:28 -080011320 { 0x00000000, 0x00b50},
Michael Chan7942e1d2005-05-29 14:58:36 -070011321 { 0x00002000, 0x1c000},
11322 { 0xffffffff, 0x00000}
11323 }, mem_tbl_5705[] = {
11324 { 0x00000100, 0x0000c},
11325 { 0x00000200, 0x00008},
Michael Chan7942e1d2005-05-29 14:58:36 -070011326 { 0x00004000, 0x00800},
11327 { 0x00006000, 0x01000},
11328 { 0x00008000, 0x02000},
11329 { 0x00010000, 0x0e000},
11330 { 0xffffffff, 0x00000}
Michael Chan79f4d132006-03-20 22:28:57 -080011331 }, mem_tbl_5755[] = {
11332 { 0x00000200, 0x00008},
11333 { 0x00004000, 0x00800},
11334 { 0x00006000, 0x00800},
11335 { 0x00008000, 0x02000},
11336 { 0x00010000, 0x0c000},
11337 { 0xffffffff, 0x00000}
Michael Chanb16250e2006-09-27 16:10:14 -070011338 }, mem_tbl_5906[] = {
11339 { 0x00000200, 0x00008},
11340 { 0x00004000, 0x00400},
11341 { 0x00006000, 0x00400},
11342 { 0x00008000, 0x01000},
11343 { 0x00010000, 0x01000},
11344 { 0xffffffff, 0x00000}
Matt Carlson8b5a6c42010-01-20 16:58:06 +000011345 }, mem_tbl_5717[] = {
11346 { 0x00000200, 0x00008},
11347 { 0x00010000, 0x0a000},
11348 { 0x00020000, 0x13c00},
11349 { 0xffffffff, 0x00000}
11350 }, mem_tbl_57765[] = {
11351 { 0x00000200, 0x00008},
11352 { 0x00004000, 0x00800},
11353 { 0x00006000, 0x09800},
11354 { 0x00010000, 0x0a000},
11355 { 0xffffffff, 0x00000}
Michael Chan7942e1d2005-05-29 14:58:36 -070011356 };
11357 struct mem_entry *mem_tbl;
11358 int err = 0;
11359 int i;
11360
Joe Perches63c3a662011-04-26 08:12:10 +000011361 if (tg3_flag(tp, 5717_PLUS))
Matt Carlson8b5a6c42010-01-20 16:58:06 +000011362 mem_tbl = mem_tbl_5717;
11363 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11364 mem_tbl = mem_tbl_57765;
Joe Perches63c3a662011-04-26 08:12:10 +000011365 else if (tg3_flag(tp, 5755_PLUS))
Matt Carlson321d32a2008-11-21 17:22:19 -080011366 mem_tbl = mem_tbl_5755;
11367 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11368 mem_tbl = mem_tbl_5906;
Joe Perches63c3a662011-04-26 08:12:10 +000011369 else if (tg3_flag(tp, 5705_PLUS))
Matt Carlson321d32a2008-11-21 17:22:19 -080011370 mem_tbl = mem_tbl_5705;
11371 else
Michael Chan7942e1d2005-05-29 14:58:36 -070011372 mem_tbl = mem_tbl_570x;
11373
11374 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
Matt Carlsonbe98da62010-07-11 09:31:46 +000011375 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
11376 if (err)
Michael Chan7942e1d2005-05-29 14:58:36 -070011377 break;
11378 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011379
Michael Chan7942e1d2005-05-29 14:58:36 -070011380 return err;
11381}
11382
Matt Carlsonbb158d62011-04-25 12:42:47 +000011383#define TG3_TSO_MSS 500
11384
11385#define TG3_TSO_IP_HDR_LEN 20
11386#define TG3_TSO_TCP_HDR_LEN 20
11387#define TG3_TSO_TCP_OPT_LEN 12
11388
11389static const u8 tg3_tso_header[] = {
113900x08, 0x00,
113910x45, 0x00, 0x00, 0x00,
113920x00, 0x00, 0x40, 0x00,
113930x40, 0x06, 0x00, 0x00,
113940x0a, 0x00, 0x00, 0x01,
113950x0a, 0x00, 0x00, 0x02,
113960x0d, 0x00, 0xe0, 0x00,
113970x00, 0x00, 0x01, 0x00,
113980x00, 0x00, 0x02, 0x00,
113990x80, 0x10, 0x10, 0x00,
114000x14, 0x09, 0x00, 0x00,
114010x01, 0x01, 0x08, 0x0a,
114020x11, 0x11, 0x11, 0x11,
114030x11, 0x11, 0x11, 0x11,
11404};
Michael Chan9f40dea2005-09-05 17:53:06 -070011405
Matt Carlson28a45952011-08-19 13:58:22 +000011406static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
Michael Chanc76949a2005-05-29 14:58:59 -070011407{
Matt Carlson5e5a7f32011-08-19 13:58:21 +000011408 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
Matt Carlsonbb158d62011-04-25 12:42:47 +000011409 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
Matt Carlson84b67b22011-07-27 14:20:52 +000011410 u32 budget;
Michael Chanc76949a2005-05-29 14:58:59 -070011411 struct sk_buff *skb, *rx_skb;
11412 u8 *tx_data;
11413 dma_addr_t map;
11414 int num_pkts, tx_len, rx_len, i, err;
11415 struct tg3_rx_buffer_desc *desc;
Matt Carlson898a56f2009-08-28 14:02:40 +000011416 struct tg3_napi *tnapi, *rnapi;
Matt Carlson8fea32b2010-09-15 08:59:58 +000011417 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
Michael Chanc76949a2005-05-29 14:58:59 -070011418
Matt Carlsonc8873402010-02-12 14:47:11 +000011419 tnapi = &tp->napi[0];
11420 rnapi = &tp->napi[0];
Matt Carlson0c1d0e22009-09-01 13:16:33 +000011421 if (tp->irq_cnt > 1) {
Joe Perches63c3a662011-04-26 08:12:10 +000011422 if (tg3_flag(tp, ENABLE_RSS))
Matt Carlson1da85aa2010-09-30 10:34:34 +000011423 rnapi = &tp->napi[1];
Joe Perches63c3a662011-04-26 08:12:10 +000011424 if (tg3_flag(tp, ENABLE_TSS))
Matt Carlsonc8873402010-02-12 14:47:11 +000011425 tnapi = &tp->napi[1];
Matt Carlson0c1d0e22009-09-01 13:16:33 +000011426 }
Matt Carlsonfd2ce372009-09-01 12:51:13 +000011427 coal_now = tnapi->coal_now | rnapi->coal_now;
Matt Carlson898a56f2009-08-28 14:02:40 +000011428
Michael Chanc76949a2005-05-29 14:58:59 -070011429 err = -EIO;
11430
Matt Carlson4852a862011-04-13 11:05:07 +000011431 tx_len = pktsz;
David S. Millera20e9c62006-07-31 22:38:16 -070011432 skb = netdev_alloc_skb(tp->dev, tx_len);
Jesper Juhla50bb7b2006-05-09 23:14:35 -070011433 if (!skb)
11434 return -ENOMEM;
11435
Michael Chanc76949a2005-05-29 14:58:59 -070011436 tx_data = skb_put(skb, tx_len);
11437 memcpy(tx_data, tp->dev->dev_addr, 6);
11438 memset(tx_data + 6, 0x0, 8);
11439
Matt Carlson4852a862011-04-13 11:05:07 +000011440 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
Michael Chanc76949a2005-05-29 14:58:59 -070011441
Matt Carlson28a45952011-08-19 13:58:22 +000011442 if (tso_loopback) {
Matt Carlsonbb158d62011-04-25 12:42:47 +000011443 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
11444
11445 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
11446 TG3_TSO_TCP_OPT_LEN;
11447
11448 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
11449 sizeof(tg3_tso_header));
11450 mss = TG3_TSO_MSS;
11451
11452 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
11453 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
11454
11455 /* Set the total length field in the IP header */
11456 iph->tot_len = htons((u16)(mss + hdr_len));
11457
11458 base_flags = (TXD_FLAG_CPU_PRE_DMA |
11459 TXD_FLAG_CPU_POST_DMA);
11460
Joe Perches63c3a662011-04-26 08:12:10 +000011461 if (tg3_flag(tp, HW_TSO_1) ||
11462 tg3_flag(tp, HW_TSO_2) ||
11463 tg3_flag(tp, HW_TSO_3)) {
Matt Carlsonbb158d62011-04-25 12:42:47 +000011464 struct tcphdr *th;
11465 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
11466 th = (struct tcphdr *)&tx_data[val];
11467 th->check = 0;
11468 } else
11469 base_flags |= TXD_FLAG_TCPUDP_CSUM;
11470
Joe Perches63c3a662011-04-26 08:12:10 +000011471 if (tg3_flag(tp, HW_TSO_3)) {
Matt Carlsonbb158d62011-04-25 12:42:47 +000011472 mss |= (hdr_len & 0xc) << 12;
11473 if (hdr_len & 0x10)
11474 base_flags |= 0x00000010;
11475 base_flags |= (hdr_len & 0x3e0) << 5;
Joe Perches63c3a662011-04-26 08:12:10 +000011476 } else if (tg3_flag(tp, HW_TSO_2))
Matt Carlsonbb158d62011-04-25 12:42:47 +000011477 mss |= hdr_len << 9;
Joe Perches63c3a662011-04-26 08:12:10 +000011478 else if (tg3_flag(tp, HW_TSO_1) ||
Matt Carlsonbb158d62011-04-25 12:42:47 +000011479 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
11480 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
11481 } else {
11482 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
11483 }
11484
11485 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
11486 } else {
11487 num_pkts = 1;
11488 data_off = ETH_HLEN;
11489 }
11490
11491 for (i = data_off; i < tx_len; i++)
Michael Chanc76949a2005-05-29 14:58:59 -070011492 tx_data[i] = (u8) (i & 0xff);
11493
Alexander Duyckf4188d82009-12-02 16:48:38 +000011494 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
11495 if (pci_dma_mapping_error(tp->pdev, map)) {
Matt Carlsona21771d2009-11-02 14:25:31 +000011496 dev_kfree_skb(skb);
11497 return -EIO;
11498 }
Michael Chanc76949a2005-05-29 14:58:59 -070011499
Matt Carlson0d681b22011-07-27 14:20:49 +000011500 val = tnapi->tx_prod;
11501 tnapi->tx_buffers[val].skb = skb;
11502 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
11503
Michael Chanc76949a2005-05-29 14:58:59 -070011504 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
Matt Carlsonfd2ce372009-09-01 12:51:13 +000011505 rnapi->coal_now);
Michael Chanc76949a2005-05-29 14:58:59 -070011506
11507 udelay(10);
11508
Matt Carlson898a56f2009-08-28 14:02:40 +000011509 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
Michael Chanc76949a2005-05-29 14:58:59 -070011510
Matt Carlson84b67b22011-07-27 14:20:52 +000011511 budget = tg3_tx_avail(tnapi);
11512 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
Matt Carlsond1a3b732011-07-27 14:20:51 +000011513 base_flags | TXD_FLAG_END, mss, 0)) {
11514 tnapi->tx_buffers[val].skb = NULL;
11515 dev_kfree_skb(skb);
11516 return -EIO;
11517 }
Michael Chanc76949a2005-05-29 14:58:59 -070011518
Matt Carlsonf3f3f272009-08-28 14:03:21 +000011519 tnapi->tx_prod++;
Michael Chanc76949a2005-05-29 14:58:59 -070011520
Matt Carlsonf3f3f272009-08-28 14:03:21 +000011521 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
11522 tr32_mailbox(tnapi->prodmbox);
Michael Chanc76949a2005-05-29 14:58:59 -070011523
11524 udelay(10);
11525
Matt Carlson303fc922009-11-02 14:27:34 +000011526 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
11527 for (i = 0; i < 35; i++) {
Michael Chanc76949a2005-05-29 14:58:59 -070011528 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
Matt Carlsonfd2ce372009-09-01 12:51:13 +000011529 coal_now);
Michael Chanc76949a2005-05-29 14:58:59 -070011530
11531 udelay(10);
11532
Matt Carlson898a56f2009-08-28 14:02:40 +000011533 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
11534 rx_idx = rnapi->hw_status->idx[0].rx_producer;
Matt Carlsonf3f3f272009-08-28 14:03:21 +000011535 if ((tx_idx == tnapi->tx_prod) &&
Michael Chanc76949a2005-05-29 14:58:59 -070011536 (rx_idx == (rx_start_idx + num_pkts)))
11537 break;
11538 }
11539
Matt Carlsonba1142e2011-11-04 09:15:00 +000011540 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
Michael Chanc76949a2005-05-29 14:58:59 -070011541 dev_kfree_skb(skb);
11542
Matt Carlsonf3f3f272009-08-28 14:03:21 +000011543 if (tx_idx != tnapi->tx_prod)
Michael Chanc76949a2005-05-29 14:58:59 -070011544 goto out;
11545
11546 if (rx_idx != rx_start_idx + num_pkts)
11547 goto out;
11548
Matt Carlsonbb158d62011-04-25 12:42:47 +000011549 val = data_off;
11550 while (rx_idx != rx_start_idx) {
11551 desc = &rnapi->rx_rcb[rx_start_idx++];
11552 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
11553 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
Michael Chanc76949a2005-05-29 14:58:59 -070011554
Matt Carlsonbb158d62011-04-25 12:42:47 +000011555 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
11556 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
Matt Carlson4852a862011-04-13 11:05:07 +000011557 goto out;
Michael Chanc76949a2005-05-29 14:58:59 -070011558
Matt Carlsonbb158d62011-04-25 12:42:47 +000011559 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
11560 - ETH_FCS_LEN;
11561
Matt Carlson28a45952011-08-19 13:58:22 +000011562 if (!tso_loopback) {
Matt Carlsonbb158d62011-04-25 12:42:47 +000011563 if (rx_len != tx_len)
11564 goto out;
11565
11566 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
11567 if (opaque_key != RXD_OPAQUE_RING_STD)
11568 goto out;
11569 } else {
11570 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
11571 goto out;
11572 }
11573 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
11574 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
Matt Carlson54e0a672011-05-19 12:12:50 +000011575 >> RXD_TCPCSUM_SHIFT != 0xffff) {
Matt Carlsonbb158d62011-04-25 12:42:47 +000011576 goto out;
11577 }
11578
11579 if (opaque_key == RXD_OPAQUE_RING_STD) {
11580 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11581 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
11582 mapping);
11583 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
11584 rx_skb = tpr->rx_jmb_buffers[desc_idx].skb;
11585 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
11586 mapping);
11587 } else
Matt Carlson4852a862011-04-13 11:05:07 +000011588 goto out;
11589
Matt Carlsonbb158d62011-04-25 12:42:47 +000011590 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
11591 PCI_DMA_FROMDEVICE);
11592
11593 for (i = data_off; i < rx_len; i++, val++) {
11594 if (*(rx_skb->data + i) != (u8) (val & 0xff))
11595 goto out;
11596 }
Matt Carlson4852a862011-04-13 11:05:07 +000011597 }
11598
Michael Chanc76949a2005-05-29 14:58:59 -070011599 err = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011600
Michael Chanc76949a2005-05-29 14:58:59 -070011601 /* tg3_free_rings will unmap and free the rx_skb */
11602out:
11603 return err;
11604}
11605
Matt Carlson00c266b2011-04-25 12:42:46 +000011606#define TG3_STD_LOOPBACK_FAILED 1
11607#define TG3_JMB_LOOPBACK_FAILED 2
Matt Carlsonbb158d62011-04-25 12:42:47 +000011608#define TG3_TSO_LOOPBACK_FAILED 4
Matt Carlson28a45952011-08-19 13:58:22 +000011609#define TG3_LOOPBACK_FAILED \
11610 (TG3_STD_LOOPBACK_FAILED | \
11611 TG3_JMB_LOOPBACK_FAILED | \
11612 TG3_TSO_LOOPBACK_FAILED)
Matt Carlson00c266b2011-04-25 12:42:46 +000011613
Matt Carlson941ec902011-08-19 13:58:23 +000011614static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
Michael Chan9f40dea2005-09-05 17:53:06 -070011615{
Matt Carlson28a45952011-08-19 13:58:22 +000011616 int err = -EIO;
Matt Carlson2215e242011-08-19 13:58:19 +000011617 u32 eee_cap;
Michael Chan9f40dea2005-09-05 17:53:06 -070011618
Matt Carlsonab789042011-01-25 15:58:54 +000011619 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
11620 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11621
Matt Carlson28a45952011-08-19 13:58:22 +000011622 if (!netif_running(tp->dev)) {
11623 data[0] = TG3_LOOPBACK_FAILED;
11624 data[1] = TG3_LOOPBACK_FAILED;
Matt Carlson941ec902011-08-19 13:58:23 +000011625 if (do_extlpbk)
11626 data[2] = TG3_LOOPBACK_FAILED;
Matt Carlson28a45952011-08-19 13:58:22 +000011627 goto done;
11628 }
11629
Michael Chanb9ec6c12006-07-25 16:37:27 -070011630 err = tg3_reset_hw(tp, 1);
Matt Carlsonab789042011-01-25 15:58:54 +000011631 if (err) {
Matt Carlson28a45952011-08-19 13:58:22 +000011632 data[0] = TG3_LOOPBACK_FAILED;
11633 data[1] = TG3_LOOPBACK_FAILED;
Matt Carlson941ec902011-08-19 13:58:23 +000011634 if (do_extlpbk)
11635 data[2] = TG3_LOOPBACK_FAILED;
Matt Carlsonab789042011-01-25 15:58:54 +000011636 goto done;
11637 }
Michael Chan9f40dea2005-09-05 17:53:06 -070011638
Joe Perches63c3a662011-04-26 08:12:10 +000011639 if (tg3_flag(tp, ENABLE_RSS)) {
Matt Carlson4a85f092011-04-20 07:57:37 +000011640 int i;
11641
11642 /* Reroute all rx packets to the 1st queue */
11643 for (i = MAC_RSS_INDIR_TBL_0;
11644 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
11645 tw32(i, 0x0);
11646 }
11647
Matt Carlson6e01b202011-08-19 13:58:20 +000011648 /* HW errata - mac loopback fails in some cases on 5780.
11649 * Normal traffic and PHY loopback are not affected by
11650 * errata. Also, the MAC loopback test is deprecated for
11651 * all newer ASIC revisions.
11652 */
11653 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
11654 !tg3_flag(tp, CPMU_PRESENT)) {
11655 tg3_mac_loopback(tp, true);
Matt Carlson9936bcf2007-10-10 18:03:07 -070011656
Matt Carlson28a45952011-08-19 13:58:22 +000011657 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11658 data[0] |= TG3_STD_LOOPBACK_FAILED;
Matt Carlson6e01b202011-08-19 13:58:20 +000011659
11660 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
Matt Carlson28a45952011-08-19 13:58:22 +000011661 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11662 data[0] |= TG3_JMB_LOOPBACK_FAILED;
Matt Carlson6e01b202011-08-19 13:58:20 +000011663
11664 tg3_mac_loopback(tp, false);
11665 }
Matt Carlson4852a862011-04-13 11:05:07 +000011666
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011667 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
Joe Perches63c3a662011-04-26 08:12:10 +000011668 !tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson5e5a7f32011-08-19 13:58:21 +000011669 int i;
11670
Matt Carlson941ec902011-08-19 13:58:23 +000011671 tg3_phy_lpbk_set(tp, 0, false);
Matt Carlson5e5a7f32011-08-19 13:58:21 +000011672
11673 /* Wait for link */
11674 for (i = 0; i < 100; i++) {
11675 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
11676 break;
11677 mdelay(1);
11678 }
11679
Matt Carlson28a45952011-08-19 13:58:22 +000011680 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11681 data[1] |= TG3_STD_LOOPBACK_FAILED;
Joe Perches63c3a662011-04-26 08:12:10 +000011682 if (tg3_flag(tp, TSO_CAPABLE) &&
Matt Carlson28a45952011-08-19 13:58:22 +000011683 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11684 data[1] |= TG3_TSO_LOOPBACK_FAILED;
Joe Perches63c3a662011-04-26 08:12:10 +000011685 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
Matt Carlson28a45952011-08-19 13:58:22 +000011686 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11687 data[1] |= TG3_JMB_LOOPBACK_FAILED;
Michael Chan9f40dea2005-09-05 17:53:06 -070011688
Matt Carlson941ec902011-08-19 13:58:23 +000011689 if (do_extlpbk) {
11690 tg3_phy_lpbk_set(tp, 0, true);
11691
11692 /* All link indications report up, but the hardware
11693 * isn't really ready for about 20 msec. Double it
11694 * to be sure.
11695 */
11696 mdelay(40);
11697
11698 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
11699 data[2] |= TG3_STD_LOOPBACK_FAILED;
11700 if (tg3_flag(tp, TSO_CAPABLE) &&
11701 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
11702 data[2] |= TG3_TSO_LOOPBACK_FAILED;
11703 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
11704 tg3_run_loopback(tp, 9000 + ETH_HLEN, false))
11705 data[2] |= TG3_JMB_LOOPBACK_FAILED;
11706 }
11707
Matt Carlson5e5a7f32011-08-19 13:58:21 +000011708 /* Re-enable gphy autopowerdown. */
11709 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11710 tg3_phy_toggle_apd(tp, true);
11711 }
Matt Carlson6833c042008-11-21 17:18:59 -080011712
Matt Carlson941ec902011-08-19 13:58:23 +000011713 err = (data[0] | data[1] | data[2]) ? -EIO : 0;
Matt Carlson28a45952011-08-19 13:58:22 +000011714
Matt Carlsonab789042011-01-25 15:58:54 +000011715done:
11716 tp->phy_flags |= eee_cap;
11717
Michael Chan9f40dea2005-09-05 17:53:06 -070011718 return err;
11719}
11720
Michael Chan4cafd3f2005-05-29 14:56:34 -070011721static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11722 u64 *data)
11723{
Michael Chan566f86a2005-05-29 14:56:58 -070011724 struct tg3 *tp = netdev_priv(dev);
Matt Carlson941ec902011-08-19 13:58:23 +000011725 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
Michael Chan566f86a2005-05-29 14:56:58 -070011726
Matt Carlsonbed98292011-07-13 09:27:29 +000011727 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
11728 tg3_power_up(tp)) {
11729 etest->flags |= ETH_TEST_FL_FAILED;
11730 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
11731 return;
11732 }
Michael Chanbc1c7562006-03-20 17:48:03 -080011733
Michael Chan566f86a2005-05-29 14:56:58 -070011734 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11735
11736 if (tg3_test_nvram(tp) != 0) {
11737 etest->flags |= ETH_TEST_FL_FAILED;
11738 data[0] = 1;
11739 }
Matt Carlson941ec902011-08-19 13:58:23 +000011740 if (!doextlpbk && tg3_test_link(tp)) {
Michael Chanca430072005-05-29 14:57:23 -070011741 etest->flags |= ETH_TEST_FL_FAILED;
11742 data[1] = 1;
11743 }
Michael Chana71116d2005-05-29 14:58:11 -070011744 if (etest->flags & ETH_TEST_FL_OFFLINE) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011745 int err, err2 = 0, irq_sync = 0;
Michael Chana71116d2005-05-29 14:58:11 -070011746
Michael Chanbbe832c2005-06-24 20:20:04 -070011747 if (netif_running(dev)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011748 tg3_phy_stop(tp);
Michael Chanbbe832c2005-06-24 20:20:04 -070011749 tg3_netif_stop(tp);
11750 irq_sync = 1;
11751 }
11752
11753 tg3_full_lock(tp, irq_sync);
Michael Chana71116d2005-05-29 14:58:11 -070011754
11755 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
Michael Chanec41c7d2006-01-17 02:40:55 -080011756 err = tg3_nvram_lock(tp);
Michael Chana71116d2005-05-29 14:58:11 -070011757 tg3_halt_cpu(tp, RX_CPU_BASE);
Joe Perches63c3a662011-04-26 08:12:10 +000011758 if (!tg3_flag(tp, 5705_PLUS))
Michael Chana71116d2005-05-29 14:58:11 -070011759 tg3_halt_cpu(tp, TX_CPU_BASE);
Michael Chanec41c7d2006-01-17 02:40:55 -080011760 if (!err)
11761 tg3_nvram_unlock(tp);
Michael Chana71116d2005-05-29 14:58:11 -070011762
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011763 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
Michael Chand9ab5ad2006-03-20 22:27:35 -080011764 tg3_phy_reset(tp);
11765
Michael Chana71116d2005-05-29 14:58:11 -070011766 if (tg3_test_registers(tp) != 0) {
11767 etest->flags |= ETH_TEST_FL_FAILED;
11768 data[2] = 1;
11769 }
Matt Carlson28a45952011-08-19 13:58:22 +000011770
Michael Chan7942e1d2005-05-29 14:58:36 -070011771 if (tg3_test_memory(tp) != 0) {
11772 etest->flags |= ETH_TEST_FL_FAILED;
11773 data[3] = 1;
11774 }
Matt Carlson28a45952011-08-19 13:58:22 +000011775
Matt Carlson941ec902011-08-19 13:58:23 +000011776 if (doextlpbk)
11777 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
11778
11779 if (tg3_test_loopback(tp, &data[4], doextlpbk))
Michael Chanc76949a2005-05-29 14:58:59 -070011780 etest->flags |= ETH_TEST_FL_FAILED;
Michael Chana71116d2005-05-29 14:58:11 -070011781
David S. Millerf47c11e2005-06-24 20:18:35 -070011782 tg3_full_unlock(tp);
11783
Michael Chand4bc3922005-05-29 14:59:20 -070011784 if (tg3_test_interrupt(tp) != 0) {
11785 etest->flags |= ETH_TEST_FL_FAILED;
Matt Carlson941ec902011-08-19 13:58:23 +000011786 data[7] = 1;
Michael Chand4bc3922005-05-29 14:59:20 -070011787 }
David S. Millerf47c11e2005-06-24 20:18:35 -070011788
11789 tg3_full_lock(tp, 0);
Michael Chand4bc3922005-05-29 14:59:20 -070011790
Michael Chana71116d2005-05-29 14:58:11 -070011791 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11792 if (netif_running(dev)) {
Joe Perches63c3a662011-04-26 08:12:10 +000011793 tg3_flag_set(tp, INIT_COMPLETE);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011794 err2 = tg3_restart_hw(tp, 1);
11795 if (!err2)
Michael Chanb9ec6c12006-07-25 16:37:27 -070011796 tg3_netif_start(tp);
Michael Chana71116d2005-05-29 14:58:11 -070011797 }
David S. Millerf47c11e2005-06-24 20:18:35 -070011798
11799 tg3_full_unlock(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011800
11801 if (irq_sync && !err2)
11802 tg3_phy_start(tp);
Michael Chana71116d2005-05-29 14:58:11 -070011803 }
Matt Carlson80096062010-08-02 11:26:06 +000011804 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000011805 tg3_power_down(tp);
Michael Chanbc1c7562006-03-20 17:48:03 -080011806
Michael Chan4cafd3f2005-05-29 14:56:34 -070011807}
11808
Linus Torvalds1da177e2005-04-16 15:20:36 -070011809static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11810{
11811 struct mii_ioctl_data *data = if_mii(ifr);
11812 struct tg3 *tp = netdev_priv(dev);
11813 int err;
11814
Joe Perches63c3a662011-04-26 08:12:10 +000011815 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000011816 struct phy_device *phydev;
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011817 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011818 return -EAGAIN;
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000011819 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Richard Cochran28b04112010-07-17 08:48:55 +000011820 return phy_mii_ioctl(phydev, ifr, cmd);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070011821 }
11822
Matt Carlson33f401a2010-04-05 10:19:27 +000011823 switch (cmd) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011824 case SIOCGMIIPHY:
Matt Carlson882e9792009-09-01 13:21:36 +000011825 data->phy_id = tp->phy_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011826
11827 /* fallthru */
11828 case SIOCGMIIREG: {
11829 u32 mii_regval;
11830
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011831 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011832 break; /* We have no PHY */
11833
Matt Carlson34eea5a2011-04-20 07:57:38 +000011834 if (!netif_running(dev))
Michael Chanbc1c7562006-03-20 17:48:03 -080011835 return -EAGAIN;
11836
David S. Millerf47c11e2005-06-24 20:18:35 -070011837 spin_lock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011838 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
David S. Millerf47c11e2005-06-24 20:18:35 -070011839 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011840
11841 data->val_out = mii_regval;
11842
11843 return err;
11844 }
11845
11846 case SIOCSMIIREG:
Matt Carlsonf07e9af2010-08-02 11:26:07 +000011847 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011848 break; /* We have no PHY */
11849
Matt Carlson34eea5a2011-04-20 07:57:38 +000011850 if (!netif_running(dev))
Michael Chanbc1c7562006-03-20 17:48:03 -080011851 return -EAGAIN;
11852
David S. Millerf47c11e2005-06-24 20:18:35 -070011853 spin_lock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011854 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
David S. Millerf47c11e2005-06-24 20:18:35 -070011855 spin_unlock_bh(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070011856
11857 return err;
11858
11859 default:
11860 /* do nothing */
11861 break;
11862 }
11863 return -EOPNOTSUPP;
11864}
11865
David S. Miller15f98502005-05-18 22:49:26 -070011866static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11867{
11868 struct tg3 *tp = netdev_priv(dev);
11869
11870 memcpy(ec, &tp->coal, sizeof(*ec));
11871 return 0;
11872}
11873
Michael Chand244c892005-07-05 14:42:33 -070011874static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11875{
11876 struct tg3 *tp = netdev_priv(dev);
11877 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11878 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11879
Joe Perches63c3a662011-04-26 08:12:10 +000011880 if (!tg3_flag(tp, 5705_PLUS)) {
Michael Chand244c892005-07-05 14:42:33 -070011881 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11882 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11883 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11884 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11885 }
11886
11887 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11888 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11889 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11890 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11891 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11892 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11893 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11894 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11895 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11896 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11897 return -EINVAL;
11898
11899 /* No rx interrupts will be generated if both are zero */
11900 if ((ec->rx_coalesce_usecs == 0) &&
11901 (ec->rx_max_coalesced_frames == 0))
11902 return -EINVAL;
11903
11904 /* No tx interrupts will be generated if both are zero */
11905 if ((ec->tx_coalesce_usecs == 0) &&
11906 (ec->tx_max_coalesced_frames == 0))
11907 return -EINVAL;
11908
11909 /* Only copy relevant parameters, ignore all others. */
11910 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11911 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11912 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11913 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11914 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11915 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11916 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11917 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11918 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11919
11920 if (netif_running(dev)) {
11921 tg3_full_lock(tp, 0);
11922 __tg3_set_coalesce(tp, &tp->coal);
11923 tg3_full_unlock(tp);
11924 }
11925 return 0;
11926}
11927
Jeff Garzik7282d492006-09-13 14:30:00 -040011928static const struct ethtool_ops tg3_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -070011929 .get_settings = tg3_get_settings,
11930 .set_settings = tg3_set_settings,
11931 .get_drvinfo = tg3_get_drvinfo,
11932 .get_regs_len = tg3_get_regs_len,
11933 .get_regs = tg3_get_regs,
11934 .get_wol = tg3_get_wol,
11935 .set_wol = tg3_set_wol,
11936 .get_msglevel = tg3_get_msglevel,
11937 .set_msglevel = tg3_set_msglevel,
11938 .nway_reset = tg3_nway_reset,
11939 .get_link = ethtool_op_get_link,
11940 .get_eeprom_len = tg3_get_eeprom_len,
11941 .get_eeprom = tg3_get_eeprom,
11942 .set_eeprom = tg3_set_eeprom,
11943 .get_ringparam = tg3_get_ringparam,
11944 .set_ringparam = tg3_set_ringparam,
11945 .get_pauseparam = tg3_get_pauseparam,
11946 .set_pauseparam = tg3_set_pauseparam,
Michael Chan4cafd3f2005-05-29 14:56:34 -070011947 .self_test = tg3_self_test,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011948 .get_strings = tg3_get_strings,
stephen hemminger81b87092011-04-04 08:43:50 +000011949 .set_phys_id = tg3_set_phys_id,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011950 .get_ethtool_stats = tg3_get_ethtool_stats,
David S. Miller15f98502005-05-18 22:49:26 -070011951 .get_coalesce = tg3_get_coalesce,
Michael Chand244c892005-07-05 14:42:33 -070011952 .set_coalesce = tg3_set_coalesce,
Jeff Garzikb9f2c042007-10-03 18:07:32 -070011953 .get_sset_count = tg3_get_sset_count,
Linus Torvalds1da177e2005-04-16 15:20:36 -070011954};
11955
11956static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11957{
Michael Chan1b277772006-03-20 22:27:48 -080011958 u32 cursize, val, magic;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011959
11960 tp->nvram_size = EEPROM_CHIP_SIZE;
11961
Matt Carlsone4f34112009-02-25 14:25:00 +000011962 if (tg3_nvram_read(tp, 0, &magic) != 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011963 return;
11964
Michael Chanb16250e2006-09-27 16:10:14 -070011965 if ((magic != TG3_EEPROM_MAGIC) &&
11966 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11967 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
Linus Torvalds1da177e2005-04-16 15:20:36 -070011968 return;
11969
11970 /*
11971 * Size the chip by reading offsets at increasing powers of two.
11972 * When we encounter our validation signature, we know the addressing
11973 * has wrapped around, and thus have our chip size.
11974 */
Michael Chan1b277772006-03-20 22:27:48 -080011975 cursize = 0x10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070011976
11977 while (cursize < tp->nvram_size) {
Matt Carlsone4f34112009-02-25 14:25:00 +000011978 if (tg3_nvram_read(tp, cursize, &val) != 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011979 return;
11980
Michael Chan18201802006-03-20 22:29:15 -080011981 if (val == magic)
Linus Torvalds1da177e2005-04-16 15:20:36 -070011982 break;
11983
11984 cursize <<= 1;
11985 }
11986
11987 tp->nvram_size = cursize;
11988}
Jeff Garzik6aa20a22006-09-13 13:24:59 -040011989
Linus Torvalds1da177e2005-04-16 15:20:36 -070011990static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11991{
11992 u32 val;
11993
Joe Perches63c3a662011-04-26 08:12:10 +000011994 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
Michael Chan1b277772006-03-20 22:27:48 -080011995 return;
11996
11997 /* Selfboot format */
Michael Chan18201802006-03-20 22:29:15 -080011998 if (val != TG3_EEPROM_MAGIC) {
Michael Chan1b277772006-03-20 22:27:48 -080011999 tg3_get_eeprom_size(tp);
12000 return;
12001 }
12002
Matt Carlson6d348f22009-02-25 14:25:52 +000012003 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012004 if (val != 0) {
Matt Carlson6d348f22009-02-25 14:25:52 +000012005 /* This is confusing. We want to operate on the
12006 * 16-bit value at offset 0xf2. The tg3_nvram_read()
12007 * call will read from NVRAM and byteswap the data
12008 * according to the byteswapping settings for all
12009 * other register accesses. This ensures the data we
12010 * want will always reside in the lower 16-bits.
12011 * However, the data in NVRAM is in LE format, which
12012 * means the data from the NVRAM read will always be
12013 * opposite the endianness of the CPU. The 16-bit
12014 * byteswap then brings the data to CPU endianness.
12015 */
12016 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012017 return;
12018 }
12019 }
Matt Carlsonfd1122a2008-05-02 16:48:36 -070012020 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012021}
12022
12023static void __devinit tg3_get_nvram_info(struct tg3 *tp)
12024{
12025 u32 nvcfg1;
12026
12027 nvcfg1 = tr32(NVRAM_CFG1);
12028 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
Joe Perches63c3a662011-04-26 08:12:10 +000012029 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000012030 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012031 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12032 tw32(NVRAM_CFG1, nvcfg1);
12033 }
12034
Matt Carlson6ff6f812011-05-19 12:12:54 +000012035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
Joe Perches63c3a662011-04-26 08:12:10 +000012036 tg3_flag(tp, 5780_CLASS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012037 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
Matt Carlson8590a602009-08-28 12:29:16 +000012038 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
12039 tp->nvram_jedecnum = JEDEC_ATMEL;
12040 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
Joe Perches63c3a662011-04-26 08:12:10 +000012041 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson8590a602009-08-28 12:29:16 +000012042 break;
12043 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
12044 tp->nvram_jedecnum = JEDEC_ATMEL;
12045 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
12046 break;
12047 case FLASH_VENDOR_ATMEL_EEPROM:
12048 tp->nvram_jedecnum = JEDEC_ATMEL;
12049 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
Joe Perches63c3a662011-04-26 08:12:10 +000012050 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson8590a602009-08-28 12:29:16 +000012051 break;
12052 case FLASH_VENDOR_ST:
12053 tp->nvram_jedecnum = JEDEC_ST;
12054 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
Joe Perches63c3a662011-04-26 08:12:10 +000012055 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson8590a602009-08-28 12:29:16 +000012056 break;
12057 case FLASH_VENDOR_SAIFUN:
12058 tp->nvram_jedecnum = JEDEC_SAIFUN;
12059 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
12060 break;
12061 case FLASH_VENDOR_SST_SMALL:
12062 case FLASH_VENDOR_SST_LARGE:
12063 tp->nvram_jedecnum = JEDEC_SST;
12064 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
12065 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012066 }
Matt Carlson8590a602009-08-28 12:29:16 +000012067 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012068 tp->nvram_jedecnum = JEDEC_ATMEL;
12069 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
Joe Perches63c3a662011-04-26 08:12:10 +000012070 tg3_flag_set(tp, NVRAM_BUFFERED);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012071 }
12072}
12073
Matt Carlsona1b950d2009-09-01 13:20:17 +000012074static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
12075{
12076 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
12077 case FLASH_5752PAGE_SIZE_256:
12078 tp->nvram_pagesize = 256;
12079 break;
12080 case FLASH_5752PAGE_SIZE_512:
12081 tp->nvram_pagesize = 512;
12082 break;
12083 case FLASH_5752PAGE_SIZE_1K:
12084 tp->nvram_pagesize = 1024;
12085 break;
12086 case FLASH_5752PAGE_SIZE_2K:
12087 tp->nvram_pagesize = 2048;
12088 break;
12089 case FLASH_5752PAGE_SIZE_4K:
12090 tp->nvram_pagesize = 4096;
12091 break;
12092 case FLASH_5752PAGE_SIZE_264:
12093 tp->nvram_pagesize = 264;
12094 break;
12095 case FLASH_5752PAGE_SIZE_528:
12096 tp->nvram_pagesize = 528;
12097 break;
12098 }
12099}
12100
Michael Chan361b4ac2005-04-21 17:11:21 -070012101static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
12102{
12103 u32 nvcfg1;
12104
12105 nvcfg1 = tr32(NVRAM_CFG1);
12106
Michael Chane6af3012005-04-21 17:12:05 -070012107 /* NVRAM protection for TPM */
12108 if (nvcfg1 & (1 << 27))
Joe Perches63c3a662011-04-26 08:12:10 +000012109 tg3_flag_set(tp, PROTECTED_NVRAM);
Michael Chane6af3012005-04-21 17:12:05 -070012110
Michael Chan361b4ac2005-04-21 17:11:21 -070012111 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
Matt Carlson8590a602009-08-28 12:29:16 +000012112 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
12113 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
12114 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012115 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson8590a602009-08-28 12:29:16 +000012116 break;
12117 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12118 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012119 tg3_flag_set(tp, NVRAM_BUFFERED);
12120 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000012121 break;
12122 case FLASH_5752VENDOR_ST_M45PE10:
12123 case FLASH_5752VENDOR_ST_M45PE20:
12124 case FLASH_5752VENDOR_ST_M45PE40:
12125 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000012126 tg3_flag_set(tp, NVRAM_BUFFERED);
12127 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000012128 break;
Michael Chan361b4ac2005-04-21 17:11:21 -070012129 }
12130
Joe Perches63c3a662011-04-26 08:12:10 +000012131 if (tg3_flag(tp, FLASH)) {
Matt Carlsona1b950d2009-09-01 13:20:17 +000012132 tg3_nvram_get_pagesize(tp, nvcfg1);
Matt Carlson8590a602009-08-28 12:29:16 +000012133 } else {
Michael Chan361b4ac2005-04-21 17:11:21 -070012134 /* For eeprom, set pagesize to maximum eeprom size */
12135 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12136
12137 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12138 tw32(NVRAM_CFG1, nvcfg1);
12139 }
12140}
12141
Michael Chand3c7b882006-03-23 01:28:25 -080012142static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
12143{
Matt Carlson989a9d22007-05-05 11:51:05 -070012144 u32 nvcfg1, protect = 0;
Michael Chand3c7b882006-03-23 01:28:25 -080012145
12146 nvcfg1 = tr32(NVRAM_CFG1);
12147
12148 /* NVRAM protection for TPM */
Matt Carlson989a9d22007-05-05 11:51:05 -070012149 if (nvcfg1 & (1 << 27)) {
Joe Perches63c3a662011-04-26 08:12:10 +000012150 tg3_flag_set(tp, PROTECTED_NVRAM);
Matt Carlson989a9d22007-05-05 11:51:05 -070012151 protect = 1;
12152 }
Michael Chand3c7b882006-03-23 01:28:25 -080012153
Matt Carlson989a9d22007-05-05 11:51:05 -070012154 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12155 switch (nvcfg1) {
Matt Carlson8590a602009-08-28 12:29:16 +000012156 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12157 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12158 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12159 case FLASH_5755VENDOR_ATMEL_FLASH_5:
12160 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012161 tg3_flag_set(tp, NVRAM_BUFFERED);
12162 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000012163 tp->nvram_pagesize = 264;
12164 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
12165 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
12166 tp->nvram_size = (protect ? 0x3e200 :
12167 TG3_NVRAM_SIZE_512KB);
12168 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
12169 tp->nvram_size = (protect ? 0x1f200 :
12170 TG3_NVRAM_SIZE_256KB);
12171 else
12172 tp->nvram_size = (protect ? 0x1f200 :
12173 TG3_NVRAM_SIZE_128KB);
12174 break;
12175 case FLASH_5752VENDOR_ST_M45PE10:
12176 case FLASH_5752VENDOR_ST_M45PE20:
12177 case FLASH_5752VENDOR_ST_M45PE40:
12178 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000012179 tg3_flag_set(tp, NVRAM_BUFFERED);
12180 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000012181 tp->nvram_pagesize = 256;
12182 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
12183 tp->nvram_size = (protect ?
12184 TG3_NVRAM_SIZE_64KB :
12185 TG3_NVRAM_SIZE_128KB);
12186 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
12187 tp->nvram_size = (protect ?
12188 TG3_NVRAM_SIZE_64KB :
12189 TG3_NVRAM_SIZE_256KB);
12190 else
12191 tp->nvram_size = (protect ?
12192 TG3_NVRAM_SIZE_128KB :
12193 TG3_NVRAM_SIZE_512KB);
12194 break;
Michael Chand3c7b882006-03-23 01:28:25 -080012195 }
12196}
12197
Michael Chan1b277772006-03-20 22:27:48 -080012198static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
12199{
12200 u32 nvcfg1;
12201
12202 nvcfg1 = tr32(NVRAM_CFG1);
12203
12204 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
Matt Carlson8590a602009-08-28 12:29:16 +000012205 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
12206 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12207 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
12208 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12209 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012210 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson8590a602009-08-28 12:29:16 +000012211 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
Michael Chan1b277772006-03-20 22:27:48 -080012212
Matt Carlson8590a602009-08-28 12:29:16 +000012213 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12214 tw32(NVRAM_CFG1, nvcfg1);
12215 break;
12216 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12217 case FLASH_5755VENDOR_ATMEL_FLASH_1:
12218 case FLASH_5755VENDOR_ATMEL_FLASH_2:
12219 case FLASH_5755VENDOR_ATMEL_FLASH_3:
12220 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012221 tg3_flag_set(tp, NVRAM_BUFFERED);
12222 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000012223 tp->nvram_pagesize = 264;
12224 break;
12225 case FLASH_5752VENDOR_ST_M45PE10:
12226 case FLASH_5752VENDOR_ST_M45PE20:
12227 case FLASH_5752VENDOR_ST_M45PE40:
12228 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000012229 tg3_flag_set(tp, NVRAM_BUFFERED);
12230 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000012231 tp->nvram_pagesize = 256;
12232 break;
Michael Chan1b277772006-03-20 22:27:48 -080012233 }
12234}
12235
Matt Carlson6b91fa02007-10-10 18:01:09 -070012236static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
12237{
12238 u32 nvcfg1, protect = 0;
12239
12240 nvcfg1 = tr32(NVRAM_CFG1);
12241
12242 /* NVRAM protection for TPM */
12243 if (nvcfg1 & (1 << 27)) {
Joe Perches63c3a662011-04-26 08:12:10 +000012244 tg3_flag_set(tp, PROTECTED_NVRAM);
Matt Carlson6b91fa02007-10-10 18:01:09 -070012245 protect = 1;
12246 }
12247
12248 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
12249 switch (nvcfg1) {
Matt Carlson8590a602009-08-28 12:29:16 +000012250 case FLASH_5761VENDOR_ATMEL_ADB021D:
12251 case FLASH_5761VENDOR_ATMEL_ADB041D:
12252 case FLASH_5761VENDOR_ATMEL_ADB081D:
12253 case FLASH_5761VENDOR_ATMEL_ADB161D:
12254 case FLASH_5761VENDOR_ATMEL_MDB021D:
12255 case FLASH_5761VENDOR_ATMEL_MDB041D:
12256 case FLASH_5761VENDOR_ATMEL_MDB081D:
12257 case FLASH_5761VENDOR_ATMEL_MDB161D:
12258 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012259 tg3_flag_set(tp, NVRAM_BUFFERED);
12260 tg3_flag_set(tp, FLASH);
12261 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
Matt Carlson8590a602009-08-28 12:29:16 +000012262 tp->nvram_pagesize = 256;
12263 break;
12264 case FLASH_5761VENDOR_ST_A_M45PE20:
12265 case FLASH_5761VENDOR_ST_A_M45PE40:
12266 case FLASH_5761VENDOR_ST_A_M45PE80:
12267 case FLASH_5761VENDOR_ST_A_M45PE16:
12268 case FLASH_5761VENDOR_ST_M_M45PE20:
12269 case FLASH_5761VENDOR_ST_M_M45PE40:
12270 case FLASH_5761VENDOR_ST_M_M45PE80:
12271 case FLASH_5761VENDOR_ST_M_M45PE16:
12272 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000012273 tg3_flag_set(tp, NVRAM_BUFFERED);
12274 tg3_flag_set(tp, FLASH);
Matt Carlson8590a602009-08-28 12:29:16 +000012275 tp->nvram_pagesize = 256;
12276 break;
Matt Carlson6b91fa02007-10-10 18:01:09 -070012277 }
12278
12279 if (protect) {
12280 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
12281 } else {
12282 switch (nvcfg1) {
Matt Carlson8590a602009-08-28 12:29:16 +000012283 case FLASH_5761VENDOR_ATMEL_ADB161D:
12284 case FLASH_5761VENDOR_ATMEL_MDB161D:
12285 case FLASH_5761VENDOR_ST_A_M45PE16:
12286 case FLASH_5761VENDOR_ST_M_M45PE16:
12287 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
12288 break;
12289 case FLASH_5761VENDOR_ATMEL_ADB081D:
12290 case FLASH_5761VENDOR_ATMEL_MDB081D:
12291 case FLASH_5761VENDOR_ST_A_M45PE80:
12292 case FLASH_5761VENDOR_ST_M_M45PE80:
12293 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12294 break;
12295 case FLASH_5761VENDOR_ATMEL_ADB041D:
12296 case FLASH_5761VENDOR_ATMEL_MDB041D:
12297 case FLASH_5761VENDOR_ST_A_M45PE40:
12298 case FLASH_5761VENDOR_ST_M_M45PE40:
12299 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12300 break;
12301 case FLASH_5761VENDOR_ATMEL_ADB021D:
12302 case FLASH_5761VENDOR_ATMEL_MDB021D:
12303 case FLASH_5761VENDOR_ST_A_M45PE20:
12304 case FLASH_5761VENDOR_ST_M_M45PE20:
12305 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12306 break;
Matt Carlson6b91fa02007-10-10 18:01:09 -070012307 }
12308 }
12309}
12310
Michael Chanb5d37722006-09-27 16:06:21 -070012311static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
12312{
12313 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012314 tg3_flag_set(tp, NVRAM_BUFFERED);
Michael Chanb5d37722006-09-27 16:06:21 -070012315 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12316}
12317
Matt Carlson321d32a2008-11-21 17:22:19 -080012318static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
12319{
12320 u32 nvcfg1;
12321
12322 nvcfg1 = tr32(NVRAM_CFG1);
12323
12324 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12325 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
12326 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
12327 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012328 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson321d32a2008-11-21 17:22:19 -080012329 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12330
12331 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12332 tw32(NVRAM_CFG1, nvcfg1);
12333 return;
12334 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12335 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12336 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12337 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12338 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12339 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12340 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12341 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012342 tg3_flag_set(tp, NVRAM_BUFFERED);
12343 tg3_flag_set(tp, FLASH);
Matt Carlson321d32a2008-11-21 17:22:19 -080012344
12345 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12346 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
12347 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
12348 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
12349 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12350 break;
12351 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
12352 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
12353 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12354 break;
12355 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
12356 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
12357 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12358 break;
12359 }
12360 break;
12361 case FLASH_5752VENDOR_ST_M45PE10:
12362 case FLASH_5752VENDOR_ST_M45PE20:
12363 case FLASH_5752VENDOR_ST_M45PE40:
12364 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000012365 tg3_flag_set(tp, NVRAM_BUFFERED);
12366 tg3_flag_set(tp, FLASH);
Matt Carlson321d32a2008-11-21 17:22:19 -080012367
12368 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12369 case FLASH_5752VENDOR_ST_M45PE10:
12370 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12371 break;
12372 case FLASH_5752VENDOR_ST_M45PE20:
12373 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12374 break;
12375 case FLASH_5752VENDOR_ST_M45PE40:
12376 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12377 break;
12378 }
12379 break;
12380 default:
Joe Perches63c3a662011-04-26 08:12:10 +000012381 tg3_flag_set(tp, NO_NVRAM);
Matt Carlson321d32a2008-11-21 17:22:19 -080012382 return;
12383 }
12384
Matt Carlsona1b950d2009-09-01 13:20:17 +000012385 tg3_nvram_get_pagesize(tp, nvcfg1);
12386 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
Joe Perches63c3a662011-04-26 08:12:10 +000012387 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
Matt Carlsona1b950d2009-09-01 13:20:17 +000012388}
12389
12390
12391static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
12392{
12393 u32 nvcfg1;
12394
12395 nvcfg1 = tr32(NVRAM_CFG1);
12396
12397 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12398 case FLASH_5717VENDOR_ATMEL_EEPROM:
12399 case FLASH_5717VENDOR_MICRO_EEPROM:
12400 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012401 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlsona1b950d2009-09-01 13:20:17 +000012402 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12403
12404 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12405 tw32(NVRAM_CFG1, nvcfg1);
12406 return;
12407 case FLASH_5717VENDOR_ATMEL_MDB011D:
12408 case FLASH_5717VENDOR_ATMEL_ADB011B:
12409 case FLASH_5717VENDOR_ATMEL_ADB011D:
12410 case FLASH_5717VENDOR_ATMEL_MDB021D:
12411 case FLASH_5717VENDOR_ATMEL_ADB021B:
12412 case FLASH_5717VENDOR_ATMEL_ADB021D:
12413 case FLASH_5717VENDOR_ATMEL_45USPT:
12414 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012415 tg3_flag_set(tp, NVRAM_BUFFERED);
12416 tg3_flag_set(tp, FLASH);
Matt Carlsona1b950d2009-09-01 13:20:17 +000012417
12418 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12419 case FLASH_5717VENDOR_ATMEL_MDB021D:
Matt Carlson66ee33b2011-04-05 14:22:51 +000012420 /* Detect size with tg3_nvram_get_size() */
12421 break;
Matt Carlsona1b950d2009-09-01 13:20:17 +000012422 case FLASH_5717VENDOR_ATMEL_ADB021B:
12423 case FLASH_5717VENDOR_ATMEL_ADB021D:
12424 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12425 break;
12426 default:
12427 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12428 break;
12429 }
Matt Carlson321d32a2008-11-21 17:22:19 -080012430 break;
Matt Carlsona1b950d2009-09-01 13:20:17 +000012431 case FLASH_5717VENDOR_ST_M_M25PE10:
12432 case FLASH_5717VENDOR_ST_A_M25PE10:
12433 case FLASH_5717VENDOR_ST_M_M45PE10:
12434 case FLASH_5717VENDOR_ST_A_M45PE10:
12435 case FLASH_5717VENDOR_ST_M_M25PE20:
12436 case FLASH_5717VENDOR_ST_A_M25PE20:
12437 case FLASH_5717VENDOR_ST_M_M45PE20:
12438 case FLASH_5717VENDOR_ST_A_M45PE20:
12439 case FLASH_5717VENDOR_ST_25USPT:
12440 case FLASH_5717VENDOR_ST_45USPT:
12441 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000012442 tg3_flag_set(tp, NVRAM_BUFFERED);
12443 tg3_flag_set(tp, FLASH);
Matt Carlsona1b950d2009-09-01 13:20:17 +000012444
12445 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
12446 case FLASH_5717VENDOR_ST_M_M25PE20:
Matt Carlsona1b950d2009-09-01 13:20:17 +000012447 case FLASH_5717VENDOR_ST_M_M45PE20:
Matt Carlson66ee33b2011-04-05 14:22:51 +000012448 /* Detect size with tg3_nvram_get_size() */
12449 break;
12450 case FLASH_5717VENDOR_ST_A_M25PE20:
Matt Carlsona1b950d2009-09-01 13:20:17 +000012451 case FLASH_5717VENDOR_ST_A_M45PE20:
12452 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12453 break;
12454 default:
12455 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12456 break;
12457 }
Matt Carlson321d32a2008-11-21 17:22:19 -080012458 break;
Matt Carlsona1b950d2009-09-01 13:20:17 +000012459 default:
Joe Perches63c3a662011-04-26 08:12:10 +000012460 tg3_flag_set(tp, NO_NVRAM);
Matt Carlsona1b950d2009-09-01 13:20:17 +000012461 return;
Matt Carlson321d32a2008-11-21 17:22:19 -080012462 }
Matt Carlsona1b950d2009-09-01 13:20:17 +000012463
12464 tg3_nvram_get_pagesize(tp, nvcfg1);
12465 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
Joe Perches63c3a662011-04-26 08:12:10 +000012466 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
Matt Carlson321d32a2008-11-21 17:22:19 -080012467}
12468
Matt Carlson9b91b5f2011-04-05 14:22:47 +000012469static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
12470{
12471 u32 nvcfg1, nvmpinstrp;
12472
12473 nvcfg1 = tr32(NVRAM_CFG1);
12474 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
12475
12476 switch (nvmpinstrp) {
12477 case FLASH_5720_EEPROM_HD:
12478 case FLASH_5720_EEPROM_LD:
12479 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012480 tg3_flag_set(tp, NVRAM_BUFFERED);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000012481
12482 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
12483 tw32(NVRAM_CFG1, nvcfg1);
12484 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
12485 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
12486 else
12487 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
12488 return;
12489 case FLASH_5720VENDOR_M_ATMEL_DB011D:
12490 case FLASH_5720VENDOR_A_ATMEL_DB011B:
12491 case FLASH_5720VENDOR_A_ATMEL_DB011D:
12492 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12493 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12494 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12495 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12496 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12497 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12498 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12499 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12500 case FLASH_5720VENDOR_ATMEL_45USPT:
12501 tp->nvram_jedecnum = JEDEC_ATMEL;
Joe Perches63c3a662011-04-26 08:12:10 +000012502 tg3_flag_set(tp, NVRAM_BUFFERED);
12503 tg3_flag_set(tp, FLASH);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000012504
12505 switch (nvmpinstrp) {
12506 case FLASH_5720VENDOR_M_ATMEL_DB021D:
12507 case FLASH_5720VENDOR_A_ATMEL_DB021B:
12508 case FLASH_5720VENDOR_A_ATMEL_DB021D:
12509 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12510 break;
12511 case FLASH_5720VENDOR_M_ATMEL_DB041D:
12512 case FLASH_5720VENDOR_A_ATMEL_DB041B:
12513 case FLASH_5720VENDOR_A_ATMEL_DB041D:
12514 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12515 break;
12516 case FLASH_5720VENDOR_M_ATMEL_DB081D:
12517 case FLASH_5720VENDOR_A_ATMEL_DB081D:
12518 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12519 break;
12520 default:
12521 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12522 break;
12523 }
12524 break;
12525 case FLASH_5720VENDOR_M_ST_M25PE10:
12526 case FLASH_5720VENDOR_M_ST_M45PE10:
12527 case FLASH_5720VENDOR_A_ST_M25PE10:
12528 case FLASH_5720VENDOR_A_ST_M45PE10:
12529 case FLASH_5720VENDOR_M_ST_M25PE20:
12530 case FLASH_5720VENDOR_M_ST_M45PE20:
12531 case FLASH_5720VENDOR_A_ST_M25PE20:
12532 case FLASH_5720VENDOR_A_ST_M45PE20:
12533 case FLASH_5720VENDOR_M_ST_M25PE40:
12534 case FLASH_5720VENDOR_M_ST_M45PE40:
12535 case FLASH_5720VENDOR_A_ST_M25PE40:
12536 case FLASH_5720VENDOR_A_ST_M45PE40:
12537 case FLASH_5720VENDOR_M_ST_M25PE80:
12538 case FLASH_5720VENDOR_M_ST_M45PE80:
12539 case FLASH_5720VENDOR_A_ST_M25PE80:
12540 case FLASH_5720VENDOR_A_ST_M45PE80:
12541 case FLASH_5720VENDOR_ST_25USPT:
12542 case FLASH_5720VENDOR_ST_45USPT:
12543 tp->nvram_jedecnum = JEDEC_ST;
Joe Perches63c3a662011-04-26 08:12:10 +000012544 tg3_flag_set(tp, NVRAM_BUFFERED);
12545 tg3_flag_set(tp, FLASH);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000012546
12547 switch (nvmpinstrp) {
12548 case FLASH_5720VENDOR_M_ST_M25PE20:
12549 case FLASH_5720VENDOR_M_ST_M45PE20:
12550 case FLASH_5720VENDOR_A_ST_M25PE20:
12551 case FLASH_5720VENDOR_A_ST_M45PE20:
12552 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
12553 break;
12554 case FLASH_5720VENDOR_M_ST_M25PE40:
12555 case FLASH_5720VENDOR_M_ST_M45PE40:
12556 case FLASH_5720VENDOR_A_ST_M25PE40:
12557 case FLASH_5720VENDOR_A_ST_M45PE40:
12558 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
12559 break;
12560 case FLASH_5720VENDOR_M_ST_M25PE80:
12561 case FLASH_5720VENDOR_M_ST_M45PE80:
12562 case FLASH_5720VENDOR_A_ST_M25PE80:
12563 case FLASH_5720VENDOR_A_ST_M45PE80:
12564 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
12565 break;
12566 default:
12567 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
12568 break;
12569 }
12570 break;
12571 default:
Joe Perches63c3a662011-04-26 08:12:10 +000012572 tg3_flag_set(tp, NO_NVRAM);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000012573 return;
12574 }
12575
12576 tg3_nvram_get_pagesize(tp, nvcfg1);
12577 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
Joe Perches63c3a662011-04-26 08:12:10 +000012578 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000012579}
12580
Linus Torvalds1da177e2005-04-16 15:20:36 -070012581/* Chips other than 5700/5701 use the NVRAM for fetching info. */
12582static void __devinit tg3_nvram_init(struct tg3 *tp)
12583{
Linus Torvalds1da177e2005-04-16 15:20:36 -070012584 tw32_f(GRC_EEPROM_ADDR,
12585 (EEPROM_ADDR_FSM_RESET |
12586 (EEPROM_DEFAULT_CLOCK_PERIOD <<
12587 EEPROM_ADDR_CLKPERD_SHIFT)));
12588
Michael Chan9d57f012006-12-07 00:23:25 -080012589 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012590
12591 /* Enable seeprom accesses. */
12592 tw32_f(GRC_LOCAL_CTRL,
12593 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
12594 udelay(100);
12595
12596 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12597 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
Joe Perches63c3a662011-04-26 08:12:10 +000012598 tg3_flag_set(tp, NVRAM);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012599
Michael Chanec41c7d2006-01-17 02:40:55 -080012600 if (tg3_nvram_lock(tp)) {
Matt Carlson5129c3a2010-04-05 10:19:23 +000012601 netdev_warn(tp->dev,
12602 "Cannot get nvram lock, %s failed\n",
Joe Perches05dbe002010-02-17 19:44:19 +000012603 __func__);
Michael Chanec41c7d2006-01-17 02:40:55 -080012604 return;
12605 }
Michael Chane6af3012005-04-21 17:12:05 -070012606 tg3_enable_nvram_access(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012607
Matt Carlson989a9d22007-05-05 11:51:05 -070012608 tp->nvram_size = 0;
12609
Michael Chan361b4ac2005-04-21 17:11:21 -070012610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12611 tg3_get_5752_nvram_info(tp);
Michael Chand3c7b882006-03-23 01:28:25 -080012612 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12613 tg3_get_5755_nvram_info(tp);
Matt Carlsond30cdd22007-10-07 23:28:35 -070012614 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
Matt Carlson57e69832008-05-25 23:48:31 -070012615 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12616 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
Michael Chan1b277772006-03-20 22:27:48 -080012617 tg3_get_5787_nvram_info(tp);
Matt Carlson6b91fa02007-10-10 18:01:09 -070012618 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
12619 tg3_get_5761_nvram_info(tp);
Michael Chanb5d37722006-09-27 16:06:21 -070012620 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12621 tg3_get_5906_nvram_info(tp);
Matt Carlsonb703df62009-12-03 08:36:21 +000012622 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12623 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Matt Carlson321d32a2008-11-21 17:22:19 -080012624 tg3_get_57780_nvram_info(tp);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000012625 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12626 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
Matt Carlsona1b950d2009-09-01 13:20:17 +000012627 tg3_get_5717_nvram_info(tp);
Matt Carlson9b91b5f2011-04-05 14:22:47 +000012628 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12629 tg3_get_5720_nvram_info(tp);
Michael Chan361b4ac2005-04-21 17:11:21 -070012630 else
12631 tg3_get_nvram_info(tp);
12632
Matt Carlson989a9d22007-05-05 11:51:05 -070012633 if (tp->nvram_size == 0)
12634 tg3_get_nvram_size(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012635
Michael Chane6af3012005-04-21 17:12:05 -070012636 tg3_disable_nvram_access(tp);
Michael Chan381291b2005-12-13 21:08:21 -080012637 tg3_nvram_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012638
12639 } else {
Joe Perches63c3a662011-04-26 08:12:10 +000012640 tg3_flag_clear(tp, NVRAM);
12641 tg3_flag_clear(tp, NVRAM_BUFFERED);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012642
12643 tg3_get_eeprom_size(tp);
12644 }
12645}
12646
Linus Torvalds1da177e2005-04-16 15:20:36 -070012647static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
12648 u32 offset, u32 len, u8 *buf)
12649{
12650 int i, j, rc = 0;
12651 u32 val;
12652
12653 for (i = 0; i < len; i += 4) {
Al Virob9fc7dc2007-12-17 22:59:57 -080012654 u32 addr;
Matt Carlsona9dc5292009-02-25 14:25:30 +000012655 __be32 data;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012656
12657 addr = offset + i;
12658
12659 memcpy(&data, buf + i, 4);
12660
Matt Carlson62cedd12009-04-20 14:52:29 -070012661 /*
12662 * The SEEPROM interface expects the data to always be opposite
12663 * the native endian format. We accomplish this by reversing
12664 * all the operations that would have been performed on the
12665 * data from a call to tg3_nvram_read_be32().
12666 */
12667 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
Linus Torvalds1da177e2005-04-16 15:20:36 -070012668
12669 val = tr32(GRC_EEPROM_ADDR);
12670 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
12671
12672 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
12673 EEPROM_ADDR_READ);
12674 tw32(GRC_EEPROM_ADDR, val |
12675 (0 << EEPROM_ADDR_DEVID_SHIFT) |
12676 (addr & EEPROM_ADDR_ADDR_MASK) |
12677 EEPROM_ADDR_START |
12678 EEPROM_ADDR_WRITE);
Jeff Garzik6aa20a22006-09-13 13:24:59 -040012679
Michael Chan9d57f012006-12-07 00:23:25 -080012680 for (j = 0; j < 1000; j++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012681 val = tr32(GRC_EEPROM_ADDR);
12682
12683 if (val & EEPROM_ADDR_COMPLETE)
12684 break;
Michael Chan9d57f012006-12-07 00:23:25 -080012685 msleep(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012686 }
12687 if (!(val & EEPROM_ADDR_COMPLETE)) {
12688 rc = -EBUSY;
12689 break;
12690 }
12691 }
12692
12693 return rc;
12694}
12695
12696/* offset and length are dword aligned */
12697static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
12698 u8 *buf)
12699{
12700 int ret = 0;
12701 u32 pagesize = tp->nvram_pagesize;
12702 u32 pagemask = pagesize - 1;
12703 u32 nvram_cmd;
12704 u8 *tmp;
12705
12706 tmp = kmalloc(pagesize, GFP_KERNEL);
12707 if (tmp == NULL)
12708 return -ENOMEM;
12709
12710 while (len) {
12711 int j;
Michael Chane6af3012005-04-21 17:12:05 -070012712 u32 phy_addr, page_off, size;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012713
12714 phy_addr = offset & ~pagemask;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040012715
Linus Torvalds1da177e2005-04-16 15:20:36 -070012716 for (j = 0; j < pagesize; j += 4) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000012717 ret = tg3_nvram_read_be32(tp, phy_addr + j,
12718 (__be32 *) (tmp + j));
12719 if (ret)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012720 break;
12721 }
12722 if (ret)
12723 break;
12724
Matt Carlsonc6cdf432010-04-05 10:19:26 +000012725 page_off = offset & pagemask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012726 size = pagesize;
12727 if (len < size)
12728 size = len;
12729
12730 len -= size;
12731
12732 memcpy(tmp + page_off, buf, size);
12733
12734 offset = offset + (pagesize - page_off);
12735
Michael Chane6af3012005-04-21 17:12:05 -070012736 tg3_enable_nvram_access(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012737
12738 /*
12739 * Before we can erase the flash page, we need
12740 * to issue a special "write enable" command.
12741 */
12742 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12743
12744 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12745 break;
12746
12747 /* Erase the target page */
12748 tw32(NVRAM_ADDR, phy_addr);
12749
12750 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12751 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12752
Matt Carlsonc6cdf432010-04-05 10:19:26 +000012753 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
Linus Torvalds1da177e2005-04-16 15:20:36 -070012754 break;
12755
12756 /* Issue another write enable to start the write. */
12757 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12758
12759 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12760 break;
12761
12762 for (j = 0; j < pagesize; j += 4) {
Al Virob9fc7dc2007-12-17 22:59:57 -080012763 __be32 data;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012764
Al Virob9fc7dc2007-12-17 22:59:57 -080012765 data = *((__be32 *) (tmp + j));
Matt Carlsona9dc5292009-02-25 14:25:30 +000012766
Al Virob9fc7dc2007-12-17 22:59:57 -080012767 tw32(NVRAM_WRDATA, be32_to_cpu(data));
Linus Torvalds1da177e2005-04-16 15:20:36 -070012768
12769 tw32(NVRAM_ADDR, phy_addr + j);
12770
12771 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12772 NVRAM_CMD_WR;
12773
12774 if (j == 0)
12775 nvram_cmd |= NVRAM_CMD_FIRST;
12776 else if (j == (pagesize - 4))
12777 nvram_cmd |= NVRAM_CMD_LAST;
12778
12779 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12780 break;
12781 }
12782 if (ret)
12783 break;
12784 }
12785
12786 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12787 tg3_nvram_exec_cmd(tp, nvram_cmd);
12788
12789 kfree(tmp);
12790
12791 return ret;
12792}
12793
12794/* offset and length are dword aligned */
12795static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12796 u8 *buf)
12797{
12798 int i, ret = 0;
12799
12800 for (i = 0; i < len; i += 4, offset += 4) {
Al Virob9fc7dc2007-12-17 22:59:57 -080012801 u32 page_off, phy_addr, nvram_cmd;
12802 __be32 data;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012803
12804 memcpy(&data, buf + i, 4);
Al Virob9fc7dc2007-12-17 22:59:57 -080012805 tw32(NVRAM_WRDATA, be32_to_cpu(data));
Linus Torvalds1da177e2005-04-16 15:20:36 -070012806
Matt Carlsonc6cdf432010-04-05 10:19:26 +000012807 page_off = offset % tp->nvram_pagesize;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012808
Michael Chan18201802006-03-20 22:29:15 -080012809 phy_addr = tg3_nvram_phys_addr(tp, offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012810
12811 tw32(NVRAM_ADDR, phy_addr);
12812
12813 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12814
Matt Carlsonc6cdf432010-04-05 10:19:26 +000012815 if (page_off == 0 || i == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012816 nvram_cmd |= NVRAM_CMD_FIRST;
Michael Chanf6d9a252006-04-29 19:00:24 -070012817 if (page_off == (tp->nvram_pagesize - 4))
Linus Torvalds1da177e2005-04-16 15:20:36 -070012818 nvram_cmd |= NVRAM_CMD_LAST;
12819
12820 if (i == (len - 4))
12821 nvram_cmd |= NVRAM_CMD_LAST;
12822
Matt Carlson321d32a2008-11-21 17:22:19 -080012823 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
Joe Perches63c3a662011-04-26 08:12:10 +000012824 !tg3_flag(tp, 5755_PLUS) &&
Michael Chan4c987482005-09-05 17:52:38 -070012825 (tp->nvram_jedecnum == JEDEC_ST) &&
12826 (nvram_cmd & NVRAM_CMD_FIRST)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012827
12828 if ((ret = tg3_nvram_exec_cmd(tp,
12829 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12830 NVRAM_CMD_DONE)))
12831
12832 break;
12833 }
Joe Perches63c3a662011-04-26 08:12:10 +000012834 if (!tg3_flag(tp, FLASH)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012835 /* We always do complete word writes to eeprom. */
12836 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12837 }
12838
12839 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12840 break;
12841 }
12842 return ret;
12843}
12844
12845/* offset and length are dword aligned */
12846static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12847{
12848 int ret;
12849
Joe Perches63c3a662011-04-26 08:12:10 +000012850 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
Michael Chan314fba32005-04-21 17:07:04 -070012851 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12852 ~GRC_LCLCTRL_GPIO_OUTPUT1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012853 udelay(40);
12854 }
12855
Joe Perches63c3a662011-04-26 08:12:10 +000012856 if (!tg3_flag(tp, NVRAM)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012857 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
Matt Carlson859a5882010-04-05 10:19:28 +000012858 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012859 u32 grc_mode;
12860
Michael Chanec41c7d2006-01-17 02:40:55 -080012861 ret = tg3_nvram_lock(tp);
12862 if (ret)
12863 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -070012864
Michael Chane6af3012005-04-21 17:12:05 -070012865 tg3_enable_nvram_access(tp);
Joe Perches63c3a662011-04-26 08:12:10 +000012866 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
Linus Torvalds1da177e2005-04-16 15:20:36 -070012867 tw32(NVRAM_WRITE1, 0x406);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012868
12869 grc_mode = tr32(GRC_MODE);
12870 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12871
Joe Perches63c3a662011-04-26 08:12:10 +000012872 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012873 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12874 buf);
Matt Carlson859a5882010-04-05 10:19:28 +000012875 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012876 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12877 buf);
12878 }
12879
12880 grc_mode = tr32(GRC_MODE);
12881 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12882
Michael Chane6af3012005-04-21 17:12:05 -070012883 tg3_disable_nvram_access(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012884 tg3_nvram_unlock(tp);
12885 }
12886
Joe Perches63c3a662011-04-26 08:12:10 +000012887 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
Michael Chan314fba32005-04-21 17:07:04 -070012888 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070012889 udelay(40);
12890 }
12891
12892 return ret;
12893}
12894
12895struct subsys_tbl_ent {
12896 u16 subsys_vendor, subsys_devid;
12897 u32 phy_id;
12898};
12899
Matt Carlson24daf2b2010-02-17 15:17:02 +000012900static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
Linus Torvalds1da177e2005-04-16 15:20:36 -070012901 /* Broadcom boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000012902 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012903 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012904 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012905 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012906 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012907 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012908 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12909 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12910 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012911 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012912 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012913 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012914 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12915 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12916 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012917 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012918 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012919 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012920 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012921 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012922 { TG3PCI_SUBVENDOR_ID_BROADCOM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012923 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070012924
12925 /* 3com boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000012926 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012927 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012928 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012929 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012930 { TG3PCI_SUBVENDOR_ID_3COM,
12931 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12932 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012933 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012934 { TG3PCI_SUBVENDOR_ID_3COM,
Matt Carlson79eb6902010-02-17 15:17:03 +000012935 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070012936
12937 /* DELL boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000012938 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000012939 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012940 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000012941 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012942 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000012943 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012944 { TG3PCI_SUBVENDOR_ID_DELL,
Matt Carlson79eb6902010-02-17 15:17:03 +000012945 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070012946
12947 /* Compaq boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000012948 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000012949 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012950 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000012951 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012952 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12953 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12954 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000012955 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
Matt Carlson24daf2b2010-02-17 15:17:02 +000012956 { TG3PCI_SUBVENDOR_ID_COMPAQ,
Matt Carlson79eb6902010-02-17 15:17:03 +000012957 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070012958
12959 /* IBM boards. */
Matt Carlson24daf2b2010-02-17 15:17:02 +000012960 { TG3PCI_SUBVENDOR_ID_IBM,
12961 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070012962};
12963
Matt Carlson24daf2b2010-02-17 15:17:02 +000012964static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012965{
12966 int i;
12967
12968 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12969 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12970 tp->pdev->subsystem_vendor) &&
12971 (subsys_id_to_phy_id[i].subsys_devid ==
12972 tp->pdev->subsystem_device))
12973 return &subsys_id_to_phy_id[i];
12974 }
12975 return NULL;
12976}
12977
Michael Chan7d0c41e2005-04-21 17:06:20 -070012978static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012979{
Linus Torvalds1da177e2005-04-16 15:20:36 -070012980 u32 val;
David S. Millerf49639e2006-06-09 11:58:36 -070012981
Matt Carlson79eb6902010-02-17 15:17:03 +000012982 tp->phy_id = TG3_PHY_ID_INVALID;
Michael Chan7d0c41e2005-04-21 17:06:20 -070012983 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12984
Gary Zambranoa85feb82007-05-05 11:52:19 -070012985 /* Assume an onboard device and WOL capable by default. */
Joe Perches63c3a662011-04-26 08:12:10 +000012986 tg3_flag_set(tp, EEPROM_WRITE_PROT);
12987 tg3_flag_set(tp, WOL_CAP);
David S. Miller72b845e2006-03-14 14:11:48 -080012988
Michael Chanb5d37722006-09-27 16:06:21 -070012989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chan9d26e212006-12-07 00:21:14 -080012990 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
Joe Perches63c3a662011-04-26 08:12:10 +000012991 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
12992 tg3_flag_set(tp, IS_NIC);
Michael Chan9d26e212006-12-07 00:21:14 -080012993 }
Matt Carlson0527ba32007-10-10 18:03:30 -070012994 val = tr32(VCPU_CFGSHDW);
12995 if (val & VCPU_CFGSHDW_ASPM_DBNC)
Joe Perches63c3a662011-04-26 08:12:10 +000012996 tg3_flag_set(tp, ASPM_WORKAROUND);
Matt Carlson0527ba32007-10-10 18:03:30 -070012997 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
Rafael J. Wysocki6fdbab92011-04-28 11:02:15 +000012998 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
Joe Perches63c3a662011-04-26 08:12:10 +000012999 tg3_flag_set(tp, WOL_ENABLE);
Rafael J. Wysocki6fdbab92011-04-28 11:02:15 +000013000 device_set_wakeup_enable(&tp->pdev->dev, true);
13001 }
Matt Carlson05ac4cb2008-11-03 16:53:46 -080013002 goto done;
Michael Chanb5d37722006-09-27 16:06:21 -070013003 }
13004
Linus Torvalds1da177e2005-04-16 15:20:36 -070013005 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
13006 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
13007 u32 nic_cfg, led_cfg;
Matt Carlsona9daf362008-05-25 23:49:44 -070013008 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
Michael Chan7d0c41e2005-04-21 17:06:20 -070013009 int eeprom_phy_serdes = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013010
13011 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
13012 tp->nic_sram_data_cfg = nic_cfg;
13013
13014 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
13015 ver >>= NIC_SRAM_DATA_VER_SHIFT;
Matt Carlson6ff6f812011-05-19 12:12:54 +000013016 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13017 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13018 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -070013019 (ver > 0) && (ver < 0x100))
13020 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
13021
Matt Carlsona9daf362008-05-25 23:49:44 -070013022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13023 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
13024
Linus Torvalds1da177e2005-04-16 15:20:36 -070013025 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
13026 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
13027 eeprom_phy_serdes = 1;
13028
13029 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
13030 if (nic_phy_id != 0) {
13031 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
13032 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
13033
13034 eeprom_phy_id = (id1 >> 16) << 10;
13035 eeprom_phy_id |= (id2 & 0xfc00) << 16;
13036 eeprom_phy_id |= (id2 & 0x03ff) << 0;
13037 } else
13038 eeprom_phy_id = 0;
13039
Michael Chan7d0c41e2005-04-21 17:06:20 -070013040 tp->phy_id = eeprom_phy_id;
Michael Chan747e8f82005-07-25 12:33:22 -070013041 if (eeprom_phy_serdes) {
Joe Perches63c3a662011-04-26 08:12:10 +000013042 if (!tg3_flag(tp, 5705_PLUS))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013043 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Matt Carlsona50d0792010-06-05 17:24:37 +000013044 else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013045 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
Michael Chan747e8f82005-07-25 12:33:22 -070013046 }
Michael Chan7d0c41e2005-04-21 17:06:20 -070013047
Joe Perches63c3a662011-04-26 08:12:10 +000013048 if (tg3_flag(tp, 5750_PLUS))
Linus Torvalds1da177e2005-04-16 15:20:36 -070013049 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
13050 SHASTA_EXT_LED_MODE_MASK);
John W. Linvillecbf46852005-04-21 17:01:29 -070013051 else
Linus Torvalds1da177e2005-04-16 15:20:36 -070013052 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
13053
13054 switch (led_cfg) {
13055 default:
13056 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
13057 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13058 break;
13059
13060 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
13061 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13062 break;
13063
13064 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
13065 tp->led_ctrl = LED_CTRL_MODE_MAC;
Michael Chan9ba27792005-06-06 15:16:20 -070013066
13067 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
13068 * read on some older 5700/5701 bootcode.
13069 */
13070 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
13071 ASIC_REV_5700 ||
13072 GET_ASIC_REV(tp->pci_chip_rev_id) ==
13073 ASIC_REV_5701)
13074 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
13075
Linus Torvalds1da177e2005-04-16 15:20:36 -070013076 break;
13077
13078 case SHASTA_EXT_LED_SHARED:
13079 tp->led_ctrl = LED_CTRL_MODE_SHARED;
13080 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
13081 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
13082 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13083 LED_CTRL_MODE_PHY_2);
13084 break;
13085
13086 case SHASTA_EXT_LED_MAC:
13087 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
13088 break;
13089
13090 case SHASTA_EXT_LED_COMBO:
13091 tp->led_ctrl = LED_CTRL_MODE_COMBO;
13092 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
13093 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
13094 LED_CTRL_MODE_PHY_2);
13095 break;
13096
Stephen Hemminger855e1112008-04-16 16:37:28 -070013097 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013098
13099 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13100 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
13101 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
13102 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
13103
Matt Carlsonb2a5c192008-04-03 21:44:44 -070013104 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
13105 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
Matt Carlson5f608912007-11-12 21:17:07 -080013106
Michael Chan9d26e212006-12-07 00:21:14 -080013107 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
Joe Perches63c3a662011-04-26 08:12:10 +000013108 tg3_flag_set(tp, EEPROM_WRITE_PROT);
Michael Chan9d26e212006-12-07 00:21:14 -080013109 if ((tp->pdev->subsystem_vendor ==
13110 PCI_VENDOR_ID_ARIMA) &&
13111 (tp->pdev->subsystem_device == 0x205a ||
13112 tp->pdev->subsystem_device == 0x2063))
Joe Perches63c3a662011-04-26 08:12:10 +000013113 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
Michael Chan9d26e212006-12-07 00:21:14 -080013114 } else {
Joe Perches63c3a662011-04-26 08:12:10 +000013115 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
13116 tg3_flag_set(tp, IS_NIC);
Michael Chan9d26e212006-12-07 00:21:14 -080013117 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013118
13119 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
Joe Perches63c3a662011-04-26 08:12:10 +000013120 tg3_flag_set(tp, ENABLE_ASF);
13121 if (tg3_flag(tp, 5750_PLUS))
13122 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013123 }
Matt Carlsonb2b98d42008-11-03 16:52:32 -080013124
13125 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
Joe Perches63c3a662011-04-26 08:12:10 +000013126 tg3_flag(tp, 5750_PLUS))
13127 tg3_flag_set(tp, ENABLE_APE);
Matt Carlsonb2b98d42008-11-03 16:52:32 -080013128
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013129 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
Gary Zambranoa85feb82007-05-05 11:52:19 -070013130 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
Joe Perches63c3a662011-04-26 08:12:10 +000013131 tg3_flag_clear(tp, WOL_CAP);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013132
Joe Perches63c3a662011-04-26 08:12:10 +000013133 if (tg3_flag(tp, WOL_CAP) &&
Rafael J. Wysocki6fdbab92011-04-28 11:02:15 +000013134 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
Joe Perches63c3a662011-04-26 08:12:10 +000013135 tg3_flag_set(tp, WOL_ENABLE);
Rafael J. Wysocki6fdbab92011-04-28 11:02:15 +000013136 device_set_wakeup_enable(&tp->pdev->dev, true);
13137 }
Matt Carlson0527ba32007-10-10 18:03:30 -070013138
Linus Torvalds1da177e2005-04-16 15:20:36 -070013139 if (cfg2 & (1 << 17))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013140 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013141
13142 /* serdes signal pre-emphasis in register 0x590 set by */
13143 /* bootcode if bit 18 is set */
13144 if (cfg2 & (1 << 18))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013145 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
Matt Carlson8ed5d972007-05-07 00:25:49 -070013146
Joe Perches63c3a662011-04-26 08:12:10 +000013147 if ((tg3_flag(tp, 57765_PLUS) ||
13148 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13149 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
Matt Carlson6833c042008-11-21 17:18:59 -080013150 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013151 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
Matt Carlson6833c042008-11-21 17:18:59 -080013152
Joe Perches63c3a662011-04-26 08:12:10 +000013153 if (tg3_flag(tp, PCI_EXPRESS) &&
Matt Carlson8c69b1e2010-08-02 11:26:00 +000013154 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Joe Perches63c3a662011-04-26 08:12:10 +000013155 !tg3_flag(tp, 57765_PLUS)) {
Matt Carlson8ed5d972007-05-07 00:25:49 -070013156 u32 cfg3;
13157
13158 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
13159 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
Joe Perches63c3a662011-04-26 08:12:10 +000013160 tg3_flag_set(tp, ASPM_WORKAROUND);
Matt Carlson8ed5d972007-05-07 00:25:49 -070013161 }
Matt Carlsona9daf362008-05-25 23:49:44 -070013162
Matt Carlson14417062010-02-17 15:16:59 +000013163 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
Joe Perches63c3a662011-04-26 08:12:10 +000013164 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
Matt Carlsona9daf362008-05-25 23:49:44 -070013165 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
Joe Perches63c3a662011-04-26 08:12:10 +000013166 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
Matt Carlsona9daf362008-05-25 23:49:44 -070013167 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
Joe Perches63c3a662011-04-26 08:12:10 +000013168 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013169 }
Matt Carlson05ac4cb2008-11-03 16:53:46 -080013170done:
Joe Perches63c3a662011-04-26 08:12:10 +000013171 if (tg3_flag(tp, WOL_CAP))
Rafael J. Wysocki43067ed2011-02-10 06:53:09 +000013172 device_set_wakeup_enable(&tp->pdev->dev,
Joe Perches63c3a662011-04-26 08:12:10 +000013173 tg3_flag(tp, WOL_ENABLE));
Rafael J. Wysocki43067ed2011-02-10 06:53:09 +000013174 else
13175 device_set_wakeup_capable(&tp->pdev->dev, false);
Michael Chan7d0c41e2005-04-21 17:06:20 -070013176}
13177
Matt Carlsonb2a5c192008-04-03 21:44:44 -070013178static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
13179{
13180 int i;
13181 u32 val;
13182
13183 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
13184 tw32(OTP_CTRL, cmd);
13185
13186 /* Wait for up to 1 ms for command to execute. */
13187 for (i = 0; i < 100; i++) {
13188 val = tr32(OTP_STATUS);
13189 if (val & OTP_STATUS_CMD_DONE)
13190 break;
13191 udelay(10);
13192 }
13193
13194 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
13195}
13196
13197/* Read the gphy configuration from the OTP region of the chip. The gphy
13198 * configuration is a 32-bit value that straddles the alignment boundary.
13199 * We do two 32-bit reads and then shift and merge the results.
13200 */
13201static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
13202{
13203 u32 bhalf_otp, thalf_otp;
13204
13205 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
13206
13207 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
13208 return 0;
13209
13210 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
13211
13212 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13213 return 0;
13214
13215 thalf_otp = tr32(OTP_READ_DATA);
13216
13217 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
13218
13219 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
13220 return 0;
13221
13222 bhalf_otp = tr32(OTP_READ_DATA);
13223
13224 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
13225}
13226
Matt Carlsone256f8a2011-03-09 16:58:24 +000013227static void __devinit tg3_phy_init_link_config(struct tg3 *tp)
13228{
13229 u32 adv = ADVERTISED_Autoneg |
13230 ADVERTISED_Pause;
13231
13232 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
13233 adv |= ADVERTISED_1000baseT_Half |
13234 ADVERTISED_1000baseT_Full;
13235
13236 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13237 adv |= ADVERTISED_100baseT_Half |
13238 ADVERTISED_100baseT_Full |
13239 ADVERTISED_10baseT_Half |
13240 ADVERTISED_10baseT_Full |
13241 ADVERTISED_TP;
13242 else
13243 adv |= ADVERTISED_FIBRE;
13244
13245 tp->link_config.advertising = adv;
13246 tp->link_config.speed = SPEED_INVALID;
13247 tp->link_config.duplex = DUPLEX_INVALID;
13248 tp->link_config.autoneg = AUTONEG_ENABLE;
13249 tp->link_config.active_speed = SPEED_INVALID;
13250 tp->link_config.active_duplex = DUPLEX_INVALID;
13251 tp->link_config.orig_speed = SPEED_INVALID;
13252 tp->link_config.orig_duplex = DUPLEX_INVALID;
13253 tp->link_config.orig_autoneg = AUTONEG_INVALID;
13254}
13255
Michael Chan7d0c41e2005-04-21 17:06:20 -070013256static int __devinit tg3_phy_probe(struct tg3 *tp)
13257{
13258 u32 hw_phy_id_1, hw_phy_id_2;
13259 u32 hw_phy_id, hw_phy_id_masked;
13260 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013261
Matt Carlsone256f8a2011-03-09 16:58:24 +000013262 /* flow control autonegotiation is default behavior */
Joe Perches63c3a662011-04-26 08:12:10 +000013263 tg3_flag_set(tp, PAUSE_AUTONEG);
Matt Carlsone256f8a2011-03-09 16:58:24 +000013264 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
13265
Joe Perches63c3a662011-04-26 08:12:10 +000013266 if (tg3_flag(tp, USE_PHYLIB))
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070013267 return tg3_phy_init(tp);
13268
Linus Torvalds1da177e2005-04-16 15:20:36 -070013269 /* Reading the PHY ID register can conflict with ASF
Nick Andrew877d0312009-01-26 11:06:57 +010013270 * firmware access to the PHY hardware.
Linus Torvalds1da177e2005-04-16 15:20:36 -070013271 */
13272 err = 0;
Joe Perches63c3a662011-04-26 08:12:10 +000013273 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
Matt Carlson79eb6902010-02-17 15:17:03 +000013274 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013275 } else {
13276 /* Now read the physical PHY_ID from the chip and verify
13277 * that it is sane. If it doesn't look good, we fall back
13278 * to either the hard-coded table based PHY_ID and failing
13279 * that the value found in the eeprom area.
13280 */
13281 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
13282 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
13283
13284 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
13285 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
13286 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
13287
Matt Carlson79eb6902010-02-17 15:17:03 +000013288 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013289 }
13290
Matt Carlson79eb6902010-02-17 15:17:03 +000013291 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070013292 tp->phy_id = hw_phy_id;
Matt Carlson79eb6902010-02-17 15:17:03 +000013293 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013294 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Michael Chanda6b2d02005-08-19 12:54:29 -070013295 else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013296 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013297 } else {
Matt Carlson79eb6902010-02-17 15:17:03 +000013298 if (tp->phy_id != TG3_PHY_ID_INVALID) {
Michael Chan7d0c41e2005-04-21 17:06:20 -070013299 /* Do nothing, phy ID already set up in
13300 * tg3_get_eeprom_hw_cfg().
13301 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070013302 } else {
13303 struct subsys_tbl_ent *p;
13304
13305 /* No eeprom signature? Try the hardcoded
13306 * subsys device table.
13307 */
Matt Carlson24daf2b2010-02-17 15:17:02 +000013308 p = tg3_lookup_by_subsys(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013309 if (!p)
13310 return -ENODEV;
13311
13312 tp->phy_id = p->phy_id;
13313 if (!tp->phy_id ||
Matt Carlson79eb6902010-02-17 15:17:03 +000013314 tp->phy_id == TG3_PHY_ID_BCM8002)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013315 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013316 }
13317 }
13318
Matt Carlsona6b68da2010-12-06 08:28:52 +000013319 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
Matt Carlson5baa5e92011-07-20 10:20:53 +000013320 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13321 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720 ||
13322 (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
Matt Carlsona6b68da2010-12-06 08:28:52 +000013323 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
13324 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
13325 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
Matt Carlson52b02d02010-10-14 10:37:41 +000013326 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
13327
Matt Carlsone256f8a2011-03-09 16:58:24 +000013328 tg3_phy_init_link_config(tp);
13329
Matt Carlsonf07e9af2010-08-02 11:26:07 +000013330 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
Joe Perches63c3a662011-04-26 08:12:10 +000013331 !tg3_flag(tp, ENABLE_APE) &&
13332 !tg3_flag(tp, ENABLE_ASF)) {
Matt Carlson42b64a42011-05-19 12:12:49 +000013333 u32 bmsr, mask;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013334
13335 tg3_readphy(tp, MII_BMSR, &bmsr);
13336 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
13337 (bmsr & BMSR_LSTATUS))
13338 goto skip_phy_reset;
Jeff Garzik6aa20a22006-09-13 13:24:59 -040013339
Linus Torvalds1da177e2005-04-16 15:20:36 -070013340 err = tg3_phy_reset(tp);
13341 if (err)
13342 return err;
13343
Matt Carlson42b64a42011-05-19 12:12:49 +000013344 tg3_phy_set_wirespeed(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013345
Michael Chan3600d912006-12-07 00:21:48 -080013346 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13347 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13348 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
13349 if (!tg3_copper_is_advertising_all(tp, mask)) {
Matt Carlson42b64a42011-05-19 12:12:49 +000013350 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
13351 tp->link_config.flowctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013352
13353 tg3_writephy(tp, MII_BMCR,
13354 BMCR_ANENABLE | BMCR_ANRESTART);
13355 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013356 }
13357
13358skip_phy_reset:
Matt Carlson79eb6902010-02-17 15:17:03 +000013359 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070013360 err = tg3_init_5401phy_dsp(tp);
13361 if (err)
13362 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013363
Linus Torvalds1da177e2005-04-16 15:20:36 -070013364 err = tg3_init_5401phy_dsp(tp);
13365 }
13366
Linus Torvalds1da177e2005-04-16 15:20:36 -070013367 return err;
13368}
13369
Matt Carlson184b8902010-04-05 10:19:25 +000013370static void __devinit tg3_read_vpd(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070013371{
Matt Carlsona4a8bb12010-09-15 09:00:00 +000013372 u8 *vpd_data;
Matt Carlson4181b2c2010-02-26 14:04:45 +000013373 unsigned int block_end, rosize, len;
Matt Carlson535a4902011-07-20 10:20:56 +000013374 u32 vpdlen;
Matt Carlson184b8902010-04-05 10:19:25 +000013375 int j, i = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013376
Matt Carlson535a4902011-07-20 10:20:56 +000013377 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
Matt Carlsona4a8bb12010-09-15 09:00:00 +000013378 if (!vpd_data)
13379 goto out_no_vpd;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013380
Matt Carlson535a4902011-07-20 10:20:56 +000013381 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
Matt Carlson4181b2c2010-02-26 14:04:45 +000013382 if (i < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070013383 goto out_not_found;
Matt Carlson4181b2c2010-02-26 14:04:45 +000013384
13385 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
13386 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
13387 i += PCI_VPD_LRDT_TAG_SIZE;
13388
Matt Carlson535a4902011-07-20 10:20:56 +000013389 if (block_end > vpdlen)
Matt Carlson4181b2c2010-02-26 14:04:45 +000013390 goto out_not_found;
13391
Matt Carlson184b8902010-04-05 10:19:25 +000013392 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13393 PCI_VPD_RO_KEYWORD_MFR_ID);
13394 if (j > 0) {
13395 len = pci_vpd_info_field_size(&vpd_data[j]);
13396
13397 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13398 if (j + len > block_end || len != 4 ||
13399 memcmp(&vpd_data[j], "1028", 4))
13400 goto partno;
13401
13402 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13403 PCI_VPD_RO_KEYWORD_VENDOR0);
13404 if (j < 0)
13405 goto partno;
13406
13407 len = pci_vpd_info_field_size(&vpd_data[j]);
13408
13409 j += PCI_VPD_INFO_FLD_HDR_SIZE;
13410 if (j + len > block_end)
13411 goto partno;
13412
13413 memcpy(tp->fw_ver, &vpd_data[j], len);
Matt Carlson535a4902011-07-20 10:20:56 +000013414 strncat(tp->fw_ver, " bc ", vpdlen - len - 1);
Matt Carlson184b8902010-04-05 10:19:25 +000013415 }
13416
13417partno:
Matt Carlson4181b2c2010-02-26 14:04:45 +000013418 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
13419 PCI_VPD_RO_KEYWORD_PARTNO);
13420 if (i < 0)
13421 goto out_not_found;
13422
13423 len = pci_vpd_info_field_size(&vpd_data[i]);
13424
13425 i += PCI_VPD_INFO_FLD_HDR_SIZE;
13426 if (len > TG3_BPN_SIZE ||
Matt Carlson535a4902011-07-20 10:20:56 +000013427 (len + i) > vpdlen)
Matt Carlson4181b2c2010-02-26 14:04:45 +000013428 goto out_not_found;
13429
13430 memcpy(tp->board_part_number, &vpd_data[i], len);
13431
Linus Torvalds1da177e2005-04-16 15:20:36 -070013432out_not_found:
Matt Carlsona4a8bb12010-09-15 09:00:00 +000013433 kfree(vpd_data);
Matt Carlson37a949c2010-09-30 10:34:33 +000013434 if (tp->board_part_number[0])
Matt Carlsona4a8bb12010-09-15 09:00:00 +000013435 return;
13436
13437out_no_vpd:
Matt Carlson37a949c2010-09-30 10:34:33 +000013438 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13439 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
13440 strcpy(tp->board_part_number, "BCM5717");
13441 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
13442 strcpy(tp->board_part_number, "BCM5718");
13443 else
13444 goto nomatch;
13445 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
13446 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
13447 strcpy(tp->board_part_number, "BCM57780");
13448 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
13449 strcpy(tp->board_part_number, "BCM57760");
13450 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
13451 strcpy(tp->board_part_number, "BCM57790");
13452 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
13453 strcpy(tp->board_part_number, "BCM57788");
13454 else
13455 goto nomatch;
13456 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13457 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
13458 strcpy(tp->board_part_number, "BCM57761");
13459 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
13460 strcpy(tp->board_part_number, "BCM57765");
13461 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
13462 strcpy(tp->board_part_number, "BCM57781");
13463 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
13464 strcpy(tp->board_part_number, "BCM57785");
13465 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
13466 strcpy(tp->board_part_number, "BCM57791");
13467 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13468 strcpy(tp->board_part_number, "BCM57795");
13469 else
13470 goto nomatch;
13471 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Michael Chanb5d37722006-09-27 16:06:21 -070013472 strcpy(tp->board_part_number, "BCM95906");
Matt Carlson37a949c2010-09-30 10:34:33 +000013473 } else {
13474nomatch:
Michael Chanb5d37722006-09-27 16:06:21 -070013475 strcpy(tp->board_part_number, "none");
Matt Carlson37a949c2010-09-30 10:34:33 +000013476 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013477}
13478
Matt Carlson9c8a6202007-10-21 16:16:08 -070013479static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
13480{
13481 u32 val;
13482
Matt Carlsone4f34112009-02-25 14:25:00 +000013483 if (tg3_nvram_read(tp, offset, &val) ||
Matt Carlson9c8a6202007-10-21 16:16:08 -070013484 (val & 0xfc000000) != 0x0c000000 ||
Matt Carlsone4f34112009-02-25 14:25:00 +000013485 tg3_nvram_read(tp, offset + 4, &val) ||
Matt Carlson9c8a6202007-10-21 16:16:08 -070013486 val != 0)
13487 return 0;
13488
13489 return 1;
13490}
13491
Matt Carlsonacd9c112009-02-25 14:26:33 +000013492static void __devinit tg3_read_bc_ver(struct tg3 *tp)
13493{
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013494 u32 val, offset, start, ver_offset;
Matt Carlson75f99362010-04-05 10:19:24 +000013495 int i, dst_off;
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013496 bool newver = false;
Matt Carlsonacd9c112009-02-25 14:26:33 +000013497
13498 if (tg3_nvram_read(tp, 0xc, &offset) ||
13499 tg3_nvram_read(tp, 0x4, &start))
13500 return;
13501
13502 offset = tg3_nvram_logical_addr(tp, offset);
13503
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013504 if (tg3_nvram_read(tp, offset, &val))
Matt Carlsonacd9c112009-02-25 14:26:33 +000013505 return;
13506
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013507 if ((val & 0xfc000000) == 0x0c000000) {
13508 if (tg3_nvram_read(tp, offset + 4, &val))
Matt Carlsonacd9c112009-02-25 14:26:33 +000013509 return;
13510
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013511 if (val == 0)
13512 newver = true;
13513 }
13514
Matt Carlson75f99362010-04-05 10:19:24 +000013515 dst_off = strlen(tp->fw_ver);
13516
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013517 if (newver) {
Matt Carlson75f99362010-04-05 10:19:24 +000013518 if (TG3_VER_SIZE - dst_off < 16 ||
13519 tg3_nvram_read(tp, offset + 8, &ver_offset))
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013520 return;
13521
13522 offset = offset + ver_offset - start;
13523 for (i = 0; i < 16; i += 4) {
13524 __be32 v;
13525 if (tg3_nvram_read_be32(tp, offset + i, &v))
13526 return;
13527
Matt Carlson75f99362010-04-05 10:19:24 +000013528 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
Matt Carlsonff3a7cb2009-02-25 14:26:58 +000013529 }
13530 } else {
13531 u32 major, minor;
13532
13533 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
13534 return;
13535
13536 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
13537 TG3_NVM_BCVER_MAJSFT;
13538 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
Matt Carlson75f99362010-04-05 10:19:24 +000013539 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
13540 "v%d.%02d", major, minor);
Matt Carlsonacd9c112009-02-25 14:26:33 +000013541 }
13542}
13543
Matt Carlsona6f6cb12009-02-25 14:27:43 +000013544static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
13545{
13546 u32 val, major, minor;
13547
13548 /* Use native endian representation */
13549 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
13550 return;
13551
13552 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
13553 TG3_NVM_HWSB_CFG1_MAJSFT;
13554 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
13555 TG3_NVM_HWSB_CFG1_MINSFT;
13556
13557 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
13558}
13559
Matt Carlsondfe00d72008-11-21 17:19:41 -080013560static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
13561{
13562 u32 offset, major, minor, build;
13563
Matt Carlson75f99362010-04-05 10:19:24 +000013564 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
Matt Carlsondfe00d72008-11-21 17:19:41 -080013565
13566 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
13567 return;
13568
13569 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
13570 case TG3_EEPROM_SB_REVISION_0:
13571 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
13572 break;
13573 case TG3_EEPROM_SB_REVISION_2:
13574 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
13575 break;
13576 case TG3_EEPROM_SB_REVISION_3:
13577 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
13578 break;
Matt Carlsona4153d42010-02-17 15:16:56 +000013579 case TG3_EEPROM_SB_REVISION_4:
13580 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
13581 break;
13582 case TG3_EEPROM_SB_REVISION_5:
13583 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
13584 break;
Matt Carlsonbba226a2010-10-14 10:37:38 +000013585 case TG3_EEPROM_SB_REVISION_6:
13586 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
13587 break;
Matt Carlsondfe00d72008-11-21 17:19:41 -080013588 default:
13589 return;
13590 }
13591
Matt Carlsone4f34112009-02-25 14:25:00 +000013592 if (tg3_nvram_read(tp, offset, &val))
Matt Carlsondfe00d72008-11-21 17:19:41 -080013593 return;
13594
13595 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
13596 TG3_EEPROM_SB_EDH_BLD_SHFT;
13597 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
13598 TG3_EEPROM_SB_EDH_MAJ_SHFT;
13599 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
13600
13601 if (minor > 99 || build > 26)
13602 return;
13603
Matt Carlson75f99362010-04-05 10:19:24 +000013604 offset = strlen(tp->fw_ver);
13605 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
13606 " v%d.%02d", major, minor);
Matt Carlsondfe00d72008-11-21 17:19:41 -080013607
13608 if (build > 0) {
Matt Carlson75f99362010-04-05 10:19:24 +000013609 offset = strlen(tp->fw_ver);
13610 if (offset < TG3_VER_SIZE - 1)
13611 tp->fw_ver[offset] = 'a' + build - 1;
Matt Carlsondfe00d72008-11-21 17:19:41 -080013612 }
13613}
13614
Matt Carlsonacd9c112009-02-25 14:26:33 +000013615static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
Michael Chanc4e65752006-03-20 22:29:32 -080013616{
13617 u32 val, offset, start;
Matt Carlsonacd9c112009-02-25 14:26:33 +000013618 int i, vlen;
Matt Carlson9c8a6202007-10-21 16:16:08 -070013619
13620 for (offset = TG3_NVM_DIR_START;
13621 offset < TG3_NVM_DIR_END;
13622 offset += TG3_NVM_DIRENT_SIZE) {
Matt Carlsone4f34112009-02-25 14:25:00 +000013623 if (tg3_nvram_read(tp, offset, &val))
Matt Carlson9c8a6202007-10-21 16:16:08 -070013624 return;
13625
13626 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
13627 break;
13628 }
13629
13630 if (offset == TG3_NVM_DIR_END)
13631 return;
13632
Joe Perches63c3a662011-04-26 08:12:10 +000013633 if (!tg3_flag(tp, 5705_PLUS))
Matt Carlson9c8a6202007-10-21 16:16:08 -070013634 start = 0x08000000;
Matt Carlsone4f34112009-02-25 14:25:00 +000013635 else if (tg3_nvram_read(tp, offset - 4, &start))
Matt Carlson9c8a6202007-10-21 16:16:08 -070013636 return;
13637
Matt Carlsone4f34112009-02-25 14:25:00 +000013638 if (tg3_nvram_read(tp, offset + 4, &offset) ||
Matt Carlson9c8a6202007-10-21 16:16:08 -070013639 !tg3_fw_img_is_valid(tp, offset) ||
Matt Carlsone4f34112009-02-25 14:25:00 +000013640 tg3_nvram_read(tp, offset + 8, &val))
Matt Carlson9c8a6202007-10-21 16:16:08 -070013641 return;
13642
13643 offset += val - start;
13644
Matt Carlsonacd9c112009-02-25 14:26:33 +000013645 vlen = strlen(tp->fw_ver);
Matt Carlson9c8a6202007-10-21 16:16:08 -070013646
Matt Carlsonacd9c112009-02-25 14:26:33 +000013647 tp->fw_ver[vlen++] = ',';
13648 tp->fw_ver[vlen++] = ' ';
Matt Carlson9c8a6202007-10-21 16:16:08 -070013649
13650 for (i = 0; i < 4; i++) {
Matt Carlsona9dc5292009-02-25 14:25:30 +000013651 __be32 v;
13652 if (tg3_nvram_read_be32(tp, offset, &v))
Matt Carlson9c8a6202007-10-21 16:16:08 -070013653 return;
13654
Al Virob9fc7dc2007-12-17 22:59:57 -080013655 offset += sizeof(v);
Matt Carlson9c8a6202007-10-21 16:16:08 -070013656
Matt Carlsonacd9c112009-02-25 14:26:33 +000013657 if (vlen > TG3_VER_SIZE - sizeof(v)) {
13658 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
Matt Carlson9c8a6202007-10-21 16:16:08 -070013659 break;
13660 }
13661
Matt Carlsonacd9c112009-02-25 14:26:33 +000013662 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
13663 vlen += sizeof(v);
Matt Carlson9c8a6202007-10-21 16:16:08 -070013664 }
Matt Carlsonacd9c112009-02-25 14:26:33 +000013665}
13666
Matt Carlson7fd76442009-02-25 14:27:20 +000013667static void __devinit tg3_read_dash_ver(struct tg3 *tp)
13668{
13669 int vlen;
13670 u32 apedata;
Matt Carlsonecc79642010-08-02 11:26:01 +000013671 char *fwtype;
Matt Carlson7fd76442009-02-25 14:27:20 +000013672
Joe Perches63c3a662011-04-26 08:12:10 +000013673 if (!tg3_flag(tp, ENABLE_APE) || !tg3_flag(tp, ENABLE_ASF))
Matt Carlson7fd76442009-02-25 14:27:20 +000013674 return;
13675
13676 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
13677 if (apedata != APE_SEG_SIG_MAGIC)
13678 return;
13679
13680 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
13681 if (!(apedata & APE_FW_STATUS_READY))
13682 return;
13683
13684 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
13685
Matt Carlsondc6d0742010-09-15 08:59:55 +000013686 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
Joe Perches63c3a662011-04-26 08:12:10 +000013687 tg3_flag_set(tp, APE_HAS_NCSI);
Matt Carlsonecc79642010-08-02 11:26:01 +000013688 fwtype = "NCSI";
Matt Carlsondc6d0742010-09-15 08:59:55 +000013689 } else {
Matt Carlsonecc79642010-08-02 11:26:01 +000013690 fwtype = "DASH";
Matt Carlsondc6d0742010-09-15 08:59:55 +000013691 }
Matt Carlsonecc79642010-08-02 11:26:01 +000013692
Matt Carlson7fd76442009-02-25 14:27:20 +000013693 vlen = strlen(tp->fw_ver);
13694
Matt Carlsonecc79642010-08-02 11:26:01 +000013695 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13696 fwtype,
Matt Carlson7fd76442009-02-25 14:27:20 +000013697 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13698 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13699 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13700 (apedata & APE_FW_VERSION_BLDMSK));
13701}
13702
Matt Carlsonacd9c112009-02-25 14:26:33 +000013703static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13704{
13705 u32 val;
Matt Carlson75f99362010-04-05 10:19:24 +000013706 bool vpd_vers = false;
13707
13708 if (tp->fw_ver[0] != 0)
13709 vpd_vers = true;
Matt Carlsonacd9c112009-02-25 14:26:33 +000013710
Joe Perches63c3a662011-04-26 08:12:10 +000013711 if (tg3_flag(tp, NO_NVRAM)) {
Matt Carlson75f99362010-04-05 10:19:24 +000013712 strcat(tp->fw_ver, "sb");
Matt Carlsondf259d82009-04-20 06:57:14 +000013713 return;
13714 }
13715
Matt Carlsonacd9c112009-02-25 14:26:33 +000013716 if (tg3_nvram_read(tp, 0, &val))
13717 return;
13718
13719 if (val == TG3_EEPROM_MAGIC)
13720 tg3_read_bc_ver(tp);
13721 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13722 tg3_read_sb_ver(tp, val);
Matt Carlsona6f6cb12009-02-25 14:27:43 +000013723 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13724 tg3_read_hwsb_ver(tp);
Matt Carlsonacd9c112009-02-25 14:26:33 +000013725 else
13726 return;
13727
Matt Carlsonc9cab242011-07-13 09:27:27 +000013728 if (vpd_vers)
Matt Carlson75f99362010-04-05 10:19:24 +000013729 goto done;
Matt Carlsonacd9c112009-02-25 14:26:33 +000013730
Matt Carlsonc9cab242011-07-13 09:27:27 +000013731 if (tg3_flag(tp, ENABLE_APE)) {
13732 if (tg3_flag(tp, ENABLE_ASF))
13733 tg3_read_dash_ver(tp);
13734 } else if (tg3_flag(tp, ENABLE_ASF)) {
13735 tg3_read_mgmtfw_ver(tp);
13736 }
Matt Carlson9c8a6202007-10-21 16:16:08 -070013737
Matt Carlson75f99362010-04-05 10:19:24 +000013738done:
Matt Carlson9c8a6202007-10-21 16:16:08 -070013739 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
Michael Chanc4e65752006-03-20 22:29:32 -080013740}
13741
Michael Chan7544b092007-05-05 13:08:32 -070013742static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13743
Matt Carlson7cb32cf2010-09-30 10:34:36 +000013744static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13745{
Joe Perches63c3a662011-04-26 08:12:10 +000013746 if (tg3_flag(tp, LRG_PROD_RING_CAP))
Matt Carlsonde9f5232011-04-05 14:22:43 +000013747 return TG3_RX_RET_MAX_SIZE_5717;
Joe Perches63c3a662011-04-26 08:12:10 +000013748 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
Matt Carlsonde9f5232011-04-05 14:22:43 +000013749 return TG3_RX_RET_MAX_SIZE_5700;
Matt Carlson7cb32cf2010-09-30 10:34:36 +000013750 else
Matt Carlsonde9f5232011-04-05 14:22:43 +000013751 return TG3_RX_RET_MAX_SIZE_5705;
Matt Carlson7cb32cf2010-09-30 10:34:36 +000013752}
13753
Matt Carlson41434702011-03-09 16:58:22 +000013754static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
Joe Perches895950c2010-12-21 02:16:08 -080013755 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13756 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13757 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
13758 { },
13759};
13760
Linus Torvalds1da177e2005-04-16 15:20:36 -070013761static int __devinit tg3_get_invariants(struct tg3 *tp)
13762{
Linus Torvalds1da177e2005-04-16 15:20:36 -070013763 u32 misc_ctrl_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013764 u32 pci_state_reg, grc_misc_cfg;
13765 u32 val;
13766 u16 pci_cmd;
Matt Carlson5e7dfd02008-11-21 17:18:16 -080013767 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070013768
Linus Torvalds1da177e2005-04-16 15:20:36 -070013769 /* Force memory write invalidate off. If we leave it on,
13770 * then on 5700_BX chips we have to enable a workaround.
13771 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13772 * to match the cacheline size. The Broadcom driver have this
13773 * workaround but turns MWI off all the times so never uses
13774 * it. This seems to suggest that the workaround is insufficient.
13775 */
13776 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13777 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13778 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13779
Matt Carlson16821282011-07-13 09:27:28 +000013780 /* Important! -- Make sure register accesses are byteswapped
13781 * correctly. Also, for those chips that require it, make
13782 * sure that indirect register accesses are enabled before
13783 * the first operation.
Linus Torvalds1da177e2005-04-16 15:20:36 -070013784 */
13785 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13786 &misc_ctrl_reg);
Matt Carlson16821282011-07-13 09:27:28 +000013787 tp->misc_host_ctrl |= (misc_ctrl_reg &
13788 MISC_HOST_CTRL_CHIPREV);
13789 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13790 tp->misc_host_ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070013791
13792 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13793 MISC_HOST_CTRL_CHIPREV_SHIFT);
Matt Carlson795d01c2007-10-07 23:28:17 -070013794 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13795 u32 prod_id_asic_rev;
13796
Matt Carlson5001e2f2009-11-13 13:03:51 +000013797 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13798 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
Matt Carlsond78b59f2011-04-05 14:22:46 +000013799 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
13800 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720)
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013801 pci_read_config_dword(tp->pdev,
13802 TG3PCI_GEN2_PRODID_ASICREV,
13803 &prod_id_asic_rev);
Matt Carlsonb703df62009-12-03 08:36:21 +000013804 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13805 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13806 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13807 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13808 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13809 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13810 pci_read_config_dword(tp->pdev,
13811 TG3PCI_GEN15_PRODID_ASICREV,
13812 &prod_id_asic_rev);
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013813 else
13814 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13815 &prod_id_asic_rev);
13816
Matt Carlson321d32a2008-11-21 17:22:19 -080013817 tp->pci_chip_rev_id = prod_id_asic_rev;
Matt Carlson795d01c2007-10-07 23:28:17 -070013818 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070013819
Michael Chanff645be2005-04-21 17:09:53 -070013820 /* Wrong chip ID in 5752 A0. This code can be removed later
13821 * as A0 is not in production.
13822 */
13823 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13824 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13825
Michael Chan68929142005-08-09 20:17:14 -070013826 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13827 * we need to disable memory and use config. cycles
13828 * only to access all registers. The 5702/03 chips
13829 * can mistakenly decode the special cycles from the
13830 * ICH chipsets as memory write cycles, causing corruption
13831 * of register and memory space. Only certain ICH bridges
13832 * will drive special cycles with non-zero data during the
13833 * address phase which can fall within the 5703's address
13834 * range. This is not an ICH bug as the PCI spec allows
13835 * non-zero address during special cycles. However, only
13836 * these ICH bridges are known to drive non-zero addresses
13837 * during special cycles.
13838 *
13839 * Since special cycles do not cross PCI bridges, we only
13840 * enable this workaround if the 5703 is on the secondary
13841 * bus of these ICH bridges.
13842 */
13843 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13844 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13845 static struct tg3_dev_id {
13846 u32 vendor;
13847 u32 device;
13848 u32 rev;
13849 } ich_chipsets[] = {
13850 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13851 PCI_ANY_ID },
13852 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13853 PCI_ANY_ID },
13854 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13855 0xa },
13856 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13857 PCI_ANY_ID },
13858 { },
13859 };
13860 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13861 struct pci_dev *bridge = NULL;
13862
13863 while (pci_id->vendor != 0) {
13864 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13865 bridge);
13866 if (!bridge) {
13867 pci_id++;
13868 continue;
13869 }
13870 if (pci_id->rev != PCI_ANY_ID) {
Auke Kok44c10132007-06-08 15:46:36 -070013871 if (bridge->revision > pci_id->rev)
Michael Chan68929142005-08-09 20:17:14 -070013872 continue;
13873 }
13874 if (bridge->subordinate &&
13875 (bridge->subordinate->number ==
13876 tp->pdev->bus->number)) {
Joe Perches63c3a662011-04-26 08:12:10 +000013877 tg3_flag_set(tp, ICH_WORKAROUND);
Michael Chan68929142005-08-09 20:17:14 -070013878 pci_dev_put(bridge);
13879 break;
13880 }
13881 }
13882 }
13883
Matt Carlson6ff6f812011-05-19 12:12:54 +000013884 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
Matt Carlson41588ba2008-04-19 18:12:33 -070013885 static struct tg3_dev_id {
13886 u32 vendor;
13887 u32 device;
13888 } bridge_chipsets[] = {
13889 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13890 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13891 { },
13892 };
13893 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13894 struct pci_dev *bridge = NULL;
13895
13896 while (pci_id->vendor != 0) {
13897 bridge = pci_get_device(pci_id->vendor,
13898 pci_id->device,
13899 bridge);
13900 if (!bridge) {
13901 pci_id++;
13902 continue;
13903 }
13904 if (bridge->subordinate &&
13905 (bridge->subordinate->number <=
13906 tp->pdev->bus->number) &&
13907 (bridge->subordinate->subordinate >=
13908 tp->pdev->bus->number)) {
Joe Perches63c3a662011-04-26 08:12:10 +000013909 tg3_flag_set(tp, 5701_DMA_BUG);
Matt Carlson41588ba2008-04-19 18:12:33 -070013910 pci_dev_put(bridge);
13911 break;
13912 }
13913 }
13914 }
13915
Michael Chan4a29cc22006-03-19 13:21:12 -080013916 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13917 * DMA addresses > 40-bit. This bridge may have other additional
13918 * 57xx devices behind it in some 4-port NIC designs for example.
13919 * Any tg3 device found behind the bridge will also need the 40-bit
13920 * DMA workaround.
13921 */
Michael Chana4e2b342005-10-26 15:46:52 -070013922 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13923 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
Joe Perches63c3a662011-04-26 08:12:10 +000013924 tg3_flag_set(tp, 5780_CLASS);
13925 tg3_flag_set(tp, 40BIT_DMA_BUG);
Michael Chan4cf78e42005-07-25 12:29:19 -070013926 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
Matt Carlson859a5882010-04-05 10:19:28 +000013927 } else {
Michael Chan4a29cc22006-03-19 13:21:12 -080013928 struct pci_dev *bridge = NULL;
13929
13930 do {
13931 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13932 PCI_DEVICE_ID_SERVERWORKS_EPB,
13933 bridge);
13934 if (bridge && bridge->subordinate &&
13935 (bridge->subordinate->number <=
13936 tp->pdev->bus->number) &&
13937 (bridge->subordinate->subordinate >=
13938 tp->pdev->bus->number)) {
Joe Perches63c3a662011-04-26 08:12:10 +000013939 tg3_flag_set(tp, 40BIT_DMA_BUG);
Michael Chan4a29cc22006-03-19 13:21:12 -080013940 pci_dev_put(bridge);
13941 break;
13942 }
13943 } while (bridge);
13944 }
Michael Chan4cf78e42005-07-25 12:29:19 -070013945
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013946 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
Matt Carlson3a1e19d2011-07-13 09:27:32 +000013947 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)
Michael Chan7544b092007-05-05 13:08:32 -070013948 tp->pdev_peer = tg3_find_peer(tp);
13949
Matt Carlsonc885e822010-08-02 11:25:57 +000013950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
Matt Carlsond78b59f2011-04-05 14:22:46 +000013951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13952 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
Joe Perches63c3a662011-04-26 08:12:10 +000013953 tg3_flag_set(tp, 5717_PLUS);
Matt Carlson0a58d662011-04-05 14:22:45 +000013954
13955 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
Joe Perches63c3a662011-04-26 08:12:10 +000013956 tg3_flag(tp, 5717_PLUS))
13957 tg3_flag_set(tp, 57765_PLUS);
Matt Carlsonc885e822010-08-02 11:25:57 +000013958
Matt Carlson321d32a2008-11-21 17:22:19 -080013959 /* Intentionally exclude ASIC_REV_5906 */
13960 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
Michael Chand9ab5ad2006-03-20 22:27:35 -080013961 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
Matt Carlsond30cdd22007-10-07 23:28:35 -070013962 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson9936bcf2007-10-10 18:03:07 -070013963 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson57e69832008-05-25 23:48:31 -070013964 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000013965 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
Joe Perches63c3a662011-04-26 08:12:10 +000013966 tg3_flag(tp, 57765_PLUS))
13967 tg3_flag_set(tp, 5755_PLUS);
Matt Carlson321d32a2008-11-21 17:22:19 -080013968
13969 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13970 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
Michael Chanb5d37722006-09-27 16:06:21 -070013971 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
Joe Perches63c3a662011-04-26 08:12:10 +000013972 tg3_flag(tp, 5755_PLUS) ||
13973 tg3_flag(tp, 5780_CLASS))
13974 tg3_flag_set(tp, 5750_PLUS);
John W. Linville6708e5c2005-04-21 17:00:52 -070013975
Matt Carlson6ff6f812011-05-19 12:12:54 +000013976 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
Joe Perches63c3a662011-04-26 08:12:10 +000013977 tg3_flag(tp, 5750_PLUS))
13978 tg3_flag_set(tp, 5705_PLUS);
John W. Linville1b440c562005-04-21 17:03:18 -070013979
Matt Carlson507399f2009-11-13 13:03:37 +000013980 /* Determine TSO capabilities */
Matt Carlsona0512942011-07-27 14:20:54 +000013981 if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0)
Matt Carlson4d163b72011-01-25 15:58:48 +000013982 ; /* Do nothing. HW bug. */
Joe Perches63c3a662011-04-26 08:12:10 +000013983 else if (tg3_flag(tp, 57765_PLUS))
13984 tg3_flag_set(tp, HW_TSO_3);
13985 else if (tg3_flag(tp, 5755_PLUS) ||
Matt Carlsone849cdc2009-11-13 13:03:38 +000013986 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Joe Perches63c3a662011-04-26 08:12:10 +000013987 tg3_flag_set(tp, HW_TSO_2);
13988 else if (tg3_flag(tp, 5750_PLUS)) {
13989 tg3_flag_set(tp, HW_TSO_1);
13990 tg3_flag_set(tp, TSO_BUG);
Matt Carlson507399f2009-11-13 13:03:37 +000013991 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13992 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
Joe Perches63c3a662011-04-26 08:12:10 +000013993 tg3_flag_clear(tp, TSO_BUG);
Matt Carlson507399f2009-11-13 13:03:37 +000013994 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13995 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13996 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
Joe Perches63c3a662011-04-26 08:12:10 +000013997 tg3_flag_set(tp, TSO_BUG);
Matt Carlson507399f2009-11-13 13:03:37 +000013998 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13999 tp->fw_needed = FIRMWARE_TG3TSO5;
14000 else
14001 tp->fw_needed = FIRMWARE_TG3TSO;
14002 }
14003
Matt Carlsondabc5c62011-05-19 12:12:52 +000014004 /* Selectively allow TSO based on operating conditions */
Matt Carlson6ff6f812011-05-19 12:12:54 +000014005 if (tg3_flag(tp, HW_TSO_1) ||
14006 tg3_flag(tp, HW_TSO_2) ||
14007 tg3_flag(tp, HW_TSO_3) ||
Matt Carlsondabc5c62011-05-19 12:12:52 +000014008 (tp->fw_needed && !tg3_flag(tp, ENABLE_ASF)))
14009 tg3_flag_set(tp, TSO_CAPABLE);
14010 else {
14011 tg3_flag_clear(tp, TSO_CAPABLE);
14012 tg3_flag_clear(tp, TSO_BUG);
14013 tp->fw_needed = NULL;
14014 }
14015
14016 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14017 tp->fw_needed = FIRMWARE_TG3;
14018
Matt Carlson507399f2009-11-13 13:03:37 +000014019 tp->irq_max = 1;
14020
Joe Perches63c3a662011-04-26 08:12:10 +000014021 if (tg3_flag(tp, 5750_PLUS)) {
14022 tg3_flag_set(tp, SUPPORT_MSI);
Michael Chan7544b092007-05-05 13:08:32 -070014023 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
14024 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
14025 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
14026 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
14027 tp->pdev_peer == tp->pdev))
Joe Perches63c3a662011-04-26 08:12:10 +000014028 tg3_flag_clear(tp, SUPPORT_MSI);
Michael Chan7544b092007-05-05 13:08:32 -070014029
Joe Perches63c3a662011-04-26 08:12:10 +000014030 if (tg3_flag(tp, 5755_PLUS) ||
Michael Chanb5d37722006-09-27 16:06:21 -070014031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
Joe Perches63c3a662011-04-26 08:12:10 +000014032 tg3_flag_set(tp, 1SHOT_MSI);
Michael Chan52c0fd82006-06-29 20:15:54 -070014033 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014034
Joe Perches63c3a662011-04-26 08:12:10 +000014035 if (tg3_flag(tp, 57765_PLUS)) {
14036 tg3_flag_set(tp, SUPPORT_MSIX);
Matt Carlson507399f2009-11-13 13:03:37 +000014037 tp->irq_max = TG3_IRQ_MAX_VECS;
14038 }
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000014039 }
Matt Carlson0e1406d2009-11-02 12:33:33 +000014040
Matt Carlson2ffcc982011-05-19 12:12:44 +000014041 if (tg3_flag(tp, 5755_PLUS))
Joe Perches63c3a662011-04-26 08:12:10 +000014042 tg3_flag_set(tp, SHORT_DMA_BUG);
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000014043
Matt Carlsone31aa982011-07-27 14:20:53 +000014044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
14045 tg3_flag_set(tp, 4K_FIFO_LIMIT);
14046
Joe Perches63c3a662011-04-26 08:12:10 +000014047 if (tg3_flag(tp, 5717_PLUS))
14048 tg3_flag_set(tp, LRG_PROD_RING_CAP);
Matt Carlsonde9f5232011-04-05 14:22:43 +000014049
Joe Perches63c3a662011-04-26 08:12:10 +000014050 if (tg3_flag(tp, 57765_PLUS) &&
Matt Carlsona0512942011-07-27 14:20:54 +000014051 tp->pci_chip_rev_id != CHIPREV_ID_5719_A0)
Joe Perches63c3a662011-04-26 08:12:10 +000014052 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
Matt Carlsonb703df62009-12-03 08:36:21 +000014053
Joe Perches63c3a662011-04-26 08:12:10 +000014054 if (!tg3_flag(tp, 5705_PLUS) ||
14055 tg3_flag(tp, 5780_CLASS) ||
14056 tg3_flag(tp, USE_JUMBO_BDFLAG))
14057 tg3_flag_set(tp, JUMBO_CAPABLE);
Michael Chan0f893dc2005-07-25 12:30:38 -070014058
Matt Carlson52f44902008-11-21 17:17:04 -080014059 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14060 &pci_state_reg);
14061
Jon Mason708ebb32011-06-27 12:56:50 +000014062 if (pci_is_pcie(tp->pdev)) {
Matt Carlson5e7dfd02008-11-21 17:18:16 -080014063 u16 lnkctl;
14064
Joe Perches63c3a662011-04-26 08:12:10 +000014065 tg3_flag_set(tp, PCI_EXPRESS);
Matt Carlson5f5c51e2007-11-12 21:19:37 -080014066
Matt Carlsoncf790032010-11-24 08:31:48 +000014067 tp->pcie_readrq = 4096;
Matt Carlsond78b59f2011-04-05 14:22:46 +000014068 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
Matt Carlsonb4495ed2011-01-25 15:58:47 +000014070 tp->pcie_readrq = 2048;
Matt Carlsoncf790032010-11-24 08:31:48 +000014071
14072 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
Matt Carlson5f5c51e2007-11-12 21:19:37 -080014073
Matt Carlson5e7dfd02008-11-21 17:18:16 -080014074 pci_read_config_word(tp->pdev,
Jon Mason708ebb32011-06-27 12:56:50 +000014075 pci_pcie_cap(tp->pdev) + PCI_EXP_LNKCTL,
Matt Carlson5e7dfd02008-11-21 17:18:16 -080014076 &lnkctl);
14077 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
Matt Carlson7196cd62011-05-19 16:02:44 +000014078 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
14079 ASIC_REV_5906) {
Joe Perches63c3a662011-04-26 08:12:10 +000014080 tg3_flag_clear(tp, HW_TSO_2);
Matt Carlsondabc5c62011-05-19 12:12:52 +000014081 tg3_flag_clear(tp, TSO_CAPABLE);
Matt Carlson7196cd62011-05-19 16:02:44 +000014082 }
Matt Carlson5e7dfd02008-11-21 17:18:16 -080014083 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson321d32a2008-11-21 17:22:19 -080014084 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson9cf74eb2009-04-20 06:58:27 +000014085 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
14086 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
Joe Perches63c3a662011-04-26 08:12:10 +000014087 tg3_flag_set(tp, CLKREQ_BUG);
Matt Carlson614b0592010-01-20 16:58:02 +000014088 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
Joe Perches63c3a662011-04-26 08:12:10 +000014089 tg3_flag_set(tp, L1PLLPD_EN);
Michael Chanc7835a72006-11-15 21:14:42 -080014090 }
Matt Carlson52f44902008-11-21 17:17:04 -080014091 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
Jon Mason708ebb32011-06-27 12:56:50 +000014092 /* BCM5785 devices are effectively PCIe devices, and should
14093 * follow PCIe codepaths, but do not have a PCIe capabilities
14094 * section.
Matt Carlson93a700a2011-08-31 11:44:54 +000014095 */
Joe Perches63c3a662011-04-26 08:12:10 +000014096 tg3_flag_set(tp, PCI_EXPRESS);
14097 } else if (!tg3_flag(tp, 5705_PLUS) ||
14098 tg3_flag(tp, 5780_CLASS)) {
Matt Carlson52f44902008-11-21 17:17:04 -080014099 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
14100 if (!tp->pcix_cap) {
Matt Carlson2445e462010-04-05 10:19:21 +000014101 dev_err(&tp->pdev->dev,
14102 "Cannot find PCI-X capability, aborting\n");
Matt Carlson52f44902008-11-21 17:17:04 -080014103 return -EIO;
14104 }
14105
14106 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
Joe Perches63c3a662011-04-26 08:12:10 +000014107 tg3_flag_set(tp, PCIX_MODE);
Matt Carlson52f44902008-11-21 17:17:04 -080014108 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014109
Michael Chan399de502005-10-03 14:02:39 -070014110 /* If we have an AMD 762 or VIA K8T800 chipset, write
14111 * reordering to the mailbox registers done by the host
14112 * controller can cause major troubles. We read back from
14113 * every mailbox register write to force the writes to be
14114 * posted to the chip in order.
14115 */
Matt Carlson41434702011-03-09 16:58:22 +000014116 if (pci_dev_present(tg3_write_reorder_chipsets) &&
Joe Perches63c3a662011-04-26 08:12:10 +000014117 !tg3_flag(tp, PCI_EXPRESS))
14118 tg3_flag_set(tp, MBOX_WRITE_REORDER);
Michael Chan399de502005-10-03 14:02:39 -070014119
Matt Carlson69fc4052008-12-21 20:19:57 -080014120 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
14121 &tp->pci_cacheline_sz);
14122 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14123 &tp->pci_lat_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014124 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14125 tp->pci_lat_timer < 64) {
14126 tp->pci_lat_timer = 64;
Matt Carlson69fc4052008-12-21 20:19:57 -080014127 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
14128 tp->pci_lat_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014129 }
14130
Matt Carlson16821282011-07-13 09:27:28 +000014131 /* Important! -- It is critical that the PCI-X hw workaround
14132 * situation is decided before the first MMIO register access.
14133 */
Matt Carlson52f44902008-11-21 17:17:04 -080014134 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
14135 /* 5700 BX chips need to have their TX producer index
14136 * mailboxes written twice to workaround a bug.
14137 */
Joe Perches63c3a662011-04-26 08:12:10 +000014138 tg3_flag_set(tp, TXD_MBOX_HWBUG);
Matt Carlson9974a352007-10-07 23:27:28 -070014139
Matt Carlson52f44902008-11-21 17:17:04 -080014140 /* If we are in PCI-X mode, enable register write workaround.
Linus Torvalds1da177e2005-04-16 15:20:36 -070014141 *
14142 * The workaround is to use indirect register accesses
14143 * for all chip writes not to mailbox registers.
14144 */
Joe Perches63c3a662011-04-26 08:12:10 +000014145 if (tg3_flag(tp, PCIX_MODE)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070014146 u32 pm_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014147
Joe Perches63c3a662011-04-26 08:12:10 +000014148 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014149
14150 /* The chip can have it's power management PCI config
14151 * space registers clobbered due to this bug.
14152 * So explicitly force the chip into D0 here.
14153 */
Matt Carlson9974a352007-10-07 23:27:28 -070014154 pci_read_config_dword(tp->pdev,
14155 tp->pm_cap + PCI_PM_CTRL,
Linus Torvalds1da177e2005-04-16 15:20:36 -070014156 &pm_reg);
14157 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
14158 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
Matt Carlson9974a352007-10-07 23:27:28 -070014159 pci_write_config_dword(tp->pdev,
14160 tp->pm_cap + PCI_PM_CTRL,
Linus Torvalds1da177e2005-04-16 15:20:36 -070014161 pm_reg);
14162
14163 /* Also, force SERR#/PERR# in PCI command. */
14164 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14165 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
14166 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14167 }
14168 }
14169
Linus Torvalds1da177e2005-04-16 15:20:36 -070014170 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
Joe Perches63c3a662011-04-26 08:12:10 +000014171 tg3_flag_set(tp, PCI_HIGH_SPEED);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014172 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
Joe Perches63c3a662011-04-26 08:12:10 +000014173 tg3_flag_set(tp, PCI_32BIT);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014174
14175 /* Chip-specific fixup from Broadcom driver */
14176 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
14177 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
14178 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
14179 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
14180 }
14181
Michael Chan1ee582d2005-08-09 20:16:46 -070014182 /* Default fast path register access methods */
Michael Chan20094932005-08-09 20:16:32 -070014183 tp->read32 = tg3_read32;
Michael Chan1ee582d2005-08-09 20:16:46 -070014184 tp->write32 = tg3_write32;
Michael Chan09ee9292005-08-09 20:17:00 -070014185 tp->read32_mbox = tg3_read32;
Michael Chan20094932005-08-09 20:16:32 -070014186 tp->write32_mbox = tg3_write32;
Michael Chan1ee582d2005-08-09 20:16:46 -070014187 tp->write32_tx_mbox = tg3_write32;
14188 tp->write32_rx_mbox = tg3_write32;
14189
14190 /* Various workaround register access methods */
Joe Perches63c3a662011-04-26 08:12:10 +000014191 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
Michael Chan1ee582d2005-08-09 20:16:46 -070014192 tp->write32 = tg3_write_indirect_reg32;
Matt Carlson98efd8a2007-05-05 12:47:25 -070014193 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
Joe Perches63c3a662011-04-26 08:12:10 +000014194 (tg3_flag(tp, PCI_EXPRESS) &&
Matt Carlson98efd8a2007-05-05 12:47:25 -070014195 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
14196 /*
14197 * Back to back register writes can cause problems on these
14198 * chips, the workaround is to read back all reg writes
14199 * except those to mailbox regs.
14200 *
14201 * See tg3_write_indirect_reg32().
14202 */
Michael Chan1ee582d2005-08-09 20:16:46 -070014203 tp->write32 = tg3_write_flush_reg32;
Matt Carlson98efd8a2007-05-05 12:47:25 -070014204 }
14205
Joe Perches63c3a662011-04-26 08:12:10 +000014206 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
Michael Chan1ee582d2005-08-09 20:16:46 -070014207 tp->write32_tx_mbox = tg3_write32_tx_mbox;
Joe Perches63c3a662011-04-26 08:12:10 +000014208 if (tg3_flag(tp, MBOX_WRITE_REORDER))
Michael Chan1ee582d2005-08-09 20:16:46 -070014209 tp->write32_rx_mbox = tg3_write_flush_reg32;
14210 }
Michael Chan20094932005-08-09 20:16:32 -070014211
Joe Perches63c3a662011-04-26 08:12:10 +000014212 if (tg3_flag(tp, ICH_WORKAROUND)) {
Michael Chan68929142005-08-09 20:17:14 -070014213 tp->read32 = tg3_read_indirect_reg32;
14214 tp->write32 = tg3_write_indirect_reg32;
14215 tp->read32_mbox = tg3_read_indirect_mbox;
14216 tp->write32_mbox = tg3_write_indirect_mbox;
14217 tp->write32_tx_mbox = tg3_write_indirect_mbox;
14218 tp->write32_rx_mbox = tg3_write_indirect_mbox;
14219
14220 iounmap(tp->regs);
Peter Hagervall22abe312005-09-16 17:01:03 -070014221 tp->regs = NULL;
Michael Chan68929142005-08-09 20:17:14 -070014222
14223 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
14224 pci_cmd &= ~PCI_COMMAND_MEMORY;
14225 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
14226 }
Michael Chanb5d37722006-09-27 16:06:21 -070014227 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14228 tp->read32_mbox = tg3_read32_mbox_5906;
14229 tp->write32_mbox = tg3_write32_mbox_5906;
14230 tp->write32_tx_mbox = tg3_write32_mbox_5906;
14231 tp->write32_rx_mbox = tg3_write32_mbox_5906;
14232 }
Michael Chan68929142005-08-09 20:17:14 -070014233
Michael Chanbbadf502006-04-06 21:46:34 -070014234 if (tp->write32 == tg3_write_indirect_reg32 ||
Joe Perches63c3a662011-04-26 08:12:10 +000014235 (tg3_flag(tp, PCIX_MODE) &&
Michael Chanbbadf502006-04-06 21:46:34 -070014236 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
David S. Millerf49639e2006-06-09 11:58:36 -070014237 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
Joe Perches63c3a662011-04-26 08:12:10 +000014238 tg3_flag_set(tp, SRAM_USE_CONFIG);
Michael Chanbbadf502006-04-06 21:46:34 -070014239
Matt Carlson16821282011-07-13 09:27:28 +000014240 /* The memory arbiter has to be enabled in order for SRAM accesses
14241 * to succeed. Normally on powerup the tg3 chip firmware will make
14242 * sure it is enabled, but other entities such as system netboot
14243 * code might disable it.
14244 */
14245 val = tr32(MEMARB_MODE);
14246 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
14247
Matt Carlson9dc5e342011-11-04 09:15:02 +000014248 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
14249 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
14250 tg3_flag(tp, 5780_CLASS)) {
14251 if (tg3_flag(tp, PCIX_MODE)) {
14252 pci_read_config_dword(tp->pdev,
14253 tp->pcix_cap + PCI_X_STATUS,
14254 &val);
14255 tp->pci_fn = val & 0x7;
14256 }
14257 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
14258 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14259 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14260 NIC_SRAM_CPMUSTAT_SIG) {
14261 tp->pci_fn = val & TG3_CPMU_STATUS_FMSK_5717;
14262 tp->pci_fn = tp->pci_fn ? 1 : 0;
14263 }
14264 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
14265 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720) {
14266 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
14267 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) ==
14268 NIC_SRAM_CPMUSTAT_SIG) {
14269 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
14270 TG3_CPMU_STATUS_FSHFT_5719;
14271 }
Matt Carlson69f11c92011-07-13 09:27:30 +000014272 }
14273
Michael Chan7d0c41e2005-04-21 17:06:20 -070014274 /* Get eeprom hw config before calling tg3_set_power_state().
Joe Perches63c3a662011-04-26 08:12:10 +000014275 * In particular, the TG3_FLAG_IS_NIC flag must be
Michael Chan7d0c41e2005-04-21 17:06:20 -070014276 * determined before calling tg3_set_power_state() so that
14277 * we know whether or not to switch out of Vaux power.
14278 * When the flag is set, it means that GPIO1 is used for eeprom
14279 * write protect and also implies that it is a LOM where GPIOs
14280 * are not used to switch power.
Jeff Garzik6aa20a22006-09-13 13:24:59 -040014281 */
Michael Chan7d0c41e2005-04-21 17:06:20 -070014282 tg3_get_eeprom_hw_cfg(tp);
14283
Joe Perches63c3a662011-04-26 08:12:10 +000014284 if (tg3_flag(tp, ENABLE_APE)) {
Matt Carlson0d3031d2007-10-10 18:02:43 -070014285 /* Allow reads and writes to the
14286 * APE register and memory space.
14287 */
14288 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
Matt Carlsonf92d9dc12010-06-05 17:24:30 +000014289 PCISTATE_ALLOW_APE_SHMEM_WR |
14290 PCISTATE_ALLOW_APE_PSPACE_WR;
Matt Carlson0d3031d2007-10-10 18:02:43 -070014291 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
14292 pci_state_reg);
Matt Carlsonc9cab242011-07-13 09:27:27 +000014293
14294 tg3_ape_lock_init(tp);
Matt Carlson0d3031d2007-10-10 18:02:43 -070014295 }
14296
Matt Carlson9936bcf2007-10-10 18:03:07 -070014297 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
Matt Carlson57e69832008-05-25 23:48:31 -070014298 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson321d32a2008-11-21 17:22:19 -080014299 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000014300 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
Joe Perches63c3a662011-04-26 08:12:10 +000014301 tg3_flag(tp, 57765_PLUS))
14302 tg3_flag_set(tp, CPMU_PRESENT);
Matt Carlsond30cdd22007-10-07 23:28:35 -070014303
Matt Carlson16821282011-07-13 09:27:28 +000014304 /* Set up tp->grc_local_ctrl before calling
14305 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
14306 * will bring 5700's external PHY out of reset.
Michael Chan314fba32005-04-21 17:07:04 -070014307 * It is also used as eeprom write protect on LOMs.
14308 */
14309 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
Matt Carlson6ff6f812011-05-19 12:12:54 +000014310 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
Joe Perches63c3a662011-04-26 08:12:10 +000014311 tg3_flag(tp, EEPROM_WRITE_PROT))
Michael Chan314fba32005-04-21 17:07:04 -070014312 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
14313 GRC_LCLCTRL_GPIO_OUTPUT1);
Michael Chan3e7d83b2005-04-21 17:10:36 -070014314 /* Unused GPIO3 must be driven as output on 5752 because there
14315 * are no pull-up resistors on unused GPIO pins.
14316 */
14317 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
14318 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
Michael Chan314fba32005-04-21 17:07:04 -070014319
Matt Carlson321d32a2008-11-21 17:22:19 -080014320 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
Matt Carlsoncb4ed1f2010-01-20 16:58:09 +000014321 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
14322 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
Michael Chanaf36e6b2006-03-23 01:28:06 -080014323 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
14324
Matt Carlson8d519ab2009-04-20 06:58:01 +000014325 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
14326 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
Matt Carlson5f0c4a32008-06-09 15:41:12 -070014327 /* Turn off the debug UART. */
14328 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
Joe Perches63c3a662011-04-26 08:12:10 +000014329 if (tg3_flag(tp, IS_NIC))
Matt Carlson5f0c4a32008-06-09 15:41:12 -070014330 /* Keep VMain power. */
14331 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
14332 GRC_LCLCTRL_GPIO_OUTPUT0;
14333 }
14334
Matt Carlson16821282011-07-13 09:27:28 +000014335 /* Switch out of Vaux if it is a NIC */
14336 tg3_pwrsrc_switch_to_vmain(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014337
Linus Torvalds1da177e2005-04-16 15:20:36 -070014338 /* Derive initial jumbo mode from MTU assigned in
14339 * ether_setup() via the alloc_etherdev() call
14340 */
Joe Perches63c3a662011-04-26 08:12:10 +000014341 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
14342 tg3_flag_set(tp, JUMBO_RING_ENABLE);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014343
14344 /* Determine WakeOnLan speed to use. */
14345 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14346 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
14347 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
14348 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
Joe Perches63c3a662011-04-26 08:12:10 +000014349 tg3_flag_clear(tp, WOL_SPEED_100MB);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014350 } else {
Joe Perches63c3a662011-04-26 08:12:10 +000014351 tg3_flag_set(tp, WOL_SPEED_100MB);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014352 }
14353
Matt Carlson7f97a4b2009-08-25 10:10:03 +000014354 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014355 tp->phy_flags |= TG3_PHYFLG_IS_FET;
Matt Carlson7f97a4b2009-08-25 10:10:03 +000014356
Linus Torvalds1da177e2005-04-16 15:20:36 -070014357 /* A few boards don't want Ethernet@WireSpeed phy feature */
Matt Carlson6ff6f812011-05-19 12:12:54 +000014358 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14359 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
Linus Torvalds1da177e2005-04-16 15:20:36 -070014360 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
Michael Chan747e8f82005-07-25 12:33:22 -070014361 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014362 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
14363 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
14364 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014365
14366 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
14367 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014368 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014369 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014370 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014371
Joe Perches63c3a662011-04-26 08:12:10 +000014372 if (tg3_flag(tp, 5705_PLUS) &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014373 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
Matt Carlson321d32a2008-11-21 17:22:19 -080014374 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
Matt Carlsonf6eb9b12009-09-01 13:19:53 +000014375 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
Joe Perches63c3a662011-04-26 08:12:10 +000014376 !tg3_flag(tp, 57765_PLUS)) {
Michael Chanc424cb22006-04-29 18:56:34 -070014377 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
Matt Carlsond30cdd22007-10-07 23:28:35 -070014378 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
Matt Carlson9936bcf2007-10-10 18:03:07 -070014379 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
14380 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
Michael Chand4011ad2007-02-13 12:17:25 -080014381 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
14382 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014383 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
Michael Chanc1d2a192007-01-08 19:57:20 -080014384 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014385 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
Matt Carlson321d32a2008-11-21 17:22:19 -080014386 } else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014387 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
Michael Chanc424cb22006-04-29 18:56:34 -070014388 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014389
Matt Carlsonb2a5c192008-04-03 21:44:44 -070014390 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14391 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
14392 tp->phy_otp = tg3_read_otp_phycfg(tp);
14393 if (tp->phy_otp == 0)
14394 tp->phy_otp = TG3_OTP_DEFAULT;
14395 }
14396
Joe Perches63c3a662011-04-26 08:12:10 +000014397 if (tg3_flag(tp, CPMU_PRESENT))
Matt Carlson8ef21422008-05-02 16:47:53 -070014398 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
14399 else
14400 tp->mi_mode = MAC_MI_MODE_BASE;
14401
Linus Torvalds1da177e2005-04-16 15:20:36 -070014402 tp->coalesce_mode = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014403 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
14404 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
14405 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
14406
Matt Carlson4d958472011-04-20 07:57:35 +000014407 /* Set these bits to enable statistics workaround. */
14408 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14409 tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 ||
14410 tp->pci_chip_rev_id == CHIPREV_ID_5720_A0) {
14411 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
14412 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
14413 }
14414
Matt Carlson321d32a2008-11-21 17:22:19 -080014415 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14416 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
Joe Perches63c3a662011-04-26 08:12:10 +000014417 tg3_flag_set(tp, USE_PHYLIB);
Matt Carlson57e69832008-05-25 23:48:31 -070014418
Matt Carlson158d7ab2008-05-29 01:37:54 -070014419 err = tg3_mdio_init(tp);
14420 if (err)
14421 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014422
14423 /* Initialize data/descriptor byte/word swapping. */
14424 val = tr32(GRC_MODE);
Matt Carlsonf2096f92011-04-05 14:22:48 +000014425 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
14426 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
14427 GRC_MODE_WORD_SWAP_B2HRX_DATA |
14428 GRC_MODE_B2HRX_ENABLE |
14429 GRC_MODE_HTX2B_ENABLE |
14430 GRC_MODE_HOST_STACKUP);
14431 else
14432 val &= GRC_MODE_HOST_STACKUP;
14433
Linus Torvalds1da177e2005-04-16 15:20:36 -070014434 tw32(GRC_MODE, val | tp->grc_mode);
14435
14436 tg3_switch_clocks(tp);
14437
14438 /* Clear this out for sanity. */
14439 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
14440
14441 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
14442 &pci_state_reg);
14443 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
Joe Perches63c3a662011-04-26 08:12:10 +000014444 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070014445 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
14446
14447 if (chiprevid == CHIPREV_ID_5701_A0 ||
14448 chiprevid == CHIPREV_ID_5701_B0 ||
14449 chiprevid == CHIPREV_ID_5701_B2 ||
14450 chiprevid == CHIPREV_ID_5701_B5) {
14451 void __iomem *sram_base;
14452
14453 /* Write some dummy words into the SRAM status block
14454 * area, see if it reads back correctly. If the return
14455 * value is bad, force enable the PCIX workaround.
14456 */
14457 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
14458
14459 writel(0x00000000, sram_base);
14460 writel(0x00000000, sram_base + 4);
14461 writel(0xffffffff, sram_base + 4);
14462 if (readl(sram_base) != 0x00000000)
Joe Perches63c3a662011-04-26 08:12:10 +000014463 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014464 }
14465 }
14466
14467 udelay(50);
14468 tg3_nvram_init(tp);
14469
14470 grc_misc_cfg = tr32(GRC_MISC_CFG);
14471 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
14472
Linus Torvalds1da177e2005-04-16 15:20:36 -070014473 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14474 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
14475 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
Joe Perches63c3a662011-04-26 08:12:10 +000014476 tg3_flag_set(tp, IS_5788);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014477
Joe Perches63c3a662011-04-26 08:12:10 +000014478 if (!tg3_flag(tp, IS_5788) &&
Matt Carlson6ff6f812011-05-19 12:12:54 +000014479 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
Joe Perches63c3a662011-04-26 08:12:10 +000014480 tg3_flag_set(tp, TAGGED_STATUS);
14481 if (tg3_flag(tp, TAGGED_STATUS)) {
David S. Millerfac9b832005-05-18 22:46:34 -070014482 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
14483 HOSTCC_MODE_CLRTICK_TXBD);
14484
14485 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
14486 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
14487 tp->misc_host_ctrl);
14488 }
14489
Matt Carlson3bda1252008-08-15 14:08:22 -070014490 /* Preserve the APE MAC_MODE bits */
Joe Perches63c3a662011-04-26 08:12:10 +000014491 if (tg3_flag(tp, ENABLE_APE))
Matt Carlsond2394e6b2010-11-24 08:31:47 +000014492 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
Matt Carlson3bda1252008-08-15 14:08:22 -070014493 else
Matt Carlson6e01b202011-08-19 13:58:20 +000014494 tp->mac_mode = 0;
Matt Carlson3bda1252008-08-15 14:08:22 -070014495
Linus Torvalds1da177e2005-04-16 15:20:36 -070014496 /* these are limited to 10/100 only */
14497 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
14498 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
14499 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
14500 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14501 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
14502 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
14503 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
14504 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
14505 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
Michael Chan676917d2006-12-07 00:20:22 -080014506 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
14507 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
Matt Carlson321d32a2008-11-21 17:22:19 -080014508 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
Matt Carlsond1101142010-02-17 15:16:55 +000014509 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
14510 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014511 (tp->phy_flags & TG3_PHYFLG_IS_FET))
14512 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014513
14514 err = tg3_phy_probe(tp);
14515 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000014516 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014517 /* ... but do not return immediately ... */
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070014518 tg3_mdio_fini(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014519 }
14520
Matt Carlson184b8902010-04-05 10:19:25 +000014521 tg3_read_vpd(tp);
Michael Chanc4e65752006-03-20 22:29:32 -080014522 tg3_read_fw_ver(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014523
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014524 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
14525 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014526 } else {
14527 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014528 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014529 else
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014530 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014531 }
14532
14533 /* 5700 {AX,BX} chips have a broken status block link
14534 * change bit implementation, so we must use the
14535 * status register in those cases.
14536 */
14537 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
Joe Perches63c3a662011-04-26 08:12:10 +000014538 tg3_flag_set(tp, USE_LINKCHG_REG);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014539 else
Joe Perches63c3a662011-04-26 08:12:10 +000014540 tg3_flag_clear(tp, USE_LINKCHG_REG);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014541
14542 /* The led_ctrl is set during tg3_phy_probe, here we might
14543 * have to force the link status polling mechanism based
14544 * upon subsystem IDs.
14545 */
14546 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
Michael Chan007a880d2007-05-31 14:49:51 -070014547 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014548 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
14549 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
Joe Perches63c3a662011-04-26 08:12:10 +000014550 tg3_flag_set(tp, USE_LINKCHG_REG);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014551 }
14552
14553 /* For all SERDES we poll the MAC status register. */
Matt Carlsonf07e9af2010-08-02 11:26:07 +000014554 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
Joe Perches63c3a662011-04-26 08:12:10 +000014555 tg3_flag_set(tp, POLL_SERDES);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014556 else
Joe Perches63c3a662011-04-26 08:12:10 +000014557 tg3_flag_clear(tp, POLL_SERDES);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014558
Matt Carlsonbf933c82011-01-25 15:58:49 +000014559 tp->rx_offset = NET_IP_ALIGN;
Matt Carlsond2757fc2010-04-12 06:58:27 +000014560 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014561 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
Joe Perches63c3a662011-04-26 08:12:10 +000014562 tg3_flag(tp, PCIX_MODE)) {
Matt Carlsonbf933c82011-01-25 15:58:49 +000014563 tp->rx_offset = 0;
Matt Carlsond2757fc2010-04-12 06:58:27 +000014564#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
Matt Carlson9dc7a112010-04-12 06:58:28 +000014565 tp->rx_copy_thresh = ~(u16)0;
Matt Carlsond2757fc2010-04-12 06:58:27 +000014566#endif
14567 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014568
Matt Carlson2c49a442010-09-30 10:34:35 +000014569 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
14570 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
Matt Carlson7cb32cf2010-09-30 10:34:36 +000014571 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
14572
Matt Carlson2c49a442010-09-30 10:34:35 +000014573 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
Michael Chanf92905d2006-06-29 20:14:29 -070014574
14575 /* Increment the rx prod index on the rx std ring by at most
14576 * 8 for these chips to workaround hw errata.
14577 */
14578 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
14579 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
14580 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
14581 tp->rx_std_max_post = 8;
14582
Joe Perches63c3a662011-04-26 08:12:10 +000014583 if (tg3_flag(tp, ASPM_WORKAROUND))
Matt Carlson8ed5d972007-05-07 00:25:49 -070014584 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
14585 PCIE_PWR_MGMT_L1_THRESH_MSK;
14586
Linus Torvalds1da177e2005-04-16 15:20:36 -070014587 return err;
14588}
14589
David S. Miller49b6e95f2007-03-29 01:38:42 -070014590#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070014591static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
14592{
14593 struct net_device *dev = tp->dev;
14594 struct pci_dev *pdev = tp->pdev;
David S. Miller49b6e95f2007-03-29 01:38:42 -070014595 struct device_node *dp = pci_device_to_OF_node(pdev);
David S. Miller374d4ca2007-03-29 01:57:57 -070014596 const unsigned char *addr;
David S. Miller49b6e95f2007-03-29 01:38:42 -070014597 int len;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014598
David S. Miller49b6e95f2007-03-29 01:38:42 -070014599 addr = of_get_property(dp, "local-mac-address", &len);
14600 if (addr && len == 6) {
14601 memcpy(dev->dev_addr, addr, 6);
14602 memcpy(dev->perm_addr, dev->dev_addr, 6);
14603 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014604 }
14605 return -ENODEV;
14606}
14607
14608static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
14609{
14610 struct net_device *dev = tp->dev;
14611
14612 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
John W. Linville2ff43692005-09-12 14:44:20 -070014613 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014614 return 0;
14615}
14616#endif
14617
14618static int __devinit tg3_get_device_address(struct tg3 *tp)
14619{
14620 struct net_device *dev = tp->dev;
14621 u32 hi, lo, mac_offset;
Michael Chan008652b2006-03-27 23:14:53 -080014622 int addr_ok = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014623
David S. Miller49b6e95f2007-03-29 01:38:42 -070014624#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070014625 if (!tg3_get_macaddr_sparc(tp))
14626 return 0;
14627#endif
14628
14629 mac_offset = 0x7c;
Matt Carlson6ff6f812011-05-19 12:12:54 +000014630 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
Joe Perches63c3a662011-04-26 08:12:10 +000014631 tg3_flag(tp, 5780_CLASS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070014632 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
14633 mac_offset = 0xcc;
14634 if (tg3_nvram_lock(tp))
14635 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
14636 else
14637 tg3_nvram_unlock(tp);
Joe Perches63c3a662011-04-26 08:12:10 +000014638 } else if (tg3_flag(tp, 5717_PLUS)) {
Matt Carlson69f11c92011-07-13 09:27:30 +000014639 if (tp->pci_fn & 1)
Matt Carlsona1b950d2009-09-01 13:20:17 +000014640 mac_offset = 0xcc;
Matt Carlson69f11c92011-07-13 09:27:30 +000014641 if (tp->pci_fn > 1)
Matt Carlsona50d0792010-06-05 17:24:37 +000014642 mac_offset += 0x18c;
Matt Carlsona1b950d2009-09-01 13:20:17 +000014643 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
Michael Chanb5d37722006-09-27 16:06:21 -070014644 mac_offset = 0x10;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014645
14646 /* First try to get it from MAC address mailbox. */
14647 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
14648 if ((hi >> 16) == 0x484b) {
14649 dev->dev_addr[0] = (hi >> 8) & 0xff;
14650 dev->dev_addr[1] = (hi >> 0) & 0xff;
14651
14652 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
14653 dev->dev_addr[2] = (lo >> 24) & 0xff;
14654 dev->dev_addr[3] = (lo >> 16) & 0xff;
14655 dev->dev_addr[4] = (lo >> 8) & 0xff;
14656 dev->dev_addr[5] = (lo >> 0) & 0xff;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014657
Michael Chan008652b2006-03-27 23:14:53 -080014658 /* Some old bootcode may report a 0 MAC address in SRAM */
14659 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
14660 }
14661 if (!addr_ok) {
14662 /* Next, try NVRAM. */
Joe Perches63c3a662011-04-26 08:12:10 +000014663 if (!tg3_flag(tp, NO_NVRAM) &&
Matt Carlsondf259d82009-04-20 06:57:14 +000014664 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
Matt Carlson6d348f22009-02-25 14:25:52 +000014665 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
Matt Carlson62cedd12009-04-20 14:52:29 -070014666 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
14667 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
Michael Chan008652b2006-03-27 23:14:53 -080014668 }
14669 /* Finally just fetch it out of the MAC control regs. */
14670 else {
14671 hi = tr32(MAC_ADDR_0_HIGH);
14672 lo = tr32(MAC_ADDR_0_LOW);
14673
14674 dev->dev_addr[5] = lo & 0xff;
14675 dev->dev_addr[4] = (lo >> 8) & 0xff;
14676 dev->dev_addr[3] = (lo >> 16) & 0xff;
14677 dev->dev_addr[2] = (lo >> 24) & 0xff;
14678 dev->dev_addr[1] = hi & 0xff;
14679 dev->dev_addr[0] = (hi >> 8) & 0xff;
14680 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070014681 }
14682
14683 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
David S. Miller7582a332008-03-20 15:53:15 -070014684#ifdef CONFIG_SPARC
Linus Torvalds1da177e2005-04-16 15:20:36 -070014685 if (!tg3_get_default_macaddr_sparc(tp))
14686 return 0;
14687#endif
14688 return -EINVAL;
14689 }
John W. Linville2ff43692005-09-12 14:44:20 -070014690 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014691 return 0;
14692}
14693
David S. Miller59e6b432005-05-18 22:50:10 -070014694#define BOUNDARY_SINGLE_CACHELINE 1
14695#define BOUNDARY_MULTI_CACHELINE 2
14696
14697static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
14698{
14699 int cacheline_size;
14700 u8 byte;
14701 int goal;
14702
14703 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
14704 if (byte == 0)
14705 cacheline_size = 1024;
14706 else
14707 cacheline_size = (int) byte * 4;
14708
14709 /* On 5703 and later chips, the boundary bits have no
14710 * effect.
14711 */
14712 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14713 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
Joe Perches63c3a662011-04-26 08:12:10 +000014714 !tg3_flag(tp, PCI_EXPRESS))
David S. Miller59e6b432005-05-18 22:50:10 -070014715 goto out;
14716
14717#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14718 goal = BOUNDARY_MULTI_CACHELINE;
14719#else
14720#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14721 goal = BOUNDARY_SINGLE_CACHELINE;
14722#else
14723 goal = 0;
14724#endif
14725#endif
14726
Joe Perches63c3a662011-04-26 08:12:10 +000014727 if (tg3_flag(tp, 57765_PLUS)) {
Matt Carlsoncbf9ca62009-11-13 13:03:40 +000014728 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14729 goto out;
14730 }
14731
David S. Miller59e6b432005-05-18 22:50:10 -070014732 if (!goal)
14733 goto out;
14734
14735 /* PCI controllers on most RISC systems tend to disconnect
14736 * when a device tries to burst across a cache-line boundary.
14737 * Therefore, letting tg3 do so just wastes PCI bandwidth.
14738 *
14739 * Unfortunately, for PCI-E there are only limited
14740 * write-side controls for this, and thus for reads
14741 * we will still get the disconnects. We'll also waste
14742 * these PCI cycles for both read and write for chips
14743 * other than 5700 and 5701 which do not implement the
14744 * boundary bits.
14745 */
Joe Perches63c3a662011-04-26 08:12:10 +000014746 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
David S. Miller59e6b432005-05-18 22:50:10 -070014747 switch (cacheline_size) {
14748 case 16:
14749 case 32:
14750 case 64:
14751 case 128:
14752 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14753 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14754 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14755 } else {
14756 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14757 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14758 }
14759 break;
14760
14761 case 256:
14762 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14763 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14764 break;
14765
14766 default:
14767 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14768 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14769 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -070014770 }
Joe Perches63c3a662011-04-26 08:12:10 +000014771 } else if (tg3_flag(tp, PCI_EXPRESS)) {
David S. Miller59e6b432005-05-18 22:50:10 -070014772 switch (cacheline_size) {
14773 case 16:
14774 case 32:
14775 case 64:
14776 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14777 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14778 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14779 break;
14780 }
14781 /* fallthrough */
14782 case 128:
14783 default:
14784 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14785 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14786 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -070014787 }
David S. Miller59e6b432005-05-18 22:50:10 -070014788 } else {
14789 switch (cacheline_size) {
14790 case 16:
14791 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14792 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14793 DMA_RWCTRL_WRITE_BNDRY_16);
14794 break;
14795 }
14796 /* fallthrough */
14797 case 32:
14798 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14799 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14800 DMA_RWCTRL_WRITE_BNDRY_32);
14801 break;
14802 }
14803 /* fallthrough */
14804 case 64:
14805 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14806 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14807 DMA_RWCTRL_WRITE_BNDRY_64);
14808 break;
14809 }
14810 /* fallthrough */
14811 case 128:
14812 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14813 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14814 DMA_RWCTRL_WRITE_BNDRY_128);
14815 break;
14816 }
14817 /* fallthrough */
14818 case 256:
14819 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14820 DMA_RWCTRL_WRITE_BNDRY_256);
14821 break;
14822 case 512:
14823 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14824 DMA_RWCTRL_WRITE_BNDRY_512);
14825 break;
14826 case 1024:
14827 default:
14828 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14829 DMA_RWCTRL_WRITE_BNDRY_1024);
14830 break;
Stephen Hemminger855e1112008-04-16 16:37:28 -070014831 }
David S. Miller59e6b432005-05-18 22:50:10 -070014832 }
14833
14834out:
14835 return val;
14836}
14837
Linus Torvalds1da177e2005-04-16 15:20:36 -070014838static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14839{
14840 struct tg3_internal_buffer_desc test_desc;
14841 u32 sram_dma_descs;
14842 int i, ret;
14843
14844 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14845
14846 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14847 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14848 tw32(RDMAC_STATUS, 0);
14849 tw32(WDMAC_STATUS, 0);
14850
14851 tw32(BUFMGR_MODE, 0);
14852 tw32(FTQ_RESET, 0);
14853
14854 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14855 test_desc.addr_lo = buf_dma & 0xffffffff;
14856 test_desc.nic_mbuf = 0x00002100;
14857 test_desc.len = size;
14858
14859 /*
14860 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14861 * the *second* time the tg3 driver was getting loaded after an
14862 * initial scan.
14863 *
14864 * Broadcom tells me:
14865 * ...the DMA engine is connected to the GRC block and a DMA
14866 * reset may affect the GRC block in some unpredictable way...
14867 * The behavior of resets to individual blocks has not been tested.
14868 *
14869 * Broadcom noted the GRC reset will also reset all sub-components.
14870 */
14871 if (to_device) {
14872 test_desc.cqid_sqid = (13 << 8) | 2;
14873
14874 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14875 udelay(40);
14876 } else {
14877 test_desc.cqid_sqid = (16 << 8) | 7;
14878
14879 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14880 udelay(40);
14881 }
14882 test_desc.flags = 0x00000005;
14883
14884 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14885 u32 val;
14886
14887 val = *(((u32 *)&test_desc) + i);
14888 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14889 sram_dma_descs + (i * sizeof(u32)));
14890 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14891 }
14892 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14893
Matt Carlson859a5882010-04-05 10:19:28 +000014894 if (to_device)
Linus Torvalds1da177e2005-04-16 15:20:36 -070014895 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
Matt Carlson859a5882010-04-05 10:19:28 +000014896 else
Linus Torvalds1da177e2005-04-16 15:20:36 -070014897 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014898
14899 ret = -ENODEV;
14900 for (i = 0; i < 40; i++) {
14901 u32 val;
14902
14903 if (to_device)
14904 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14905 else
14906 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14907 if ((val & 0xffff) == sram_dma_descs) {
14908 ret = 0;
14909 break;
14910 }
14911
14912 udelay(100);
14913 }
14914
14915 return ret;
14916}
14917
David S. Millerded73402005-05-23 13:59:47 -070014918#define TEST_BUFFER_SIZE 0x2000
Linus Torvalds1da177e2005-04-16 15:20:36 -070014919
Matt Carlson41434702011-03-09 16:58:22 +000014920static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
Joe Perches895950c2010-12-21 02:16:08 -080014921 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14922 { },
14923};
14924
Linus Torvalds1da177e2005-04-16 15:20:36 -070014925static int __devinit tg3_test_dma(struct tg3 *tp)
14926{
14927 dma_addr_t buf_dma;
David S. Miller59e6b432005-05-18 22:50:10 -070014928 u32 *buf, saved_dma_rwctrl;
Matt Carlsoncbf9ca62009-11-13 13:03:40 +000014929 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014930
Matt Carlson4bae65c2010-11-24 08:31:52 +000014931 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14932 &buf_dma, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014933 if (!buf) {
14934 ret = -ENOMEM;
14935 goto out_nofree;
14936 }
14937
14938 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14939 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14940
David S. Miller59e6b432005-05-18 22:50:10 -070014941 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -070014942
Joe Perches63c3a662011-04-26 08:12:10 +000014943 if (tg3_flag(tp, 57765_PLUS))
Matt Carlsoncbf9ca62009-11-13 13:03:40 +000014944 goto out;
14945
Joe Perches63c3a662011-04-26 08:12:10 +000014946 if (tg3_flag(tp, PCI_EXPRESS)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070014947 /* DMA read watermark not used on PCIE */
14948 tp->dma_rwctrl |= 0x00180000;
Joe Perches63c3a662011-04-26 08:12:10 +000014949 } else if (!tg3_flag(tp, PCIX_MODE)) {
Michael Chan85e94ce2005-04-21 17:05:28 -070014950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
Linus Torvalds1da177e2005-04-16 15:20:36 -070014952 tp->dma_rwctrl |= 0x003f0000;
14953 else
14954 tp->dma_rwctrl |= 0x003f000f;
14955 } else {
14956 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14957 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14958 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
Michael Chan49afdeb2007-02-13 12:17:03 -080014959 u32 read_water = 0x7;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014960
Michael Chan4a29cc22006-03-19 13:21:12 -080014961 /* If the 5704 is behind the EPB bridge, we can
14962 * do the less restrictive ONE_DMA workaround for
14963 * better performance.
14964 */
Joe Perches63c3a662011-04-26 08:12:10 +000014965 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
Michael Chan4a29cc22006-03-19 13:21:12 -080014966 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14967 tp->dma_rwctrl |= 0x8000;
14968 else if (ccval == 0x6 || ccval == 0x7)
Linus Torvalds1da177e2005-04-16 15:20:36 -070014969 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14970
Michael Chan49afdeb2007-02-13 12:17:03 -080014971 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14972 read_water = 4;
David S. Miller59e6b432005-05-18 22:50:10 -070014973 /* Set bit 23 to enable PCIX hw bug fix */
Michael Chan49afdeb2007-02-13 12:17:03 -080014974 tp->dma_rwctrl |=
14975 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14976 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14977 (1 << 23);
Michael Chan4cf78e42005-07-25 12:29:19 -070014978 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14979 /* 5780 always in PCIX mode */
14980 tp->dma_rwctrl |= 0x00144000;
Michael Chana4e2b342005-10-26 15:46:52 -070014981 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14982 /* 5714 always in PCIX mode */
14983 tp->dma_rwctrl |= 0x00148000;
Linus Torvalds1da177e2005-04-16 15:20:36 -070014984 } else {
14985 tp->dma_rwctrl |= 0x001b000f;
14986 }
14987 }
14988
14989 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14990 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14991 tp->dma_rwctrl &= 0xfffffff0;
14992
14993 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14994 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14995 /* Remove this if it causes problems for some boards. */
14996 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14997
14998 /* On 5700/5701 chips, we need to set this bit.
14999 * Otherwise the chip will issue cacheline transactions
15000 * to streamable DMA memory with not all the byte
15001 * enables turned on. This is an error on several
15002 * RISC PCI controllers, in particular sparc64.
15003 *
15004 * On 5703/5704 chips, this bit has been reassigned
15005 * a different meaning. In particular, it is used
15006 * on those chips to enable a PCI-X workaround.
15007 */
15008 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
15009 }
15010
15011 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15012
15013#if 0
15014 /* Unneeded, already done by tg3_get_invariants. */
15015 tg3_switch_clocks(tp);
15016#endif
15017
Linus Torvalds1da177e2005-04-16 15:20:36 -070015018 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
15019 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
15020 goto out;
15021
David S. Miller59e6b432005-05-18 22:50:10 -070015022 /* It is best to perform DMA test with maximum write burst size
15023 * to expose the 5700/5701 write DMA bug.
15024 */
15025 saved_dma_rwctrl = tp->dma_rwctrl;
15026 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15027 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15028
Linus Torvalds1da177e2005-04-16 15:20:36 -070015029 while (1) {
15030 u32 *p = buf, i;
15031
15032 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
15033 p[i] = i;
15034
15035 /* Send the buffer to the chip. */
15036 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
15037 if (ret) {
Matt Carlson2445e462010-04-05 10:19:21 +000015038 dev_err(&tp->pdev->dev,
15039 "%s: Buffer write failed. err = %d\n",
15040 __func__, ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015041 break;
15042 }
15043
15044#if 0
15045 /* validate data reached card RAM correctly. */
15046 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15047 u32 val;
15048 tg3_read_mem(tp, 0x2100 + (i*4), &val);
15049 if (le32_to_cpu(val) != p[i]) {
Matt Carlson2445e462010-04-05 10:19:21 +000015050 dev_err(&tp->pdev->dev,
15051 "%s: Buffer corrupted on device! "
15052 "(%d != %d)\n", __func__, val, i);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015053 /* ret = -ENODEV here? */
15054 }
15055 p[i] = 0;
15056 }
15057#endif
15058 /* Now read it back. */
15059 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
15060 if (ret) {
Matt Carlson5129c3a2010-04-05 10:19:23 +000015061 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
15062 "err = %d\n", __func__, ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015063 break;
15064 }
15065
15066 /* Verify it. */
15067 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
15068 if (p[i] == i)
15069 continue;
15070
David S. Miller59e6b432005-05-18 22:50:10 -070015071 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15072 DMA_RWCTRL_WRITE_BNDRY_16) {
15073 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015074 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
15075 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15076 break;
15077 } else {
Matt Carlson2445e462010-04-05 10:19:21 +000015078 dev_err(&tp->pdev->dev,
15079 "%s: Buffer corrupted on read back! "
15080 "(%d != %d)\n", __func__, p[i], i);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015081 ret = -ENODEV;
15082 goto out;
15083 }
15084 }
15085
15086 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
15087 /* Success. */
15088 ret = 0;
15089 break;
15090 }
15091 }
David S. Miller59e6b432005-05-18 22:50:10 -070015092 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
15093 DMA_RWCTRL_WRITE_BNDRY_16) {
15094 /* DMA test passed without adjusting DMA boundary,
Michael Chan6d1cfba2005-06-08 14:13:14 -070015095 * now look for chipsets that are known to expose the
15096 * DMA bug without failing the test.
David S. Miller59e6b432005-05-18 22:50:10 -070015097 */
Matt Carlson41434702011-03-09 16:58:22 +000015098 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
Michael Chan6d1cfba2005-06-08 14:13:14 -070015099 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
15100 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
Matt Carlson859a5882010-04-05 10:19:28 +000015101 } else {
Michael Chan6d1cfba2005-06-08 14:13:14 -070015102 /* Safe to use the calculated DMA boundary. */
15103 tp->dma_rwctrl = saved_dma_rwctrl;
Matt Carlson859a5882010-04-05 10:19:28 +000015104 }
Michael Chan6d1cfba2005-06-08 14:13:14 -070015105
David S. Miller59e6b432005-05-18 22:50:10 -070015106 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
15107 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015108
15109out:
Matt Carlson4bae65c2010-11-24 08:31:52 +000015110 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015111out_nofree:
15112 return ret;
15113}
15114
Linus Torvalds1da177e2005-04-16 15:20:36 -070015115static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
15116{
Joe Perches63c3a662011-04-26 08:12:10 +000015117 if (tg3_flag(tp, 57765_PLUS)) {
Matt Carlson666bc832010-01-20 16:58:03 +000015118 tp->bufmgr_config.mbuf_read_dma_low_water =
15119 DEFAULT_MB_RDMA_LOW_WATER_5705;
15120 tp->bufmgr_config.mbuf_mac_rx_low_water =
15121 DEFAULT_MB_MACRX_LOW_WATER_57765;
15122 tp->bufmgr_config.mbuf_high_water =
15123 DEFAULT_MB_HIGH_WATER_57765;
15124
15125 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15126 DEFAULT_MB_RDMA_LOW_WATER_5705;
15127 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15128 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
15129 tp->bufmgr_config.mbuf_high_water_jumbo =
15130 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
Joe Perches63c3a662011-04-26 08:12:10 +000015131 } else if (tg3_flag(tp, 5705_PLUS)) {
Michael Chanfdfec172005-07-25 12:31:48 -070015132 tp->bufmgr_config.mbuf_read_dma_low_water =
15133 DEFAULT_MB_RDMA_LOW_WATER_5705;
15134 tp->bufmgr_config.mbuf_mac_rx_low_water =
15135 DEFAULT_MB_MACRX_LOW_WATER_5705;
15136 tp->bufmgr_config.mbuf_high_water =
15137 DEFAULT_MB_HIGH_WATER_5705;
Michael Chanb5d37722006-09-27 16:06:21 -070015138 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
15139 tp->bufmgr_config.mbuf_mac_rx_low_water =
15140 DEFAULT_MB_MACRX_LOW_WATER_5906;
15141 tp->bufmgr_config.mbuf_high_water =
15142 DEFAULT_MB_HIGH_WATER_5906;
15143 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015144
Michael Chanfdfec172005-07-25 12:31:48 -070015145 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15146 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
15147 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15148 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
15149 tp->bufmgr_config.mbuf_high_water_jumbo =
15150 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
15151 } else {
15152 tp->bufmgr_config.mbuf_read_dma_low_water =
15153 DEFAULT_MB_RDMA_LOW_WATER;
15154 tp->bufmgr_config.mbuf_mac_rx_low_water =
15155 DEFAULT_MB_MACRX_LOW_WATER;
15156 tp->bufmgr_config.mbuf_high_water =
15157 DEFAULT_MB_HIGH_WATER;
15158
15159 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
15160 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
15161 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
15162 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
15163 tp->bufmgr_config.mbuf_high_water_jumbo =
15164 DEFAULT_MB_HIGH_WATER_JUMBO;
15165 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015166
15167 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
15168 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
15169}
15170
15171static char * __devinit tg3_phy_string(struct tg3 *tp)
15172{
Matt Carlson79eb6902010-02-17 15:17:03 +000015173 switch (tp->phy_id & TG3_PHY_ID_MASK) {
15174 case TG3_PHY_ID_BCM5400: return "5400";
15175 case TG3_PHY_ID_BCM5401: return "5401";
15176 case TG3_PHY_ID_BCM5411: return "5411";
15177 case TG3_PHY_ID_BCM5701: return "5701";
15178 case TG3_PHY_ID_BCM5703: return "5703";
15179 case TG3_PHY_ID_BCM5704: return "5704";
15180 case TG3_PHY_ID_BCM5705: return "5705";
15181 case TG3_PHY_ID_BCM5750: return "5750";
15182 case TG3_PHY_ID_BCM5752: return "5752";
15183 case TG3_PHY_ID_BCM5714: return "5714";
15184 case TG3_PHY_ID_BCM5780: return "5780";
15185 case TG3_PHY_ID_BCM5755: return "5755";
15186 case TG3_PHY_ID_BCM5787: return "5787";
15187 case TG3_PHY_ID_BCM5784: return "5784";
15188 case TG3_PHY_ID_BCM5756: return "5722/5756";
15189 case TG3_PHY_ID_BCM5906: return "5906";
15190 case TG3_PHY_ID_BCM5761: return "5761";
15191 case TG3_PHY_ID_BCM5718C: return "5718C";
15192 case TG3_PHY_ID_BCM5718S: return "5718S";
15193 case TG3_PHY_ID_BCM57765: return "57765";
Matt Carlson302b5002010-06-05 17:24:38 +000015194 case TG3_PHY_ID_BCM5719C: return "5719C";
Matt Carlson6418f2c2011-04-05 14:22:49 +000015195 case TG3_PHY_ID_BCM5720C: return "5720C";
Matt Carlson79eb6902010-02-17 15:17:03 +000015196 case TG3_PHY_ID_BCM8002: return "8002/serdes";
Linus Torvalds1da177e2005-04-16 15:20:36 -070015197 case 0: return "serdes";
15198 default: return "unknown";
Stephen Hemminger855e1112008-04-16 16:37:28 -070015199 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015200}
15201
Michael Chanf9804dd2005-09-27 12:13:10 -070015202static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
15203{
Joe Perches63c3a662011-04-26 08:12:10 +000015204 if (tg3_flag(tp, PCI_EXPRESS)) {
Michael Chanf9804dd2005-09-27 12:13:10 -070015205 strcpy(str, "PCI Express");
15206 return str;
Joe Perches63c3a662011-04-26 08:12:10 +000015207 } else if (tg3_flag(tp, PCIX_MODE)) {
Michael Chanf9804dd2005-09-27 12:13:10 -070015208 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
15209
15210 strcpy(str, "PCIX:");
15211
15212 if ((clock_ctrl == 7) ||
15213 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
15214 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
15215 strcat(str, "133MHz");
15216 else if (clock_ctrl == 0)
15217 strcat(str, "33MHz");
15218 else if (clock_ctrl == 2)
15219 strcat(str, "50MHz");
15220 else if (clock_ctrl == 4)
15221 strcat(str, "66MHz");
15222 else if (clock_ctrl == 6)
15223 strcat(str, "100MHz");
Michael Chanf9804dd2005-09-27 12:13:10 -070015224 } else {
15225 strcpy(str, "PCI:");
Joe Perches63c3a662011-04-26 08:12:10 +000015226 if (tg3_flag(tp, PCI_HIGH_SPEED))
Michael Chanf9804dd2005-09-27 12:13:10 -070015227 strcat(str, "66MHz");
15228 else
15229 strcat(str, "33MHz");
15230 }
Joe Perches63c3a662011-04-26 08:12:10 +000015231 if (tg3_flag(tp, PCI_32BIT))
Michael Chanf9804dd2005-09-27 12:13:10 -070015232 strcat(str, ":32-bit");
15233 else
15234 strcat(str, ":64-bit");
15235 return str;
15236}
15237
Michael Chan8c2dc7e2005-12-19 16:26:02 -080015238static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -070015239{
15240 struct pci_dev *peer;
15241 unsigned int func, devnr = tp->pdev->devfn & ~7;
15242
15243 for (func = 0; func < 8; func++) {
15244 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15245 if (peer && peer != tp->pdev)
15246 break;
15247 pci_dev_put(peer);
15248 }
Michael Chan16fe9d72005-12-13 21:09:54 -080015249 /* 5704 can be configured in single-port mode, set peer to
15250 * tp->pdev in that case.
15251 */
15252 if (!peer) {
15253 peer = tp->pdev;
15254 return peer;
15255 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015256
15257 /*
15258 * We don't need to keep the refcount elevated; there's no way
15259 * to remove one half of this device without removing the other
15260 */
15261 pci_dev_put(peer);
15262
15263 return peer;
15264}
15265
David S. Miller15f98502005-05-18 22:49:26 -070015266static void __devinit tg3_init_coal(struct tg3 *tp)
15267{
15268 struct ethtool_coalesce *ec = &tp->coal;
15269
15270 memset(ec, 0, sizeof(*ec));
15271 ec->cmd = ETHTOOL_GCOALESCE;
15272 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
15273 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
15274 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
15275 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
15276 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
15277 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
15278 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
15279 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
15280 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
15281
15282 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
15283 HOSTCC_MODE_CLRTICK_TXBD)) {
15284 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
15285 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
15286 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
15287 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
15288 }
Michael Chand244c892005-07-05 14:42:33 -070015289
Joe Perches63c3a662011-04-26 08:12:10 +000015290 if (tg3_flag(tp, 5705_PLUS)) {
Michael Chand244c892005-07-05 14:42:33 -070015291 ec->rx_coalesce_usecs_irq = 0;
15292 ec->tx_coalesce_usecs_irq = 0;
15293 ec->stats_block_coalesce_usecs = 0;
15294 }
David S. Miller15f98502005-05-18 22:49:26 -070015295}
15296
Stephen Hemminger7c7d64b2008-11-19 22:25:36 -080015297static const struct net_device_ops tg3_netdev_ops = {
15298 .ndo_open = tg3_open,
15299 .ndo_stop = tg3_close,
Stephen Hemminger00829822008-11-20 20:14:53 -080015300 .ndo_start_xmit = tg3_start_xmit,
Eric Dumazet511d2222010-07-07 20:44:24 +000015301 .ndo_get_stats64 = tg3_get_stats64,
Stephen Hemminger00829822008-11-20 20:14:53 -080015302 .ndo_validate_addr = eth_validate_addr,
Jiri Pirkoafc4b132011-08-16 06:29:01 +000015303 .ndo_set_rx_mode = tg3_set_rx_mode,
Stephen Hemminger00829822008-11-20 20:14:53 -080015304 .ndo_set_mac_address = tg3_set_mac_addr,
15305 .ndo_do_ioctl = tg3_ioctl,
15306 .ndo_tx_timeout = tg3_tx_timeout,
15307 .ndo_change_mtu = tg3_change_mtu,
Michał Mirosławdc668912011-04-07 03:35:07 +000015308 .ndo_fix_features = tg3_fix_features,
Mahesh Bandewar06c03c02011-05-08 06:51:48 +000015309 .ndo_set_features = tg3_set_features,
Stephen Hemminger00829822008-11-20 20:14:53 -080015310#ifdef CONFIG_NET_POLL_CONTROLLER
15311 .ndo_poll_controller = tg3_poll_controller,
15312#endif
15313};
15314
Linus Torvalds1da177e2005-04-16 15:20:36 -070015315static int __devinit tg3_init_one(struct pci_dev *pdev,
15316 const struct pci_device_id *ent)
15317{
Linus Torvalds1da177e2005-04-16 15:20:36 -070015318 struct net_device *dev;
15319 struct tg3 *tp;
Matt Carlson646c9ed2009-09-01 12:58:41 +000015320 int i, err, pm_cap;
15321 u32 sndmbx, rcvmbx, intmbx;
Michael Chanf9804dd2005-09-27 12:13:10 -070015322 char str[40];
Michael Chan72f2afb2006-03-06 19:28:35 -080015323 u64 dma_mask, persist_dma_mask;
Matt Carlson0da06062011-05-19 12:12:53 +000015324 u32 features = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015325
Joe Perches05dbe002010-02-17 19:44:19 +000015326 printk_once(KERN_INFO "%s\n", version);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015327
15328 err = pci_enable_device(pdev);
15329 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000015330 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015331 return err;
15332 }
15333
Linus Torvalds1da177e2005-04-16 15:20:36 -070015334 err = pci_request_regions(pdev, DRV_MODULE_NAME);
15335 if (err) {
Matt Carlson2445e462010-04-05 10:19:21 +000015336 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015337 goto err_out_disable_pdev;
15338 }
15339
15340 pci_set_master(pdev);
15341
15342 /* Find power-management capability. */
15343 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
15344 if (pm_cap == 0) {
Matt Carlson2445e462010-04-05 10:19:21 +000015345 dev_err(&pdev->dev,
15346 "Cannot find Power Management capability, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015347 err = -EIO;
15348 goto err_out_free_res;
15349 }
15350
Matt Carlson16821282011-07-13 09:27:28 +000015351 err = pci_set_power_state(pdev, PCI_D0);
15352 if (err) {
15353 dev_err(&pdev->dev, "Transition to D0 failed, aborting\n");
15354 goto err_out_free_res;
15355 }
15356
Matt Carlsonfe5f5782009-09-01 13:09:39 +000015357 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015358 if (!dev) {
Matt Carlson2445e462010-04-05 10:19:21 +000015359 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015360 err = -ENOMEM;
Matt Carlson16821282011-07-13 09:27:28 +000015361 goto err_out_power_down;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015362 }
15363
Linus Torvalds1da177e2005-04-16 15:20:36 -070015364 SET_NETDEV_DEV(dev, &pdev->dev);
15365
Linus Torvalds1da177e2005-04-16 15:20:36 -070015366 tp = netdev_priv(dev);
15367 tp->pdev = pdev;
15368 tp->dev = dev;
15369 tp->pm_cap = pm_cap;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015370 tp->rx_mode = TG3_DEF_RX_MODE;
15371 tp->tx_mode = TG3_DEF_TX_MODE;
Matt Carlson8ef21422008-05-02 16:47:53 -070015372
Linus Torvalds1da177e2005-04-16 15:20:36 -070015373 if (tg3_debug > 0)
15374 tp->msg_enable = tg3_debug;
15375 else
15376 tp->msg_enable = TG3_DEF_MSG_ENABLE;
15377
15378 /* The word/byte swap controls here control register access byte
15379 * swapping. DMA data byte swapping is controlled in the GRC_MODE
15380 * setting below.
15381 */
15382 tp->misc_host_ctrl =
15383 MISC_HOST_CTRL_MASK_PCI_INT |
15384 MISC_HOST_CTRL_WORD_SWAP |
15385 MISC_HOST_CTRL_INDIR_ACCESS |
15386 MISC_HOST_CTRL_PCISTATE_RW;
15387
15388 /* The NONFRM (non-frame) byte/word swap controls take effect
15389 * on descriptor entries, anything which isn't packet data.
15390 *
15391 * The StrongARM chips on the board (one for tx, one for rx)
15392 * are running in big-endian mode.
15393 */
15394 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
15395 GRC_MODE_WSWAP_NONFRM_DATA);
15396#ifdef __BIG_ENDIAN
15397 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
15398#endif
15399 spin_lock_init(&tp->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015400 spin_lock_init(&tp->indirect_lock);
David Howellsc4028952006-11-22 14:57:56 +000015401 INIT_WORK(&tp->reset_task, tg3_reset_task);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015402
Matt Carlsond5fe4882008-11-21 17:20:32 -080015403 tp->regs = pci_ioremap_bar(pdev, BAR_0);
Andy Gospodarekab0049b2007-09-06 20:42:14 +010015404 if (!tp->regs) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015405 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070015406 err = -ENOMEM;
15407 goto err_out_free_dev;
15408 }
15409
Matt Carlsonc9cab242011-07-13 09:27:27 +000015410 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
15411 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
15412 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
15413 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
15414 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15415 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15416 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15417 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720) {
15418 tg3_flag_set(tp, ENABLE_APE);
15419 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
15420 if (!tp->aperegs) {
15421 dev_err(&pdev->dev,
15422 "Cannot map APE registers, aborting\n");
15423 err = -ENOMEM;
15424 goto err_out_iounmap;
15425 }
15426 }
15427
Linus Torvalds1da177e2005-04-16 15:20:36 -070015428 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
15429 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015430
Linus Torvalds1da177e2005-04-16 15:20:36 -070015431 dev->ethtool_ops = &tg3_ethtool_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015432 dev->watchdog_timeo = TG3_TX_TIMEOUT;
Matt Carlson2ffcc982011-05-19 12:12:44 +000015433 dev->netdev_ops = &tg3_netdev_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015434 dev->irq = pdev->irq;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015435
15436 err = tg3_get_invariants(tp);
15437 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015438 dev_err(&pdev->dev,
15439 "Problem fetching invariants of chip, aborting\n");
Matt Carlsonc9cab242011-07-13 09:27:27 +000015440 goto err_out_apeunmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015441 }
15442
Michael Chan4a29cc22006-03-19 13:21:12 -080015443 /* The EPB bridge inside 5714, 5715, and 5780 and any
15444 * device behind the EPB cannot support DMA addresses > 40-bit.
Michael Chan72f2afb2006-03-06 19:28:35 -080015445 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
15446 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
15447 * do DMA address check in tg3_start_xmit().
15448 */
Joe Perches63c3a662011-04-26 08:12:10 +000015449 if (tg3_flag(tp, IS_5788))
Yang Hongyang284901a2009-04-06 19:01:15 -070015450 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
Joe Perches63c3a662011-04-26 08:12:10 +000015451 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
Yang Hongyang50cf1562009-04-06 19:01:14 -070015452 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
Michael Chan72f2afb2006-03-06 19:28:35 -080015453#ifdef CONFIG_HIGHMEM
Yang Hongyang6a355282009-04-06 19:01:13 -070015454 dma_mask = DMA_BIT_MASK(64);
Michael Chan72f2afb2006-03-06 19:28:35 -080015455#endif
Michael Chan4a29cc22006-03-19 13:21:12 -080015456 } else
Yang Hongyang6a355282009-04-06 19:01:13 -070015457 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
Michael Chan72f2afb2006-03-06 19:28:35 -080015458
15459 /* Configure DMA attributes. */
Yang Hongyang284901a2009-04-06 19:01:15 -070015460 if (dma_mask > DMA_BIT_MASK(32)) {
Michael Chan72f2afb2006-03-06 19:28:35 -080015461 err = pci_set_dma_mask(pdev, dma_mask);
15462 if (!err) {
Matt Carlson0da06062011-05-19 12:12:53 +000015463 features |= NETIF_F_HIGHDMA;
Michael Chan72f2afb2006-03-06 19:28:35 -080015464 err = pci_set_consistent_dma_mask(pdev,
15465 persist_dma_mask);
15466 if (err < 0) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015467 dev_err(&pdev->dev, "Unable to obtain 64 bit "
15468 "DMA for consistent allocations\n");
Matt Carlsonc9cab242011-07-13 09:27:27 +000015469 goto err_out_apeunmap;
Michael Chan72f2afb2006-03-06 19:28:35 -080015470 }
15471 }
15472 }
Yang Hongyang284901a2009-04-06 19:01:15 -070015473 if (err || dma_mask == DMA_BIT_MASK(32)) {
15474 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Michael Chan72f2afb2006-03-06 19:28:35 -080015475 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015476 dev_err(&pdev->dev,
15477 "No usable DMA configuration, aborting\n");
Matt Carlsonc9cab242011-07-13 09:27:27 +000015478 goto err_out_apeunmap;
Michael Chan72f2afb2006-03-06 19:28:35 -080015479 }
15480 }
15481
Michael Chanfdfec172005-07-25 12:31:48 -070015482 tg3_init_bufmgr_config(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015483
Matt Carlson0da06062011-05-19 12:12:53 +000015484 features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
15485
15486 /* 5700 B0 chips do not support checksumming correctly due
15487 * to hardware bugs.
15488 */
15489 if (tp->pci_chip_rev_id != CHIPREV_ID_5700_B0) {
15490 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
15491
15492 if (tg3_flag(tp, 5755_PLUS))
15493 features |= NETIF_F_IPV6_CSUM;
15494 }
15495
Michael Chan4e3a7aa2006-03-20 17:47:44 -080015496 /* TSO is on by default on chips that support hardware TSO.
15497 * Firmware TSO on older chips gives lower performance, so it
15498 * is off by default, but can be enabled using ethtool.
15499 */
Joe Perches63c3a662011-04-26 08:12:10 +000015500 if ((tg3_flag(tp, HW_TSO_1) ||
15501 tg3_flag(tp, HW_TSO_2) ||
15502 tg3_flag(tp, HW_TSO_3)) &&
Matt Carlson0da06062011-05-19 12:12:53 +000015503 (features & NETIF_F_IP_CSUM))
15504 features |= NETIF_F_TSO;
Joe Perches63c3a662011-04-26 08:12:10 +000015505 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
Matt Carlson0da06062011-05-19 12:12:53 +000015506 if (features & NETIF_F_IPV6_CSUM)
15507 features |= NETIF_F_TSO6;
Joe Perches63c3a662011-04-26 08:12:10 +000015508 if (tg3_flag(tp, HW_TSO_3) ||
Matt Carlsone849cdc2009-11-13 13:03:38 +000015509 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
Matt Carlson57e69832008-05-25 23:48:31 -070015510 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
15511 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
Joe Perches63c3a662011-04-26 08:12:10 +000015512 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
Michał Mirosławdc668912011-04-07 03:35:07 +000015513 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
Matt Carlson0da06062011-05-19 12:12:53 +000015514 features |= NETIF_F_TSO_ECN;
Michael Chanb0026622006-07-03 19:42:14 -070015515 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015516
Matt Carlsond542fe22011-05-19 16:02:43 +000015517 dev->features |= features;
15518 dev->vlan_features |= features;
15519
Mahesh Bandewar06c03c02011-05-08 06:51:48 +000015520 /*
15521 * Add loopback capability only for a subset of devices that support
15522 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
15523 * loopback for the remaining devices.
15524 */
15525 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780 &&
15526 !tg3_flag(tp, CPMU_PRESENT))
15527 /* Add the loopback capability */
Matt Carlson0da06062011-05-19 12:12:53 +000015528 features |= NETIF_F_LOOPBACK;
15529
Matt Carlson0da06062011-05-19 12:12:53 +000015530 dev->hw_features |= features;
Mahesh Bandewar06c03c02011-05-08 06:51:48 +000015531
Linus Torvalds1da177e2005-04-16 15:20:36 -070015532 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
Joe Perches63c3a662011-04-26 08:12:10 +000015533 !tg3_flag(tp, TSO_CAPABLE) &&
Linus Torvalds1da177e2005-04-16 15:20:36 -070015534 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
Joe Perches63c3a662011-04-26 08:12:10 +000015535 tg3_flag_set(tp, MAX_RXPEND_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015536 tp->rx_pending = 63;
15537 }
15538
Linus Torvalds1da177e2005-04-16 15:20:36 -070015539 err = tg3_get_device_address(tp);
15540 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015541 dev_err(&pdev->dev,
15542 "Could not obtain valid ethernet address, aborting\n");
Matt Carlsonc9cab242011-07-13 09:27:27 +000015543 goto err_out_apeunmap;
Matt Carlson0d3031d2007-10-10 18:02:43 -070015544 }
15545
Matt Carlsonc88864d2007-11-12 21:07:01 -080015546 /*
15547 * Reset chip in case UNDI or EFI driver did not shutdown
15548 * DMA self test will enable WDMAC and we'll see (spurious)
15549 * pending DMA on the PCI bus at that point.
15550 */
15551 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
15552 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
15553 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
15554 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15555 }
15556
15557 err = tg3_test_dma(tp);
15558 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015559 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
Matt Carlsonc88864d2007-11-12 21:07:01 -080015560 goto err_out_apeunmap;
15561 }
15562
Matt Carlson78f90dc2009-11-13 13:03:42 +000015563 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
15564 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
15565 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
Matt Carlson6fd45cb2010-09-15 08:59:57 +000015566 for (i = 0; i < tp->irq_max; i++) {
Matt Carlson78f90dc2009-11-13 13:03:42 +000015567 struct tg3_napi *tnapi = &tp->napi[i];
15568
15569 tnapi->tp = tp;
15570 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
15571
15572 tnapi->int_mbox = intmbx;
Matt Carlson93a700a2011-08-31 11:44:54 +000015573 if (i <= 4)
Matt Carlson78f90dc2009-11-13 13:03:42 +000015574 intmbx += 0x8;
15575 else
15576 intmbx += 0x4;
15577
15578 tnapi->consmbox = rcvmbx;
15579 tnapi->prodmbox = sndmbx;
15580
Matt Carlson66cfd1b2010-09-30 10:34:30 +000015581 if (i)
Matt Carlson78f90dc2009-11-13 13:03:42 +000015582 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
Matt Carlson66cfd1b2010-09-30 10:34:30 +000015583 else
Matt Carlson78f90dc2009-11-13 13:03:42 +000015584 tnapi->coal_now = HOSTCC_MODE_NOW;
Matt Carlson78f90dc2009-11-13 13:03:42 +000015585
Joe Perches63c3a662011-04-26 08:12:10 +000015586 if (!tg3_flag(tp, SUPPORT_MSIX))
Matt Carlson78f90dc2009-11-13 13:03:42 +000015587 break;
15588
15589 /*
15590 * If we support MSIX, we'll be using RSS. If we're using
15591 * RSS, the first vector only handles link interrupts and the
15592 * remaining vectors handle rx and tx interrupts. Reuse the
15593 * mailbox values for the next iteration. The values we setup
15594 * above are still useful for the single vectored mode.
15595 */
15596 if (!i)
15597 continue;
15598
15599 rcvmbx += 0x8;
15600
15601 if (sndmbx & 0x4)
15602 sndmbx -= 0x4;
15603 else
15604 sndmbx += 0xc;
15605 }
15606
Matt Carlsonc88864d2007-11-12 21:07:01 -080015607 tg3_init_coal(tp);
15608
Michael Chanc49a1562006-12-17 17:07:29 -080015609 pci_set_drvdata(pdev, dev);
15610
Matt Carlsoncd0d7222011-07-13 09:27:33 +000015611 if (tg3_flag(tp, 5717_PLUS)) {
15612 /* Resume a low-power mode */
15613 tg3_frob_aux_power(tp, false);
15614 }
15615
Linus Torvalds1da177e2005-04-16 15:20:36 -070015616 err = register_netdev(dev);
15617 if (err) {
Matt Carlsonab96b242010-04-05 10:19:22 +000015618 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
Matt Carlson0d3031d2007-10-10 18:02:43 -070015619 goto err_out_apeunmap;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015620 }
15621
Joe Perches05dbe002010-02-17 19:44:19 +000015622 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
15623 tp->board_part_number,
15624 tp->pci_chip_rev_id,
15625 tg3_bus_string(tp, str),
15626 dev->dev_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015627
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015628 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
Matt Carlson3f0e3ad2009-11-02 14:24:36 +000015629 struct phy_device *phydev;
15630 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
Matt Carlson5129c3a2010-04-05 10:19:23 +000015631 netdev_info(dev,
15632 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
Joe Perches05dbe002010-02-17 19:44:19 +000015633 phydev->drv->name, dev_name(&phydev->dev));
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015634 } else {
15635 char *ethtype;
15636
15637 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
15638 ethtype = "10/100Base-TX";
15639 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
15640 ethtype = "1000Base-SX";
15641 else
15642 ethtype = "10/100/1000Base-T";
15643
Matt Carlson5129c3a2010-04-05 10:19:23 +000015644 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
Matt Carlson47007832011-04-20 07:57:43 +000015645 "(WireSpeed[%d], EEE[%d])\n",
15646 tg3_phy_string(tp), ethtype,
15647 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
15648 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015649 }
Matt Carlsondf59c942008-11-03 16:52:56 -080015650
Joe Perches05dbe002010-02-17 19:44:19 +000015651 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
Michał Mirosławdc668912011-04-07 03:35:07 +000015652 (dev->features & NETIF_F_RXCSUM) != 0,
Joe Perches63c3a662011-04-26 08:12:10 +000015653 tg3_flag(tp, USE_LINKCHG_REG) != 0,
Matt Carlsonf07e9af2010-08-02 11:26:07 +000015654 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
Joe Perches63c3a662011-04-26 08:12:10 +000015655 tg3_flag(tp, ENABLE_ASF) != 0,
15656 tg3_flag(tp, TSO_CAPABLE) != 0);
Joe Perches05dbe002010-02-17 19:44:19 +000015657 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
15658 tp->dma_rwctrl,
15659 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
15660 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015661
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000015662 pci_save_state(pdev);
15663
Linus Torvalds1da177e2005-04-16 15:20:36 -070015664 return 0;
15665
Matt Carlson0d3031d2007-10-10 18:02:43 -070015666err_out_apeunmap:
15667 if (tp->aperegs) {
15668 iounmap(tp->aperegs);
15669 tp->aperegs = NULL;
15670 }
15671
Linus Torvalds1da177e2005-04-16 15:20:36 -070015672err_out_iounmap:
Michael Chan68929142005-08-09 20:17:14 -070015673 if (tp->regs) {
15674 iounmap(tp->regs);
Peter Hagervall22abe312005-09-16 17:01:03 -070015675 tp->regs = NULL;
Michael Chan68929142005-08-09 20:17:14 -070015676 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015677
15678err_out_free_dev:
15679 free_netdev(dev);
15680
Matt Carlson16821282011-07-13 09:27:28 +000015681err_out_power_down:
15682 pci_set_power_state(pdev, PCI_D3hot);
15683
Linus Torvalds1da177e2005-04-16 15:20:36 -070015684err_out_free_res:
15685 pci_release_regions(pdev);
15686
15687err_out_disable_pdev:
15688 pci_disable_device(pdev);
15689 pci_set_drvdata(pdev, NULL);
15690 return err;
15691}
15692
15693static void __devexit tg3_remove_one(struct pci_dev *pdev)
15694{
15695 struct net_device *dev = pci_get_drvdata(pdev);
15696
15697 if (dev) {
15698 struct tg3 *tp = netdev_priv(dev);
15699
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -080015700 if (tp->fw)
15701 release_firmware(tp->fw);
15702
Matt Carlsondb219972011-11-04 09:15:03 +000015703 tg3_reset_task_cancel(tp);
Matt Carlson158d7ab2008-05-29 01:37:54 -070015704
David S. Miller1805b2f2011-10-24 18:18:09 -040015705 if (tg3_flag(tp, USE_PHYLIB)) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015706 tg3_phy_fini(tp);
Matt Carlson158d7ab2008-05-29 01:37:54 -070015707 tg3_mdio_fini(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015708 }
Matt Carlson158d7ab2008-05-29 01:37:54 -070015709
Linus Torvalds1da177e2005-04-16 15:20:36 -070015710 unregister_netdev(dev);
Matt Carlson0d3031d2007-10-10 18:02:43 -070015711 if (tp->aperegs) {
15712 iounmap(tp->aperegs);
15713 tp->aperegs = NULL;
15714 }
Michael Chan68929142005-08-09 20:17:14 -070015715 if (tp->regs) {
15716 iounmap(tp->regs);
Peter Hagervall22abe312005-09-16 17:01:03 -070015717 tp->regs = NULL;
Michael Chan68929142005-08-09 20:17:14 -070015718 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070015719 free_netdev(dev);
15720 pci_release_regions(pdev);
15721 pci_disable_device(pdev);
15722 pci_set_drvdata(pdev, NULL);
15723 }
15724}
15725
Eric Dumazetaa6027c2011-01-01 05:22:46 +000015726#ifdef CONFIG_PM_SLEEP
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015727static int tg3_suspend(struct device *device)
Linus Torvalds1da177e2005-04-16 15:20:36 -070015728{
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015729 struct pci_dev *pdev = to_pci_dev(device);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015730 struct net_device *dev = pci_get_drvdata(pdev);
15731 struct tg3 *tp = netdev_priv(dev);
15732 int err;
15733
15734 if (!netif_running(dev))
15735 return 0;
15736
Matt Carlsondb219972011-11-04 09:15:03 +000015737 tg3_reset_task_cancel(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015738 tg3_phy_stop(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015739 tg3_netif_stop(tp);
15740
15741 del_timer_sync(&tp->timer);
15742
David S. Millerf47c11e2005-06-24 20:18:35 -070015743 tg3_full_lock(tp, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015744 tg3_disable_ints(tp);
David S. Millerf47c11e2005-06-24 20:18:35 -070015745 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015746
15747 netif_device_detach(dev);
15748
David S. Millerf47c11e2005-06-24 20:18:35 -070015749 tg3_full_lock(tp, 0);
Michael Chan944d9802005-05-29 14:57:48 -070015750 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
Joe Perches63c3a662011-04-26 08:12:10 +000015751 tg3_flag_clear(tp, INIT_COMPLETE);
David S. Millerf47c11e2005-06-24 20:18:35 -070015752 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015753
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015754 err = tg3_power_down_prepare(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015755 if (err) {
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015756 int err2;
15757
David S. Millerf47c11e2005-06-24 20:18:35 -070015758 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015759
Joe Perches63c3a662011-04-26 08:12:10 +000015760 tg3_flag_set(tp, INIT_COMPLETE);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015761 err2 = tg3_restart_hw(tp, 1);
15762 if (err2)
Michael Chanb9ec6c12006-07-25 16:37:27 -070015763 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015764
15765 tp->timer.expires = jiffies + tp->timer_offset;
15766 add_timer(&tp->timer);
15767
15768 netif_device_attach(dev);
15769 tg3_netif_start(tp);
15770
Michael Chanb9ec6c12006-07-25 16:37:27 -070015771out:
David S. Millerf47c11e2005-06-24 20:18:35 -070015772 tg3_full_unlock(tp);
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015773
15774 if (!err2)
15775 tg3_phy_start(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015776 }
15777
15778 return err;
15779}
15780
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015781static int tg3_resume(struct device *device)
Linus Torvalds1da177e2005-04-16 15:20:36 -070015782{
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015783 struct pci_dev *pdev = to_pci_dev(device);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015784 struct net_device *dev = pci_get_drvdata(pdev);
15785 struct tg3 *tp = netdev_priv(dev);
15786 int err;
15787
15788 if (!netif_running(dev))
15789 return 0;
15790
Linus Torvalds1da177e2005-04-16 15:20:36 -070015791 netif_device_attach(dev);
15792
David S. Millerf47c11e2005-06-24 20:18:35 -070015793 tg3_full_lock(tp, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015794
Joe Perches63c3a662011-04-26 08:12:10 +000015795 tg3_flag_set(tp, INIT_COMPLETE);
Michael Chanb9ec6c12006-07-25 16:37:27 -070015796 err = tg3_restart_hw(tp, 1);
15797 if (err)
15798 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015799
15800 tp->timer.expires = jiffies + tp->timer_offset;
15801 add_timer(&tp->timer);
15802
Linus Torvalds1da177e2005-04-16 15:20:36 -070015803 tg3_netif_start(tp);
15804
Michael Chanb9ec6c12006-07-25 16:37:27 -070015805out:
David S. Millerf47c11e2005-06-24 20:18:35 -070015806 tg3_full_unlock(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015807
Matt Carlsonb02fd9e2008-05-25 23:47:41 -070015808 if (!err)
15809 tg3_phy_start(tp);
15810
Michael Chanb9ec6c12006-07-25 16:37:27 -070015811 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015812}
15813
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015814static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
Eric Dumazetaa6027c2011-01-01 05:22:46 +000015815#define TG3_PM_OPS (&tg3_pm_ops)
15816
15817#else
15818
15819#define TG3_PM_OPS NULL
15820
15821#endif /* CONFIG_PM_SLEEP */
Rafael J. Wysockic866b7e2010-12-25 12:56:23 +000015822
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000015823/**
15824 * tg3_io_error_detected - called when PCI error is detected
15825 * @pdev: Pointer to PCI device
15826 * @state: The current pci connection state
15827 *
15828 * This function is called after a PCI bus error affecting
15829 * this device has been detected.
15830 */
15831static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
15832 pci_channel_state_t state)
15833{
15834 struct net_device *netdev = pci_get_drvdata(pdev);
15835 struct tg3 *tp = netdev_priv(netdev);
15836 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
15837
15838 netdev_info(netdev, "PCI I/O error detected\n");
15839
15840 rtnl_lock();
15841
15842 if (!netif_running(netdev))
15843 goto done;
15844
15845 tg3_phy_stop(tp);
15846
15847 tg3_netif_stop(tp);
15848
15849 del_timer_sync(&tp->timer);
Joe Perches63c3a662011-04-26 08:12:10 +000015850 tg3_flag_clear(tp, RESTART_TIMER);
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000015851
15852 /* Want to make sure that the reset task doesn't run */
Matt Carlsondb219972011-11-04 09:15:03 +000015853 tg3_reset_task_cancel(tp);
Joe Perches63c3a662011-04-26 08:12:10 +000015854 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
15855 tg3_flag_clear(tp, RESTART_TIMER);
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000015856
15857 netif_device_detach(netdev);
15858
15859 /* Clean up software state, even if MMIO is blocked */
15860 tg3_full_lock(tp, 0);
15861 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
15862 tg3_full_unlock(tp);
15863
15864done:
15865 if (state == pci_channel_io_perm_failure)
15866 err = PCI_ERS_RESULT_DISCONNECT;
15867 else
15868 pci_disable_device(pdev);
15869
15870 rtnl_unlock();
15871
15872 return err;
15873}
15874
15875/**
15876 * tg3_io_slot_reset - called after the pci bus has been reset.
15877 * @pdev: Pointer to PCI device
15878 *
15879 * Restart the card from scratch, as if from a cold-boot.
15880 * At this point, the card has exprienced a hard reset,
15881 * followed by fixups by BIOS, and has its config space
15882 * set up identically to what it was at cold boot.
15883 */
15884static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
15885{
15886 struct net_device *netdev = pci_get_drvdata(pdev);
15887 struct tg3 *tp = netdev_priv(netdev);
15888 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
15889 int err;
15890
15891 rtnl_lock();
15892
15893 if (pci_enable_device(pdev)) {
15894 netdev_err(netdev, "Cannot re-enable PCI device after reset.\n");
15895 goto done;
15896 }
15897
15898 pci_set_master(pdev);
15899 pci_restore_state(pdev);
15900 pci_save_state(pdev);
15901
15902 if (!netif_running(netdev)) {
15903 rc = PCI_ERS_RESULT_RECOVERED;
15904 goto done;
15905 }
15906
15907 err = tg3_power_up(tp);
Matt Carlsonbed98292011-07-13 09:27:29 +000015908 if (err)
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000015909 goto done;
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000015910
15911 rc = PCI_ERS_RESULT_RECOVERED;
15912
15913done:
15914 rtnl_unlock();
15915
15916 return rc;
15917}
15918
15919/**
15920 * tg3_io_resume - called when traffic can start flowing again.
15921 * @pdev: Pointer to PCI device
15922 *
15923 * This callback is called when the error recovery driver tells
15924 * us that its OK to resume normal operation.
15925 */
15926static void tg3_io_resume(struct pci_dev *pdev)
15927{
15928 struct net_device *netdev = pci_get_drvdata(pdev);
15929 struct tg3 *tp = netdev_priv(netdev);
15930 int err;
15931
15932 rtnl_lock();
15933
15934 if (!netif_running(netdev))
15935 goto done;
15936
15937 tg3_full_lock(tp, 0);
Joe Perches63c3a662011-04-26 08:12:10 +000015938 tg3_flag_set(tp, INIT_COMPLETE);
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000015939 err = tg3_restart_hw(tp, 1);
15940 tg3_full_unlock(tp);
15941 if (err) {
15942 netdev_err(netdev, "Cannot restart hardware after reset.\n");
15943 goto done;
15944 }
15945
15946 netif_device_attach(netdev);
15947
15948 tp->timer.expires = jiffies + tp->timer_offset;
15949 add_timer(&tp->timer);
15950
15951 tg3_netif_start(tp);
15952
15953 tg3_phy_start(tp);
15954
15955done:
15956 rtnl_unlock();
15957}
15958
15959static struct pci_error_handlers tg3_err_handler = {
15960 .error_detected = tg3_io_error_detected,
15961 .slot_reset = tg3_io_slot_reset,
15962 .resume = tg3_io_resume
15963};
15964
Linus Torvalds1da177e2005-04-16 15:20:36 -070015965static struct pci_driver tg3_driver = {
15966 .name = DRV_MODULE_NAME,
15967 .id_table = tg3_pci_tbl,
15968 .probe = tg3_init_one,
15969 .remove = __devexit_p(tg3_remove_one),
Matt Carlsonb45aa2f2011-04-25 12:42:48 +000015970 .err_handler = &tg3_err_handler,
Eric Dumazetaa6027c2011-01-01 05:22:46 +000015971 .driver.pm = TG3_PM_OPS,
Linus Torvalds1da177e2005-04-16 15:20:36 -070015972};
15973
15974static int __init tg3_init(void)
15975{
Jeff Garzik29917622006-08-19 17:48:59 -040015976 return pci_register_driver(&tg3_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -070015977}
15978
15979static void __exit tg3_cleanup(void)
15980{
15981 pci_unregister_driver(&tg3_driver);
15982}
15983
15984module_init(tg3_init);
15985module_exit(tg3_cleanup);