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review.evervolv.com / android_kernel_oneplus_msm8996 / db40517c75e1a33a886c8cadfa2d95f0fe5f5f4c / . / sound / soc / codecs / wm8962.c
blob: bd4b0db4cdaadb11fe12caed12b8e8e2f5bab7b1 [file] [log] [blame]
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1/*
2 * wm8962.c -- WM8962 ALSA SoC Audio driver
3 *
Mark Brown656baae2012-05-23 12:39:07 +0100[diff] [blame]4 * Copyright 2010-2 Wolfson Microelectronics plc
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]20#include <linux/gpio.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]21#include <linux/i2c.h>
22#include <linux/input.h>
Mark Brownd23031a42012-02-01 12:48:59 +0000[diff] [blame]23#include <linux/pm_runtime.h>
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]24#include <linux/regmap.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]25#include <linux/regulator/consumer.h>
26#include <linux/slab.h>
27#include <linux/workqueue.h>
28#include <sound/core.h>
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]29#include <sound/jack.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]33#include <sound/initval.h>
34#include <sound/tlv.h>
35#include <sound/wm8962.h>
Mark Brown2bbb5d62010-12-05 12:50:12 +0000[diff] [blame]36#include <trace/events/asoc.h>
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]37
38#include "wm8962.h"
39
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]40#define WM8962_NUM_SUPPLIES 8
41static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
42 "DCVDD",
43 "DBVDD",
44 "AVDD",
45 "CPVDD",
46 "MICVDD",
47 "PLLVDD",
48 "SPKVDD1",
49 "SPKVDD2",
50};
51
52/* codec private data */
53struct wm8962_priv {
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]54 struct regmap *regmap;
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]55 struct snd_soc_codec *codec;
56
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]57 int sysclk;
58 int sysclk_rate;
59
60 int bclk; /* Desired BCLK */
61 int lrclk;
62
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]63 struct completion fll_lock;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]64 int fll_src;
65 int fll_fref;
66 int fll_fout;
67
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]68 u16 dsp2_ena;
69
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]70 struct delayed_work mic_work;
71 struct snd_soc_jack *jack;
72
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]73 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
74 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
75
76#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
77 struct input_dev *beep;
78 struct work_struct beep_work;
79 int beep_rate;
80#endif
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]81
82#ifdef CONFIG_GPIOLIB
83 struct gpio_chip gpio_chip;
84#endif
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]85
86 int irq;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]87};
88
89/* We can't use the same notifier block for more than one supply and
90 * there's no way I can see to get from a callback to the caller
91 * except container_of().
92 */
93#define WM8962_REGULATOR_EVENT(n) \
94static int wm8962_regulator_event_##n(struct notifier_block *nb, \
95 unsigned long event, void *data) \
96{ \
97 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
98 disable_nb[n]); \
99 if (event & REGULATOR_EVENT_DISABLE) { \
Mark Brown5539a102012-01-25 21:10:21 +0000[diff] [blame]100 regcache_mark_dirty(wm8962->regmap); \
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]101 } \
102 return 0; \
103}
104
105WM8962_REGULATOR_EVENT(0)
106WM8962_REGULATOR_EVENT(1)
107WM8962_REGULATOR_EVENT(2)
108WM8962_REGULATOR_EVENT(3)
109WM8962_REGULATOR_EVENT(4)
110WM8962_REGULATOR_EVENT(5)
111WM8962_REGULATOR_EVENT(6)
112WM8962_REGULATOR_EVENT(7)
113
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]114static struct reg_default wm8962_reg[] = {
115 { 0, 0x009F }, /* R0 - Left Input volume */
116 { 1, 0x049F }, /* R1 - Right Input volume */
117 { 2, 0x0000 }, /* R2 - HPOUTL volume */
118 { 3, 0x0000 }, /* R3 - HPOUTR volume */
Mark Brownba106ce2012-03-06 00:25:28 +0000[diff] [blame]119
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]120 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
121 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
122 { 7, 0x000A }, /* R7 - Audio Interface 0 */
Mark Brownba106ce2012-03-06 00:25:28 +0000[diff] [blame]123
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]124 { 9, 0x0300 }, /* R9 - Audio Interface 1 */
125 { 10, 0x00C0 }, /* R10 - Left DAC volume */
126 { 11, 0x00C0 }, /* R11 - Right DAC volume */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]127
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]128 { 14, 0x0040 }, /* R14 - Audio Interface 2 */
129 { 15, 0x6243 }, /* R15 - Software Reset */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]130
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]131 { 17, 0x007B }, /* R17 - ALC1 */
Mark Brownba106ce2012-03-06 00:25:28 +0000[diff] [blame]132
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]133 { 19, 0x1C32 }, /* R19 - ALC3 */
134 { 20, 0x3200 }, /* R20 - Noise Gate */
135 { 21, 0x00C0 }, /* R21 - Left ADC volume */
136 { 22, 0x00C0 }, /* R22 - Right ADC volume */
137 { 23, 0x0160 }, /* R23 - Additional control(1) */
138 { 24, 0x0000 }, /* R24 - Additional control(2) */
139 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */
140 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */
141 { 27, 0x0010 }, /* R27 - Additional Control (3) */
142 { 28, 0x0000 }, /* R28 - Anti-pop */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]143
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]144 { 30, 0x005E }, /* R30 - Clocking 3 */
145 { 31, 0x0000 }, /* R31 - Input mixer control (1) */
146 { 32, 0x0145 }, /* R32 - Left input mixer volume */
147 { 33, 0x0145 }, /* R33 - Right input mixer volume */
148 { 34, 0x0009 }, /* R34 - Input mixer control (2) */
149 { 35, 0x0003 }, /* R35 - Input bias control */
150 { 37, 0x0008 }, /* R37 - Left input PGA control */
151 { 38, 0x0008 }, /* R38 - Right input PGA control */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]152
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]153 { 40, 0x0000 }, /* R40 - SPKOUTL volume */
154 { 41, 0x0000 }, /* R41 - SPKOUTR volume */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]155
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]156 { 51, 0x0003 }, /* R51 - Class D Control 2 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]157
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]158 { 56, 0x0506 }, /* R56 - Clocking 4 */
159 { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */
160 { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]161
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]162 { 60, 0x0300 }, /* R60 - DC Servo 0 */
163 { 61, 0x0300 }, /* R61 - DC Servo 1 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]164
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]165 { 64, 0x0810 }, /* R64 - DC Servo 4 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]166
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]167 { 68, 0x001B }, /* R68 - Analogue PGA Bias */
168 { 69, 0x0000 }, /* R69 - Analogue HP 0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]169
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]170 { 71, 0x01FB }, /* R71 - Analogue HP 2 */
171 { 72, 0x0000 }, /* R72 - Charge Pump 1 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]172
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]173 { 82, 0x0004 }, /* R82 - Charge Pump B */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]174
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]175 { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]176
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]177 { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]178
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]179 { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */
180 { 94, 0x0000 }, /* R94 - Control Interface */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]181
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]182 { 99, 0x0000 }, /* R99 - Mixer Enables */
183 { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */
184 { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */
185 { 102, 0x013F }, /* R102 - Headphone Mixer (3) */
186 { 103, 0x013F }, /* R103 - Headphone Mixer (4) */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]187
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]188 { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */
189 { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */
190 { 107, 0x013F }, /* R107 - Speaker Mixer (3) */
191 { 108, 0x013F }, /* R108 - Speaker Mixer (4) */
192 { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */
193 { 110, 0x0002 }, /* R110 - Beep Generator (1) */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]194
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]195 { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */
196 { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]197
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]198 { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]199
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]200 { 124, 0x0011 }, /* R124 - Analogue Clocking1 */
201 { 125, 0x004B }, /* R125 - Analogue Clocking2 */
202 { 126, 0x000D }, /* R126 - Analogue Clocking3 */
203 { 127, 0x0000 }, /* R127 - PLL Software Reset */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]204
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]205 { 131, 0x0000 }, /* R131 - PLL 4 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]206
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]207 { 136, 0x0067 }, /* R136 - PLL 9 */
208 { 137, 0x001C }, /* R137 - PLL 10 */
209 { 138, 0x0071 }, /* R138 - PLL 11 */
210 { 139, 0x00C7 }, /* R139 - PLL 12 */
211 { 140, 0x0067 }, /* R140 - PLL 13 */
212 { 141, 0x0048 }, /* R141 - PLL 14 */
213 { 142, 0x0022 }, /* R142 - PLL 15 */
214 { 143, 0x0097 }, /* R143 - PLL 16 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]215
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]216 { 155, 0x000C }, /* R155 - FLL Control (1) */
217 { 156, 0x0039 }, /* R156 - FLL Control (2) */
218 { 157, 0x0180 }, /* R157 - FLL Control (3) */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]219
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]220 { 159, 0x0032 }, /* R159 - FLL Control (5) */
221 { 160, 0x0018 }, /* R160 - FLL Control (6) */
222 { 161, 0x007D }, /* R161 - FLL Control (7) */
223 { 162, 0x0008 }, /* R162 - FLL Control (8) */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]224
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]225 { 252, 0x0005 }, /* R252 - General test 1 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]226
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]227 { 256, 0x0000 }, /* R256 - DF1 */
228 { 257, 0x0000 }, /* R257 - DF2 */
229 { 258, 0x0000 }, /* R258 - DF3 */
230 { 259, 0x0000 }, /* R259 - DF4 */
231 { 260, 0x0000 }, /* R260 - DF5 */
232 { 261, 0x0000 }, /* R261 - DF6 */
233 { 262, 0x0000 }, /* R262 - DF7 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]234
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]235 { 264, 0x0000 }, /* R264 - LHPF1 */
236 { 265, 0x0000 }, /* R265 - LHPF2 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]237
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]238 { 268, 0x0000 }, /* R268 - THREED1 */
239 { 269, 0x0000 }, /* R269 - THREED2 */
240 { 270, 0x0000 }, /* R270 - THREED3 */
241 { 271, 0x0000 }, /* R271 - THREED4 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]242
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]243 { 276, 0x000C }, /* R276 - DRC 1 */
244 { 277, 0x0925 }, /* R277 - DRC 2 */
245 { 278, 0x0000 }, /* R278 - DRC 3 */
246 { 279, 0x0000 }, /* R279 - DRC 4 */
247 { 280, 0x0000 }, /* R280 - DRC 5 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]248
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]249 { 285, 0x0000 }, /* R285 - Tloopback */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]250
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]251 { 335, 0x0004 }, /* R335 - EQ1 */
252 { 336, 0x6318 }, /* R336 - EQ2 */
253 { 337, 0x6300 }, /* R337 - EQ3 */
254 { 338, 0x0FCA }, /* R338 - EQ4 */
255 { 339, 0x0400 }, /* R339 - EQ5 */
256 { 340, 0x00D8 }, /* R340 - EQ6 */
257 { 341, 0x1EB5 }, /* R341 - EQ7 */
258 { 342, 0xF145 }, /* R342 - EQ8 */
259 { 343, 0x0B75 }, /* R343 - EQ9 */
260 { 344, 0x01C5 }, /* R344 - EQ10 */
261 { 345, 0x1C58 }, /* R345 - EQ11 */
262 { 346, 0xF373 }, /* R346 - EQ12 */
263 { 347, 0x0A54 }, /* R347 - EQ13 */
264 { 348, 0x0558 }, /* R348 - EQ14 */
265 { 349, 0x168E }, /* R349 - EQ15 */
266 { 350, 0xF829 }, /* R350 - EQ16 */
267 { 351, 0x07AD }, /* R351 - EQ17 */
268 { 352, 0x1103 }, /* R352 - EQ18 */
269 { 353, 0x0564 }, /* R353 - EQ19 */
270 { 354, 0x0559 }, /* R354 - EQ20 */
271 { 355, 0x4000 }, /* R355 - EQ21 */
272 { 356, 0x6318 }, /* R356 - EQ22 */
273 { 357, 0x6300 }, /* R357 - EQ23 */
274 { 358, 0x0FCA }, /* R358 - EQ24 */
275 { 359, 0x0400 }, /* R359 - EQ25 */
276 { 360, 0x00D8 }, /* R360 - EQ26 */
277 { 361, 0x1EB5 }, /* R361 - EQ27 */
278 { 362, 0xF145 }, /* R362 - EQ28 */
279 { 363, 0x0B75 }, /* R363 - EQ29 */
280 { 364, 0x01C5 }, /* R364 - EQ30 */
281 { 365, 0x1C58 }, /* R365 - EQ31 */
282 { 366, 0xF373 }, /* R366 - EQ32 */
283 { 367, 0x0A54 }, /* R367 - EQ33 */
284 { 368, 0x0558 }, /* R368 - EQ34 */
285 { 369, 0x168E }, /* R369 - EQ35 */
286 { 370, 0xF829 }, /* R370 - EQ36 */
287 { 371, 0x07AD }, /* R371 - EQ37 */
288 { 372, 0x1103 }, /* R372 - EQ38 */
289 { 373, 0x0564 }, /* R373 - EQ39 */
290 { 374, 0x0559 }, /* R374 - EQ40 */
291 { 375, 0x4000 }, /* R375 - EQ41 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]292
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]293 { 513, 0x0000 }, /* R513 - GPIO 2 */
294 { 514, 0x0000 }, /* R514 - GPIO 3 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]295
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]296 { 516, 0x8100 }, /* R516 - GPIO 5 */
297 { 517, 0x8100 }, /* R517 - GPIO 6 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]298
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]299 { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */
300 { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]301
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]302 { 576, 0x0000 }, /* R576 - Interrupt Control */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]303
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]304 { 584, 0x002D }, /* R584 - IRQ Debounce */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]305
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]306 { 586, 0x0000 }, /* R586 - MICINT Source Pol */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]307
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]308 { 768, 0x1C00 }, /* R768 - DSP2 Power Management */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]309
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]310 { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]311
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]312 { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */
313 { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */
314 { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]315
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]316 { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */
317 { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]318
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]319 { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */
320 { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]321
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]322 { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */
323 { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]324
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]325 { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]326
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]327 { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */
328 { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */
329 { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */
330 { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */
331 { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */
332 { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]333
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]334 { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */
335 { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */
336 { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */
337 { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */
338 { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */
339 { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */
340 { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */
341 { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */
342 { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */
343 { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */
344 { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */
345 { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */
346 { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */
347 { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */
348 { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */
349 { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */
350 { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */
351 { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */
352 { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */
353 { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */
354 { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */
355 { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */
356 { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */
357 { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */
358 { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */
359 { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */
360 { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */
361 { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */
362 { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */
363 { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]364
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]365 { 17048, 0x0083 }, /* R17408 - HPF_C_1 */
366 { 17049, 0x98AD }, /* R17409 - HPF_C_0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]367
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]368 { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */
369 { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */
370 { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */
371 { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */
372 { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */
373 { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */
374 { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */
375 { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */
376 { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */
377 { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */
378 { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */
379 { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */
380 { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */
381 { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */
382 { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */
383 { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */
384 { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */
385 { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */
386 { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */
387 { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */
388 { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */
389 { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */
390 { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */
391 { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */
392 { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */
393 { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */
394 { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */
395 { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */
396 { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */
397 { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */
398 { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */
399 { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */
400 { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */
401 { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */
402 { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */
403 { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */
404 { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */
405 { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */
406 { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */
407 { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */
408 { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */
409 { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */
410 { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */
411 { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */
412 { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */
413 { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */
414 { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */
415 { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */
416 { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */
417 { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */
418 { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */
419 { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */
420 { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */
421 { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */
422 { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */
423 { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */
424 { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */
425 { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */
426 { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */
427 { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */
428 { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */
429 { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */
430 { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */
431 { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]432
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]433 { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */
434 { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */
435 { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */
436 { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]437
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]438 { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */
439 { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */
440 { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */
441 { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */
442 { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */
443 { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */
444 { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */
445 { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */
446 { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */
447 { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */
448 { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */
449 { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */
450 { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */
451 { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */
452 { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */
453 { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */
454 { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */
455 { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */
456 { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */
457 { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */
458 { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */
459 { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */
460 { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */
461 { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */
462 { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */
463 { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */
464 { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */
465 { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */
466 { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */
467 { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */
468 { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */
469 { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */
470 { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */
471 { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */
472 { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */
473 { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */
474 { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */
475 { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */
476 { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */
477 { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */
478 { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */
479 { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */
480 { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */
481 { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */
482 { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */
483 { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */
484 { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */
485 { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */
486 { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */
487 { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */
488 { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */
489 { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */
490 { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */
491 { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */
492 { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */
493 { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */
494 { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */
495 { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */
496 { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */
497 { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */
498 { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */
499 { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */
500 { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */
501 { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]502
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]503 { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */
504 { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */
505 { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */
506 { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */
507 { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */
508 { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */
509 { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */
510 { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */
511 { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */
512 { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */
513 { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */
514 { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */
515 { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */
516 { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */
517 { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */
518 { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */
519 { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */
520 { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */
521 { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */
522 { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */
523 { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */
524 { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */
525 { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */
526 { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */
527 { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */
528 { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */
529 { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */
530 { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */
531 { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */
532 { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */
533 { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */
534 { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */
535 { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */
536 { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */
537 { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */
538 { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */
539 { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */
540 { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */
541 { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */
542 { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */
543 { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */
544 { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */
545 { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */
546 { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */
547 { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */
548 { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */
549 { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */
550 { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */
551 { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */
552 { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */
553 { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */
554 { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */
555 { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */
556 { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */
557 { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */
558 { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */
559 { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */
560 { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */
561 { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */
562 { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */
563 { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */
564 { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */
565 { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */
566 { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]567
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]568 { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */
569 { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */
570 { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */
571 { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]572
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]573 { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */
574 { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */
575 { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */
576 { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */
577 { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */
578 { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */
579 { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */
580 { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */
581 { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */
582 { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */
583 { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */
584 { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */
585 { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */
586 { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */
587 { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */
588 { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */
589 { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */
590 { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */
591 { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */
592 { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */
593 { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */
594 { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */
595 { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */
596 { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */
597 { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */
598 { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */
599 { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */
600 { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */
601 { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */
602 { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */
603 { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */
604 { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */
605 { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */
606 { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */
607 { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */
608 { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */
609 { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */
610 { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */
611 { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */
612 { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */
613 { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */
614 { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */
615 { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */
616 { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */
617 { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */
618 { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */
619 { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */
620 { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */
621 { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */
622 { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */
623 { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */
624 { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */
625 { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */
626 { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */
627 { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */
628 { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */
629 { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */
630 { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */
631 { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */
632 { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */
633 { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */
634 { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */
635 { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */
636 { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]637
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]638 { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */
639 { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */
640 { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */
641 { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */
642 { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */
643 { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */
644 { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */
645 { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */
646 { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */
647 { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */
648 { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */
649 { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */
650 { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */
651 { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */
652 { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */
653 { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */
654 { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */
655 { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */
656 { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */
657 { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */
658 { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */
659 { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */
660 { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */
661 { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */
662 { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */
663 { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */
664 { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */
665 { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */
666 { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */
667 { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */
668 { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */
669 { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */
670 { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */
671 { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */
672 { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */
673 { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */
674 { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */
675 { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */
676 { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */
677 { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */
678 { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */
679 { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */
680 { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */
681 { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */
682 { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */
683 { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */
684 { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */
685 { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */
686 { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */
687 { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */
688 { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */
689 { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */
690 { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */
691 { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */
692 { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */
693 { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */
694 { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */
695 { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */
696 { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */
697 { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */
698 { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */
699 { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */
700 { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */
701 { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */
702 { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */
703 { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */
704 { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */
705 { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */
706 { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */
707 { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */
708 { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */
709 { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */
710 { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */
711 { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */
712 { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */
713 { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */
714 { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */
715 { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */
716 { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */
717 { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */
718 { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */
719 { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */
720 { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */
721 { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */
722 { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */
723 { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */
724 { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */
725 { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */
726 { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */
727 { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */
728 { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */
729 { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */
730 { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */
731 { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */
732 { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */
733 { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */
734 { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */
735 { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */
736 { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */
737 { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */
738 { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */
739 { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */
740 { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */
741 { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */
742 { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */
743 { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */
744 { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */
745 { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */
746 { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */
747 { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */
748 { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */
749 { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */
750 { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */
751 { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */
752 { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */
753 { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */
754 { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */
755 { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */
756 { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */
757 { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */
758 { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */
759 { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */
760 { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */
761 { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */
762 { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */
763 { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */
764 { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */
765 { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */
766 { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */
767 { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */
768 { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */
769 { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */
770 { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */
771 { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */
772 { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */
773 { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */
774 { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */
775 { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */
776 { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */
777 { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */
778 { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */
779 { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */
780 { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */
781 { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */
782 { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */
783 { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */
784 { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */
785 { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */
Mark Brownf57f6c02010-10-07 17:41:04 -0700[diff] [blame]786};
787
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]788static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]789{
Mark Browncef6d1d2012-01-11 20:13:19 -0800[diff] [blame]790 switch (reg) {
791 case WM8962_CLOCKING1:
792 case WM8962_CLOCKING2:
793 case WM8962_SOFTWARE_RESET:
794 case WM8962_ALC2:
795 case WM8962_THERMAL_SHUTDOWN_STATUS:
796 case WM8962_ADDITIONAL_CONTROL_4:
797 case WM8962_CLASS_D_CONTROL_1:
798 case WM8962_DC_SERVO_6:
799 case WM8962_INTERRUPT_STATUS_1:
800 case WM8962_INTERRUPT_STATUS_2:
801 case WM8962_DSP2_EXECCONTROL:
802 return true;
803 default:
804 return false;
805 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]806}
807
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]808static bool wm8962_readable_register(struct device *dev, unsigned int reg)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]809{
Mark Browncef6d1d2012-01-11 20:13:19 -0800[diff] [blame]810 switch (reg) {
811 case WM8962_LEFT_INPUT_VOLUME:
812 case WM8962_RIGHT_INPUT_VOLUME:
813 case WM8962_HPOUTL_VOLUME:
814 case WM8962_HPOUTR_VOLUME:
815 case WM8962_CLOCKING1:
816 case WM8962_ADC_DAC_CONTROL_1:
817 case WM8962_ADC_DAC_CONTROL_2:
818 case WM8962_AUDIO_INTERFACE_0:
819 case WM8962_CLOCKING2:
820 case WM8962_AUDIO_INTERFACE_1:
821 case WM8962_LEFT_DAC_VOLUME:
822 case WM8962_RIGHT_DAC_VOLUME:
823 case WM8962_AUDIO_INTERFACE_2:
824 case WM8962_SOFTWARE_RESET:
825 case WM8962_ALC1:
826 case WM8962_ALC2:
827 case WM8962_ALC3:
828 case WM8962_NOISE_GATE:
829 case WM8962_LEFT_ADC_VOLUME:
830 case WM8962_RIGHT_ADC_VOLUME:
831 case WM8962_ADDITIONAL_CONTROL_1:
832 case WM8962_ADDITIONAL_CONTROL_2:
833 case WM8962_PWR_MGMT_1:
834 case WM8962_PWR_MGMT_2:
835 case WM8962_ADDITIONAL_CONTROL_3:
836 case WM8962_ANTI_POP:
837 case WM8962_CLOCKING_3:
838 case WM8962_INPUT_MIXER_CONTROL_1:
839 case WM8962_LEFT_INPUT_MIXER_VOLUME:
840 case WM8962_RIGHT_INPUT_MIXER_VOLUME:
841 case WM8962_INPUT_MIXER_CONTROL_2:
842 case WM8962_INPUT_BIAS_CONTROL:
843 case WM8962_LEFT_INPUT_PGA_CONTROL:
844 case WM8962_RIGHT_INPUT_PGA_CONTROL:
845 case WM8962_SPKOUTL_VOLUME:
846 case WM8962_SPKOUTR_VOLUME:
847 case WM8962_THERMAL_SHUTDOWN_STATUS:
848 case WM8962_ADDITIONAL_CONTROL_4:
849 case WM8962_CLASS_D_CONTROL_1:
850 case WM8962_CLASS_D_CONTROL_2:
851 case WM8962_CLOCKING_4:
852 case WM8962_DAC_DSP_MIXING_1:
853 case WM8962_DAC_DSP_MIXING_2:
854 case WM8962_DC_SERVO_0:
855 case WM8962_DC_SERVO_1:
856 case WM8962_DC_SERVO_4:
857 case WM8962_DC_SERVO_6:
858 case WM8962_ANALOGUE_PGA_BIAS:
859 case WM8962_ANALOGUE_HP_0:
860 case WM8962_ANALOGUE_HP_2:
861 case WM8962_CHARGE_PUMP_1:
862 case WM8962_CHARGE_PUMP_B:
863 case WM8962_WRITE_SEQUENCER_CONTROL_1:
864 case WM8962_WRITE_SEQUENCER_CONTROL_2:
865 case WM8962_WRITE_SEQUENCER_CONTROL_3:
866 case WM8962_CONTROL_INTERFACE:
867 case WM8962_MIXER_ENABLES:
868 case WM8962_HEADPHONE_MIXER_1:
869 case WM8962_HEADPHONE_MIXER_2:
870 case WM8962_HEADPHONE_MIXER_3:
871 case WM8962_HEADPHONE_MIXER_4:
872 case WM8962_SPEAKER_MIXER_1:
873 case WM8962_SPEAKER_MIXER_2:
874 case WM8962_SPEAKER_MIXER_3:
875 case WM8962_SPEAKER_MIXER_4:
876 case WM8962_SPEAKER_MIXER_5:
877 case WM8962_BEEP_GENERATOR_1:
878 case WM8962_OSCILLATOR_TRIM_3:
879 case WM8962_OSCILLATOR_TRIM_4:
880 case WM8962_OSCILLATOR_TRIM_7:
881 case WM8962_ANALOGUE_CLOCKING1:
882 case WM8962_ANALOGUE_CLOCKING2:
883 case WM8962_ANALOGUE_CLOCKING3:
884 case WM8962_PLL_SOFTWARE_RESET:
885 case WM8962_PLL2:
886 case WM8962_PLL_4:
887 case WM8962_PLL_9:
888 case WM8962_PLL_10:
889 case WM8962_PLL_11:
890 case WM8962_PLL_12:
891 case WM8962_PLL_13:
892 case WM8962_PLL_14:
893 case WM8962_PLL_15:
894 case WM8962_PLL_16:
895 case WM8962_FLL_CONTROL_1:
896 case WM8962_FLL_CONTROL_2:
897 case WM8962_FLL_CONTROL_3:
898 case WM8962_FLL_CONTROL_5:
899 case WM8962_FLL_CONTROL_6:
900 case WM8962_FLL_CONTROL_7:
901 case WM8962_FLL_CONTROL_8:
902 case WM8962_GENERAL_TEST_1:
903 case WM8962_DF1:
904 case WM8962_DF2:
905 case WM8962_DF3:
906 case WM8962_DF4:
907 case WM8962_DF5:
908 case WM8962_DF6:
909 case WM8962_DF7:
910 case WM8962_LHPF1:
911 case WM8962_LHPF2:
912 case WM8962_THREED1:
913 case WM8962_THREED2:
914 case WM8962_THREED3:
915 case WM8962_THREED4:
916 case WM8962_DRC_1:
917 case WM8962_DRC_2:
918 case WM8962_DRC_3:
919 case WM8962_DRC_4:
920 case WM8962_DRC_5:
921 case WM8962_TLOOPBACK:
922 case WM8962_EQ1:
923 case WM8962_EQ2:
924 case WM8962_EQ3:
925 case WM8962_EQ4:
926 case WM8962_EQ5:
927 case WM8962_EQ6:
928 case WM8962_EQ7:
929 case WM8962_EQ8:
930 case WM8962_EQ9:
931 case WM8962_EQ10:
932 case WM8962_EQ11:
933 case WM8962_EQ12:
934 case WM8962_EQ13:
935 case WM8962_EQ14:
936 case WM8962_EQ15:
937 case WM8962_EQ16:
938 case WM8962_EQ17:
939 case WM8962_EQ18:
940 case WM8962_EQ19:
941 case WM8962_EQ20:
942 case WM8962_EQ21:
943 case WM8962_EQ22:
944 case WM8962_EQ23:
945 case WM8962_EQ24:
946 case WM8962_EQ25:
947 case WM8962_EQ26:
948 case WM8962_EQ27:
949 case WM8962_EQ28:
950 case WM8962_EQ29:
951 case WM8962_EQ30:
952 case WM8962_EQ31:
953 case WM8962_EQ32:
954 case WM8962_EQ33:
955 case WM8962_EQ34:
956 case WM8962_EQ35:
957 case WM8962_EQ36:
958 case WM8962_EQ37:
959 case WM8962_EQ38:
960 case WM8962_EQ39:
961 case WM8962_EQ40:
962 case WM8962_EQ41:
963 case WM8962_GPIO_BASE:
964 case WM8962_GPIO_2:
965 case WM8962_GPIO_3:
966 case WM8962_GPIO_5:
967 case WM8962_GPIO_6:
968 case WM8962_INTERRUPT_STATUS_1:
969 case WM8962_INTERRUPT_STATUS_2:
970 case WM8962_INTERRUPT_STATUS_1_MASK:
971 case WM8962_INTERRUPT_STATUS_2_MASK:
972 case WM8962_INTERRUPT_CONTROL:
973 case WM8962_IRQ_DEBOUNCE:
974 case WM8962_MICINT_SOURCE_POL:
975 case WM8962_DSP2_POWER_MANAGEMENT:
976 case WM8962_DSP2_EXECCONTROL:
977 case WM8962_DSP2_INSTRUCTION_RAM_0:
978 case WM8962_DSP2_ADDRESS_RAM_2:
979 case WM8962_DSP2_ADDRESS_RAM_1:
980 case WM8962_DSP2_ADDRESS_RAM_0:
981 case WM8962_DSP2_DATA1_RAM_1:
982 case WM8962_DSP2_DATA1_RAM_0:
983 case WM8962_DSP2_DATA2_RAM_1:
984 case WM8962_DSP2_DATA2_RAM_0:
985 case WM8962_DSP2_DATA3_RAM_1:
986 case WM8962_DSP2_DATA3_RAM_0:
987 case WM8962_DSP2_COEFF_RAM_0:
988 case WM8962_RETUNEADC_SHARED_COEFF_1:
989 case WM8962_RETUNEADC_SHARED_COEFF_0:
990 case WM8962_RETUNEDAC_SHARED_COEFF_1:
991 case WM8962_RETUNEDAC_SHARED_COEFF_0:
992 case WM8962_SOUNDSTAGE_ENABLES_1:
993 case WM8962_SOUNDSTAGE_ENABLES_0:
994 case WM8962_HDBASS_AI_1:
995 case WM8962_HDBASS_AI_0:
996 case WM8962_HDBASS_AR_1:
997 case WM8962_HDBASS_AR_0:
998 case WM8962_HDBASS_B_1:
999 case WM8962_HDBASS_B_0:
1000 case WM8962_HDBASS_K_1:
1001 case WM8962_HDBASS_K_0:
1002 case WM8962_HDBASS_N1_1:
1003 case WM8962_HDBASS_N1_0:
1004 case WM8962_HDBASS_N2_1:
1005 case WM8962_HDBASS_N2_0:
1006 case WM8962_HDBASS_N3_1:
1007 case WM8962_HDBASS_N3_0:
1008 case WM8962_HDBASS_N4_1:
1009 case WM8962_HDBASS_N4_0:
1010 case WM8962_HDBASS_N5_1:
1011 case WM8962_HDBASS_N5_0:
1012 case WM8962_HDBASS_X1_1:
1013 case WM8962_HDBASS_X1_0:
1014 case WM8962_HDBASS_X2_1:
1015 case WM8962_HDBASS_X2_0:
1016 case WM8962_HDBASS_X3_1:
1017 case WM8962_HDBASS_X3_0:
1018 case WM8962_HDBASS_ATK_1:
1019 case WM8962_HDBASS_ATK_0:
1020 case WM8962_HDBASS_DCY_1:
1021 case WM8962_HDBASS_DCY_0:
1022 case WM8962_HDBASS_PG_1:
1023 case WM8962_HDBASS_PG_0:
1024 case WM8962_HPF_C_1:
1025 case WM8962_HPF_C_0:
1026 case WM8962_ADCL_RETUNE_C1_1:
1027 case WM8962_ADCL_RETUNE_C1_0:
1028 case WM8962_ADCL_RETUNE_C2_1:
1029 case WM8962_ADCL_RETUNE_C2_0:
1030 case WM8962_ADCL_RETUNE_C3_1:
1031 case WM8962_ADCL_RETUNE_C3_0:
1032 case WM8962_ADCL_RETUNE_C4_1:
1033 case WM8962_ADCL_RETUNE_C4_0:
1034 case WM8962_ADCL_RETUNE_C5_1:
1035 case WM8962_ADCL_RETUNE_C5_0:
1036 case WM8962_ADCL_RETUNE_C6_1:
1037 case WM8962_ADCL_RETUNE_C6_0:
1038 case WM8962_ADCL_RETUNE_C7_1:
1039 case WM8962_ADCL_RETUNE_C7_0:
1040 case WM8962_ADCL_RETUNE_C8_1:
1041 case WM8962_ADCL_RETUNE_C8_0:
1042 case WM8962_ADCL_RETUNE_C9_1:
1043 case WM8962_ADCL_RETUNE_C9_0:
1044 case WM8962_ADCL_RETUNE_C10_1:
1045 case WM8962_ADCL_RETUNE_C10_0:
1046 case WM8962_ADCL_RETUNE_C11_1:
1047 case WM8962_ADCL_RETUNE_C11_0:
1048 case WM8962_ADCL_RETUNE_C12_1:
1049 case WM8962_ADCL_RETUNE_C12_0:
1050 case WM8962_ADCL_RETUNE_C13_1:
1051 case WM8962_ADCL_RETUNE_C13_0:
1052 case WM8962_ADCL_RETUNE_C14_1:
1053 case WM8962_ADCL_RETUNE_C14_0:
1054 case WM8962_ADCL_RETUNE_C15_1:
1055 case WM8962_ADCL_RETUNE_C15_0:
1056 case WM8962_ADCL_RETUNE_C16_1:
1057 case WM8962_ADCL_RETUNE_C16_0:
1058 case WM8962_ADCL_RETUNE_C17_1:
1059 case WM8962_ADCL_RETUNE_C17_0:
1060 case WM8962_ADCL_RETUNE_C18_1:
1061 case WM8962_ADCL_RETUNE_C18_0:
1062 case WM8962_ADCL_RETUNE_C19_1:
1063 case WM8962_ADCL_RETUNE_C19_0:
1064 case WM8962_ADCL_RETUNE_C20_1:
1065 case WM8962_ADCL_RETUNE_C20_0:
1066 case WM8962_ADCL_RETUNE_C21_1:
1067 case WM8962_ADCL_RETUNE_C21_0:
1068 case WM8962_ADCL_RETUNE_C22_1:
1069 case WM8962_ADCL_RETUNE_C22_0:
1070 case WM8962_ADCL_RETUNE_C23_1:
1071 case WM8962_ADCL_RETUNE_C23_0:
1072 case WM8962_ADCL_RETUNE_C24_1:
1073 case WM8962_ADCL_RETUNE_C24_0:
1074 case WM8962_ADCL_RETUNE_C25_1:
1075 case WM8962_ADCL_RETUNE_C25_0:
1076 case WM8962_ADCL_RETUNE_C26_1:
1077 case WM8962_ADCL_RETUNE_C26_0:
1078 case WM8962_ADCL_RETUNE_C27_1:
1079 case WM8962_ADCL_RETUNE_C27_0:
1080 case WM8962_ADCL_RETUNE_C28_1:
1081 case WM8962_ADCL_RETUNE_C28_0:
1082 case WM8962_ADCL_RETUNE_C29_1:
1083 case WM8962_ADCL_RETUNE_C29_0:
1084 case WM8962_ADCL_RETUNE_C30_1:
1085 case WM8962_ADCL_RETUNE_C30_0:
1086 case WM8962_ADCL_RETUNE_C31_1:
1087 case WM8962_ADCL_RETUNE_C31_0:
1088 case WM8962_ADCL_RETUNE_C32_1:
1089 case WM8962_ADCL_RETUNE_C32_0:
1090 case WM8962_RETUNEADC_PG2_1:
1091 case WM8962_RETUNEADC_PG2_0:
1092 case WM8962_RETUNEADC_PG_1:
1093 case WM8962_RETUNEADC_PG_0:
1094 case WM8962_ADCR_RETUNE_C1_1:
1095 case WM8962_ADCR_RETUNE_C1_0:
1096 case WM8962_ADCR_RETUNE_C2_1:
1097 case WM8962_ADCR_RETUNE_C2_0:
1098 case WM8962_ADCR_RETUNE_C3_1:
1099 case WM8962_ADCR_RETUNE_C3_0:
1100 case WM8962_ADCR_RETUNE_C4_1:
1101 case WM8962_ADCR_RETUNE_C4_0:
1102 case WM8962_ADCR_RETUNE_C5_1:
1103 case WM8962_ADCR_RETUNE_C5_0:
1104 case WM8962_ADCR_RETUNE_C6_1:
1105 case WM8962_ADCR_RETUNE_C6_0:
1106 case WM8962_ADCR_RETUNE_C7_1:
1107 case WM8962_ADCR_RETUNE_C7_0:
1108 case WM8962_ADCR_RETUNE_C8_1:
1109 case WM8962_ADCR_RETUNE_C8_0:
1110 case WM8962_ADCR_RETUNE_C9_1:
1111 case WM8962_ADCR_RETUNE_C9_0:
1112 case WM8962_ADCR_RETUNE_C10_1:
1113 case WM8962_ADCR_RETUNE_C10_0:
1114 case WM8962_ADCR_RETUNE_C11_1:
1115 case WM8962_ADCR_RETUNE_C11_0:
1116 case WM8962_ADCR_RETUNE_C12_1:
1117 case WM8962_ADCR_RETUNE_C12_0:
1118 case WM8962_ADCR_RETUNE_C13_1:
1119 case WM8962_ADCR_RETUNE_C13_0:
1120 case WM8962_ADCR_RETUNE_C14_1:
1121 case WM8962_ADCR_RETUNE_C14_0:
1122 case WM8962_ADCR_RETUNE_C15_1:
1123 case WM8962_ADCR_RETUNE_C15_0:
1124 case WM8962_ADCR_RETUNE_C16_1:
1125 case WM8962_ADCR_RETUNE_C16_0:
1126 case WM8962_ADCR_RETUNE_C17_1:
1127 case WM8962_ADCR_RETUNE_C17_0:
1128 case WM8962_ADCR_RETUNE_C18_1:
1129 case WM8962_ADCR_RETUNE_C18_0:
1130 case WM8962_ADCR_RETUNE_C19_1:
1131 case WM8962_ADCR_RETUNE_C19_0:
1132 case WM8962_ADCR_RETUNE_C20_1:
1133 case WM8962_ADCR_RETUNE_C20_0:
1134 case WM8962_ADCR_RETUNE_C21_1:
1135 case WM8962_ADCR_RETUNE_C21_0:
1136 case WM8962_ADCR_RETUNE_C22_1:
1137 case WM8962_ADCR_RETUNE_C22_0:
1138 case WM8962_ADCR_RETUNE_C23_1:
1139 case WM8962_ADCR_RETUNE_C23_0:
1140 case WM8962_ADCR_RETUNE_C24_1:
1141 case WM8962_ADCR_RETUNE_C24_0:
1142 case WM8962_ADCR_RETUNE_C25_1:
1143 case WM8962_ADCR_RETUNE_C25_0:
1144 case WM8962_ADCR_RETUNE_C26_1:
1145 case WM8962_ADCR_RETUNE_C26_0:
1146 case WM8962_ADCR_RETUNE_C27_1:
1147 case WM8962_ADCR_RETUNE_C27_0:
1148 case WM8962_ADCR_RETUNE_C28_1:
1149 case WM8962_ADCR_RETUNE_C28_0:
1150 case WM8962_ADCR_RETUNE_C29_1:
1151 case WM8962_ADCR_RETUNE_C29_0:
1152 case WM8962_ADCR_RETUNE_C30_1:
1153 case WM8962_ADCR_RETUNE_C30_0:
1154 case WM8962_ADCR_RETUNE_C31_1:
1155 case WM8962_ADCR_RETUNE_C31_0:
1156 case WM8962_ADCR_RETUNE_C32_1:
1157 case WM8962_ADCR_RETUNE_C32_0:
1158 case WM8962_DACL_RETUNE_C1_1:
1159 case WM8962_DACL_RETUNE_C1_0:
1160 case WM8962_DACL_RETUNE_C2_1:
1161 case WM8962_DACL_RETUNE_C2_0:
1162 case WM8962_DACL_RETUNE_C3_1:
1163 case WM8962_DACL_RETUNE_C3_0:
1164 case WM8962_DACL_RETUNE_C4_1:
1165 case WM8962_DACL_RETUNE_C4_0:
1166 case WM8962_DACL_RETUNE_C5_1:
1167 case WM8962_DACL_RETUNE_C5_0:
1168 case WM8962_DACL_RETUNE_C6_1:
1169 case WM8962_DACL_RETUNE_C6_0:
1170 case WM8962_DACL_RETUNE_C7_1:
1171 case WM8962_DACL_RETUNE_C7_0:
1172 case WM8962_DACL_RETUNE_C8_1:
1173 case WM8962_DACL_RETUNE_C8_0:
1174 case WM8962_DACL_RETUNE_C9_1:
1175 case WM8962_DACL_RETUNE_C9_0:
1176 case WM8962_DACL_RETUNE_C10_1:
1177 case WM8962_DACL_RETUNE_C10_0:
1178 case WM8962_DACL_RETUNE_C11_1:
1179 case WM8962_DACL_RETUNE_C11_0:
1180 case WM8962_DACL_RETUNE_C12_1:
1181 case WM8962_DACL_RETUNE_C12_0:
1182 case WM8962_DACL_RETUNE_C13_1:
1183 case WM8962_DACL_RETUNE_C13_0:
1184 case WM8962_DACL_RETUNE_C14_1:
1185 case WM8962_DACL_RETUNE_C14_0:
1186 case WM8962_DACL_RETUNE_C15_1:
1187 case WM8962_DACL_RETUNE_C15_0:
1188 case WM8962_DACL_RETUNE_C16_1:
1189 case WM8962_DACL_RETUNE_C16_0:
1190 case WM8962_DACL_RETUNE_C17_1:
1191 case WM8962_DACL_RETUNE_C17_0:
1192 case WM8962_DACL_RETUNE_C18_1:
1193 case WM8962_DACL_RETUNE_C18_0:
1194 case WM8962_DACL_RETUNE_C19_1:
1195 case WM8962_DACL_RETUNE_C19_0:
1196 case WM8962_DACL_RETUNE_C20_1:
1197 case WM8962_DACL_RETUNE_C20_0:
1198 case WM8962_DACL_RETUNE_C21_1:
1199 case WM8962_DACL_RETUNE_C21_0:
1200 case WM8962_DACL_RETUNE_C22_1:
1201 case WM8962_DACL_RETUNE_C22_0:
1202 case WM8962_DACL_RETUNE_C23_1:
1203 case WM8962_DACL_RETUNE_C23_0:
1204 case WM8962_DACL_RETUNE_C24_1:
1205 case WM8962_DACL_RETUNE_C24_0:
1206 case WM8962_DACL_RETUNE_C25_1:
1207 case WM8962_DACL_RETUNE_C25_0:
1208 case WM8962_DACL_RETUNE_C26_1:
1209 case WM8962_DACL_RETUNE_C26_0:
1210 case WM8962_DACL_RETUNE_C27_1:
1211 case WM8962_DACL_RETUNE_C27_0:
1212 case WM8962_DACL_RETUNE_C28_1:
1213 case WM8962_DACL_RETUNE_C28_0:
1214 case WM8962_DACL_RETUNE_C29_1:
1215 case WM8962_DACL_RETUNE_C29_0:
1216 case WM8962_DACL_RETUNE_C30_1:
1217 case WM8962_DACL_RETUNE_C30_0:
1218 case WM8962_DACL_RETUNE_C31_1:
1219 case WM8962_DACL_RETUNE_C31_0:
1220 case WM8962_DACL_RETUNE_C32_1:
1221 case WM8962_DACL_RETUNE_C32_0:
1222 case WM8962_RETUNEDAC_PG2_1:
1223 case WM8962_RETUNEDAC_PG2_0:
1224 case WM8962_RETUNEDAC_PG_1:
1225 case WM8962_RETUNEDAC_PG_0:
1226 case WM8962_DACR_RETUNE_C1_1:
1227 case WM8962_DACR_RETUNE_C1_0:
1228 case WM8962_DACR_RETUNE_C2_1:
1229 case WM8962_DACR_RETUNE_C2_0:
1230 case WM8962_DACR_RETUNE_C3_1:
1231 case WM8962_DACR_RETUNE_C3_0:
1232 case WM8962_DACR_RETUNE_C4_1:
1233 case WM8962_DACR_RETUNE_C4_0:
1234 case WM8962_DACR_RETUNE_C5_1:
1235 case WM8962_DACR_RETUNE_C5_0:
1236 case WM8962_DACR_RETUNE_C6_1:
1237 case WM8962_DACR_RETUNE_C6_0:
1238 case WM8962_DACR_RETUNE_C7_1:
1239 case WM8962_DACR_RETUNE_C7_0:
1240 case WM8962_DACR_RETUNE_C8_1:
1241 case WM8962_DACR_RETUNE_C8_0:
1242 case WM8962_DACR_RETUNE_C9_1:
1243 case WM8962_DACR_RETUNE_C9_0:
1244 case WM8962_DACR_RETUNE_C10_1:
1245 case WM8962_DACR_RETUNE_C10_0:
1246 case WM8962_DACR_RETUNE_C11_1:
1247 case WM8962_DACR_RETUNE_C11_0:
1248 case WM8962_DACR_RETUNE_C12_1:
1249 case WM8962_DACR_RETUNE_C12_0:
1250 case WM8962_DACR_RETUNE_C13_1:
1251 case WM8962_DACR_RETUNE_C13_0:
1252 case WM8962_DACR_RETUNE_C14_1:
1253 case WM8962_DACR_RETUNE_C14_0:
1254 case WM8962_DACR_RETUNE_C15_1:
1255 case WM8962_DACR_RETUNE_C15_0:
1256 case WM8962_DACR_RETUNE_C16_1:
1257 case WM8962_DACR_RETUNE_C16_0:
1258 case WM8962_DACR_RETUNE_C17_1:
1259 case WM8962_DACR_RETUNE_C17_0:
1260 case WM8962_DACR_RETUNE_C18_1:
1261 case WM8962_DACR_RETUNE_C18_0:
1262 case WM8962_DACR_RETUNE_C19_1:
1263 case WM8962_DACR_RETUNE_C19_0:
1264 case WM8962_DACR_RETUNE_C20_1:
1265 case WM8962_DACR_RETUNE_C20_0:
1266 case WM8962_DACR_RETUNE_C21_1:
1267 case WM8962_DACR_RETUNE_C21_0:
1268 case WM8962_DACR_RETUNE_C22_1:
1269 case WM8962_DACR_RETUNE_C22_0:
1270 case WM8962_DACR_RETUNE_C23_1:
1271 case WM8962_DACR_RETUNE_C23_0:
1272 case WM8962_DACR_RETUNE_C24_1:
1273 case WM8962_DACR_RETUNE_C24_0:
1274 case WM8962_DACR_RETUNE_C25_1:
1275 case WM8962_DACR_RETUNE_C25_0:
1276 case WM8962_DACR_RETUNE_C26_1:
1277 case WM8962_DACR_RETUNE_C26_0:
1278 case WM8962_DACR_RETUNE_C27_1:
1279 case WM8962_DACR_RETUNE_C27_0:
1280 case WM8962_DACR_RETUNE_C28_1:
1281 case WM8962_DACR_RETUNE_C28_0:
1282 case WM8962_DACR_RETUNE_C29_1:
1283 case WM8962_DACR_RETUNE_C29_0:
1284 case WM8962_DACR_RETUNE_C30_1:
1285 case WM8962_DACR_RETUNE_C30_0:
1286 case WM8962_DACR_RETUNE_C31_1:
1287 case WM8962_DACR_RETUNE_C31_0:
1288 case WM8962_DACR_RETUNE_C32_1:
1289 case WM8962_DACR_RETUNE_C32_0:
1290 case WM8962_VSS_XHD2_1:
1291 case WM8962_VSS_XHD2_0:
1292 case WM8962_VSS_XHD3_1:
1293 case WM8962_VSS_XHD3_0:
1294 case WM8962_VSS_XHN1_1:
1295 case WM8962_VSS_XHN1_0:
1296 case WM8962_VSS_XHN2_1:
1297 case WM8962_VSS_XHN2_0:
1298 case WM8962_VSS_XHN3_1:
1299 case WM8962_VSS_XHN3_0:
1300 case WM8962_VSS_XLA_1:
1301 case WM8962_VSS_XLA_0:
1302 case WM8962_VSS_XLB_1:
1303 case WM8962_VSS_XLB_0:
1304 case WM8962_VSS_XLG_1:
1305 case WM8962_VSS_XLG_0:
1306 case WM8962_VSS_PG2_1:
1307 case WM8962_VSS_PG2_0:
1308 case WM8962_VSS_PG_1:
1309 case WM8962_VSS_PG_0:
1310 case WM8962_VSS_XTD1_1:
1311 case WM8962_VSS_XTD1_0:
1312 case WM8962_VSS_XTD2_1:
1313 case WM8962_VSS_XTD2_0:
1314 case WM8962_VSS_XTD3_1:
1315 case WM8962_VSS_XTD3_0:
1316 case WM8962_VSS_XTD4_1:
1317 case WM8962_VSS_XTD4_0:
1318 case WM8962_VSS_XTD5_1:
1319 case WM8962_VSS_XTD5_0:
1320 case WM8962_VSS_XTD6_1:
1321 case WM8962_VSS_XTD6_0:
1322 case WM8962_VSS_XTD7_1:
1323 case WM8962_VSS_XTD7_0:
1324 case WM8962_VSS_XTD8_1:
1325 case WM8962_VSS_XTD8_0:
1326 case WM8962_VSS_XTD9_1:
1327 case WM8962_VSS_XTD9_0:
1328 case WM8962_VSS_XTD10_1:
1329 case WM8962_VSS_XTD10_0:
1330 case WM8962_VSS_XTD11_1:
1331 case WM8962_VSS_XTD11_0:
1332 case WM8962_VSS_XTD12_1:
1333 case WM8962_VSS_XTD12_0:
1334 case WM8962_VSS_XTD13_1:
1335 case WM8962_VSS_XTD13_0:
1336 case WM8962_VSS_XTD14_1:
1337 case WM8962_VSS_XTD14_0:
1338 case WM8962_VSS_XTD15_1:
1339 case WM8962_VSS_XTD15_0:
1340 case WM8962_VSS_XTD16_1:
1341 case WM8962_VSS_XTD16_0:
1342 case WM8962_VSS_XTD17_1:
1343 case WM8962_VSS_XTD17_0:
1344 case WM8962_VSS_XTD18_1:
1345 case WM8962_VSS_XTD18_0:
1346 case WM8962_VSS_XTD19_1:
1347 case WM8962_VSS_XTD19_0:
1348 case WM8962_VSS_XTD20_1:
1349 case WM8962_VSS_XTD20_0:
1350 case WM8962_VSS_XTD21_1:
1351 case WM8962_VSS_XTD21_0:
1352 case WM8962_VSS_XTD22_1:
1353 case WM8962_VSS_XTD22_0:
1354 case WM8962_VSS_XTD23_1:
1355 case WM8962_VSS_XTD23_0:
1356 case WM8962_VSS_XTD24_1:
1357 case WM8962_VSS_XTD24_0:
1358 case WM8962_VSS_XTD25_1:
1359 case WM8962_VSS_XTD25_0:
1360 case WM8962_VSS_XTD26_1:
1361 case WM8962_VSS_XTD26_0:
1362 case WM8962_VSS_XTD27_1:
1363 case WM8962_VSS_XTD27_0:
1364 case WM8962_VSS_XTD28_1:
1365 case WM8962_VSS_XTD28_0:
1366 case WM8962_VSS_XTD29_1:
1367 case WM8962_VSS_XTD29_0:
1368 case WM8962_VSS_XTD30_1:
1369 case WM8962_VSS_XTD30_0:
1370 case WM8962_VSS_XTD31_1:
1371 case WM8962_VSS_XTD31_0:
1372 case WM8962_VSS_XTD32_1:
1373 case WM8962_VSS_XTD32_0:
1374 case WM8962_VSS_XTS1_1:
1375 case WM8962_VSS_XTS1_0:
1376 case WM8962_VSS_XTS2_1:
1377 case WM8962_VSS_XTS2_0:
1378 case WM8962_VSS_XTS3_1:
1379 case WM8962_VSS_XTS3_0:
1380 case WM8962_VSS_XTS4_1:
1381 case WM8962_VSS_XTS4_0:
1382 case WM8962_VSS_XTS5_1:
1383 case WM8962_VSS_XTS5_0:
1384 case WM8962_VSS_XTS6_1:
1385 case WM8962_VSS_XTS6_0:
1386 case WM8962_VSS_XTS7_1:
1387 case WM8962_VSS_XTS7_0:
1388 case WM8962_VSS_XTS8_1:
1389 case WM8962_VSS_XTS8_0:
1390 case WM8962_VSS_XTS9_1:
1391 case WM8962_VSS_XTS9_0:
1392 case WM8962_VSS_XTS10_1:
1393 case WM8962_VSS_XTS10_0:
1394 case WM8962_VSS_XTS11_1:
1395 case WM8962_VSS_XTS11_0:
1396 case WM8962_VSS_XTS12_1:
1397 case WM8962_VSS_XTS12_0:
1398 case WM8962_VSS_XTS13_1:
1399 case WM8962_VSS_XTS13_0:
1400 case WM8962_VSS_XTS14_1:
1401 case WM8962_VSS_XTS14_0:
1402 case WM8962_VSS_XTS15_1:
1403 case WM8962_VSS_XTS15_0:
1404 case WM8962_VSS_XTS16_1:
1405 case WM8962_VSS_XTS16_0:
1406 case WM8962_VSS_XTS17_1:
1407 case WM8962_VSS_XTS17_0:
1408 case WM8962_VSS_XTS18_1:
1409 case WM8962_VSS_XTS18_0:
1410 case WM8962_VSS_XTS19_1:
1411 case WM8962_VSS_XTS19_0:
1412 case WM8962_VSS_XTS20_1:
1413 case WM8962_VSS_XTS20_0:
1414 case WM8962_VSS_XTS21_1:
1415 case WM8962_VSS_XTS21_0:
1416 case WM8962_VSS_XTS22_1:
1417 case WM8962_VSS_XTS22_0:
1418 case WM8962_VSS_XTS23_1:
1419 case WM8962_VSS_XTS23_0:
1420 case WM8962_VSS_XTS24_1:
1421 case WM8962_VSS_XTS24_0:
1422 case WM8962_VSS_XTS25_1:
1423 case WM8962_VSS_XTS25_0:
1424 case WM8962_VSS_XTS26_1:
1425 case WM8962_VSS_XTS26_0:
1426 case WM8962_VSS_XTS27_1:
1427 case WM8962_VSS_XTS27_0:
1428 case WM8962_VSS_XTS28_1:
1429 case WM8962_VSS_XTS28_0:
1430 case WM8962_VSS_XTS29_1:
1431 case WM8962_VSS_XTS29_0:
1432 case WM8962_VSS_XTS30_1:
1433 case WM8962_VSS_XTS30_0:
1434 case WM8962_VSS_XTS31_1:
1435 case WM8962_VSS_XTS31_0:
1436 case WM8962_VSS_XTS32_1:
1437 case WM8962_VSS_XTS32_0:
1438 return true;
1439 default:
1440 return false;
1441 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1442}
1443
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1444static int wm8962_reset(struct wm8962_priv *wm8962)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1445{
Mark Brown4f4488a2011-11-01 13:36:10 +0000[diff] [blame]1446 int ret;
1447
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1448 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
Mark Brown4f4488a2011-11-01 13:36:10 +0000[diff] [blame]1449 if (ret != 0)
1450 return ret;
1451
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]1452 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1453}
1454
1455static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1456static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1457static const unsigned int mixinpga_tlv[] = {
Clemens Ladisch43e9dc72011-11-20 15:13:27 +0100[diff] [blame]1458 TLV_DB_RANGE_HEAD(5),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1459 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1460 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1461 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1462 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1463 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
1464};
1465static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1466static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1467static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1468static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1469static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1470static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1471static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1472static const unsigned int classd_tlv[] = {
Clemens Ladisch43e9dc72011-11-20 15:13:27 +0100[diff] [blame]1473 TLV_DB_RANGE_HEAD(2),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1474 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1475 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
1476};
Mark Brown8f63aaa882011-06-07 23:14:37 +0100[diff] [blame]1477static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1478
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1479static int wm8962_dsp2_write_config(struct snd_soc_codec *codec)
1480{
Mark Brown26b427a2012-02-23 20:19:47 +0000[diff] [blame]1481 return regcache_sync_region(codec->control_data,
1482 WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1483}
1484
1485static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val)
1486{
1487 u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME);
1488 u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME);
1489 u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1);
1490
1491 /* Mute the ADCs and DACs */
1492 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0);
1493 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1494 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1495 WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1496
1497 snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val);
1498
1499 /* Restore the ADCs and DACs */
1500 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl);
1501 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr);
1502 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1503 WM8962_DAC_MUTE, dac);
1504
1505 return 0;
1506}
1507
1508static int wm8962_dsp2_start(struct snd_soc_codec *codec)
1509{
1510 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1511
1512 wm8962_dsp2_write_config(codec);
1513
1514 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1515
1516 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1517
1518 return 0;
1519}
1520
1521static int wm8962_dsp2_stop(struct snd_soc_codec *codec)
1522{
1523 wm8962_dsp2_set_enable(codec, 0);
1524
1525 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1526
1527 return 0;
1528}
1529
1530#define WM8962_DSP2_ENABLE(xname, xshift) \
1531{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1532 .info = wm8962_dsp2_ena_info, \
1533 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1534 .private_value = xshift }
1535
1536static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1537 struct snd_ctl_elem_info *uinfo)
1538{
1539 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1540
1541 uinfo->count = 1;
1542 uinfo->value.integer.min = 0;
1543 uinfo->value.integer.max = 1;
1544
1545 return 0;
1546}
1547
1548static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1549 struct snd_ctl_elem_value *ucontrol)
1550{
1551 int shift = kcontrol->private_value;
1552 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1553 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1554
1555 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1556
1557 return 0;
1558}
1559
1560static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1561 struct snd_ctl_elem_value *ucontrol)
1562{
1563 int shift = kcontrol->private_value;
1564 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1565 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1566 int old = wm8962->dsp2_ena;
1567 int ret = 0;
1568 int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) &
1569 WM8962_DSP2_ENA;
1570
1571 mutex_lock(&codec->mutex);
1572
1573 if (ucontrol->value.integer.value[0])
1574 wm8962->dsp2_ena |= 1 << shift;
1575 else
1576 wm8962->dsp2_ena &= ~(1 << shift);
1577
1578 if (wm8962->dsp2_ena == old)
1579 goto out;
1580
1581 ret = 1;
1582
1583 if (dsp2_running) {
1584 if (wm8962->dsp2_ena)
1585 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1586 else
1587 wm8962_dsp2_stop(codec);
1588 }
1589
1590out:
1591 mutex_unlock(&codec->mutex);
1592
1593 return ret;
1594}
1595
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1596/* The VU bits for the headphones are in a different register to the mute
1597 * bits and only take effect on the PGA if it is actually powered.
1598 */
1599static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1600 struct snd_ctl_elem_value *ucontrol)
1601{
1602 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Lars-Peter Clausen7f87e302010-12-28 21:38:01 +0100[diff] [blame]1603 u16 *reg_cache = codec->reg_cache;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1604 int ret;
1605
1606 /* Apply the update (if any) */
1607 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1608 if (ret == 0)
1609 return 0;
1610
1611 /* If the left PGA is enabled hit that VU bit... */
Mark Brown0f82bdf2011-06-07 23:42:04 +0100[diff] [blame]1612 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1613 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
1614 reg_cache[WM8962_HPOUTL_VOLUME]);
1615
1616 /* ...otherwise the right. The VU is stereo. */
Mark Brown0f82bdf2011-06-07 23:42:04 +0100[diff] [blame]1617 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1618 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
1619 reg_cache[WM8962_HPOUTR_VOLUME]);
1620
1621 return 0;
1622}
1623
1624/* The VU bits for the speakers are in a different register to the mute
1625 * bits and only take effect on the PGA if it is actually powered.
1626 */
1627static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1628 struct snd_ctl_elem_value *ucontrol)
1629{
1630 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1631 int ret;
1632
1633 /* Apply the update (if any) */
1634 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1635 if (ret == 0)
1636 return 0;
1637
1638 /* If the left PGA is enabled hit that VU bit... */
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1639 ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1640 if (ret & WM8962_SPKOUTL_PGA_ENA) {
1641 snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
1642 snd_soc_read(codec, WM8962_SPKOUTL_VOLUME));
1643 return 1;
1644 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1645
1646 /* ...otherwise the right. The VU is stereo. */
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1647 if (ret & WM8962_SPKOUTR_PGA_ENA)
1648 snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
1649 snd_soc_read(codec, WM8962_SPKOUTR_VOLUME));
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1650
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1651 return 1;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1652}
1653
Mark Brown6be449e2011-04-26 16:04:37 +0100[diff] [blame]1654static const char *cap_hpf_mode_text[] = {
1655 "Hi-fi", "Application"
1656};
1657
1658static const struct soc_enum cap_hpf_mode =
1659 SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text);
1660
Mark Brown1ab63da2011-08-21 10:54:38 +0100[diff] [blame]1661
1662static const char *cap_lhpf_mode_text[] = {
1663 "LPF", "HPF"
1664};
1665
1666static const struct soc_enum cap_lhpf_mode =
1667 SOC_ENUM_SINGLE(WM8962_LHPF1, 1, 2, cap_lhpf_mode_text);
1668
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1669static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1670SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1671
1672SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1673 mixin_tlv),
1674SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1675 mixinpga_tlv),
1676SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1677 mixin_tlv),
1678
1679SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1680 mixin_tlv),
1681SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1682 mixinpga_tlv),
1683SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1684 mixin_tlv),
1685
1686SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1687 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1688SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1689 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1690SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1691 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1692SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1693 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
Mark Brown6be449e2011-04-26 16:04:37 +0100[diff] [blame]1694SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1695SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1696SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
Mark Brown1ab63da2011-08-21 10:54:38 +0100[diff] [blame]1697SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1698SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1699
1700SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1701 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1702
1703SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1704 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1705SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
Mark Brown5f52ee42012-01-11 16:31:00 -0800[diff] [blame]1706SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1707SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1708
1709SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1710 5, 1, 0),
1711
1712SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1713
1714SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1715 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1716SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1717 snd_soc_get_volsw, wm8962_put_hp_sw),
1718SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1719 7, 1, 0),
1720SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1721 hp_tlv),
1722
1723SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1724 WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1725
1726SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1727 3, 7, 0, bypass_tlv),
1728SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1729 0, 7, 0, bypass_tlv),
1730SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1731 7, 1, 1, inmix_tlv),
1732SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1733 6, 1, 1, inmix_tlv),
1734
1735SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1736 3, 7, 0, bypass_tlv),
1737SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1738 0, 7, 0, bypass_tlv),
1739SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1740 7, 1, 1, inmix_tlv),
1741SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1742 6, 1, 1, inmix_tlv),
1743
1744SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1745 classd_tlv),
Mark Brown8f63aaa882011-06-07 23:14:37 +0100[diff] [blame]1746
1747SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1748SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1749 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1750SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1751 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1752SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1753 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1754SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1755 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1756SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1757 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1758
Mark Brown69e5a392012-02-21 23:21:17 +0000[diff] [blame]1759SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1760SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1761
Mark Brownacf31d42012-02-21 23:24:46 +0000[diff] [blame]1762SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1763SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1764
Mark Brownfd0ca452012-02-21 23:25:05 +0000[diff] [blame]1765SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1766SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1767
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1768WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
Mark Brown5462fcc2012-02-21 23:33:26 +0000[diff] [blame]1769SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1770WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1771WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
Mark Brown93a86be2012-03-06 00:29:37 +0000[diff] [blame]1772SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1773WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
Mark Brown5462fcc2012-02-21 23:33:26 +0000[diff] [blame]1774SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1775};
1776
1777static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1778SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1779SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1780 snd_soc_get_volsw, wm8962_put_spk_sw),
1781SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1782
1783SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1784SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1785 3, 7, 0, bypass_tlv),
1786SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1787 0, 7, 0, bypass_tlv),
1788SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1789 7, 1, 1, inmix_tlv),
1790SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1791 6, 1, 1, inmix_tlv),
1792SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1793 7, 1, 0, inmix_tlv),
1794SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1795 6, 1, 0, inmix_tlv),
1796};
1797
1798static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1799SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1800 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1801SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1802 snd_soc_get_volsw, wm8962_put_spk_sw),
1803SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1804 7, 1, 0),
1805
1806SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1807 WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1808
1809SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1810 3, 7, 0, bypass_tlv),
1811SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1812 0, 7, 0, bypass_tlv),
1813SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1814 7, 1, 1, inmix_tlv),
1815SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1816 6, 1, 1, inmix_tlv),
1817SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1818 7, 1, 0, inmix_tlv),
1819SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1820 6, 1, 0, inmix_tlv),
1821
1822SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1823 3, 7, 0, bypass_tlv),
1824SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1825 0, 7, 0, bypass_tlv),
1826SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1827 7, 1, 1, inmix_tlv),
1828SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1829 6, 1, 1, inmix_tlv),
1830SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1831 5, 1, 0, inmix_tlv),
1832SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1833 4, 1, 0, inmix_tlv),
1834};
1835
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1836static int cp_event(struct snd_soc_dapm_widget *w,
1837 struct snd_kcontrol *kcontrol, int event)
1838{
1839 switch (event) {
1840 case SND_SOC_DAPM_POST_PMU:
1841 msleep(5);
1842 break;
1843
1844 default:
1845 BUG();
1846 return -EINVAL;
1847 }
1848
1849 return 0;
1850}
1851
1852static int hp_event(struct snd_soc_dapm_widget *w,
1853 struct snd_kcontrol *kcontrol, int event)
1854{
1855 struct snd_soc_codec *codec = w->codec;
1856 int timeout;
1857 int reg;
1858 int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1859 WM8962_DCS_STARTUP_DONE_HP1R);
1860
1861 switch (event) {
1862 case SND_SOC_DAPM_POST_PMU:
1863 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1864 WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1865 WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1866 udelay(20);
1867
1868 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1869 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1870 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1871
1872 /* Start the DC servo */
1873 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1874 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1875 WM8962_HP1L_DCS_STARTUP |
1876 WM8962_HP1R_DCS_STARTUP,
1877 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1878 WM8962_HP1L_DCS_STARTUP |
1879 WM8962_HP1R_DCS_STARTUP);
1880
1881 /* Wait for it to complete, should be well under 100ms */
1882 timeout = 0;
1883 do {
1884 msleep(1);
1885 reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
1886 if (reg < 0) {
1887 dev_err(codec->dev,
1888 "Failed to read DCS status: %d\n",
1889 reg);
1890 continue;
1891 }
1892 dev_dbg(codec->dev, "DCS status: %x\n", reg);
1893 } while (++timeout < 200 && (reg & expected) != expected);
1894
1895 if ((reg & expected) != expected)
1896 dev_err(codec->dev, "DC servo timed out\n");
1897 else
1898 dev_dbg(codec->dev, "DC servo complete after %dms\n",
1899 timeout);
1900
1901 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1902 WM8962_HP1L_ENA_OUTP |
1903 WM8962_HP1R_ENA_OUTP,
1904 WM8962_HP1L_ENA_OUTP |
1905 WM8962_HP1R_ENA_OUTP);
1906 udelay(20);
1907
1908 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1909 WM8962_HP1L_RMV_SHORT |
1910 WM8962_HP1R_RMV_SHORT,
1911 WM8962_HP1L_RMV_SHORT |
1912 WM8962_HP1R_RMV_SHORT);
1913 break;
1914
1915 case SND_SOC_DAPM_PRE_PMD:
1916 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1917 WM8962_HP1L_RMV_SHORT |
1918 WM8962_HP1R_RMV_SHORT, 0);
1919
1920 udelay(20);
1921
1922 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1923 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1924 WM8962_HP1L_DCS_STARTUP |
1925 WM8962_HP1R_DCS_STARTUP,
1926 0);
1927
1928 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1929 WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1930 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1931 WM8962_HP1L_ENA_OUTP |
1932 WM8962_HP1R_ENA_OUTP, 0);
1933
1934 break;
1935
1936 default:
1937 BUG();
1938 return -EINVAL;
1939
1940 }
1941
1942 return 0;
1943}
1944
1945/* VU bits for the output PGAs only take effect while the PGA is powered */
1946static int out_pga_event(struct snd_soc_dapm_widget *w,
1947 struct snd_kcontrol *kcontrol, int event)
1948{
1949 struct snd_soc_codec *codec = w->codec;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1950 int reg;
1951
1952 switch (w->shift) {
1953 case WM8962_HPOUTR_PGA_ENA_SHIFT:
1954 reg = WM8962_HPOUTR_VOLUME;
1955 break;
1956 case WM8962_HPOUTL_PGA_ENA_SHIFT:
1957 reg = WM8962_HPOUTL_VOLUME;
1958 break;
1959 case WM8962_SPKOUTR_PGA_ENA_SHIFT:
1960 reg = WM8962_SPKOUTR_VOLUME;
1961 break;
1962 case WM8962_SPKOUTL_PGA_ENA_SHIFT:
1963 reg = WM8962_SPKOUTL_VOLUME;
1964 break;
1965 default:
1966 BUG();
1967 return -EINVAL;
1968 }
1969
1970 switch (event) {
1971 case SND_SOC_DAPM_POST_PMU:
Mark Brown38f3f312011-09-23 21:26:33 +0100[diff] [blame]1972 return snd_soc_write(codec, reg, snd_soc_read(codec, reg));
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]1973 default:
1974 BUG();
1975 return -EINVAL;
1976 }
1977}
1978
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]1979static int dsp2_event(struct snd_soc_dapm_widget *w,
1980 struct snd_kcontrol *kcontrol, int event)
1981{
1982 struct snd_soc_codec *codec = w->codec;
1983 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1984
1985 switch (event) {
1986 case SND_SOC_DAPM_POST_PMU:
1987 if (wm8962->dsp2_ena)
1988 wm8962_dsp2_start(codec);
1989 break;
1990
1991 case SND_SOC_DAPM_PRE_PMD:
1992 if (wm8962->dsp2_ena)
1993 wm8962_dsp2_stop(codec);
1994 break;
1995
1996 default:
1997 BUG();
1998 return -EINVAL;
1999 }
2000
2001 return 0;
2002}
2003
Mark Brown31794bc2012-02-13 22:00:47 -0800[diff] [blame]2004static const char *st_text[] = { "None", "Left", "Right" };
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2005
2006static const struct soc_enum str_enum =
2007 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
2008
2009static const struct snd_kcontrol_new str_mux =
2010 SOC_DAPM_ENUM("Right Sidetone", str_enum);
2011
2012static const struct soc_enum stl_enum =
2013 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
2014
2015static const struct snd_kcontrol_new stl_mux =
2016 SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2017
2018static const char *outmux_text[] = { "DAC", "Mixer" };
2019
2020static const struct soc_enum spkoutr_enum =
2021 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
2022
2023static const struct snd_kcontrol_new spkoutr_mux =
2024 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2025
2026static const struct soc_enum spkoutl_enum =
2027 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
2028
2029static const struct snd_kcontrol_new spkoutl_mux =
2030 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2031
2032static const struct soc_enum hpoutr_enum =
2033 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
2034
2035static const struct snd_kcontrol_new hpoutr_mux =
2036 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2037
2038static const struct soc_enum hpoutl_enum =
2039 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
2040
2041static const struct snd_kcontrol_new hpoutl_mux =
2042 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2043
2044static const struct snd_kcontrol_new inpgal[] = {
2045SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2046SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2047SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2048SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2049};
2050
2051static const struct snd_kcontrol_new inpgar[] = {
2052SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2053SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2054SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2055SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2056};
2057
2058static const struct snd_kcontrol_new mixinl[] = {
2059SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2060SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2061SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2062};
2063
2064static const struct snd_kcontrol_new mixinr[] = {
2065SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2066SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2067SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2068};
2069
2070static const struct snd_kcontrol_new hpmixl[] = {
2071SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2072SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2073SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2074SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2075SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2076SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2077};
2078
2079static const struct snd_kcontrol_new hpmixr[] = {
2080SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2081SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2082SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2083SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2084SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2085SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2086};
2087
2088static const struct snd_kcontrol_new spkmixl[] = {
2089SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2090SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2091SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2092SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2093SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2094SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2095};
2096
2097static const struct snd_kcontrol_new spkmixr[] = {
2098SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2099SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2100SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2101SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2102SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2103SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2104};
2105
2106static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2107SND_SOC_DAPM_INPUT("IN1L"),
2108SND_SOC_DAPM_INPUT("IN1R"),
2109SND_SOC_DAPM_INPUT("IN2L"),
2110SND_SOC_DAPM_INPUT("IN2R"),
2111SND_SOC_DAPM_INPUT("IN3L"),
2112SND_SOC_DAPM_INPUT("IN3R"),
2113SND_SOC_DAPM_INPUT("IN4L"),
2114SND_SOC_DAPM_INPUT("IN4R"),
Mark Brown36c6b542011-11-27 16:24:18 +0000[diff] [blame]2115SND_SOC_DAPM_SIGGEN("Beep"),
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]2116SND_SOC_DAPM_INPUT("DMICDAT"),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2117
Mark Brown086d7f82011-09-23 16:22:48 +0100[diff] [blame]2118SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
Mark Browna4f28c02010-09-29 13:24:35 -0700[diff] [blame]2119
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2120SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
Mark Browna968d9d2012-01-27 19:54:03 +0000[diff] [blame]2121SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2122SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2123 SND_SOC_DAPM_POST_PMU),
2124SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2125SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2126 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2127 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2128SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2129SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2130
2131SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2132 inpgal, ARRAY_SIZE(inpgal)),
2133SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2134 inpgar, ARRAY_SIZE(inpgar)),
2135SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2136 mixinl, ARRAY_SIZE(mixinl)),
2137SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2138 mixinr, ARRAY_SIZE(mixinr)),
2139
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2140SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]2141
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2142SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2143SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2144
2145SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2146SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2147
2148SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2149SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2150
2151SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2152SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2153
2154SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2155 hpmixl, ARRAY_SIZE(hpmixl)),
2156SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2157 hpmixr, ARRAY_SIZE(hpmixr)),
2158
2159SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2160 out_pga_event, SND_SOC_DAPM_POST_PMU),
2161SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2162 out_pga_event, SND_SOC_DAPM_POST_PMU),
2163
2164SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2165 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2166
2167SND_SOC_DAPM_OUTPUT("HPOUTL"),
2168SND_SOC_DAPM_OUTPUT("HPOUTR"),
2169};
2170
2171static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2172SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2173 spkmixl, ARRAY_SIZE(spkmixl)),
2174SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2175 out_pga_event, SND_SOC_DAPM_POST_PMU),
2176SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2177SND_SOC_DAPM_OUTPUT("SPKOUT"),
2178};
2179
2180static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2181SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2182 spkmixl, ARRAY_SIZE(spkmixl)),
2183SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2184 spkmixr, ARRAY_SIZE(spkmixr)),
2185
2186SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2187 out_pga_event, SND_SOC_DAPM_POST_PMU),
2188SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2189 out_pga_event, SND_SOC_DAPM_POST_PMU),
2190
2191SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2192SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2193
2194SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2195SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2196};
2197
2198static const struct snd_soc_dapm_route wm8962_intercon[] = {
2199 { "INPGAL", "IN1L Switch", "IN1L" },
2200 { "INPGAL", "IN2L Switch", "IN2L" },
2201 { "INPGAL", "IN3L Switch", "IN3L" },
2202 { "INPGAL", "IN4L Switch", "IN4L" },
2203
2204 { "INPGAR", "IN1R Switch", "IN1R" },
2205 { "INPGAR", "IN2R Switch", "IN2R" },
2206 { "INPGAR", "IN3R Switch", "IN3R" },
2207 { "INPGAR", "IN4R Switch", "IN4R" },
2208
2209 { "MIXINL", "IN2L Switch", "IN2L" },
2210 { "MIXINL", "IN3L Switch", "IN3L" },
2211 { "MIXINL", "PGA Switch", "INPGAL" },
2212
2213 { "MIXINR", "IN2R Switch", "IN2R" },
2214 { "MIXINR", "IN3R Switch", "IN3R" },
2215 { "MIXINR", "PGA Switch", "INPGAR" },
2216
Mark Brown821f4202010-09-21 17:53:38 +0100[diff] [blame]2217 { "MICBIAS", NULL, "SYSCLK" },
2218
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2219 { "DMIC_ENA", NULL, "DMICDAT" },
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]2220
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2221 { "ADCL", NULL, "SYSCLK" },
2222 { "ADCL", NULL, "TOCLK" },
2223 { "ADCL", NULL, "MIXINL" },
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2224 { "ADCL", NULL, "DMIC_ENA" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2225 { "ADCL", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2226
2227 { "ADCR", NULL, "SYSCLK" },
2228 { "ADCR", NULL, "TOCLK" },
2229 { "ADCR", NULL, "MIXINR" },
Mark Brown3f7d55a2011-09-23 16:39:31 +0100[diff] [blame]2230 { "ADCR", NULL, "DMIC_ENA" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2231 { "ADCR", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2232
2233 { "STL", "Left", "ADCL" },
2234 { "STL", "Right", "ADCR" },
Mark Brown1355ab12012-03-01 16:40:51 +0000[diff] [blame]2235 { "STL", NULL, "Class G" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2236
2237 { "STR", "Left", "ADCL" },
2238 { "STR", "Right", "ADCR" },
Mark Brown1355ab12012-03-01 16:40:51 +0000[diff] [blame]2239 { "STR", NULL, "Class G" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2240
2241 { "DACL", NULL, "SYSCLK" },
2242 { "DACL", NULL, "TOCLK" },
2243 { "DACL", NULL, "Beep" },
2244 { "DACL", NULL, "STL" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2245 { "DACL", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2246
2247 { "DACR", NULL, "SYSCLK" },
2248 { "DACR", NULL, "TOCLK" },
2249 { "DACR", NULL, "Beep" },
2250 { "DACR", NULL, "STR" },
Mark Brown6f88a4e2011-08-17 10:03:51 +0900[diff] [blame]2251 { "DACR", NULL, "DSP2" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2252
2253 { "HPMIXL", "IN4L Switch", "IN4L" },
2254 { "HPMIXL", "IN4R Switch", "IN4R" },
2255 { "HPMIXL", "DACL Switch", "DACL" },
2256 { "HPMIXL", "DACR Switch", "DACR" },
2257 { "HPMIXL", "MIXINL Switch", "MIXINL" },
2258 { "HPMIXL", "MIXINR Switch", "MIXINR" },
2259
2260 { "HPMIXR", "IN4L Switch", "IN4L" },
2261 { "HPMIXR", "IN4R Switch", "IN4R" },
2262 { "HPMIXR", "DACL Switch", "DACL" },
2263 { "HPMIXR", "DACR Switch", "DACR" },
2264 { "HPMIXR", "MIXINL Switch", "MIXINL" },
2265 { "HPMIXR", "MIXINR Switch", "MIXINR" },
2266
2267 { "Left Bypass", NULL, "HPMIXL" },
2268 { "Left Bypass", NULL, "Class G" },
2269
2270 { "Right Bypass", NULL, "HPMIXR" },
2271 { "Right Bypass", NULL, "Class G" },
2272
2273 { "HPOUTL PGA", "Mixer", "Left Bypass" },
2274 { "HPOUTL PGA", "DAC", "DACL" },
2275
2276 { "HPOUTR PGA", "Mixer", "Right Bypass" },
2277 { "HPOUTR PGA", "DAC", "DACR" },
2278
2279 { "HPOUT", NULL, "HPOUTL PGA" },
2280 { "HPOUT", NULL, "HPOUTR PGA" },
2281 { "HPOUT", NULL, "Charge Pump" },
2282 { "HPOUT", NULL, "SYSCLK" },
2283 { "HPOUT", NULL, "TOCLK" },
2284
2285 { "HPOUTL", NULL, "HPOUT" },
2286 { "HPOUTR", NULL, "HPOUT" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2287
2288 { "HPOUTL", NULL, "TEMP_HP" },
2289 { "HPOUTR", NULL, "TEMP_HP" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2290};
2291
2292static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2293 { "Speaker Mixer", "IN4L Switch", "IN4L" },
2294 { "Speaker Mixer", "IN4R Switch", "IN4R" },
2295 { "Speaker Mixer", "DACL Switch", "DACL" },
2296 { "Speaker Mixer", "DACR Switch", "DACR" },
2297 { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2298 { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2299
2300 { "Speaker PGA", "Mixer", "Speaker Mixer" },
2301 { "Speaker PGA", "DAC", "DACL" },
2302
2303 { "Speaker Output", NULL, "Speaker PGA" },
2304 { "Speaker Output", NULL, "SYSCLK" },
2305 { "Speaker Output", NULL, "TOCLK" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2306 { "Speaker Output", NULL, "TEMP_SPK" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2307
2308 { "SPKOUT", NULL, "Speaker Output" },
2309};
2310
2311static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2312 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2313 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2314 { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2315 { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2316 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2317 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2318
2319 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2320 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2321 { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2322 { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2323 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2324 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2325
2326 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2327 { "SPKOUTL PGA", "DAC", "DACL" },
2328
2329 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2330 { "SPKOUTR PGA", "DAC", "DACR" },
2331
2332 { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2333 { "SPKOUTL Output", NULL, "SYSCLK" },
2334 { "SPKOUTL Output", NULL, "TOCLK" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2335 { "SPKOUTL Output", NULL, "TEMP_SPK" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2336
2337 { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2338 { "SPKOUTR Output", NULL, "SYSCLK" },
2339 { "SPKOUTR Output", NULL, "TOCLK" },
Mark Brown94b88e62011-11-04 17:48:28 +0000[diff] [blame]2340 { "SPKOUTR Output", NULL, "TEMP_SPK" },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2341
2342 { "SPKOUTL", NULL, "SPKOUTL Output" },
2343 { "SPKOUTR", NULL, "SPKOUTR Output" },
2344};
2345
2346static int wm8962_add_widgets(struct snd_soc_codec *codec)
2347{
2348 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2349 struct snd_soc_dapm_context *dapm = &codec->dapm;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2350
Liam Girdwood022658b2012-02-03 17:43:09 +0000[diff] [blame]2351 snd_soc_add_codec_controls(codec, wm8962_snd_controls,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2352 ARRAY_SIZE(wm8962_snd_controls));
2353 if (pdata && pdata->spk_mono)
Liam Girdwood022658b2012-02-03 17:43:09 +0000[diff] [blame]2354 snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2355 ARRAY_SIZE(wm8962_spk_mono_controls));
2356 else
Liam Girdwood022658b2012-02-03 17:43:09 +0000[diff] [blame]2357 snd_soc_add_codec_controls(codec, wm8962_spk_stereo_controls,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2358 ARRAY_SIZE(wm8962_spk_stereo_controls));
2359
2360
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2361 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2362 ARRAY_SIZE(wm8962_dapm_widgets));
2363 if (pdata && pdata->spk_mono)
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2364 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2365 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2366 else
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2367 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2368 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2369
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2370 snd_soc_dapm_add_routes(dapm, wm8962_intercon,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2371 ARRAY_SIZE(wm8962_intercon));
2372 if (pdata && pdata->spk_mono)
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2373 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2374 ARRAY_SIZE(wm8962_spk_mono_intercon));
2375 else
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2376 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2377 ARRAY_SIZE(wm8962_spk_stereo_intercon));
2378
2379
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2380 snd_soc_dapm_disable_pin(dapm, "Beep");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2381
2382 return 0;
2383}
2384
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2385/* -1 for reserved values */
2386static const int bclk_divs[] = {
2387 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2388};
2389
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2390static const int sysclk_rates[] = {
Mark Brown07fabd12012-02-16 00:19:47 -0800[diff] [blame]2391 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2392};
2393
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2394static void wm8962_configure_bclk(struct snd_soc_codec *codec)
2395{
2396 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2397 int dspclk, i;
2398 int clocking2 = 0;
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2399 int clocking4 = 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2400 int aif2 = 0;
2401
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2402 if (!wm8962->sysclk_rate) {
2403 dev_dbg(codec->dev, "No SYSCLK configured\n");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2404 return;
2405 }
2406
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2407 if (!wm8962->bclk || !wm8962->lrclk) {
2408 dev_dbg(codec->dev, "No audio clocks configured\n");
2409 return;
2410 }
2411
2412 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2413 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2414 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2415 break;
2416 }
2417 }
2418
2419 if (i == ARRAY_SIZE(sysclk_rates)) {
2420 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
2421 wm8962->sysclk_rate / wm8962->lrclk);
2422 return;
2423 }
2424
Mark Browneeba1f82012-02-16 00:19:30 -0800[diff] [blame]2425 dev_dbg(codec->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2426
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2427 snd_soc_update_bits(codec, WM8962_CLOCKING_4,
2428 WM8962_SYSCLK_RATE_MASK, clocking4);
2429
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2430 dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
2431 if (dspclk < 0) {
2432 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
2433 return;
2434 }
2435
2436 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2437 switch (dspclk) {
2438 case 0:
2439 dspclk = wm8962->sysclk_rate;
2440 break;
2441 case 1:
2442 dspclk = wm8962->sysclk_rate / 2;
2443 break;
2444 case 2:
2445 dspclk = wm8962->sysclk_rate / 4;
2446 break;
2447 default:
2448 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2449 dspclk = wm8962->sysclk;
2450 }
2451
2452 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2453
2454 /* We're expecting an exact match */
2455 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2456 if (bclk_divs[i] < 0)
2457 continue;
2458
2459 if (dspclk / bclk_divs[i] == wm8962->bclk) {
2460 dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
2461 bclk_divs[i], wm8962->bclk);
2462 clocking2 |= i;
2463 break;
2464 }
2465 }
2466 if (i == ARRAY_SIZE(bclk_divs)) {
2467 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
2468 dspclk / wm8962->bclk);
2469 return;
2470 }
2471
2472 aif2 |= wm8962->bclk / wm8962->lrclk;
2473 dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
2474 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2475
2476 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2477 WM8962_BCLK_DIV_MASK, clocking2);
2478 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
2479 WM8962_AIF_RATE_MASK, aif2);
2480}
2481
2482static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2483 enum snd_soc_bias_level level)
2484{
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2485 if (level == codec->dapm.bias_level)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2486 return 0;
2487
2488 switch (level) {
2489 case SND_SOC_BIAS_ON:
2490 break;
2491
2492 case SND_SOC_BIAS_PREPARE:
2493 /* VMID 2*50k */
2494 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2495 WM8962_VMID_SEL_MASK, 0x80);
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2496
2497 wm8962_configure_bclk(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2498 break;
2499
2500 case SND_SOC_BIAS_STANDBY:
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2501 /* VMID 2*250k */
2502 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2503 WM8962_VMID_SEL_MASK, 0x100);
Mark Brown9d40e552012-07-30 18:24:19 +0100[diff] [blame]2504
2505 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2506 msleep(100);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2507 break;
2508
2509 case SND_SOC_BIAS_OFF:
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2510 break;
2511 }
Mark Brownd23031a42012-02-01 12:48:59 +0000[diff] [blame]2512
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]2513 codec->dapm.bias_level = level;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2514 return 0;
2515}
2516
2517static const struct {
2518 int rate;
2519 int reg;
2520} sr_vals[] = {
2521 { 48000, 0 },
2522 { 44100, 0 },
2523 { 32000, 1 },
2524 { 22050, 2 },
2525 { 24000, 2 },
2526 { 16000, 3 },
2527 { 11025, 4 },
2528 { 12000, 4 },
2529 { 8000, 5 },
2530 { 88200, 6 },
2531 { 96000, 6 },
2532};
2533
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2534static int wm8962_hw_params(struct snd_pcm_substream *substream,
2535 struct snd_pcm_hw_params *params,
2536 struct snd_soc_dai *dai)
2537{
Mark Browne6968a12012-04-04 15:58:16 +0100[diff] [blame]2538 struct snd_soc_codec *codec = dai->codec;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2539 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2540 int i;
2541 int aif0 = 0;
2542 int adctl3 = 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2543
2544 wm8962->bclk = snd_soc_params_to_bclk(params);
Mark Brown4c6c0b52012-02-08 19:02:24 +0000[diff] [blame]2545 if (params_channels(params) == 1)
2546 wm8962->bclk *= 2;
2547
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2548 wm8962->lrclk = params_rate(params);
2549
2550 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2551 if (sr_vals[i].rate == wm8962->lrclk) {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2552 adctl3 |= sr_vals[i].reg;
2553 break;
2554 }
2555 }
2556 if (i == ARRAY_SIZE(sr_vals)) {
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2557 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2558 return -EINVAL;
2559 }
2560
Mark Brown417ceff2011-06-08 14:44:06 +0100[diff] [blame]2561 if (wm8962->lrclk % 8000 == 0)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2562 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2563
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2564 switch (params_format(params)) {
2565 case SNDRV_PCM_FORMAT_S16_LE:
2566 break;
2567 case SNDRV_PCM_FORMAT_S20_3LE:
Susan Gao2b6712b2012-01-30 13:57:04 -0800[diff] [blame]2568 aif0 |= 0x4;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2569 break;
2570 case SNDRV_PCM_FORMAT_S24_LE:
Susan Gao2b6712b2012-01-30 13:57:04 -0800[diff] [blame]2571 aif0 |= 0x8;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2572 break;
2573 case SNDRV_PCM_FORMAT_S32_LE:
Susan Gao2b6712b2012-01-30 13:57:04 -0800[diff] [blame]2574 aif0 |= 0xc;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2575 break;
2576 default:
2577 return -EINVAL;
2578 }
2579
2580 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2581 WM8962_WL_MASK, aif0);
2582 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
2583 WM8962_SAMPLE_RATE_INT_MODE |
2584 WM8962_SAMPLE_RATE_MASK, adctl3);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2585
Mark Brown081413f2012-07-02 18:19:58 +0100[diff] [blame]2586 dev_dbg(codec->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
2587 wm8962->bclk, wm8962->lrclk);
2588
Mark Brown19935022012-02-16 00:46:44 -0800[diff] [blame]2589 if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
2590 wm8962_configure_bclk(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2591
2592 return 0;
2593}
2594
2595static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2596 unsigned int freq, int dir)
2597{
2598 struct snd_soc_codec *codec = dai->codec;
2599 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2600 int src;
2601
2602 switch (clk_id) {
2603 case WM8962_SYSCLK_MCLK:
2604 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2605 src = 0;
2606 break;
2607 case WM8962_SYSCLK_FLL:
2608 wm8962->sysclk = WM8962_SYSCLK_FLL;
2609 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2610 break;
2611 default:
2612 return -EINVAL;
2613 }
2614
2615 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2616 src);
2617
2618 wm8962->sysclk_rate = freq;
2619
Mark Brown71de4d22012-02-16 22:26:23 -0800[diff] [blame]2620 wm8962_configure_bclk(codec);
2621
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2622 return 0;
2623}
2624
2625static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2626{
2627 struct snd_soc_codec *codec = dai->codec;
2628 int aif0 = 0;
2629
2630 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2631 case SND_SOC_DAIFMT_DSP_B:
Susan Gaofbc7c622011-09-29 11:08:18 +0100[diff] [blame]2632 aif0 |= WM8962_LRCLK_INV | 3;
2633 case SND_SOC_DAIFMT_DSP_A:
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2634 aif0 |= 3;
2635
2636 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2637 case SND_SOC_DAIFMT_NB_NF:
2638 case SND_SOC_DAIFMT_IB_NF:
2639 break;
2640 default:
2641 return -EINVAL;
2642 }
2643 break;
2644
2645 case SND_SOC_DAIFMT_RIGHT_J:
2646 break;
2647 case SND_SOC_DAIFMT_LEFT_J:
2648 aif0 |= 1;
2649 break;
2650 case SND_SOC_DAIFMT_I2S:
2651 aif0 |= 2;
2652 break;
2653 default:
2654 return -EINVAL;
2655 }
2656
2657 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2658 case SND_SOC_DAIFMT_NB_NF:
2659 break;
2660 case SND_SOC_DAIFMT_IB_NF:
2661 aif0 |= WM8962_BCLK_INV;
2662 break;
2663 case SND_SOC_DAIFMT_NB_IF:
2664 aif0 |= WM8962_LRCLK_INV;
2665 break;
2666 case SND_SOC_DAIFMT_IB_IF:
2667 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2668 break;
2669 default:
2670 return -EINVAL;
2671 }
2672
2673 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2674 case SND_SOC_DAIFMT_CBM_CFM:
2675 aif0 |= WM8962_MSTR;
2676 break;
2677 case SND_SOC_DAIFMT_CBS_CFS:
2678 break;
2679 default:
2680 return -EINVAL;
2681 }
2682
2683 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2684 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2685 WM8962_LRCLK_INV, aif0);
2686
2687 return 0;
2688}
2689
2690struct _fll_div {
2691 u16 fll_fratio;
2692 u16 fll_outdiv;
2693 u16 fll_refclk_div;
2694 u16 n;
2695 u16 theta;
2696 u16 lambda;
2697};
2698
2699/* The size in bits of the FLL divide multiplied by 10
2700 * to allow rounding later */
2701#define FIXED_FLL_SIZE ((1 << 16) * 10)
2702
2703static struct {
2704 unsigned int min;
2705 unsigned int max;
2706 u16 fll_fratio;
2707 int ratio;
2708} fll_fratios[] = {
2709 { 0, 64000, 4, 16 },
2710 { 64000, 128000, 3, 8 },
2711 { 128000, 256000, 2, 4 },
2712 { 256000, 1000000, 1, 2 },
2713 { 1000000, 13500000, 0, 1 },
2714};
2715
2716static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2717 unsigned int Fout)
2718{
2719 unsigned int target;
2720 unsigned int div;
2721 unsigned int fratio, gcd_fll;
2722 int i;
2723
2724 /* Fref must be <=13.5MHz */
2725 div = 1;
2726 fll_div->fll_refclk_div = 0;
2727 while ((Fref / div) > 13500000) {
2728 div *= 2;
2729 fll_div->fll_refclk_div++;
2730
2731 if (div > 4) {
2732 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2733 Fref);
2734 return -EINVAL;
2735 }
2736 }
2737
2738 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2739
2740 /* Apply the division for our remaining calculations */
2741 Fref /= div;
2742
2743 /* Fvco should be 90-100MHz; don't check the upper bound */
2744 div = 2;
2745 while (Fout * div < 90000000) {
2746 div++;
2747 if (div > 64) {
2748 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2749 Fout);
2750 return -EINVAL;
2751 }
2752 }
2753 target = Fout * div;
2754 fll_div->fll_outdiv = div - 1;
2755
2756 pr_debug("FLL Fvco=%dHz\n", target);
2757
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]2758 /* Find an appropriate FLL_FRATIO and factor it out of the target */
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2759 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2760 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2761 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2762 fratio = fll_fratios[i].ratio;
2763 break;
2764 }
2765 }
2766 if (i == ARRAY_SIZE(fll_fratios)) {
2767 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2768 return -EINVAL;
2769 }
2770
2771 fll_div->n = target / (fratio * Fref);
2772
2773 if (target % Fref == 0) {
2774 fll_div->theta = 0;
2775 fll_div->lambda = 0;
2776 } else {
2777 gcd_fll = gcd(target, fratio * Fref);
2778
2779 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2780 / gcd_fll;
2781 fll_div->lambda = (fratio * Fref) / gcd_fll;
2782 }
2783
2784 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2785 fll_div->n, fll_div->theta, fll_div->lambda);
2786 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2787 fll_div->fll_fratio, fll_div->fll_outdiv,
2788 fll_div->fll_refclk_div);
2789
2790 return 0;
2791}
2792
Mark Brown92a43522011-04-25 18:44:01 +0100[diff] [blame]2793static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2794 unsigned int Fref, unsigned int Fout)
2795{
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2796 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2797 struct _fll_div fll_div;
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]2798 unsigned long timeout;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2799 int ret;
Mark Browna968d9d2012-01-27 19:54:03 +0000[diff] [blame]2800 int fll1 = 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2801
2802 /* Any change? */
2803 if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2804 Fout == wm8962->fll_fout)
2805 return 0;
2806
2807 if (Fout == 0) {
2808 dev_dbg(codec->dev, "FLL disabled\n");
2809
2810 wm8962->fll_fref = 0;
2811 wm8962->fll_fout = 0;
2812
2813 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2814 WM8962_FLL_ENA, 0);
2815
Mark Brownd23031a42012-02-01 12:48:59 +0000[diff] [blame]2816 pm_runtime_put(codec->dev);
2817
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2818 return 0;
2819 }
2820
2821 ret = fll_factors(&fll_div, Fref, Fout);
2822 if (ret != 0)
2823 return ret;
2824
Mark Browna968d9d2012-01-27 19:54:03 +0000[diff] [blame]2825 /* Parameters good, disable so we can reprogram */
2826 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2827
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2828 switch (fll_id) {
2829 case WM8962_FLL_MCLK:
2830 case WM8962_FLL_BCLK:
2831 case WM8962_FLL_OSC:
2832 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2833 break;
2834 case WM8962_FLL_INT:
2835 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2836 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2837 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
2838 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2839 break;
2840 default:
2841 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2842 return -EINVAL;
2843 }
2844
2845 if (fll_div.theta || fll_div.lambda)
2846 fll1 |= WM8962_FLL_FRAC;
2847
2848 /* Stop the FLL while we reconfigure */
2849 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2850
2851 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
2852 WM8962_FLL_OUTDIV_MASK |
2853 WM8962_FLL_REFCLK_DIV_MASK,
2854 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2855 (fll_div.fll_refclk_div));
2856
2857 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
2858 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2859
2860 snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
2861 snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
2862 snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
2863
Mark Brown4df0cb22011-08-21 17:18:52 +0100[diff] [blame]2864 try_wait_for_completion(&wm8962->fll_lock);
2865
Mark Brownd23031a42012-02-01 12:48:59 +0000[diff] [blame]2866 pm_runtime_get_sync(codec->dev);
Mark Brown2a761cd2011-11-01 15:19:23 +0000[diff] [blame]2867
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2868 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2869 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
Mark Browna968d9d2012-01-27 19:54:03 +0000[diff] [blame]2870 WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2871
2872 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2873
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]2874 ret = 0;
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]2875
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]2876 if (fll1 & WM8962_FLL_ENA) {
2877 /* This should be a massive overestimate but go even
2878 * higher if we'll error out
2879 */
2880 if (wm8962->irq)
2881 timeout = msecs_to_jiffies(5);
2882 else
2883 timeout = msecs_to_jiffies(1);
2884
2885 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2886 timeout);
2887
2888 if (timeout == 0 && wm8962->irq) {
2889 dev_err(codec->dev, "FLL lock timed out");
2890 ret = -ETIMEDOUT;
2891 }
2892 }
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]2893
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2894 wm8962->fll_fref = Fref;
2895 wm8962->fll_fout = Fout;
2896 wm8962->fll_src = source;
2897
Mark Brown649a1a02011-06-07 23:16:29 +0100[diff] [blame]2898 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2899}
2900
2901static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2902{
2903 struct snd_soc_codec *codec = dai->codec;
2904 int val;
2905
2906 if (mute)
2907 val = WM8962_DAC_MUTE;
2908 else
2909 val = 0;
2910
2911 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
2912 WM8962_DAC_MUTE, val);
2913}
2914
2915#define WM8962_RATES SNDRV_PCM_RATE_8000_96000
2916
2917#define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2918 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2919
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100[diff] [blame]2920static const struct snd_soc_dai_ops wm8962_dai_ops = {
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2921 .hw_params = wm8962_hw_params,
2922 .set_sysclk = wm8962_set_dai_sysclk,
2923 .set_fmt = wm8962_set_dai_fmt,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2924 .digital_mute = wm8962_mute,
2925};
2926
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]2927static struct snd_soc_dai_driver wm8962_dai = {
2928 .name = "wm8962",
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2929 .playback = {
2930 .stream_name = "Playback",
Mark Brown4c6c0b52012-02-08 19:02:24 +0000[diff] [blame]2931 .channels_min = 1,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2932 .channels_max = 2,
2933 .rates = WM8962_RATES,
2934 .formats = WM8962_FORMATS,
2935 },
2936 .capture = {
2937 .stream_name = "Capture",
Mark Brown4c6c0b52012-02-08 19:02:24 +0000[diff] [blame]2938 .channels_min = 1,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2939 .channels_max = 2,
2940 .rates = WM8962_RATES,
2941 .formats = WM8962_FORMATS,
2942 },
2943 .ops = &wm8962_dai_ops,
2944 .symmetric_rates = 1,
2945};
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]2946
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]2947static void wm8962_mic_work(struct work_struct *work)
2948{
2949 struct wm8962_priv *wm8962 = container_of(work,
2950 struct wm8962_priv,
2951 mic_work.work);
2952 struct snd_soc_codec *codec = wm8962->codec;
2953 int status = 0;
2954 int irq_pol = 0;
2955 int reg;
2956
2957 reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
2958
2959 if (reg & WM8962_MICDET_STS) {
2960 status |= SND_JACK_MICROPHONE;
2961 irq_pol |= WM8962_MICD_IRQ_POL;
2962 }
2963
2964 if (reg & WM8962_MICSHORT_STS) {
2965 status |= SND_JACK_BTN_0;
2966 irq_pol |= WM8962_MICSCD_IRQ_POL;
2967 }
2968
2969 snd_soc_jack_report(wm8962->jack, status,
2970 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
2971
2972 snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
2973 WM8962_MICSCD_IRQ_POL |
2974 WM8962_MICD_IRQ_POL, irq_pol);
2975}
2976
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]2977static irqreturn_t wm8962_irq(int irq, void *data)
2978{
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]2979 struct device *dev = data;
2980 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
2981 unsigned int mask;
2982 unsigned int active;
2983 int reg, ret;
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]2984
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]2985 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
2986 &mask);
2987 if (ret != 0) {
2988 dev_err(dev, "Failed to read interrupt mask: %d\n",
2989 ret);
2990 return IRQ_NONE;
2991 }
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]2992
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]2993 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
2994 if (ret != 0) {
2995 dev_err(dev, "Failed to read interrupt: %d\n", ret);
2996 return IRQ_NONE;
2997 }
2998
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]2999 active &= ~mask;
3000
Mark Browne6ef5872011-08-21 11:47:14 +0100[diff] [blame]3001 if (!active)
3002 return IRQ_NONE;
3003
Mark Brown3198b9e2011-07-20 13:50:10 +0100[diff] [blame]3004 /* Acknowledge the interrupts */
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3005 ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
3006 if (ret != 0)
3007 dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
Mark Brown3198b9e2011-07-20 13:50:10 +0100[diff] [blame]3008
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3009 if (active & WM8962_FLL_LOCK_EINT) {
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3010 dev_dbg(dev, "FLL locked\n");
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3011 complete(&wm8962->fll_lock);
3012 }
3013
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3014 if (active & WM8962_FIFOS_ERR_EINT)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3015 dev_err(dev, "FIFO error\n");
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3016
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3017 if (active & WM8962_TEMP_SHUT_EINT) {
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3018 dev_crit(dev, "Thermal shutdown\n");
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3019
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3020 ret = regmap_read(wm8962->regmap,
3021 WM8962_THERMAL_SHUTDOWN_STATUS, &reg);
3022 if (ret != 0) {
3023 dev_warn(dev, "Failed to read thermal status: %d\n",
3024 ret);
3025 reg = 0;
3026 }
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3027
3028 if (reg & WM8962_TEMP_ERR_HP)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3029 dev_crit(dev, "Headphone thermal error\n");
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3030 if (reg & WM8962_TEMP_WARN_HP)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3031 dev_crit(dev, "Headphone thermal warning\n");
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3032 if (reg & WM8962_TEMP_ERR_SPK)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3033 dev_crit(dev, "Speaker thermal error\n");
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3034 if (reg & WM8962_TEMP_WARN_SPK)
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3035 dev_crit(dev, "Speaker thermal warning\n");
Mark Brownfbf04072011-08-21 18:07:44 +0100[diff] [blame]3036 }
3037
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3038 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3039 dev_dbg(dev, "Microphone event detected\n");
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3040
Mark Brown6dc47e92010-12-28 02:14:25 +0000[diff] [blame]3041#ifndef CONFIG_SND_SOC_WM8962_MODULE
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3042 trace_snd_soc_jack_irq(dev_name(dev));
Mark Brown1435b942010-12-23 01:56:20 +0000[diff] [blame]3043#endif
Mark Brown2bbb5d62010-12-05 12:50:12 +0000[diff] [blame]3044
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3045 pm_wakeup_event(dev, 300);
Mark Brown11e16eb2010-11-03 14:45:07 -0400[diff] [blame]3046
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3047 schedule_delayed_work(&wm8962->mic_work,
3048 msecs_to_jiffies(250));
3049 }
3050
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3051 return IRQ_HANDLED;
3052}
3053
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3054/**
3055 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
3056 *
3057 * @codec: WM8962 codec
3058 * @jack: jack to report detection events on
3059 *
3060 * Enable microphone detection via IRQ on the WM8962. If GPIOs are
3061 * being used to bring out signals to the processor then only platform
3062 * data configuration is needed for WM8962 and processor GPIOs should
3063 * be configured using snd_soc_jack_add_gpios() instead.
3064 *
3065 * If no jack is supplied detection will be disabled.
3066 */
3067int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3068{
3069 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3070 int irq_mask, enable;
3071
3072 wm8962->jack = jack;
3073 if (jack) {
3074 irq_mask = 0;
3075 enable = WM8962_MICDET_ENA;
3076 } else {
3077 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3078 enable = 0;
3079 }
3080
3081 snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
3082 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3083 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3084 WM8962_MICDET_ENA, enable);
3085
3086 /* Send an initial empty report */
3087 snd_soc_jack_report(wm8962->jack, 0,
3088 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3089
Mark Browna5ef9882011-11-01 16:00:15 +0000[diff] [blame]3090 if (jack) {
Mark Browndb0e5542011-11-01 15:59:03 +0000[diff] [blame]3091 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
Mark Browna5ef9882011-11-01 16:00:15 +0000[diff] [blame]3092 snd_soc_dapm_force_enable_pin(&codec->dapm, "MICBIAS");
Mark Brown00ae3b82011-11-01 16:02:01 +0000[diff] [blame]3093 } else {
3094 snd_soc_dapm_disable_pin(&codec->dapm, "SYSCLK");
3095 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS");
Mark Browna5ef9882011-11-01 16:00:15 +0000[diff] [blame]3096 }
Mark Browndb0e5542011-11-01 15:59:03 +0000[diff] [blame]3097
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3098 return 0;
3099}
3100EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3101
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3102#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
3103static int beep_rates[] = {
3104 500, 1000, 2000, 4000,
3105};
3106
3107static void wm8962_beep_work(struct work_struct *work)
3108{
3109 struct wm8962_priv *wm8962 =
3110 container_of(work, struct wm8962_priv, beep_work);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3111 struct snd_soc_codec *codec = wm8962->codec;
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3112 struct snd_soc_dapm_context *dapm = &codec->dapm;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3113 int i;
3114 int reg = 0;
3115 int best = 0;
3116
3117 if (wm8962->beep_rate) {
3118 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3119 if (abs(wm8962->beep_rate - beep_rates[i]) <
3120 abs(wm8962->beep_rate - beep_rates[best]))
3121 best = i;
3122 }
3123
3124 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
3125 beep_rates[best], wm8962->beep_rate);
3126
3127 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3128
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3129 snd_soc_dapm_enable_pin(dapm, "Beep");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3130 } else {
3131 dev_dbg(codec->dev, "Disabling beep\n");
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3132 snd_soc_dapm_disable_pin(dapm, "Beep");
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3133 }
3134
3135 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3136 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3137
Liam Girdwoodce6120c2010-11-05 15:53:46 +0200[diff] [blame]3138 snd_soc_dapm_sync(dapm);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3139}
3140
3141/* For usability define a way of injecting beep events for the device -
3142 * many systems will not have a keyboard.
3143 */
3144static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3145 unsigned int code, int hz)
3146{
3147 struct snd_soc_codec *codec = input_get_drvdata(dev);
3148 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3149
3150 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
3151
3152 switch (code) {
3153 case SND_BELL:
3154 if (hz)
3155 hz = 1000;
3156 case SND_TONE:
3157 break;
3158 default:
3159 return -1;
3160 }
3161
3162 /* Kick the beep from a workqueue */
3163 wm8962->beep_rate = hz;
3164 schedule_work(&wm8962->beep_work);
3165 return 0;
3166}
3167
3168static ssize_t wm8962_beep_set(struct device *dev,
3169 struct device_attribute *attr,
3170 const char *buf, size_t count)
3171{
3172 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3173 long int time;
Mark Brown74a557e2010-11-03 09:37:06 -0400[diff] [blame]3174 int ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3175
Mark Brown74a557e2010-11-03 09:37:06 -0400[diff] [blame]3176 ret = strict_strtol(buf, 10, &time);
3177 if (ret != 0)
3178 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3179
3180 input_event(wm8962->beep, EV_SND, SND_TONE, time);
3181
3182 return count;
3183}
3184
3185static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3186
3187static void wm8962_init_beep(struct snd_soc_codec *codec)
3188{
3189 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3190 int ret;
3191
3192 wm8962->beep = input_allocate_device();
3193 if (!wm8962->beep) {
3194 dev_err(codec->dev, "Failed to allocate beep device\n");
3195 return;
3196 }
3197
3198 INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3199 wm8962->beep_rate = 0;
3200
3201 wm8962->beep->name = "WM8962 Beep Generator";
3202 wm8962->beep->phys = dev_name(codec->dev);
3203 wm8962->beep->id.bustype = BUS_I2C;
3204
3205 wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3206 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3207 wm8962->beep->event = wm8962_beep_event;
3208 wm8962->beep->dev.parent = codec->dev;
3209 input_set_drvdata(wm8962->beep, codec);
3210
3211 ret = input_register_device(wm8962->beep);
3212 if (ret != 0) {
3213 input_free_device(wm8962->beep);
3214 wm8962->beep = NULL;
3215 dev_err(codec->dev, "Failed to register beep device\n");
3216 }
3217
3218 ret = device_create_file(codec->dev, &dev_attr_beep);
3219 if (ret != 0) {
3220 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
3221 ret);
3222 }
3223}
3224
3225static void wm8962_free_beep(struct snd_soc_codec *codec)
3226{
3227 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3228
3229 device_remove_file(codec->dev, &dev_attr_beep);
3230 input_unregister_device(wm8962->beep);
3231 cancel_work_sync(&wm8962->beep_work);
3232 wm8962->beep = NULL;
3233
3234 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3235}
3236#else
3237static void wm8962_init_beep(struct snd_soc_codec *codec)
3238{
3239}
3240
3241static void wm8962_free_beep(struct snd_soc_codec *codec)
3242{
3243}
3244#endif
3245
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3246static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio)
3247{
3248 int mask = 0;
3249 int val = 0;
3250
3251 /* Some of the GPIOs are behind MFP configuration and need to
3252 * be put into GPIO mode. */
3253 switch (gpio) {
3254 case 2:
3255 mask = WM8962_CLKOUT2_SEL_MASK;
3256 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3257 break;
3258 case 3:
3259 mask = WM8962_CLKOUT3_SEL_MASK;
3260 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3261 break;
3262 default:
3263 break;
3264 }
3265
3266 if (mask)
3267 snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1,
3268 mask, val);
3269}
3270
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3271#ifdef CONFIG_GPIOLIB
3272static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
3273{
3274 return container_of(chip, struct wm8962_priv, gpio_chip);
3275}
3276
3277static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3278{
3279 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3280 struct snd_soc_codec *codec = wm8962->codec;
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3281
3282 /* The WM8962 GPIOs aren't linearly numbered. For simplicity
3283 * we export linear numbers and error out if the unsupported
3284 * ones are requsted.
3285 */
3286 switch (offset + 1) {
3287 case 2:
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3288 case 3:
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3289 case 5:
3290 case 6:
3291 break;
3292 default:
3293 return -EINVAL;
3294 }
3295
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3296 wm8962_set_gpio_mode(codec, offset + 1);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3297
3298 return 0;
3299}
3300
3301static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3302{
3303 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3304 struct snd_soc_codec *codec = wm8962->codec;
3305
3306 snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
Mark Brownd71bb812011-01-31 13:41:03 +0000[diff] [blame]3307 WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3308}
3309
3310static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3311 unsigned offset, int value)
3312{
3313 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3314 struct snd_soc_codec *codec = wm8962->codec;
Axel Linfe75fe02011-12-30 23:38:03 +0800[diff] [blame]3315 int ret, val;
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3316
3317 /* Force function 1 (logic output) */
3318 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3319
Axel Linfe75fe02011-12-30 23:38:03 +0800[diff] [blame]3320 ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3321 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3322 if (ret < 0)
3323 return ret;
3324
3325 return 0;
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3326}
3327
3328static struct gpio_chip wm8962_template_chip = {
3329 .label = "wm8962",
3330 .owner = THIS_MODULE,
3331 .request = wm8962_gpio_request,
3332 .direction_output = wm8962_gpio_direction_out,
3333 .set = wm8962_gpio_set,
3334 .can_sleep = 1,
3335};
3336
3337static void wm8962_init_gpio(struct snd_soc_codec *codec)
3338{
3339 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3340 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3341 int ret;
3342
3343 wm8962->gpio_chip = wm8962_template_chip;
3344 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3345 wm8962->gpio_chip.dev = codec->dev;
3346
3347 if (pdata && pdata->gpio_base)
3348 wm8962->gpio_chip.base = pdata->gpio_base;
3349 else
3350 wm8962->gpio_chip.base = -1;
3351
3352 ret = gpiochip_add(&wm8962->gpio_chip);
3353 if (ret != 0)
3354 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
3355}
3356
3357static void wm8962_free_gpio(struct snd_soc_codec *codec)
3358{
3359 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3360 int ret;
3361
3362 ret = gpiochip_remove(&wm8962->gpio_chip);
3363 if (ret != 0)
3364 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
3365}
3366#else
3367static void wm8962_init_gpio(struct snd_soc_codec *codec)
3368{
3369}
3370
3371static void wm8962_free_gpio(struct snd_soc_codec *codec)
3372{
3373}
3374#endif
3375
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3376static int wm8962_probe(struct snd_soc_codec *codec)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3377{
3378 int ret;
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3379 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3380 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
Lars-Peter Clausen7f87e302010-12-28 21:38:01 +0100[diff] [blame]3381 u16 *reg_cache = codec->reg_cache;
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3382 int i, trigger, irq_pol;
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]3383 bool dmicclk, dmicdat;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3384
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3385 wm8962->codec = codec;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3386 codec->control_data = wm8962->regmap;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3387
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3388 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3389 if (ret != 0) {
3390 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3391 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3392 }
3393
3394 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3395 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3396 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3397 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3398 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3399 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3400 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3401 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3402
3403 /* This should really be moved into the regulator core */
3404 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3405 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3406 &wm8962->disable_nb[i]);
3407 if (ret != 0) {
3408 dev_err(codec->dev,
3409 "Failed to register regulator notifier: %d\n",
3410 ret);
3411 }
3412 }
3413
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3414 /* SYSCLK defaults to on; make sure it is off so we can safely
3415 * write to registers if the device is declocked.
3416 */
3417 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
3418
Mark Browna115c722011-08-04 13:23:38 +0900[diff] [blame]3419 /* Ensure we have soft control over all registers */
3420 snd_soc_update_bits(codec, WM8962_CLOCKING2,
3421 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3422
Mark Brown2af8de82011-11-01 13:53:37 +0000[diff] [blame]3423 /* Ensure that the oscillator and PLLs are disabled */
3424 snd_soc_update_bits(codec, WM8962_PLL2,
3425 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3426 0);
3427
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3428 if (pdata) {
3429 /* Apply static configuration for GPIOs */
3430 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3431 if (pdata->gpio_init[i]) {
3432 wm8962_set_gpio_mode(codec, i + 1);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3433 snd_soc_write(codec, 0x200 + i,
3434 pdata->gpio_init[i] & 0xffff);
Mark Brown8ca2aa92010-10-01 17:46:37 -0700[diff] [blame]3435 }
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3436
3437 /* Put the speakers into mono mode? */
3438 if (pdata->spk_mono)
Lars-Peter Clausen7f87e302010-12-28 21:38:01 +0100[diff] [blame]3439 reg_cache[WM8962_CLASS_D_CONTROL_2]
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3440 |= WM8962_SPK_MONO;
Mark Browna4f28c02010-09-29 13:24:35 -0700[diff] [blame]3441
3442 /* Micbias setup, detection enable and detection
3443 * threasholds. */
3444 if (pdata->mic_cfg)
3445 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3446 WM8962_MICDET_ENA |
3447 WM8962_MICDET_THR_MASK |
3448 WM8962_MICSHORT_THR_MASK |
3449 WM8962_MICBIAS_LVL,
3450 pdata->mic_cfg);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3451 }
3452
3453 /* Latch volume update bits */
Mark Browna1b3b5e2010-12-24 16:59:30 +0000[diff] [blame]3454 snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME,
3455 WM8962_IN_VU, WM8962_IN_VU);
3456 snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME,
3457 WM8962_IN_VU, WM8962_IN_VU);
3458 snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME,
3459 WM8962_ADC_VU, WM8962_ADC_VU);
3460 snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME,
3461 WM8962_ADC_VU, WM8962_ADC_VU);
3462 snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME,
3463 WM8962_DAC_VU, WM8962_DAC_VU);
3464 snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME,
3465 WM8962_DAC_VU, WM8962_DAC_VU);
3466 snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME,
3467 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3468 snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME,
3469 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3470 snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME,
3471 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3472 snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME,
3473 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3474
Mark Brown8f63aaa882011-06-07 23:14:37 +0100[diff] [blame]3475 /* Stereo control for EQ */
3476 snd_soc_update_bits(codec, WM8962_EQ1, WM8962_EQ_SHARED_COEFF, 0);
3477
Mark Brown0469e7b2011-11-08 15:22:09 +0000[diff] [blame]3478 /* Don't debouce interrupts so we don't need SYSCLK */
3479 snd_soc_update_bits(codec, WM8962_IRQ_DEBOUNCE,
3480 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3481 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3482 0);
3483
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3484 wm8962_add_widgets(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3485
Mark Browne47ac372011-04-25 20:14:21 +0100[diff] [blame]3486 /* Save boards having to disable DMIC when not in use */
3487 dmicclk = false;
3488 dmicdat = false;
3489 for (i = 0; i < WM8962_MAX_GPIO; i++) {
3490 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
3491 & WM8962_GP2_FN_MASK) {
3492 case WM8962_GPIO_FN_DMICCLK:
3493 dmicclk = true;
3494 break;
3495 case WM8962_GPIO_FN_DMICDAT:
3496 dmicdat = true;
3497 break;
3498 default:
3499 break;
3500 }
3501 }
3502 if (!dmicclk || !dmicdat) {
3503 dev_dbg(codec->dev, "DMIC not in use, disabling\n");
3504 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
3505 }
3506 if (dmicclk != dmicdat)
3507 dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
3508
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3509 wm8962_init_beep(codec);
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3510 wm8962_init_gpio(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3511
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3512 if (wm8962->irq) {
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3513 if (pdata && pdata->irq_active_low) {
3514 trigger = IRQF_TRIGGER_LOW;
3515 irq_pol = WM8962_IRQ_POL;
3516 } else {
3517 trigger = IRQF_TRIGGER_HIGH;
3518 irq_pol = 0;
3519 }
3520
3521 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
3522 WM8962_IRQ_POL, irq_pol);
3523
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3524 ret = request_threaded_irq(wm8962->irq, NULL, wm8962_irq,
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3525 trigger | IRQF_ONESHOT,
Mark Brown05126152012-02-23 21:49:37 +0000[diff] [blame]3526 "wm8962", codec->dev);
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3527 if (ret != 0) {
3528 dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3529 wm8962->irq, ret);
3530 wm8962->irq = 0;
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3531 /* Non-fatal */
3532 } else {
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3533 /* Enable some IRQs by default */
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3534 snd_soc_update_bits(codec,
3535 WM8962_INTERRUPT_STATUS_2_MASK,
Mark Brown3b8a6d82011-04-25 17:53:43 +0100[diff] [blame]3536 WM8962_FLL_LOCK_EINT |
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3537 WM8962_TEMP_SHUT_EINT |
3538 WM8962_FIFOS_ERR_EINT, 0);
3539 }
3540 }
3541
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3542 return 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3543}
3544
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3545static int wm8962_remove(struct snd_soc_codec *codec)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3546{
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3547 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3548 int i;
3549
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3550 if (wm8962->irq)
3551 free_irq(wm8962->irq, codec);
Mark Brown45e65502010-09-28 16:01:20 -0700[diff] [blame]3552
Mark Brown77113082010-09-30 15:37:53 -0700[diff] [blame]3553 cancel_delayed_work_sync(&wm8962->mic_work);
3554
Mark Brown3367b8d2010-09-20 17:34:58 +0100[diff] [blame]3555 wm8962_free_gpio(codec);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3556 wm8962_free_beep(codec);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3557 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3558 regulator_unregister_notifier(wm8962->supplies[i].consumer,
3559 &wm8962->disable_nb[i]);
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3560
3561 return 0;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3562}
3563
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3564static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
3565 .probe = wm8962_probe,
3566 .remove = wm8962_remove,
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3567 .set_bias_level = wm8962_set_bias_level,
Mark Brown92a43522011-04-25 18:44:01 +0100[diff] [blame]3568 .set_pll = wm8962_set_fll,
Mark Brown2693efd2012-01-27 19:36:45 +0000[diff] [blame]3569 .idle_bias_off = true,
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3570};
3571
Mark Brown182c51c2012-01-24 21:07:55 +0000[diff] [blame]3572/* Improve power consumption for IN4 DC measurement mode */
3573static const struct reg_default wm8962_dc_measure[] = {
3574 { 0xfd, 0x1 },
3575 { 0xcc, 0x40 },
3576 { 0xfd, 0 },
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3577};
3578
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3579static const struct regmap_config wm8962_regmap = {
3580 .reg_bits = 16,
3581 .val_bits = 16,
3582
3583 .max_register = WM8962_MAX_REGISTER,
3584 .reg_defaults = wm8962_reg,
3585 .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3586 .volatile_reg = wm8962_volatile_register,
3587 .readable_reg = wm8962_readable_register,
3588 .cache_type = REGCACHE_RBTREE,
3589};
3590
Bill Pemberton7a79e942012-12-07 09:26:37 -0500[diff] [blame]3591static int wm8962_i2c_probe(struct i2c_client *i2c,
3592 const struct i2c_device_id *id)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3593{
Mark Brown182c51c2012-01-24 21:07:55 +0000[diff] [blame]3594 struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3595 struct wm8962_priv *wm8962;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3596 unsigned int reg;
3597 int ret, i;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3598
Mark Brownbe086aa2011-11-27 19:56:52 +0000[diff] [blame]3599 wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv),
3600 GFP_KERNEL);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3601 if (wm8962 == NULL)
3602 return -ENOMEM;
3603
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3604 i2c_set_clientdata(i2c, wm8962);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3605
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3606 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3607 init_completion(&wm8962->fll_lock);
Mark Brownc7356da2011-06-07 23:13:53 +0100[diff] [blame]3608 wm8962->irq = i2c->irq;
3609
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3610 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3611 wm8962->supplies[i].supply = wm8962_supply_names[i];
3612
Sachin Kamat92437cb2012-11-26 17:19:35 +0530[diff] [blame]3613 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3614 wm8962->supplies);
3615 if (ret != 0) {
3616 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
Mark Brownbe086aa2011-11-27 19:56:52 +0000[diff] [blame]3617 goto err;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3618 }
3619
3620 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3621 wm8962->supplies);
3622 if (ret != 0) {
3623 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
Sachin Kamat92437cb2012-11-26 17:19:35 +0530[diff] [blame]3624 return ret;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3625 }
3626
Sachin Kamatb439c6d2012-11-26 17:19:44 +0530[diff] [blame]3627 wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3628 if (IS_ERR(wm8962->regmap)) {
3629 ret = PTR_ERR(wm8962->regmap);
3630 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3631 goto err_enable;
3632 }
3633
3634 /*
3635 * We haven't marked the chip revision as volatile due to
3636 * sharing a register with the right input volume; explicitly
3637 * bypass the cache to read it.
3638 */
3639 regcache_cache_bypass(wm8962->regmap, true);
3640
3641 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, &reg);
3642 if (ret < 0) {
3643 dev_err(&i2c->dev, "Failed to read ID register\n");
Sachin Kamatb439c6d2012-11-26 17:19:44 +0530[diff] [blame]3644 goto err_enable;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3645 }
3646 if (reg != 0x6243) {
3647 dev_err(&i2c->dev,
Axel Lin905b4192012-02-16 10:33:45 +0800[diff] [blame]3648 "Device is not a WM8962, ID %x != 0x6243\n", reg);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3649 ret = -EINVAL;
Sachin Kamatb439c6d2012-11-26 17:19:44 +0530[diff] [blame]3650 goto err_enable;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3651 }
3652
3653 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, &reg);
3654 if (ret < 0) {
3655 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3656 ret);
Sachin Kamatb439c6d2012-11-26 17:19:44 +0530[diff] [blame]3657 goto err_enable;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3658 }
3659
3660 dev_info(&i2c->dev, "customer id %x revision %c\n",
3661 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3662 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3663 + 'A');
3664
3665 regcache_cache_bypass(wm8962->regmap, false);
3666
3667 ret = wm8962_reset(wm8962);
3668 if (ret < 0) {
3669 dev_err(&i2c->dev, "Failed to issue reset\n");
Sachin Kamatb439c6d2012-11-26 17:19:44 +0530[diff] [blame]3670 goto err_enable;
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3671 }
3672
Mark Brown182c51c2012-01-24 21:07:55 +0000[diff] [blame]3673 if (pdata && pdata->in4_dc_measure) {
3674 ret = regmap_register_patch(wm8962->regmap,
3675 wm8962_dc_measure,
3676 ARRAY_SIZE(wm8962_dc_measure));
3677 if (ret != 0)
3678 dev_err(&i2c->dev,
3679 "Failed to configure for DC mesurement: %d\n",
3680 ret);
3681 }
3682
Mark Brownd23031a42012-02-01 12:48:59 +0000[diff] [blame]3683 pm_runtime_enable(&i2c->dev);
3684 pm_request_idle(&i2c->dev);
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3685
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3686 ret = snd_soc_register_codec(&i2c->dev,
3687 &soc_codec_dev_wm8962, &wm8962_dai, 1);
3688 if (ret < 0)
Sachin Kamatb439c6d2012-11-26 17:19:44 +0530[diff] [blame]3689 goto err_enable;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3690
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3691 /* The drivers should power up as needed */
3692 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3693
3694 return 0;
3695
Mark Brown7b16f562011-11-01 19:32:25 +0000[diff] [blame]3696err_enable:
3697 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
Mark Brownbe086aa2011-11-27 19:56:52 +0000[diff] [blame]3698err:
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3699 return ret;
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3700}
3701
Bill Pemberton7a79e942012-12-07 09:26:37 -0500[diff] [blame]3702static int wm8962_i2c_remove(struct i2c_client *client)
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3703{
Mark Brown54d8d0a2010-08-12 15:02:11 +0100[diff] [blame]3704 snd_soc_unregister_codec(&client->dev);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3705 return 0;
3706}
3707
Mark Brownd23031a42012-02-01 12:48:59 +0000[diff] [blame]3708#ifdef CONFIG_PM_RUNTIME
3709static int wm8962_runtime_resume(struct device *dev)
3710{
3711 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3712 int ret;
3713
3714 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3715 wm8962->supplies);
3716 if (ret != 0) {
3717 dev_err(dev,
3718 "Failed to enable supplies: %d\n", ret);
3719 return ret;
3720 }
3721
3722 regcache_cache_only(wm8962->regmap, false);
Mark Browne4dd7672012-07-11 19:03:48 +0100[diff] [blame]3723
3724 wm8962_reset(wm8962);
3725
Mark Brownd23031a42012-02-01 12:48:59 +0000[diff] [blame]3726 regcache_sync(wm8962->regmap);
3727
Mark Brownd23031a42012-02-01 12:48:59 +0000[diff] [blame]3728 return 0;
3729}
3730
3731static int wm8962_runtime_suspend(struct device *dev)
3732{
3733 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3734
Mark Brownd23031a42012-02-01 12:48:59 +0000[diff] [blame]3735 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3736 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3737
3738 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3739 WM8962_STARTUP_BIAS_ENA |
3740 WM8962_VMID_BUF_ENA, 0);
3741
3742 regcache_cache_only(wm8962->regmap, true);
3743
3744 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3745 wm8962->supplies);
3746
3747 return 0;
3748}
3749#endif
3750
3751static struct dev_pm_ops wm8962_pm = {
3752 SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3753};
3754
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3755static const struct i2c_device_id wm8962_i2c_id[] = {
3756 { "wm8962", 0 },
3757 { }
3758};
3759MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3760
3761static struct i2c_driver wm8962_i2c_driver = {
3762 .driver = {
Mark Brownea738ba2010-09-20 20:36:19 +0100[diff] [blame]3763 .name = "wm8962",
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3764 .owner = THIS_MODULE,
Mark Brownd23031a42012-02-01 12:48:59 +0000[diff] [blame]3765 .pm = &wm8962_pm,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3766 },
3767 .probe = wm8962_i2c_probe,
Bill Pemberton7a79e942012-12-07 09:26:37 -0500[diff] [blame]3768 .remove = wm8962_i2c_remove,
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3769 .id_table = wm8962_i2c_id,
3770};
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3771
Mark Brown9d50a762012-02-16 22:43:39 -0800[diff] [blame]3772module_i2c_driver(wm8962_i2c_driver);
Mark Brown9a76f1f2010-08-05 13:20:59 +0100[diff] [blame]3773
3774MODULE_DESCRIPTION("ASoC WM8962 driver");
3775MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3776MODULE_LICENSE("GPL");