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Catalin Marinasb3901d52012-03-05 11:49:28 +00001/*
2 * Based on arch/arm/kernel/process.c
3 *
4 * Original Copyright (C) 1995 Linus Torvalds
5 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <stdarg.h>
22
23#include <linux/export.h>
24#include <linux/sched.h>
25#include <linux/kernel.h>
26#include <linux/mm.h>
27#include <linux/stddef.h>
28#include <linux/unistd.h>
29#include <linux/user.h>
30#include <linux/delay.h>
31#include <linux/reboot.h>
32#include <linux/interrupt.h>
33#include <linux/kallsyms.h>
34#include <linux/init.h>
35#include <linux/cpu.h>
36#include <linux/elfcore.h>
37#include <linux/pm.h>
38#include <linux/tick.h>
39#include <linux/utsname.h>
40#include <linux/uaccess.h>
41#include <linux/random.h>
42#include <linux/hw_breakpoint.h>
43#include <linux/personality.h>
44#include <linux/notifier.h>
45
46#include <asm/compat.h>
47#include <asm/cacheflush.h>
48#include <asm/processor.h>
49#include <asm/stacktrace.h>
50#include <asm/fpsimd.h>
51
52static void setup_restart(void)
53{
54 /*
55 * Tell the mm system that we are going to reboot -
56 * we may need it to insert some 1:1 mappings so that
57 * soft boot works.
58 */
59 setup_mm_for_reboot();
60
61 /* Clean and invalidate caches */
62 flush_cache_all();
63
64 /* Turn D-cache off */
65 cpu_cache_off();
66
67 /* Push out any further dirty data, and ensure cache is empty */
68 flush_cache_all();
69}
70
71void soft_restart(unsigned long addr)
72{
73 setup_restart();
74 cpu_reset(addr);
75}
76
77/*
78 * Function pointers to optional machine specific functions
79 */
80void (*pm_power_off)(void);
81EXPORT_SYMBOL_GPL(pm_power_off);
82
83void (*pm_restart)(const char *cmd);
84EXPORT_SYMBOL_GPL(pm_restart);
85
86
87/*
88 * This is our default idle handler.
89 */
90static void default_idle(void)
91{
92 /*
93 * This should do all the clock switching and wait for interrupt
94 * tricks
95 */
96 cpu_do_idle();
97 local_irq_enable();
98}
99
Catalin Marinasb3901d52012-03-05 11:49:28 +0000100/*
Len Browndc883ca2013-02-09 23:15:13 -0500101 * The idle thread.
102 * We always respect 'hlt_counter' to prevent low power idle.
Catalin Marinasb3901d52012-03-05 11:49:28 +0000103 */
104void cpu_idle(void)
105{
106 local_fiq_enable();
107
108 /* endless idle loop with no priority at all */
109 while (1) {
110 tick_nohz_idle_enter();
111 rcu_idle_enter();
112 while (!need_resched()) {
113 /*
114 * We need to disable interrupts here to ensure
115 * we don't miss a wakeup call.
116 */
117 local_irq_disable();
118 if (!need_resched()) {
119 stop_critical_timings();
Len Browndc883ca2013-02-09 23:15:13 -0500120 default_idle();
Catalin Marinasb3901d52012-03-05 11:49:28 +0000121 start_critical_timings();
122 /*
Len Browndc883ca2013-02-09 23:15:13 -0500123 * default_idle functions should always return
Catalin Marinasb3901d52012-03-05 11:49:28 +0000124 * with IRQs enabled.
125 */
126 WARN_ON(irqs_disabled());
127 } else {
128 local_irq_enable();
129 }
130 }
131 rcu_idle_exit();
132 tick_nohz_idle_exit();
133 schedule_preempt_disabled();
134 }
135}
136
137void machine_shutdown(void)
138{
139#ifdef CONFIG_SMP
140 smp_send_stop();
141#endif
142}
143
144void machine_halt(void)
145{
146 machine_shutdown();
147 while (1);
148}
149
150void machine_power_off(void)
151{
152 machine_shutdown();
153 if (pm_power_off)
154 pm_power_off();
155}
156
157void machine_restart(char *cmd)
158{
159 machine_shutdown();
160
161 /* Disable interrupts first */
162 local_irq_disable();
163 local_fiq_disable();
164
165 /* Now call the architecture specific reboot code. */
166 if (pm_restart)
167 pm_restart(cmd);
168
169 /*
170 * Whoops - the architecture was unable to reboot.
171 */
172 printk("Reboot failed -- System halted\n");
173 while (1);
174}
175
176void __show_regs(struct pt_regs *regs)
177{
178 int i;
179
180 printk("CPU: %d %s (%s %.*s)\n",
181 raw_smp_processor_id(), print_tainted(),
182 init_utsname()->release,
183 (int)strcspn(init_utsname()->version, " "),
184 init_utsname()->version);
185 print_symbol("PC is at %s\n", instruction_pointer(regs));
186 print_symbol("LR is at %s\n", regs->regs[30]);
187 printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
188 regs->pc, regs->regs[30], regs->pstate);
189 printk("sp : %016llx\n", regs->sp);
190 for (i = 29; i >= 0; i--) {
191 printk("x%-2d: %016llx ", i, regs->regs[i]);
192 if (i % 2 == 0)
193 printk("\n");
194 }
195 printk("\n");
196}
197
198void show_regs(struct pt_regs * regs)
199{
200 printk("\n");
201 printk("Pid: %d, comm: %20s\n", task_pid_nr(current), current->comm);
202 __show_regs(regs);
203}
204
205/*
206 * Free current thread data structures etc..
207 */
208void exit_thread(void)
209{
210}
211
212void flush_thread(void)
213{
214 fpsimd_flush_thread();
215 flush_ptrace_hw_breakpoint(current);
216}
217
218void release_thread(struct task_struct *dead_task)
219{
220}
221
222int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
223{
224 fpsimd_save_state(&current->thread.fpsimd_state);
225 *dst = *src;
226 return 0;
227}
228
229asmlinkage void ret_from_fork(void) asm("ret_from_fork");
230
231int copy_thread(unsigned long clone_flags, unsigned long stack_start,
Al Viroafa86fc2012-10-22 22:51:14 -0400232 unsigned long stk_sz, struct task_struct *p)
Catalin Marinasb3901d52012-03-05 11:49:28 +0000233{
234 struct pt_regs *childregs = task_pt_regs(p);
235 unsigned long tls = p->thread.tp_value;
236
Catalin Marinasb3901d52012-03-05 11:49:28 +0000237 memset(&p->thread.cpu_context, 0, sizeof(struct cpu_context));
Catalin Marinasb3901d52012-03-05 11:49:28 +0000238
Al Viro9ac08002012-10-21 15:56:52 -0400239 if (likely(!(p->flags & PF_KTHREAD))) {
240 *childregs = *current_pt_regs();
Catalin Marinasc34501d2012-10-05 12:31:20 +0100241 childregs->regs[0] = 0;
242 if (is_compat_thread(task_thread_info(p))) {
Al Viroe0fd18c2012-10-18 00:55:54 -0400243 if (stack_start)
244 childregs->compat_sp = stack_start;
Catalin Marinasc34501d2012-10-05 12:31:20 +0100245 } else {
246 /*
247 * Read the current TLS pointer from tpidr_el0 as it may be
248 * out-of-sync with the saved value.
249 */
250 asm("mrs %0, tpidr_el0" : "=r" (tls));
Al Viroe0fd18c2012-10-18 00:55:54 -0400251 if (stack_start) {
252 /* 16-byte aligned stack mandatory on AArch64 */
253 if (stack_start & 15)
254 return -EINVAL;
255 childregs->sp = stack_start;
256 }
Catalin Marinasc34501d2012-10-05 12:31:20 +0100257 }
258 /*
259 * If a TLS pointer was passed to clone (4th argument), use it
260 * for the new thread.
261 */
262 if (clone_flags & CLONE_SETTLS)
Al Viro9ac08002012-10-21 15:56:52 -0400263 tls = childregs->regs[3];
Catalin Marinasc34501d2012-10-05 12:31:20 +0100264 } else {
265 memset(childregs, 0, sizeof(struct pt_regs));
266 childregs->pstate = PSR_MODE_EL1h;
267 p->thread.cpu_context.x19 = stack_start;
268 p->thread.cpu_context.x20 = stk_sz;
269 }
270 p->thread.cpu_context.pc = (unsigned long)ret_from_fork;
271 p->thread.cpu_context.sp = (unsigned long)childregs;
Catalin Marinasb3901d52012-03-05 11:49:28 +0000272 p->thread.tp_value = tls;
273
274 ptrace_hw_copy_thread(p);
275
276 return 0;
277}
278
279static void tls_thread_switch(struct task_struct *next)
280{
281 unsigned long tpidr, tpidrro;
282
283 if (!is_compat_task()) {
284 asm("mrs %0, tpidr_el0" : "=r" (tpidr));
285 current->thread.tp_value = tpidr;
286 }
287
288 if (is_compat_thread(task_thread_info(next))) {
289 tpidr = 0;
290 tpidrro = next->thread.tp_value;
291 } else {
292 tpidr = next->thread.tp_value;
293 tpidrro = 0;
294 }
295
296 asm(
297 " msr tpidr_el0, %0\n"
298 " msr tpidrro_el0, %1"
299 : : "r" (tpidr), "r" (tpidrro));
300}
301
302/*
303 * Thread switching.
304 */
305struct task_struct *__switch_to(struct task_struct *prev,
306 struct task_struct *next)
307{
308 struct task_struct *last;
309
310 fpsimd_thread_switch(next);
311 tls_thread_switch(next);
312 hw_breakpoint_thread_switch(next);
313
314 /* the actual thread switch */
315 last = cpu_switch_to(prev, next);
316
317 return last;
318}
319
Catalin Marinasb3901d52012-03-05 11:49:28 +0000320unsigned long get_wchan(struct task_struct *p)
321{
322 struct stackframe frame;
323 int count = 0;
324 if (!p || p == current || p->state == TASK_RUNNING)
325 return 0;
326
327 frame.fp = thread_saved_fp(p);
328 frame.sp = thread_saved_sp(p);
329 frame.pc = thread_saved_pc(p);
330 do {
331 int ret = unwind_frame(&frame);
332 if (ret < 0)
333 return 0;
334 if (!in_sched_functions(frame.pc))
335 return frame.pc;
336 } while (count ++ < 16);
337 return 0;
338}
339
340unsigned long arch_align_stack(unsigned long sp)
341{
342 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
343 sp -= get_random_int() & ~PAGE_MASK;
344 return sp & ~0xf;
345}
346
347static unsigned long randomize_base(unsigned long base)
348{
349 unsigned long range_end = base + (STACK_RND_MASK << PAGE_SHIFT) + 1;
350 return randomize_range(base, range_end, 0) ? : base;
351}
352
353unsigned long arch_randomize_brk(struct mm_struct *mm)
354{
355 return randomize_base(mm->brk);
356}
357
358unsigned long randomize_et_dyn(unsigned long base)
359{
360 return randomize_base(base);
361}