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review.evervolv.com / android_kernel_oneplus_msm8996 / dd4969a892ea522ecf9d7d826ba1531ce044d46f / . / drivers / scsi / mvsas / mv_sas.h
blob: 7a954a95a217d2cac5519ab2a5e441c639fe0553 [file] [log] [blame]
Jeff Garzikdd4969a2009-05-08 17:44:01 -0400[diff] [blame^]1/*
2 mv_sas.h - Marvell 88SE6440 SAS/SATA support
3
4 Copyright 2007 Red Hat, Inc.
5 Copyright 2008 Marvell. <kewei@marvell.com>
6
7 This program is free software; you can redistribute it and/or
8 modify it under the terms of the GNU General Public License as
9 published by the Free Software Foundation; either version 2,
10 or (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty
14 of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 See the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public
18 License along with this program; see the file COPYING. If not,
19 write to the Free Software Foundation, 675 Mass Ave, Cambridge,
20 MA 02139, USA.
21
22 */
23
24#ifndef _MV_SAS_H_
25#define _MV_SAS_H_
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/spinlock.h>
30#include <linux/delay.h>
31#include <linux/types.h>
32#include <linux/ctype.h>
33#include <linux/dma-mapping.h>
34#include <linux/pci.h>
35#include <linux/platform_device.h>
36#include <linux/interrupt.h>
37#include <linux/irq.h>
38#include <linux/vmalloc.h>
39#include <scsi/libsas.h>
40#include <scsi/scsi_tcq.h>
41#include <scsi/sas_ata.h>
42#include <linux/version.h>
43#include "mv_defs.h"
44
45#define DRV_NAME "mvsas"
46#define DRV_VERSION "0.5.2"
47#define _MV_DUMP 0
48#define MVS_DISABLE_NVRAM
49#define MVS_DISABLE_MSI
50
51#define MVS_ID_NOT_MAPPED 0x7f
52#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
53
54#define for_each_phy(__lseq_mask, __mc, __lseq, __rest) \
55 for ((__mc) = (__lseq_mask), (__lseq) = 0; \
56 (__mc) != 0 && __rest; \
57 (++__lseq), (__mc) >>= 1)
58
59struct mvs_chip_info {
60 u32 n_phy;
61 u32 srs_sz;
62 u32 slot_width;
63};
64
65struct mvs_err_info {
66 __le32 flags;
67 __le32 flags2;
68};
69
70struct mvs_cmd_hdr {
71 __le32 flags; /* PRD tbl len; SAS, SATA ctl */
72 __le32 lens; /* cmd, max resp frame len */
73 __le32 tags; /* targ port xfer tag; tag */
74 __le32 data_len; /* data xfer len */
75 __le64 cmd_tbl; /* command table address */
76 __le64 open_frame; /* open addr frame address */
77 __le64 status_buf; /* status buffer address */
78 __le64 prd_tbl; /* PRD tbl address */
79 __le32 reserved[4];
80};
81
82struct mvs_port {
83 struct asd_sas_port sas_port;
84 u8 port_attached;
85 u8 taskfileset;
86 u8 wide_port_phymap;
87 struct list_head list;
88};
89
90struct mvs_phy {
91 struct mvs_port *port;
92 struct asd_sas_phy sas_phy;
93 struct sas_identify identify;
94 struct scsi_device *sdev;
95 u64 dev_sas_addr;
96 u64 att_dev_sas_addr;
97 u32 att_dev_info;
98 u32 dev_info;
99 u32 phy_type;
100 u32 phy_status;
101 u32 irq_status;
102 u32 frame_rcvd_size;
103 u8 frame_rcvd[32];
104 u8 phy_attached;
105 enum sas_linkrate minimum_linkrate;
106 enum sas_linkrate maximum_linkrate;
107};
108
109struct mvs_slot_info {
110 struct list_head list;
111 struct sas_task *task;
112 u32 n_elem;
113 u32 tx;
114
115 /* DMA buffer for storing cmd tbl, open addr frame, status buffer,
116 * and PRD table
117 */
118 void *buf;
119 dma_addr_t buf_dma;
120#if _MV_DUMP
121 u32 cmd_size;
122#endif
123
124 void *response;
125 struct mvs_port *port;
126};
127
128struct mvs_info {
129 unsigned long flags;
130
131 /* host-wide lock */
132 spinlock_t lock;
133
134 /* our device */
135 struct pci_dev *pdev;
136
137 /* enhanced mode registers */
138 void __iomem *regs;
139
140 /* peripheral registers */
141 void __iomem *peri_regs;
142
143 u8 sas_addr[SAS_ADDR_SIZE];
144
145 /* SCSI/SAS glue */
146 struct sas_ha_struct sas;
147 struct Scsi_Host *shost;
148
149 /* TX (delivery) DMA ring */
150 __le32 *tx;
151 dma_addr_t tx_dma;
152
153 /* cached next-producer idx */
154 u32 tx_prod;
155
156 /* RX (completion) DMA ring */
157 __le32 *rx;
158 dma_addr_t rx_dma;
159
160 /* RX consumer idx */
161 u32 rx_cons;
162
163 /* RX'd FIS area */
164 __le32 *rx_fis;
165 dma_addr_t rx_fis_dma;
166
167 /* DMA command header slots */
168 struct mvs_cmd_hdr *slot;
169 dma_addr_t slot_dma;
170
171 const struct mvs_chip_info *chip;
172
173 u8 tags[MVS_SLOTS];
174 struct mvs_slot_info slot_info[MVS_SLOTS];
175 /* further per-slot information */
176 struct mvs_phy phy[MVS_MAX_PHYS];
177 struct mvs_port port[MVS_MAX_PHYS];
178#ifdef MVS_USE_TASKLET
179 struct tasklet_struct tasklet;
180#endif
181};
182
183int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
184 void *funcdata);
185int mvs_slave_configure(struct scsi_device *sdev);
186void mvs_scan_start(struct Scsi_Host *shost);
187int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
188int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags);
189int mvs_task_abort(struct sas_task *task);
190void mvs_port_formed(struct asd_sas_phy *sas_phy);
191int mvs_I_T_nexus_reset(struct domain_device *dev);
192void mvs_int_full(struct mvs_info *mvi);
193void mvs_tag_init(struct mvs_info *mvi);
194int mvs_nvram_read(struct mvs_info *mvi, u32 addr, void *buf, u32 buflen);
195int __devinit mvs_hw_init(struct mvs_info *mvi);
196void __devinit mvs_print_info(struct mvs_info *mvi);
197void mvs_hba_interrupt_enable(struct mvs_info *mvi);
198void mvs_hba_interrupt_disable(struct mvs_info *mvi);
199void mvs_detect_porttype(struct mvs_info *mvi, int i);
200u8 mvs_assign_reg_set(struct mvs_info *mvi, struct mvs_port *port);
201void mvs_enable_xmt(struct mvs_info *mvi, int PhyId);
202void __devinit mvs_phy_hacks(struct mvs_info *mvi);
203void mvs_free_reg_set(struct mvs_info *mvi, struct mvs_port *port);
204
205#endif