| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 1 | /* | 
 | 2 |  * linux/kernel/irq/chip.c | 
 | 3 |  * | 
 | 4 |  * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | 
 | 5 |  * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | 
 | 6 |  * | 
 | 7 |  * This file contains the core interrupt handling code, for irq-chip | 
 | 8 |  * based architectures. | 
 | 9 |  * | 
 | 10 |  * Detailed information is available in Documentation/DocBook/genericirq | 
 | 11 |  */ | 
 | 12 |  | 
 | 13 | #include <linux/irq.h> | 
| Michael Ellerman | 7fe3730 | 2007-04-18 19:39:21 +1000 | [diff] [blame] | 14 | #include <linux/msi.h> | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 15 | #include <linux/module.h> | 
 | 16 | #include <linux/interrupt.h> | 
 | 17 | #include <linux/kernel_stat.h> | 
 | 18 |  | 
| Steven Rostedt | f069686 | 2012-01-25 20:18:55 -0500 | [diff] [blame] | 19 | #include <trace/events/irq.h> | 
 | 20 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 21 | #include "internals.h" | 
 | 22 |  | 
| Eric W. Biederman | 3a16d71 | 2006-10-04 02:16:37 -0700 | [diff] [blame] | 23 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 24 |  *	irq_set_chip - set the irq chip for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 25 |  *	@irq:	irq number | 
 | 26 |  *	@chip:	pointer to irq chip description structure | 
 | 27 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 28 | int irq_set_chip(unsigned int irq, struct irq_chip *chip) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 29 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 30 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 31 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 32 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 33 | 	if (!desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 34 | 		return -EINVAL; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 35 |  | 
 | 36 | 	if (!chip) | 
 | 37 | 		chip = &no_irq_chip; | 
 | 38 |  | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 39 | 	desc->irq_data.chip = chip; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 40 | 	irq_put_desc_unlock(desc, flags); | 
| David Daney | d72274e | 2011-03-25 12:38:48 -0700 | [diff] [blame] | 41 | 	/* | 
 | 42 | 	 * For !CONFIG_SPARSE_IRQ make the irq show up in | 
 | 43 | 	 * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is | 
 | 44 | 	 * already marked, and this call is harmless. | 
 | 45 | 	 */ | 
 | 46 | 	irq_reserve_irq(irq); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 47 | 	return 0; | 
 | 48 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 49 | EXPORT_SYMBOL(irq_set_chip); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 50 |  | 
 | 51 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 52 |  *	irq_set_type - set the irq trigger type for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 53 |  *	@irq:	irq number | 
| David Brownell | 0c5d1eb | 2008-10-01 14:46:18 -0700 | [diff] [blame] | 54 |  *	@type:	IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 55 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 56 | int irq_set_irq_type(unsigned int irq, unsigned int type) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 57 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 58 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 59 | 	struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 60 | 	int ret = 0; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 61 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 62 | 	if (!desc) | 
 | 63 | 		return -EINVAL; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 64 |  | 
| David Brownell | f2b662d | 2008-12-01 14:31:38 -0800 | [diff] [blame] | 65 | 	type &= IRQ_TYPE_SENSE_MASK; | 
| Russell King | a09b659 | 2012-03-05 15:07:25 -0800 | [diff] [blame] | 66 | 	ret = __irq_set_trigger(desc, irq, type); | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 67 | 	irq_put_desc_busunlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 68 | 	return ret; | 
 | 69 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 70 | EXPORT_SYMBOL(irq_set_irq_type); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 71 |  | 
 | 72 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 73 |  *	irq_set_handler_data - set irq handler data for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 74 |  *	@irq:	Interrupt number | 
 | 75 |  *	@data:	Pointer to interrupt specific data | 
 | 76 |  * | 
 | 77 |  *	Set the hardware irq controller data for an irq | 
 | 78 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 79 | int irq_set_handler_data(unsigned int irq, void *data) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 80 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 81 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 82 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 83 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 84 | 	if (!desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 85 | 		return -EINVAL; | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 86 | 	desc->irq_data.handler_data = data; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 87 | 	irq_put_desc_unlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 88 | 	return 0; | 
 | 89 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 90 | EXPORT_SYMBOL(irq_set_handler_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 91 |  | 
 | 92 | /** | 
| Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 93 |  *	irq_set_msi_desc_off - set MSI descriptor data for an irq at offset | 
 | 94 |  *	@irq_base:	Interrupt number base | 
 | 95 |  *	@irq_offset:	Interrupt number offset | 
 | 96 |  *	@entry:		Pointer to MSI descriptor data | 
 | 97 |  * | 
 | 98 |  *	Set the MSI descriptor entry for an irq at offset | 
 | 99 |  */ | 
 | 100 | int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, | 
 | 101 | 			 struct msi_desc *entry) | 
 | 102 | { | 
 | 103 | 	unsigned long flags; | 
 | 104 | 	struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL); | 
 | 105 |  | 
 | 106 | 	if (!desc) | 
 | 107 | 		return -EINVAL; | 
 | 108 | 	desc->irq_data.msi_desc = entry; | 
 | 109 | 	if (entry && !irq_offset) | 
 | 110 | 		entry->irq = irq_base; | 
 | 111 | 	irq_put_desc_unlock(desc, flags); | 
 | 112 | 	return 0; | 
 | 113 | } | 
 | 114 |  | 
 | 115 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 116 |  *	irq_set_msi_desc - set MSI descriptor data for an irq | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 117 |  *	@irq:	Interrupt number | 
| Randy Dunlap | 472900b | 2007-02-16 01:28:25 -0800 | [diff] [blame] | 118 |  *	@entry:	Pointer to MSI descriptor data | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 119 |  * | 
| Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 120 |  *	Set the MSI descriptor entry for an irq | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 121 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 122 | int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry) | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 123 | { | 
| Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 124 | 	return irq_set_msi_desc_off(irq, 0, entry); | 
| Eric W. Biederman | 5b912c1 | 2007-01-28 12:52:03 -0700 | [diff] [blame] | 125 | } | 
 | 126 |  | 
 | 127 | /** | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 128 |  *	irq_set_chip_data - set irq chip data for an irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 129 |  *	@irq:	Interrupt number | 
 | 130 |  *	@data:	Pointer to chip specific data | 
 | 131 |  * | 
 | 132 |  *	Set the hardware irq chip data for an irq | 
 | 133 |  */ | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 134 | int irq_set_chip_data(unsigned int irq, void *data) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 135 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 136 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 137 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 138 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 139 | 	if (!desc) | 
| Yinghai Lu | 7d94f7c | 2008-08-19 20:50:14 -0700 | [diff] [blame] | 140 | 		return -EINVAL; | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 141 | 	desc->irq_data.chip_data = data; | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 142 | 	irq_put_desc_unlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 143 | 	return 0; | 
 | 144 | } | 
| Thomas Gleixner | a0cd9ca | 2011-02-10 11:36:33 +0100 | [diff] [blame] | 145 | EXPORT_SYMBOL(irq_set_chip_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 146 |  | 
| Thomas Gleixner | f303a6d | 2010-09-28 17:34:01 +0200 | [diff] [blame] | 147 | struct irq_data *irq_get_irq_data(unsigned int irq) | 
 | 148 | { | 
 | 149 | 	struct irq_desc *desc = irq_to_desc(irq); | 
 | 150 |  | 
 | 151 | 	return desc ? &desc->irq_data : NULL; | 
 | 152 | } | 
 | 153 | EXPORT_SYMBOL_GPL(irq_get_irq_data); | 
 | 154 |  | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 155 | static void irq_state_clr_disabled(struct irq_desc *desc) | 
 | 156 | { | 
| Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 157 | 	irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED); | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 158 | } | 
 | 159 |  | 
 | 160 | static void irq_state_set_disabled(struct irq_desc *desc) | 
 | 161 | { | 
| Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 162 | 	irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 163 | } | 
 | 164 |  | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 165 | static void irq_state_clr_masked(struct irq_desc *desc) | 
 | 166 | { | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 167 | 	irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 168 | } | 
 | 169 |  | 
 | 170 | static void irq_state_set_masked(struct irq_desc *desc) | 
 | 171 | { | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 172 | 	irqd_set(&desc->irq_data, IRQD_IRQ_MASKED); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 173 | } | 
 | 174 |  | 
| Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 175 | int irq_startup(struct irq_desc *desc, bool resend) | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 176 | { | 
| Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 177 | 	int ret = 0; | 
 | 178 |  | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 179 | 	irq_state_clr_disabled(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 180 | 	desc->depth = 0; | 
 | 181 |  | 
| Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 182 | 	if (desc->irq_data.chip->irq_startup) { | 
| Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 183 | 		ret = desc->irq_data.chip->irq_startup(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 184 | 		irq_state_clr_masked(desc); | 
| Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 185 | 	} else { | 
 | 186 | 		irq_enable(desc); | 
| Thomas Gleixner | 3aae994 | 2011-02-04 10:17:52 +0100 | [diff] [blame] | 187 | 	} | 
| Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 188 | 	if (resend) | 
 | 189 | 		check_irq_resend(desc, desc->irq_data.irq); | 
 | 190 | 	return ret; | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 191 | } | 
 | 192 |  | 
 | 193 | void irq_shutdown(struct irq_desc *desc) | 
 | 194 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 195 | 	irq_state_set_disabled(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 196 | 	desc->depth = 1; | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 197 | 	if (desc->irq_data.chip->irq_shutdown) | 
 | 198 | 		desc->irq_data.chip->irq_shutdown(&desc->irq_data); | 
| Geert Uytterhoeven | ed585a6 | 2011-09-11 13:59:27 +0200 | [diff] [blame] | 199 | 	else if (desc->irq_data.chip->irq_disable) | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 200 | 		desc->irq_data.chip->irq_disable(&desc->irq_data); | 
 | 201 | 	else | 
 | 202 | 		desc->irq_data.chip->irq_mask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 203 | 	irq_state_set_masked(desc); | 
| Thomas Gleixner | 4699923 | 2011-02-02 21:41:14 +0000 | [diff] [blame] | 204 | } | 
 | 205 |  | 
| Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 206 | void irq_enable(struct irq_desc *desc) | 
 | 207 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 208 | 	irq_state_clr_disabled(desc); | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 209 | 	if (desc->irq_data.chip->irq_enable) | 
 | 210 | 		desc->irq_data.chip->irq_enable(&desc->irq_data); | 
 | 211 | 	else | 
 | 212 | 		desc->irq_data.chip->irq_unmask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 213 | 	irq_state_clr_masked(desc); | 
| Thomas Gleixner | 8792347 | 2011-02-03 12:27:44 +0100 | [diff] [blame] | 214 | } | 
 | 215 |  | 
 | 216 | void irq_disable(struct irq_desc *desc) | 
 | 217 | { | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 218 | 	irq_state_set_disabled(desc); | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 219 | 	if (desc->irq_data.chip->irq_disable) { | 
 | 220 | 		desc->irq_data.chip->irq_disable(&desc->irq_data); | 
| Thomas Gleixner | a61d825 | 2011-02-21 12:54:34 +0100 | [diff] [blame] | 221 | 		irq_state_set_masked(desc); | 
| Thomas Gleixner | 50f7c03 | 2011-02-03 13:23:54 +0100 | [diff] [blame] | 222 | 	} | 
| Thomas Gleixner | 89d694b | 2008-02-18 18:25:17 +0100 | [diff] [blame] | 223 | } | 
 | 224 |  | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 225 | void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu) | 
 | 226 | { | 
 | 227 | 	if (desc->irq_data.chip->irq_enable) | 
 | 228 | 		desc->irq_data.chip->irq_enable(&desc->irq_data); | 
 | 229 | 	else | 
 | 230 | 		desc->irq_data.chip->irq_unmask(&desc->irq_data); | 
 | 231 | 	cpumask_set_cpu(cpu, desc->percpu_enabled); | 
 | 232 | } | 
 | 233 |  | 
 | 234 | void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu) | 
 | 235 | { | 
 | 236 | 	if (desc->irq_data.chip->irq_disable) | 
 | 237 | 		desc->irq_data.chip->irq_disable(&desc->irq_data); | 
 | 238 | 	else | 
 | 239 | 		desc->irq_data.chip->irq_mask(&desc->irq_data); | 
 | 240 | 	cpumask_clear_cpu(cpu, desc->percpu_enabled); | 
 | 241 | } | 
 | 242 |  | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 243 | static inline void mask_ack_irq(struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 244 | { | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 245 | 	if (desc->irq_data.chip->irq_mask_ack) | 
 | 246 | 		desc->irq_data.chip->irq_mask_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 247 | 	else { | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 248 | 		desc->irq_data.chip->irq_mask(&desc->irq_data); | 
| Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 249 | 		if (desc->irq_data.chip->irq_ack) | 
 | 250 | 			desc->irq_data.chip->irq_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 251 | 	} | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 252 | 	irq_state_set_masked(desc); | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 253 | } | 
 | 254 |  | 
| Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 255 | void mask_irq(struct irq_desc *desc) | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 256 | { | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 257 | 	if (desc->irq_data.chip->irq_mask) { | 
 | 258 | 		desc->irq_data.chip->irq_mask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 259 | 		irq_state_set_masked(desc); | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 260 | 	} | 
 | 261 | } | 
 | 262 |  | 
| Thomas Gleixner | d4d5e08 | 2011-02-10 13:16:14 +0100 | [diff] [blame] | 263 | void unmask_irq(struct irq_desc *desc) | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 264 | { | 
| Thomas Gleixner | 0eda58b | 2010-09-27 12:44:44 +0000 | [diff] [blame] | 265 | 	if (desc->irq_data.chip->irq_unmask) { | 
 | 266 | 		desc->irq_data.chip->irq_unmask(&desc->irq_data); | 
| Thomas Gleixner | 6e40262 | 2011-02-08 12:36:06 +0100 | [diff] [blame] | 267 | 		irq_state_clr_masked(desc); | 
| Thomas Gleixner | 0b1adaa | 2010-03-09 19:45:54 +0100 | [diff] [blame] | 268 | 	} | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 269 | } | 
 | 270 |  | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 271 | /* | 
 | 272 |  *	handle_nested_irq - Handle a nested irq from a irq thread | 
 | 273 |  *	@irq:	the interrupt number | 
 | 274 |  * | 
 | 275 |  *	Handle interrupts which are nested into a threaded interrupt | 
 | 276 |  *	handler. The handler function is called inside the calling | 
 | 277 |  *	threads context. | 
 | 278 |  */ | 
 | 279 | void handle_nested_irq(unsigned int irq) | 
 | 280 | { | 
 | 281 | 	struct irq_desc *desc = irq_to_desc(irq); | 
 | 282 | 	struct irqaction *action; | 
 | 283 | 	irqreturn_t action_ret; | 
 | 284 |  | 
 | 285 | 	might_sleep(); | 
 | 286 |  | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 287 | 	raw_spin_lock_irq(&desc->lock); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 288 |  | 
| Thomas Gleixner | 293a7a0 | 2012-10-16 15:07:49 -0700 | [diff] [blame] | 289 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 290 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
 | 291 |  | 
 | 292 | 	action = desc->action; | 
| Ning Jiang | 23812b9 | 2012-05-22 00:19:20 +0800 | [diff] [blame] | 293 | 	if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) { | 
 | 294 | 		desc->istate |= IRQS_PENDING; | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 295 | 		goto out_unlock; | 
| Ning Jiang | 23812b9 | 2012-05-22 00:19:20 +0800 | [diff] [blame] | 296 | 	} | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 297 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 298 | 	irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS); | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 299 | 	raw_spin_unlock_irq(&desc->lock); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 300 |  | 
 | 301 | 	action_ret = action->thread_fn(action->irq, action->dev_id); | 
 | 302 | 	if (!noirqdebug) | 
 | 303 | 		note_interrupt(irq, desc, action_ret); | 
 | 304 |  | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 305 | 	raw_spin_lock_irq(&desc->lock); | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 306 | 	irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 307 |  | 
 | 308 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 309 | 	raw_spin_unlock_irq(&desc->lock); | 
| Thomas Gleixner | 399b5da | 2009-08-13 13:21:38 +0200 | [diff] [blame] | 310 | } | 
 | 311 | EXPORT_SYMBOL_GPL(handle_nested_irq); | 
 | 312 |  | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 313 | static bool irq_check_poll(struct irq_desc *desc) | 
 | 314 | { | 
| Thomas Gleixner | 6954b75 | 2011-02-07 20:55:35 +0100 | [diff] [blame] | 315 | 	if (!(desc->istate & IRQS_POLL_INPROGRESS)) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 316 | 		return false; | 
 | 317 | 	return irq_wait_for_poll(desc); | 
 | 318 | } | 
 | 319 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 320 | /** | 
 | 321 |  *	handle_simple_irq - Simple and software-decoded IRQs. | 
 | 322 |  *	@irq:	the interrupt number | 
 | 323 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 324 |  * | 
 | 325 |  *	Simple interrupts are either sent from a demultiplexing interrupt | 
 | 326 |  *	handler or come from hardware, where no interrupt hardware control | 
 | 327 |  *	is necessary. | 
 | 328 |  * | 
 | 329 |  *	Note: The caller is expected to handle the ack, clear, mask and | 
 | 330 |  *	unmask issues if necessary. | 
 | 331 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 332 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 333 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 334 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 335 | 	raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 336 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 337 | 	if (unlikely(irqd_irq_inprogress(&desc->irq_data))) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 338 | 		if (!irq_check_poll(desc)) | 
 | 339 | 			goto out_unlock; | 
 | 340 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 341 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 342 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 343 |  | 
| Ning Jiang | 23812b9 | 2012-05-22 00:19:20 +0800 | [diff] [blame] | 344 | 	if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { | 
 | 345 | 		desc->istate |= IRQS_PENDING; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 346 | 		goto out_unlock; | 
| Ning Jiang | 23812b9 | 2012-05-22 00:19:20 +0800 | [diff] [blame] | 347 | 	} | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 348 |  | 
| Thomas Gleixner | 107781e | 2011-02-07 01:21:02 +0100 | [diff] [blame] | 349 | 	handle_irq_event(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 350 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 351 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 352 | 	raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 353 | } | 
| Jonathan Cameron | edf76f8 | 2011-05-18 10:39:04 +0100 | [diff] [blame] | 354 | EXPORT_SYMBOL_GPL(handle_simple_irq); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 355 |  | 
| Thomas Gleixner | ac56376 | 2012-02-07 17:58:03 +0100 | [diff] [blame] | 356 | /* | 
 | 357 |  * Called unconditionally from handle_level_irq() and only for oneshot | 
 | 358 |  * interrupts from handle_fasteoi_irq() | 
 | 359 |  */ | 
 | 360 | static void cond_unmask_irq(struct irq_desc *desc) | 
 | 361 | { | 
 | 362 | 	/* | 
 | 363 | 	 * We need to unmask in the following cases: | 
 | 364 | 	 * - Standard level irq (IRQF_ONESHOT is not set) | 
 | 365 | 	 * - Oneshot irq which did not wake the thread (caused by a | 
 | 366 | 	 *   spurious interrupt or a primary handler handling it | 
 | 367 | 	 *   completely). | 
 | 368 | 	 */ | 
 | 369 | 	if (!irqd_irq_disabled(&desc->irq_data) && | 
 | 370 | 	    irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) | 
 | 371 | 		unmask_irq(desc); | 
 | 372 | } | 
 | 373 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 374 | /** | 
 | 375 |  *	handle_level_irq - Level type irq handler | 
 | 376 |  *	@irq:	the interrupt number | 
 | 377 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 378 |  * | 
 | 379 |  *	Level type interrupts are active as long as the hardware line has | 
 | 380 |  *	the active level. This may require to mask the interrupt and unmask | 
 | 381 |  *	it after the associated handler has acknowledged the device, so the | 
 | 382 |  *	interrupt line is back to inactive. | 
 | 383 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 384 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 385 | handle_level_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 386 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 387 | 	raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 388 | 	mask_ack_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 389 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 390 | 	if (unlikely(irqd_irq_inprogress(&desc->irq_data))) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 391 | 		if (!irq_check_poll(desc)) | 
 | 392 | 			goto out_unlock; | 
 | 393 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 394 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 395 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 396 |  | 
 | 397 | 	/* | 
 | 398 | 	 * If its disabled or no action available | 
 | 399 | 	 * keep it masked and get out of here | 
 | 400 | 	 */ | 
| Thomas Gleixner | d4dc0f9 | 2012-04-25 12:54:54 +0200 | [diff] [blame] | 401 | 	if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { | 
 | 402 | 		desc->istate |= IRQS_PENDING; | 
| Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 403 | 		goto out_unlock; | 
| Thomas Gleixner | d4dc0f9 | 2012-04-25 12:54:54 +0200 | [diff] [blame] | 404 | 	} | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 405 |  | 
| Thomas Gleixner | 1529866 | 2011-02-07 01:22:17 +0100 | [diff] [blame] | 406 | 	handle_irq_event(desc); | 
| Thomas Gleixner | b25c340 | 2009-08-13 12:17:22 +0200 | [diff] [blame] | 407 |  | 
| Thomas Gleixner | ac56376 | 2012-02-07 17:58:03 +0100 | [diff] [blame] | 408 | 	cond_unmask_irq(desc); | 
 | 409 |  | 
| Ingo Molnar | 86998aa | 2006-09-19 11:14:34 +0200 | [diff] [blame] | 410 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 411 | 	raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 412 | } | 
| Ingo Molnar | 14819ea | 2009-01-14 12:34:21 +0100 | [diff] [blame] | 413 | EXPORT_SYMBOL_GPL(handle_level_irq); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 414 |  | 
| Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 415 | #ifdef CONFIG_IRQ_PREFLOW_FASTEOI | 
 | 416 | static inline void preflow_handler(struct irq_desc *desc) | 
 | 417 | { | 
 | 418 | 	if (desc->preflow_handler) | 
 | 419 | 		desc->preflow_handler(&desc->irq_data); | 
 | 420 | } | 
 | 421 | #else | 
 | 422 | static inline void preflow_handler(struct irq_desc *desc) { } | 
 | 423 | #endif | 
 | 424 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 425 | /** | 
| Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 426 |  *	handle_fasteoi_irq - irq handler for transparent controllers | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 427 |  *	@irq:	the interrupt number | 
 | 428 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 429 |  * | 
| Ingo Molnar | 47c2a3a | 2006-06-29 02:25:03 -0700 | [diff] [blame] | 430 |  *	Only a single callback will be issued to the chip: an ->eoi() | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 431 |  *	call when the interrupt has been serviced. This enables support | 
 | 432 |  *	for modern forms of interrupt handlers, which handle the flow | 
 | 433 |  *	details in hardware, transparently. | 
 | 434 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 435 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 436 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 437 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 438 | 	raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 439 |  | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 440 | 	if (unlikely(irqd_irq_inprogress(&desc->irq_data))) | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 441 | 		if (!irq_check_poll(desc)) | 
 | 442 | 			goto out; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 443 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 444 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 445 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 446 |  | 
 | 447 | 	/* | 
 | 448 | 	 * If its disabled or no action available | 
| Ingo Molnar | 76d2160 | 2007-02-16 01:28:24 -0800 | [diff] [blame] | 449 | 	 * then mask it and get out of here: | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 450 | 	 */ | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 451 | 	if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) { | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 452 | 		desc->istate |= IRQS_PENDING; | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 453 | 		mask_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 454 | 		goto out; | 
| Benjamin Herrenschmidt | 98bb244 | 2006-06-29 02:25:01 -0700 | [diff] [blame] | 455 | 	} | 
| Thomas Gleixner | c69e375 | 2011-03-02 11:49:21 +0100 | [diff] [blame] | 456 |  | 
 | 457 | 	if (desc->istate & IRQS_ONESHOT) | 
 | 458 | 		mask_irq(desc); | 
 | 459 |  | 
| Thomas Gleixner | 7812957 | 2011-02-10 15:14:20 +0100 | [diff] [blame] | 460 | 	preflow_handler(desc); | 
| Thomas Gleixner | a7ae4de | 2011-02-07 01:23:07 +0100 | [diff] [blame] | 461 | 	handle_irq_event(desc); | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 462 |  | 
| Thomas Gleixner | ac56376 | 2012-02-07 17:58:03 +0100 | [diff] [blame] | 463 | 	if (desc->istate & IRQS_ONESHOT) | 
 | 464 | 		cond_unmask_irq(desc); | 
 | 465 |  | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 466 | out_eoi: | 
| Thomas Gleixner | 0c5c155 | 2010-09-27 12:44:53 +0000 | [diff] [blame] | 467 | 	desc->irq_data.chip->irq_eoi(&desc->irq_data); | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 468 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 469 | 	raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | 77694b4 | 2011-02-15 10:33:57 +0100 | [diff] [blame] | 470 | 	return; | 
 | 471 | out: | 
 | 472 | 	if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED)) | 
 | 473 | 		goto out_eoi; | 
 | 474 | 	goto out_unlock; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 475 | } | 
 | 476 |  | 
 | 477 | /** | 
 | 478 |  *	handle_edge_irq - edge type IRQ handler | 
 | 479 |  *	@irq:	the interrupt number | 
 | 480 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 481 |  * | 
 | 482 |  *	Interrupt occures on the falling and/or rising edge of a hardware | 
| Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 483 |  *	signal. The occurrence is latched into the irq controller hardware | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 484 |  *	and must be acked in order to be reenabled. After the ack another | 
 | 485 |  *	interrupt can happen on the same source even before the first one | 
| Uwe Kleine-König | dfff061 | 2010-02-12 21:58:11 +0100 | [diff] [blame] | 486 |  *	is handled by the associated event handler. If this happens it | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 487 |  *	might be necessary to disable (mask) the interrupt depending on the | 
 | 488 |  *	controller hardware. This requires to reenable the interrupt inside | 
 | 489 |  *	of the loop which handles the interrupts which have arrived while | 
 | 490 |  *	the handler was running. If all pending interrupts are handled, the | 
 | 491 |  *	loop is left. | 
 | 492 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 493 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 494 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 495 | { | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 496 | 	raw_spin_lock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 497 |  | 
| Thomas Gleixner | 163ef30 | 2011-02-08 11:39:15 +0100 | [diff] [blame] | 498 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 499 | 	/* | 
 | 500 | 	 * If we're currently running this IRQ, or its disabled, | 
 | 501 | 	 * we shouldn't process the IRQ. Mark it pending, handle | 
 | 502 | 	 * the necessary masking and go out | 
 | 503 | 	 */ | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 504 | 	if (unlikely(irqd_irq_disabled(&desc->irq_data) || | 
 | 505 | 		     irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 506 | 		if (!irq_check_poll(desc)) { | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 507 | 			desc->istate |= IRQS_PENDING; | 
| Thomas Gleixner | fe200ae | 2011-02-07 10:34:30 +0100 | [diff] [blame] | 508 | 			mask_ack_irq(desc); | 
 | 509 | 			goto out_unlock; | 
 | 510 | 		} | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 511 | 	} | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 512 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 513 |  | 
 | 514 | 	/* Start handling the irq */ | 
| Thomas Gleixner | 22a4916 | 2010-09-27 12:44:47 +0000 | [diff] [blame] | 515 | 	desc->irq_data.chip->irq_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 516 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 517 | 	do { | 
| Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 518 | 		if (unlikely(!desc->action)) { | 
| Thomas Gleixner | e2c0f8f | 2010-09-27 12:44:42 +0000 | [diff] [blame] | 519 | 			mask_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 520 | 			goto out_unlock; | 
 | 521 | 		} | 
 | 522 |  | 
 | 523 | 		/* | 
 | 524 | 		 * When another irq arrived while we were handling | 
 | 525 | 		 * one, we could have masked the irq. | 
 | 526 | 		 * Renable it, if it was not disabled in meantime. | 
 | 527 | 		 */ | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 528 | 		if (unlikely(desc->istate & IRQS_PENDING)) { | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 529 | 			if (!irqd_irq_disabled(&desc->irq_data) && | 
 | 530 | 			    irqd_irq_masked(&desc->irq_data)) | 
| Thomas Gleixner | c1594b7 | 2011-02-07 22:11:30 +0100 | [diff] [blame] | 531 | 				unmask_irq(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 532 | 		} | 
 | 533 |  | 
| Thomas Gleixner | a60a5dc | 2011-02-07 01:24:07 +0100 | [diff] [blame] | 534 | 		handle_irq_event(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 535 |  | 
| Thomas Gleixner | 2a0d6fb | 2011-02-08 12:17:57 +0100 | [diff] [blame] | 536 | 	} while ((desc->istate & IRQS_PENDING) && | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 537 | 		 !irqd_irq_disabled(&desc->irq_data)); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 538 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 539 | out_unlock: | 
| Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 540 | 	raw_spin_unlock(&desc->lock); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 541 | } | 
| Jiri Kosina | 3911ff3 | 2012-05-13 12:13:15 +0200 | [diff] [blame] | 542 | EXPORT_SYMBOL(handle_edge_irq); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 543 |  | 
| Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 544 | #ifdef CONFIG_IRQ_EDGE_EOI_HANDLER | 
 | 545 | /** | 
 | 546 |  *	handle_edge_eoi_irq - edge eoi type IRQ handler | 
 | 547 |  *	@irq:	the interrupt number | 
 | 548 |  *	@desc:	the interrupt description structure for this irq | 
 | 549 |  * | 
 | 550 |  * Similar as the above handle_edge_irq, but using eoi and w/o the | 
 | 551 |  * mask/unmask logic. | 
 | 552 |  */ | 
 | 553 | void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc) | 
 | 554 | { | 
 | 555 | 	struct irq_chip *chip = irq_desc_get_chip(desc); | 
 | 556 |  | 
 | 557 | 	raw_spin_lock(&desc->lock); | 
 | 558 |  | 
 | 559 | 	desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING); | 
 | 560 | 	/* | 
 | 561 | 	 * If we're currently running this IRQ, or its disabled, | 
 | 562 | 	 * we shouldn't process the IRQ. Mark it pending, handle | 
 | 563 | 	 * the necessary masking and go out | 
 | 564 | 	 */ | 
 | 565 | 	if (unlikely(irqd_irq_disabled(&desc->irq_data) || | 
 | 566 | 		     irqd_irq_inprogress(&desc->irq_data) || !desc->action)) { | 
 | 567 | 		if (!irq_check_poll(desc)) { | 
 | 568 | 			desc->istate |= IRQS_PENDING; | 
 | 569 | 			goto out_eoi; | 
 | 570 | 		} | 
 | 571 | 	} | 
 | 572 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
 | 573 |  | 
 | 574 | 	do { | 
 | 575 | 		if (unlikely(!desc->action)) | 
 | 576 | 			goto out_eoi; | 
 | 577 |  | 
 | 578 | 		handle_irq_event(desc); | 
 | 579 |  | 
 | 580 | 	} while ((desc->istate & IRQS_PENDING) && | 
 | 581 | 		 !irqd_irq_disabled(&desc->irq_data)); | 
 | 582 |  | 
| Stephen Rothwell | ac0e044 | 2011-03-30 10:55:12 +1100 | [diff] [blame] | 583 | out_eoi: | 
| Thomas Gleixner | 0521c8f | 2011-03-28 16:13:24 +0200 | [diff] [blame] | 584 | 	chip->irq_eoi(&desc->irq_data); | 
 | 585 | 	raw_spin_unlock(&desc->lock); | 
 | 586 | } | 
 | 587 | #endif | 
 | 588 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 589 | /** | 
| Liuweni | 24b26d4 | 2009-11-04 20:11:05 +0800 | [diff] [blame] | 590 |  *	handle_percpu_irq - Per CPU local irq handler | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 591 |  *	@irq:	the interrupt number | 
 | 592 |  *	@desc:	the interrupt description structure for this irq | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 593 |  * | 
 | 594 |  *	Per CPU interrupts on SMP machines without locking requirements | 
 | 595 |  */ | 
| Harvey Harrison | 7ad5b3a | 2008-02-08 04:19:53 -0800 | [diff] [blame] | 596 | void | 
| David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 597 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 598 | { | 
| Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 599 | 	struct irq_chip *chip = irq_desc_get_chip(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 600 |  | 
| Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 601 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 602 |  | 
| Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 603 | 	if (chip->irq_ack) | 
 | 604 | 		chip->irq_ack(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 605 |  | 
| Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 606 | 	handle_irq_event_percpu(desc, desc->action); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 607 |  | 
| Thomas Gleixner | 849f061 | 2011-02-07 01:25:41 +0100 | [diff] [blame] | 608 | 	if (chip->irq_eoi) | 
 | 609 | 		chip->irq_eoi(&desc->irq_data); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 610 | } | 
 | 611 |  | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 612 | /** | 
 | 613 |  * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids | 
 | 614 |  * @irq:	the interrupt number | 
 | 615 |  * @desc:	the interrupt description structure for this irq | 
 | 616 |  * | 
 | 617 |  * Per CPU interrupts on SMP machines without locking requirements. Same as | 
 | 618 |  * handle_percpu_irq() above but with the following extras: | 
 | 619 |  * | 
 | 620 |  * action->percpu_dev_id is a pointer to percpu variables which | 
 | 621 |  * contain the real device id for the cpu on which this handler is | 
 | 622 |  * called | 
 | 623 |  */ | 
 | 624 | void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc) | 
 | 625 | { | 
 | 626 | 	struct irq_chip *chip = irq_desc_get_chip(desc); | 
 | 627 | 	struct irqaction *action = desc->action; | 
 | 628 | 	void *dev_id = __this_cpu_ptr(action->percpu_dev_id); | 
 | 629 | 	irqreturn_t res; | 
 | 630 |  | 
 | 631 | 	kstat_incr_irqs_this_cpu(irq, desc); | 
 | 632 |  | 
 | 633 | 	if (chip->irq_ack) | 
 | 634 | 		chip->irq_ack(&desc->irq_data); | 
 | 635 |  | 
 | 636 | 	trace_irq_handler_entry(irq, action); | 
 | 637 | 	res = action->handler(irq, dev_id); | 
 | 638 | 	trace_irq_handler_exit(irq, action, res); | 
 | 639 |  | 
 | 640 | 	if (chip->irq_eoi) | 
 | 641 | 		chip->irq_eoi(&desc->irq_data); | 
 | 642 | } | 
 | 643 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 644 | void | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 645 | __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, | 
| Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 646 | 		  const char *name) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 647 | { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 648 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 649 | 	struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 650 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 651 | 	if (!desc) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 652 | 		return; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 653 |  | 
| Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 654 | 	if (!handle) { | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 655 | 		handle = handle_bad_irq; | 
| Thomas Gleixner | 091738a | 2011-02-14 20:16:43 +0100 | [diff] [blame] | 656 | 	} else { | 
 | 657 | 		if (WARN_ON(desc->irq_data.chip == &no_irq_chip)) | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 658 | 			goto out; | 
| Thomas Gleixner | f8b5473 | 2006-07-01 22:30:08 +0100 | [diff] [blame] | 659 | 	} | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 660 |  | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 661 | 	/* Uninstall? */ | 
 | 662 | 	if (handle == handle_bad_irq) { | 
| Thomas Gleixner | 6b8ff31 | 2010-10-01 12:58:38 +0200 | [diff] [blame] | 663 | 		if (desc->irq_data.chip != &no_irq_chip) | 
| Thomas Gleixner | 9205e31 | 2010-09-27 12:44:50 +0000 | [diff] [blame] | 664 | 			mask_ack_irq(desc); | 
| Thomas Gleixner | 801a0e9 | 2011-03-27 11:02:49 +0200 | [diff] [blame] | 665 | 		irq_state_set_disabled(desc); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 666 | 		desc->depth = 1; | 
 | 667 | 	} | 
 | 668 | 	desc->handle_irq = handle; | 
| Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 669 | 	desc->name = name; | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 670 |  | 
 | 671 | 	if (handle != handle_bad_irq && is_chained) { | 
| Thomas Gleixner | 1ccb4e6 | 2011-02-09 14:44:17 +0100 | [diff] [blame] | 672 | 		irq_settings_set_noprobe(desc); | 
 | 673 | 		irq_settings_set_norequest(desc); | 
| Paul Mundt | 7f1b124 | 2011-04-07 06:01:44 +0900 | [diff] [blame] | 674 | 		irq_settings_set_nothread(desc); | 
| Thomas Gleixner | b4bc724 | 2012-02-08 11:57:52 +0100 | [diff] [blame] | 675 | 		irq_startup(desc, true); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 676 | 	} | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 677 | out: | 
 | 678 | 	irq_put_desc_busunlock(desc, flags); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 679 | } | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 680 | EXPORT_SYMBOL_GPL(__irq_set_handler); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 681 |  | 
 | 682 | void | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 683 | irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | 
| Ingo Molnar | a460e74 | 2006-10-17 00:10:03 -0700 | [diff] [blame] | 684 | 			      irq_flow_handler_t handle, const char *name) | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 685 | { | 
| Thomas Gleixner | 35e857c | 2011-02-10 12:20:23 +0100 | [diff] [blame] | 686 | 	irq_set_chip(irq, chip); | 
| Thomas Gleixner | 3836ca0 | 2011-02-14 20:09:19 +0100 | [diff] [blame] | 687 | 	__irq_set_handler(irq, handle, 0, name); | 
| Thomas Gleixner | dd87eb3 | 2006-06-29 02:24:53 -0700 | [diff] [blame] | 688 | } | 
| Kuninori Morimoto | b3ae66f | 2012-07-30 22:39:06 -0700 | [diff] [blame] | 689 | EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name); | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 690 |  | 
| Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 691 | void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set) | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 692 | { | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 693 | 	unsigned long flags; | 
| Marc Zyngier | 31d9d9b | 2011-09-23 17:03:06 +0100 | [diff] [blame] | 694 | 	struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 695 |  | 
| Thomas Gleixner | 4424718 | 2010-09-28 10:40:18 +0200 | [diff] [blame] | 696 | 	if (!desc) | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 697 | 		return; | 
| Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 698 | 	irq_settings_clr_and_set(desc, clr, set); | 
 | 699 |  | 
| Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 700 | 	irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU | | 
| Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 701 | 		   IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT); | 
| Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 702 | 	if (irq_settings_has_no_balance_set(desc)) | 
 | 703 | 		irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | 
 | 704 | 	if (irq_settings_is_per_cpu(desc)) | 
 | 705 | 		irqd_set(&desc->irq_data, IRQD_PER_CPU); | 
| Thomas Gleixner | e1ef824 | 2011-02-10 22:25:31 +0100 | [diff] [blame] | 706 | 	if (irq_settings_can_move_pcntxt(desc)) | 
 | 707 | 		irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT); | 
| Thomas Gleixner | 0ef5ca1 | 2011-03-28 21:59:37 +0200 | [diff] [blame] | 708 | 	if (irq_settings_is_level(desc)) | 
 | 709 | 		irqd_set(&desc->irq_data, IRQD_LEVEL); | 
| Thomas Gleixner | a005677 | 2011-02-08 17:11:03 +0100 | [diff] [blame] | 710 |  | 
| Thomas Gleixner | 876dbd4 | 2011-02-08 17:28:12 +0100 | [diff] [blame] | 711 | 	irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc)); | 
 | 712 |  | 
| Thomas Gleixner | 02725e7 | 2011-02-12 10:37:36 +0100 | [diff] [blame] | 713 | 	irq_put_desc_unlock(desc, flags); | 
| Ralf Baechle | 46f4f8f | 2008-02-08 04:22:01 -0800 | [diff] [blame] | 714 | } | 
| Jonathan Cameron | edf76f8 | 2011-05-18 10:39:04 +0100 | [diff] [blame] | 715 | EXPORT_SYMBOL_GPL(irq_modify_status); | 
| David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 716 |  | 
 | 717 | /** | 
 | 718 |  *	irq_cpu_online - Invoke all irq_cpu_online functions. | 
 | 719 |  * | 
 | 720 |  *	Iterate through all irqs and invoke the chip.irq_cpu_online() | 
 | 721 |  *	for each. | 
 | 722 |  */ | 
 | 723 | void irq_cpu_online(void) | 
 | 724 | { | 
 | 725 | 	struct irq_desc *desc; | 
 | 726 | 	struct irq_chip *chip; | 
 | 727 | 	unsigned long flags; | 
 | 728 | 	unsigned int irq; | 
 | 729 |  | 
 | 730 | 	for_each_active_irq(irq) { | 
 | 731 | 		desc = irq_to_desc(irq); | 
 | 732 | 		if (!desc) | 
 | 733 | 			continue; | 
 | 734 |  | 
 | 735 | 		raw_spin_lock_irqsave(&desc->lock, flags); | 
 | 736 |  | 
 | 737 | 		chip = irq_data_get_irq_chip(&desc->irq_data); | 
| Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 738 | 		if (chip && chip->irq_cpu_online && | 
 | 739 | 		    (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 740 | 		     !irqd_irq_disabled(&desc->irq_data))) | 
| David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 741 | 			chip->irq_cpu_online(&desc->irq_data); | 
 | 742 |  | 
 | 743 | 		raw_spin_unlock_irqrestore(&desc->lock, flags); | 
 | 744 | 	} | 
 | 745 | } | 
 | 746 |  | 
 | 747 | /** | 
 | 748 |  *	irq_cpu_offline - Invoke all irq_cpu_offline functions. | 
 | 749 |  * | 
 | 750 |  *	Iterate through all irqs and invoke the chip.irq_cpu_offline() | 
 | 751 |  *	for each. | 
 | 752 |  */ | 
 | 753 | void irq_cpu_offline(void) | 
 | 754 | { | 
 | 755 | 	struct irq_desc *desc; | 
 | 756 | 	struct irq_chip *chip; | 
 | 757 | 	unsigned long flags; | 
 | 758 | 	unsigned int irq; | 
 | 759 |  | 
 | 760 | 	for_each_active_irq(irq) { | 
 | 761 | 		desc = irq_to_desc(irq); | 
 | 762 | 		if (!desc) | 
 | 763 | 			continue; | 
 | 764 |  | 
 | 765 | 		raw_spin_lock_irqsave(&desc->lock, flags); | 
 | 766 |  | 
 | 767 | 		chip = irq_data_get_irq_chip(&desc->irq_data); | 
| Thomas Gleixner | b3d4223 | 2011-03-27 16:05:36 +0200 | [diff] [blame] | 768 | 		if (chip && chip->irq_cpu_offline && | 
 | 769 | 		    (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) || | 
| Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 770 | 		     !irqd_irq_disabled(&desc->irq_data))) | 
| David Daney | 0fdb4b2 | 2011-03-25 12:38:49 -0700 | [diff] [blame] | 771 | 			chip->irq_cpu_offline(&desc->irq_data); | 
 | 772 |  | 
 | 773 | 		raw_spin_unlock_irqrestore(&desc->lock, flags); | 
 | 774 | 	} | 
 | 775 | } |