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review.evervolv.com / android_kernel_oneplus_msm8996 / deb7aab6379502fd173cd34efa005108eb0b111b / . / drivers / video / via / viamode.c
blob: 9ff9424ea6c359e1ed7cda6f2a095ab9bf63f9c6 [file] [log] [blame]
Joseph Chan9f291632008-10-15 22:03:29 -0700[diff] [blame]1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23struct res_map_refresh res_map_refresh_tbl[] = {
24/*hres, vres, vclock, vmode_refresh*/
25 {480, 640, RES_480X640_60HZ_PIXCLOCK, 60},
26 {640, 480, RES_640X480_60HZ_PIXCLOCK, 60},
27 {640, 480, RES_640X480_75HZ_PIXCLOCK, 75},
28 {640, 480, RES_640X480_85HZ_PIXCLOCK, 85},
29 {640, 480, RES_640X480_100HZ_PIXCLOCK, 100},
30 {640, 480, RES_640X480_120HZ_PIXCLOCK, 120},
31 {720, 480, RES_720X480_60HZ_PIXCLOCK, 60},
32 {720, 576, RES_720X576_60HZ_PIXCLOCK, 60},
33 {800, 480, RES_800X480_60HZ_PIXCLOCK, 60},
34 {800, 600, RES_800X600_60HZ_PIXCLOCK, 60},
35 {800, 600, RES_800X600_75HZ_PIXCLOCK, 75},
36 {800, 600, RES_800X600_85HZ_PIXCLOCK, 85},
37 {800, 600, RES_800X600_100HZ_PIXCLOCK, 100},
38 {800, 600, RES_800X600_120HZ_PIXCLOCK, 120},
39 {848, 480, RES_848X480_60HZ_PIXCLOCK, 60},
40 {856, 480, RES_856X480_60HZ_PIXCLOCK, 60},
41 {1024, 512, RES_1024X512_60HZ_PIXCLOCK, 60},
42 {1024, 600, RES_1024X600_60HZ_PIXCLOCK, 60},
43 {1024, 768, RES_1024X768_60HZ_PIXCLOCK, 60},
44 {1024, 768, RES_1024X768_75HZ_PIXCLOCK, 75},
45 {1024, 768, RES_1024X768_85HZ_PIXCLOCK, 85},
46 {1024, 768, RES_1024X768_100HZ_PIXCLOCK, 100},
47/* {1152,864, RES_1152X864_70HZ_PIXCLOCK, 70},*/
48 {1152, 864, RES_1152X864_75HZ_PIXCLOCK, 75},
49 {1280, 768, RES_1280X768_60HZ_PIXCLOCK, 60},
50 {1280, 800, RES_1280X800_60HZ_PIXCLOCK, 60},
51 {1280, 960, RES_1280X960_60HZ_PIXCLOCK, 60},
52 {1280, 1024, RES_1280X1024_60HZ_PIXCLOCK, 60},
53 {1280, 1024, RES_1280X1024_75HZ_PIXCLOCK, 75},
54 {1280, 1024, RES_1280X768_85HZ_PIXCLOCK, 85},
55 {1440, 1050, RES_1440X1050_60HZ_PIXCLOCK, 60},
56 {1600, 1200, RES_1600X1200_60HZ_PIXCLOCK, 60},
57 {1600, 1200, RES_1600X1200_75HZ_PIXCLOCK, 75},
58 {1280, 720, RES_1280X720_60HZ_PIXCLOCK, 60},
59 {1920, 1080, RES_1920X1080_60HZ_PIXCLOCK, 60},
60 {1400, 1050, RES_1400X1050_60HZ_PIXCLOCK, 60},
61 {1400, 1050, RES_1400X1050_75HZ_PIXCLOCK, 75},
62 {1368, 768, RES_1368X768_60HZ_PIXCLOCK, 60},
63 {960, 600, RES_960X600_60HZ_PIXCLOCK, 60},
64 {1000, 600, RES_1000X600_60HZ_PIXCLOCK, 60},
65 {1024, 576, RES_1024X576_60HZ_PIXCLOCK, 60},
66 {1088, 612, RES_1088X612_60HZ_PIXCLOCK, 60},
67 {1152, 720, RES_1152X720_60HZ_PIXCLOCK, 60},
68 {1200, 720, RES_1200X720_60HZ_PIXCLOCK, 60},
69 {1280, 600, RES_1280X600_60HZ_PIXCLOCK, 60},
70 {1280, 720, RES_1280X720_50HZ_PIXCLOCK, 50},
71 {1280, 768, RES_1280X768_50HZ_PIXCLOCK, 50},
72 {1360, 768, RES_1360X768_60HZ_PIXCLOCK, 60},
73 {1366, 768, RES_1366X768_50HZ_PIXCLOCK, 50},
74 {1366, 768, RES_1366X768_60HZ_PIXCLOCK, 60},
75 {1440, 900, RES_1440X900_60HZ_PIXCLOCK, 60},
76 {1440, 900, RES_1440X900_75HZ_PIXCLOCK, 75},
77 {1600, 900, RES_1600X900_60HZ_PIXCLOCK, 60},
78 {1600, 1024, RES_1600X1024_60HZ_PIXCLOCK, 60},
79 {1680, 1050, RES_1680X1050_60HZ_PIXCLOCK, 60},
80 {1680, 1050, RES_1680X1050_75HZ_PIXCLOCK, 75},
81 {1792, 1344, RES_1792X1344_60HZ_PIXCLOCK, 60},
82 {1856, 1392, RES_1856X1392_60HZ_PIXCLOCK, 60},
83 {1920, 1200, RES_1920X1200_60HZ_PIXCLOCK, 60},
84 {1920, 1440, RES_1920X1440_60HZ_PIXCLOCK, 60},
85 {1920, 1440, RES_1920X1440_75HZ_PIXCLOCK, 75},
86 {2048, 1536, RES_2048X1536_60HZ_PIXCLOCK, 60}
87};
88
89struct io_reg CN400_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
90{VIASR, SR15, 0x02, 0x02},
91{VIASR, SR16, 0xBF, 0x08},
92{VIASR, SR17, 0xFF, 0x1F},
93{VIASR, SR18, 0xFF, 0x4E},
94{VIASR, SR1A, 0xFB, 0x08},
95{VIASR, SR1E, 0x0F, 0x01},
96{VIASR, SR2A, 0xFF, 0x00},
97{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
98{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
99{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
100{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
101{VIACR, CR32, 0xFF, 0x00},
102{VIACR, CR33, 0xFF, 0x00},
Joseph Chan9f291632008-10-15 22:03:29 -0700[diff] [blame]103{VIACR, CR35, 0xFF, 0x00},
104{VIACR, CR36, 0x08, 0x00},
Joseph Chan9f291632008-10-15 22:03:29 -0700[diff] [blame]105{VIACR, CR69, 0xFF, 0x00},
106{VIACR, CR6A, 0xFF, 0x40},
107{VIACR, CR6B, 0xFF, 0x00},
108{VIACR, CR6C, 0xFF, 0x00},
109{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
110{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
111{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
112{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
113{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
114{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
115{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
116{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
117{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
118{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
119{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
120{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
121{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
122{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
123{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
124{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
125{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
126{VIACR, CR8B, 0xFF, 0x69}, /* LCD Power Sequence Control 0 */
127{VIACR, CR8C, 0xFF, 0x57}, /* LCD Power Sequence Control 1 */
128{VIACR, CR8D, 0xFF, 0x00}, /* LCD Power Sequence Control 2 */
129{VIACR, CR8E, 0xFF, 0x7B}, /* LCD Power Sequence Control 3 */
130{VIACR, CR8F, 0xFF, 0x03}, /* LCD Power Sequence Control 4 */
131{VIACR, CR90, 0xFF, 0x30}, /* LCD Power Sequence Control 5 */
132{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
133{VIACR, CR96, 0xFF, 0x00},
134{VIACR, CR97, 0xFF, 0x00},
135{VIACR, CR99, 0xFF, 0x00},
136{VIACR, CR9B, 0xFF, 0x00}
137};
138
139/* Video Mode Table for VT3314 chipset*/
140/* Common Setting for Video Mode */
141struct io_reg CN700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
142{VIASR, SR15, 0x02, 0x02},
143{VIASR, SR16, 0xBF, 0x08},
144{VIASR, SR17, 0xFF, 0x1F},
145{VIASR, SR18, 0xFF, 0x4E},
146{VIASR, SR1A, 0xFB, 0x82},
147{VIASR, SR1B, 0xFF, 0xF0},
148{VIASR, SR1F, 0xFF, 0x00},
149{VIASR, SR1E, 0xFF, 0x01},
150{VIASR, SR22, 0xFF, 0x1F},
151{VIASR, SR2A, 0x0F, 0x00},
152{VIASR, SR2E, 0xFF, 0xFF},
153{VIASR, SR3F, 0xFF, 0xFF},
154{VIASR, SR40, 0xF7, 0x00},
155{VIASR, CR30, 0xFF, 0x04},
156{VIACR, CR32, 0xFF, 0x00},
157{VIACR, CR33, 0x7F, 0x00},
Joseph Chan9f291632008-10-15 22:03:29 -0700[diff] [blame]158{VIACR, CR35, 0xFF, 0x00},
159{VIACR, CR36, 0xFF, 0x31},
160{VIACR, CR41, 0xFF, 0x80},
161{VIACR, CR42, 0xFF, 0x00},
162{VIACR, CR55, 0x80, 0x00},
163{VIACR, CR5D, 0x80, 0x00}, /*Horizontal Retrace Start bit[11] should be 0*/
Joseph Chan9f291632008-10-15 22:03:29 -0700[diff] [blame]164{VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
165{VIACR, CR69, 0xFF, 0x00},
166{VIACR, CR6A, 0xFD, 0x40},
167{VIACR, CR6B, 0xFF, 0x00},
168{VIACR, CR6C, 0xFF, 0x00},
169{VIACR, CR77, 0xFF, 0x00}, /* LCD scaling Factor */
170{VIACR, CR78, 0xFF, 0x00}, /* LCD scaling Factor */
171{VIACR, CR79, 0xFF, 0x00}, /* LCD scaling Factor */
172{VIACR, CR9F, 0x03, 0x00}, /* LCD scaling Factor */
173{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
174{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
175{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
176{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
177{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
178{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
179{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
180{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
181{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
182{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
183{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
184{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
185{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
186{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
187{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
188{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
189{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
190{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
191{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
192{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
193{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
194{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
195{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
196{VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
197{VIACR, CR96, 0xFF, 0x00},
198{VIACR, CR97, 0xFF, 0x00},
199{VIACR, CR99, 0xFF, 0x00},
200{VIACR, CR9B, 0xFF, 0x00},
201{VIACR, CR9D, 0xFF, 0x80},
202{VIACR, CR9E, 0xFF, 0x80}
203};
204
205struct io_reg KM400_ModeXregs[] = {
206 {VIASR, SR10, 0xFF, 0x01}, /* Unlock Register */
207 {VIASR, SR16, 0xFF, 0x08}, /* Display FIFO threshold Control */
208 {VIASR, SR17, 0xFF, 0x1F}, /* Display FIFO Control */
209 {VIASR, SR18, 0xFF, 0x4E}, /* GFX PREQ threshold */
210 {VIASR, SR1A, 0xFF, 0x0a}, /* GFX PREQ threshold */
211 {VIASR, SR1F, 0xFF, 0x00}, /* Memory Control 0 */
212 {VIASR, SR1B, 0xFF, 0xF0}, /* Power Management Control 0 */
213 {VIASR, SR1E, 0xFF, 0x01}, /* Power Management Control */
214 {VIASR, SR20, 0xFF, 0x00}, /* Sequencer Arbiter Control 0 */
215 {VIASR, SR21, 0xFF, 0x00}, /* Sequencer Arbiter Control 1 */
216 {VIASR, SR22, 0xFF, 0x1F}, /* Display Arbiter Control 1 */
217 {VIASR, SR2A, 0xFF, 0x00}, /* Power Management Control 5 */
218 {VIASR, SR2D, 0xFF, 0xFF}, /* Power Management Control 1 */
219 {VIASR, SR2E, 0xFF, 0xFF}, /* Power Management Control 2 */
220 {VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
221 {VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
222 {VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
223 {VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
224 {VIACR, CR33, 0xFF, 0x00},
225 {VIACR, CR55, 0x80, 0x00},
226 {VIACR, CR5D, 0x80, 0x00},
227 {VIACR, CR36, 0xFF, 0x01}, /* Power Mangement 3 */
Joseph Chan9f291632008-10-15 22:03:29 -0700[diff] [blame]228 {VIACR, CR68, 0xFF, 0x67}, /* Default FIFO For IGA2 */
229 {VIACR, CR6A, 0x20, 0x20}, /* Extended FIFO On */
230 {VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
231 {VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
232 {VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
233 {VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
234 {VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
235 {VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
236 {VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
237 {VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
238 {VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
239 {VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
240 {VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
241 {VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
242 {VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
243 {VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
244 {VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
245 {VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
246 {VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
247 {VIACR, CR8B, 0xFF, 0x2D}, /* LCD Power Sequence Control 0 */
248 {VIACR, CR8C, 0xFF, 0x2D}, /* LCD Power Sequence Control 1 */
249 {VIACR, CR8D, 0xFF, 0xC8}, /* LCD Power Sequence Control 2 */
250 {VIACR, CR8E, 0xFF, 0x36}, /* LCD Power Sequence Control 3 */
251 {VIACR, CR8F, 0xFF, 0x00}, /* LCD Power Sequence Control 4 */
252 {VIACR, CR90, 0xFF, 0x10}, /* LCD Power Sequence Control 5 */
253 {VIACR, CR91, 0xFF, 0xA0}, /* 24/12 bit LVDS Data off */
254 {VIACR, CR96, 0xFF, 0x03}, /* DVP0 ; DVP0 Clock Skew */
255 {VIACR, CR97, 0xFF, 0x03}, /* DFP high ; DFPH Clock Skew */
256 {VIACR, CR99, 0xFF, 0x03}, /* DFP low ; DFPL Clock Skew*/
257 {VIACR, CR9B, 0xFF, 0x07} /* DVI on DVP1 ; DVP1 Clock Skew*/
258};
259
260/* For VT3324: Common Setting for Video Mode */
261struct io_reg CX700_ModeXregs[] = { {VIASR, SR10, 0xFF, 0x01},
262{VIASR, SR15, 0x02, 0x02},
263{VIASR, SR16, 0xBF, 0x08},
264{VIASR, SR17, 0xFF, 0x1F},
265{VIASR, SR18, 0xFF, 0x4E},
266{VIASR, SR1A, 0xFB, 0x08},
267{VIASR, SR1B, 0xFF, 0xF0},
268{VIASR, SR1E, 0xFF, 0x01},
269{VIASR, SR2A, 0xFF, 0x00},
270{VIASR, SR2D, 0xFF, 0xFF}, /* VCK and LCK PLL power on. */
271{VIACR, CR0A, 0xFF, 0x1E}, /* Cursor Start */
272{VIACR, CR0B, 0xFF, 0x00}, /* Cursor End */
273{VIACR, CR0E, 0xFF, 0x00}, /* Cursor Location High */
274{VIACR, CR0F, 0xFF, 0x00}, /* Cursor Localtion Low */
275{VIACR, CR32, 0xFF, 0x00},
276{VIACR, CR33, 0xFF, 0x00},
Joseph Chan9f291632008-10-15 22:03:29 -0700[diff] [blame]277{VIACR, CR35, 0xFF, 0x00},
278{VIACR, CR36, 0x08, 0x00},
279{VIACR, CR47, 0xC8, 0x00}, /* Clear VCK Plus. */
Joseph Chan9f291632008-10-15 22:03:29 -0700[diff] [blame]280{VIACR, CR69, 0xFF, 0x00},
281{VIACR, CR6A, 0xFF, 0x40},
282{VIACR, CR6B, 0xFF, 0x00},
283{VIACR, CR6C, 0xFF, 0x00},
284{VIACR, CR7A, 0xFF, 0x01}, /* LCD Scaling Parameter 1 */
285{VIACR, CR7B, 0xFF, 0x02}, /* LCD Scaling Parameter 2 */
286{VIACR, CR7C, 0xFF, 0x03}, /* LCD Scaling Parameter 3 */
287{VIACR, CR7D, 0xFF, 0x04}, /* LCD Scaling Parameter 4 */
288{VIACR, CR7E, 0xFF, 0x07}, /* LCD Scaling Parameter 5 */
289{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Scaling Parameter 6 */
290{VIACR, CR80, 0xFF, 0x0D}, /* LCD Scaling Parameter 7 */
291{VIACR, CR81, 0xFF, 0x13}, /* LCD Scaling Parameter 8 */
292{VIACR, CR82, 0xFF, 0x16}, /* LCD Scaling Parameter 9 */
293{VIACR, CR83, 0xFF, 0x19}, /* LCD Scaling Parameter 10 */
294{VIACR, CR84, 0xFF, 0x1C}, /* LCD Scaling Parameter 11 */
295{VIACR, CR85, 0xFF, 0x1D}, /* LCD Scaling Parameter 12 */
296{VIACR, CR86, 0xFF, 0x1E}, /* LCD Scaling Parameter 13 */
297{VIACR, CR87, 0xFF, 0x1F}, /* LCD Scaling Parameter 14 */
298{VIACR, CR88, 0xFF, 0x40}, /* LCD Panel Type */
299{VIACR, CR89, 0xFF, 0x00}, /* LCD Timing Control 0 */
300{VIACR, CR8A, 0xFF, 0x88}, /* LCD Timing Control 1 */
301{VIACR, CRD4, 0xFF, 0x81}, /* Second power sequence control */
302{VIACR, CR8B, 0xFF, 0x5D}, /* LCD Power Sequence Control 0 */
303{VIACR, CR8C, 0xFF, 0x2B}, /* LCD Power Sequence Control 1 */
304{VIACR, CR8D, 0xFF, 0x6F}, /* LCD Power Sequence Control 2 */
305{VIACR, CR8E, 0xFF, 0x2B}, /* LCD Power Sequence Control 3 */
306{VIACR, CR8F, 0xFF, 0x01}, /* LCD Power Sequence Control 4 */
307{VIACR, CR90, 0xFF, 0x01}, /* LCD Power Sequence Control 5 */
308{VIACR, CR91, 0xFF, 0x80}, /* 24/12 bit LVDS Data off */
309{VIACR, CR96, 0xFF, 0x00},
310{VIACR, CR97, 0xFF, 0x00},
311{VIACR, CR99, 0xFF, 0x00},
312{VIACR, CR9B, 0xFF, 0x00},
313{VIACR, CRD2, 0xFF, 0xFF} /* TMDS/LVDS control register. */
314};
315
Joseph Chan9f291632008-10-15 22:03:29 -0700[diff] [blame]316/* Video Mode Table */
317/* Common Setting for Video Mode */
318struct io_reg CLE266_ModeXregs[] = { {VIASR, SR1E, 0xF0, 0x00},
319{VIASR, SR2A, 0x0F, 0x00},
320{VIASR, SR15, 0x02, 0x02},
321{VIASR, SR16, 0xBF, 0x08},
322{VIASR, SR17, 0xFF, 0x1F},
323{VIASR, SR18, 0xFF, 0x4E},
324{VIASR, SR1A, 0xFB, 0x08},
325
326{VIACR, CR32, 0xFF, 0x00},
Joseph Chan9f291632008-10-15 22:03:29 -0700[diff] [blame]327{VIACR, CR35, 0xFF, 0x00},
328{VIACR, CR36, 0x08, 0x00},
329{VIACR, CR6A, 0xFF, 0x80},
330{VIACR, CR6A, 0xFF, 0xC0},
331
332{VIACR, CR55, 0x80, 0x00},
333{VIACR, CR5D, 0x80, 0x00},
334
335{VIAGR, GR20, 0xFF, 0x00},
336{VIAGR, GR21, 0xFF, 0x00},
337{VIAGR, GR22, 0xFF, 0x00},
338 /* LCD Parameters */
339{VIACR, CR7A, 0xFF, 0x01}, /* LCD Parameter 1 */
340{VIACR, CR7B, 0xFF, 0x02}, /* LCD Parameter 2 */
341{VIACR, CR7C, 0xFF, 0x03}, /* LCD Parameter 3 */
342{VIACR, CR7D, 0xFF, 0x04}, /* LCD Parameter 4 */
343{VIACR, CR7E, 0xFF, 0x07}, /* LCD Parameter 5 */
344{VIACR, CR7F, 0xFF, 0x0A}, /* LCD Parameter 6 */
345{VIACR, CR80, 0xFF, 0x0D}, /* LCD Parameter 7 */
346{VIACR, CR81, 0xFF, 0x13}, /* LCD Parameter 8 */
347{VIACR, CR82, 0xFF, 0x16}, /* LCD Parameter 9 */
348{VIACR, CR83, 0xFF, 0x19}, /* LCD Parameter 10 */
349{VIACR, CR84, 0xFF, 0x1C}, /* LCD Parameter 11 */
350{VIACR, CR85, 0xFF, 0x1D}, /* LCD Parameter 12 */
351{VIACR, CR86, 0xFF, 0x1E}, /* LCD Parameter 13 */
352{VIACR, CR87, 0xFF, 0x1F}, /* LCD Parameter 14 */
353
354};
355
356/* Mode:1024X768 */
357struct io_reg PM1024x768[] = { {VIASR, 0x16, 0xBF, 0x0C},
358{VIASR, 0x18, 0xFF, 0x4C}
359};
360
361struct patch_table res_patch_table[] = {
362 {VIA_RES_1024X768, ARRAY_SIZE(PM1024x768), PM1024x768}
363};
364
365/* struct VPITTable {
366 unsigned char Misc;
367 unsigned char SR[StdSR];
368 unsigned char CR[StdCR];
369 unsigned char GR[StdGR];
370 unsigned char AR[StdAR];
371 };*/
372
373struct VPITTable VPIT = {
374 /* Msic */
375 0xC7,
376 /* Sequencer */
377 {0x01, 0x0F, 0x00, 0x0E},
378 /* Graphic Controller */
379 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0F, 0xFF},
380 /* Attribute Controller */
381 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
382 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
383 0x01, 0x00, 0x0F, 0x00}
384};
385
386/********************/
387/* Mode Table */
388/********************/
389
390/* 480x640 */
391struct crt_mode_table CRTM480x640[] = {
392 /* r_rate, vclk, hsp, vsp */
393 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
394 {REFRESH_60, CLK_25_175M, M480X640_R60_HSP, M480X640_R60_VSP,
395 {624, 480, 480, 144, 504, 48, 663, 640, 640, 23, 641, 3} } /* GTF*/
396};
397
398/* 640x480*/
399struct crt_mode_table CRTM640x480[] = {
400 /*r_rate,vclk,hsp,vsp */
401 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
402 {REFRESH_60, CLK_25_175M, M640X480_R60_HSP, M640X480_R60_VSP,
403 {800, 640, 648, 144, 656, 96, 525, 480, 480, 45, 490, 2} },
404 {REFRESH_75, CLK_31_500M, M640X480_R75_HSP, M640X480_R75_VSP,
405 {840, 640, 640, 200, 656, 64, 500, 480, 480, 20, 481, 3} },
406 {REFRESH_85, CLK_36_000M, M640X480_R85_HSP, M640X480_R85_VSP,
407 {832, 640, 640, 192, 696, 56, 509, 480, 480, 29, 481, 3} },
408 {REFRESH_100, CLK_43_163M, M640X480_R100_HSP, M640X480_R100_VSP,
409 {848, 640, 640, 208, 680, 64, 509, 480, 480, 29, 481, 3} }, /*GTF*/
410 {REFRESH_120, CLK_52_406M, M640X480_R120_HSP,
411 M640X480_R120_VSP,
412 {848, 640, 640, 208, 680, 64, 515, 480, 480, 35, 481,
413 3} } /*GTF*/
414};
415
416/*720x480 (GTF)*/
417struct crt_mode_table CRTM720x480[] = {
418 /*r_rate,vclk,hsp,vsp */
419 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
420 {REFRESH_60, CLK_26_880M, M720X480_R60_HSP, M720X480_R60_VSP,
421 {896, 720, 720, 176, 736, 72, 497, 480, 480, 17, 481, 3} }
422
423};
424
425/*720x576 (GTF)*/
426struct crt_mode_table CRTM720x576[] = {
427 /*r_rate,vclk,hsp,vsp */
428 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
429 {REFRESH_60, CLK_32_668M, M720X576_R60_HSP, M720X576_R60_VSP,
430 {912, 720, 720, 192, 744, 72, 597, 576, 576, 21, 577, 3} }
431};
432
433/* 800x480 (CVT) */
434struct crt_mode_table CRTM800x480[] = {
435 /* r_rate, vclk, hsp, vsp */
436 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
437 {REFRESH_60, CLK_29_581M, M800X480_R60_HSP, M800X480_R60_VSP,
438 {992, 800, 800, 192, 824, 72, 500, 480, 480, 20, 483, 7} }
439};
440
441/* 800x600*/
442struct crt_mode_table CRTM800x600[] = {
443 /*r_rate,vclk,hsp,vsp */
444 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
445 {REFRESH_60, CLK_40_000M, M800X600_R60_HSP, M800X600_R60_VSP,
446 {1056, 800, 800, 256, 840, 128, 628, 600, 600, 28, 601, 4} },
447 {REFRESH_75, CLK_49_500M, M800X600_R75_HSP, M800X600_R75_VSP,
448 {1056, 800, 800, 256, 816, 80, 625, 600, 600, 25, 601, 3} },
449 {REFRESH_85, CLK_56_250M, M800X600_R85_HSP, M800X600_R85_VSP,
450 {1048, 800, 800, 248, 832, 64, 631, 600, 600, 31, 601, 3} },
451 {REFRESH_100, CLK_68_179M, M800X600_R100_HSP, M800X600_R100_VSP,
452 {1072, 800, 800, 272, 848, 88, 636, 600, 600, 36, 601, 3} },
453 {REFRESH_120, CLK_83_950M, M800X600_R120_HSP,
454 M800X600_R120_VSP,
455 {1088, 800, 800, 288, 856, 88, 643, 600, 600, 43, 601,
456 3} }
457};
458
459/* 848x480 (CVT) */
460struct crt_mode_table CRTM848x480[] = {
461 /* r_rate, vclk, hsp, vsp */
462 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
463 {REFRESH_60, CLK_31_500M, M848X480_R60_HSP, M848X480_R60_VSP,
464 {1056, 848, 848, 208, 872, 80, 500, 480, 480, 20, 483, 5} }
465};
466
467/*856x480 (GTF) convert to 852x480*/
468struct crt_mode_table CRTM852x480[] = {
469 /*r_rate,vclk,hsp,vsp */
470 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
471 {REFRESH_60, CLK_31_728M, M852X480_R60_HSP, M852X480_R60_VSP,
472 {1064, 856, 856, 208, 872, 88, 497, 480, 480, 17, 481, 3} }
473};
474
475/*1024x512 (GTF)*/
476struct crt_mode_table CRTM1024x512[] = {
477 /*r_rate,vclk,hsp,vsp */
478 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
479 {REFRESH_60, CLK_41_291M, M1024X512_R60_HSP, M1024X512_R60_VSP,
480 {1296, 1024, 1024, 272, 1056, 104, 531, 512, 512, 19, 513, 3} }
481
482};
483
484/* 1024x600*/
485struct crt_mode_table CRTM1024x600[] = {
486 /*r_rate,vclk,hsp,vsp */
487 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
488 {REFRESH_60, CLK_48_875M, M1024X600_R60_HSP, M1024X600_R60_VSP,
489 {1312, 1024, 1024, 288, 1064, 104, 622, 600, 600, 22, 601, 3} },
490};
491
492/* 1024x768*/
493struct crt_mode_table CRTM1024x768[] = {
494 /*r_rate,vclk,hsp,vsp */
495 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
496 {REFRESH_60, CLK_65_000M, M1024X768_R60_HSP, M1024X768_R60_VSP,
497 {1344, 1024, 1024, 320, 1048, 136, 806, 768, 768, 38, 771, 6} },
498 {REFRESH_75, CLK_78_750M, M1024X768_R75_HSP, M1024X768_R75_VSP,
499 {1312, 1024, 1024, 288, 1040, 96, 800, 768, 768, 32, 769, 3} },
500 {REFRESH_85, CLK_94_500M, M1024X768_R85_HSP, M1024X768_R85_VSP,
501 {1376, 1024, 1024, 352, 1072, 96, 808, 768, 768, 40, 769, 3} },
502 {REFRESH_100, CLK_113_309M, M1024X768_R100_HSP, M1024X768_R100_VSP,
503 {1392, 1024, 1024, 368, 1096, 112, 814, 768, 768, 46, 769, 3} }
504};
505
506/* 1152x864*/
507struct crt_mode_table CRTM1152x864[] = {
508 /*r_rate,vclk,hsp,vsp */
509 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
510 {REFRESH_75, CLK_108_000M, M1152X864_R75_HSP, M1152X864_R75_VSP,
511 {1600, 1152, 1152, 448, 1216, 128, 900, 864, 864, 36, 865, 3} }
512
513};
514
515/* 1280x720 (HDMI 720P)*/
516struct crt_mode_table CRTM1280x720[] = {
517 /*r_rate,vclk,hsp,vsp */
518 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
519 {REFRESH_60, CLK_74_481M, M1280X720_R60_HSP, M1280X720_R60_VSP,
520 {1648, 1280, 1280, 368, 1392, 40, 750, 720, 720, 30, 725, 5} },
521 {REFRESH_50, CLK_60_466M, M1280X720_R50_HSP, M1280X720_R50_VSP,
522 {1632, 1280, 1280, 352, 1328, 128, 741, 720, 720, 21, 721, 3} }
523};
524
525/*1280x768 (GTF)*/
526struct crt_mode_table CRTM1280x768[] = {
527 /*r_rate,vclk,hsp,vsp */
528 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
529 {REFRESH_60, CLK_80_136M, M1280X768_R60_HSP, M1280X768_R60_VSP,
530 {1680, 1280, 1280, 400, 1344, 136, 795, 768, 768, 27, 769, 3} },
531 {REFRESH_50, CLK_65_178M, M1280X768_R50_HSP, M1280X768_R50_VSP,
532 {1648, 1280, 1280, 368, 1336, 128, 791, 768, 768, 23, 769, 3} }
533};
534
535/* 1280x800 (CVT) */
536struct crt_mode_table CRTM1280x800[] = {
537 /* r_rate, vclk, hsp, vsp */
538 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
539 {REFRESH_60, CLK_83_375M, M1280X800_R60_HSP, M1280X800_R60_VSP,
540 {1680, 1280, 1280, 400, 1352, 128, 831, 800, 800, 31, 803, 6} }
541};
542
543/*1280x960*/
544struct crt_mode_table CRTM1280x960[] = {
545 /*r_rate,vclk,hsp,vsp */
546 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
547 {REFRESH_60, CLK_108_000M, M1280X960_R60_HSP, M1280X960_R60_VSP,
548 {1800, 1280, 1280, 520, 1376, 112, 1000, 960, 960, 40, 961, 3} }
549};
550
551/* 1280x1024*/
552struct crt_mode_table CRTM1280x1024[] = {
553 /*r_rate,vclk,,hsp,vsp */
554 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
555 {REFRESH_60, CLK_108_000M, M1280X1024_R60_HSP, M1280X1024_R60_VSP,
556 {1688, 1280, 1280, 408, 1328, 112, 1066, 1024, 1024, 42, 1025,
557 3} },
558 {REFRESH_75, CLK_135_000M, M1280X1024_R75_HSP, M1280X1024_R75_VSP,
559 {1688, 1280, 1280, 408, 1296, 144, 1066, 1024, 1024, 42, 1025,
560 3} },
561 {REFRESH_85, CLK_157_500M, M1280X1024_R85_HSP, M1280X1024_R85_VSP,
562 {1728, 1280, 1280, 448, 1344, 160, 1072, 1024, 1024, 48, 1025, 3} }
563};
564
565/* 1368x768 (GTF) */
566struct crt_mode_table CRTM1368x768[] = {
567 /* r_rate, vclk, hsp, vsp */
568 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
569 {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP,
570 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} }
571};
572
573/*1440x1050 (GTF)*/
574struct crt_mode_table CRTM1440x1050[] = {
575 /*r_rate,vclk,hsp,vsp */
576 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
577 {REFRESH_60, CLK_125_104M, M1440X1050_R60_HSP, M1440X1050_R60_VSP,
578 {1936, 1440, 1440, 496, 1536, 152, 1077, 1040, 1040, 37, 1041, 3} }
579};
580
581/* 1600x1200*/
582struct crt_mode_table CRTM1600x1200[] = {
583 /*r_rate,vclk,hsp,vsp */
584 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
585 {REFRESH_60, CLK_162_000M, M1600X1200_R60_HSP, M1600X1200_R60_VSP,
586 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201,
587 3} },
588 {REFRESH_75, CLK_202_500M, M1600X1200_R75_HSP, M1600X1200_R75_VSP,
589 {2160, 1600, 1600, 560, 1664, 192, 1250, 1200, 1200, 50, 1201, 3} }
590
591};
592
593/* 1680x1050 (CVT) */
594struct crt_mode_table CRTM1680x1050[] = {
595 /* r_rate, vclk, hsp, vsp */
596 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
597 {REFRESH_60, CLK_146_760M, M1680x1050_R60_HSP, M1680x1050_R60_VSP,
598 {2240, 1680, 1680, 560, 1784, 176, 1089, 1050, 1050, 39, 1053,
599 6} },
600 {REFRESH_75, CLK_187_000M, M1680x1050_R75_HSP, M1680x1050_R75_VSP,
601 {2272, 1680, 1680, 592, 1800, 176, 1099, 1050, 1050, 49, 1053, 6} }
602};
603
604/* 1680x1050 (CVT Reduce Blanking) */
605struct crt_mode_table CRTM1680x1050_RB[] = {
606 /* r_rate, vclk, hsp, vsp */
607 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
608 {REFRESH_60, CLK_119_000M, M1680x1050_RB_R60_HSP,
609 M1680x1050_RB_R60_VSP,
610 {1840, 1680, 1680, 160, 1728, 32, 1080, 1050, 1050, 30, 1053, 6} }
611};
612
613/* 1920x1080 (CVT)*/
614struct crt_mode_table CRTM1920x1080[] = {
615 /*r_rate,vclk,hsp,vsp */
616 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
617 {REFRESH_60, CLK_172_798M, M1920X1080_R60_HSP, M1920X1080_R60_VSP,
618 {2576, 1920, 1920, 656, 2048, 200, 1120, 1080, 1080, 40, 1083, 5} }
619};
620
621/* 1920x1080 (CVT with Reduce Blanking) */
622struct crt_mode_table CRTM1920x1080_RB[] = {
623 /* r_rate, vclk, hsp, vsp */
624 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
625 {REFRESH_60, CLK_138_400M, M1920X1080_RB_R60_HSP,
626 M1920X1080_RB_R60_VSP,
627 {2080, 1920, 1920, 160, 1968, 32, 1111, 1080, 1080, 31, 1083, 5} }
628};
629
630/* 1920x1440*/
631struct crt_mode_table CRTM1920x1440[] = {
632 /*r_rate,vclk,hsp,vsp */
633 /*HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
634 {REFRESH_60, CLK_234_000M, M1920X1440_R60_HSP, M1920X1440_R60_VSP,
635 {2600, 1920, 1920, 680, 2048, 208, 1500, 1440, 1440, 60, 1441,
636 3} },
637 {REFRESH_75, CLK_297_500M, M1920X1440_R75_HSP, M1920X1440_R75_VSP,
638 {2640, 1920, 1920, 720, 2064, 224, 1500, 1440, 1440, 60, 1441, 3} }
639};
640
641/* 1400x1050 (CVT) */
642struct crt_mode_table CRTM1400x1050[] = {
643 /* r_rate, vclk, hsp, vsp */
644 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
645 {REFRESH_60, CLK_121_750M, M1400X1050_R60_HSP, M1400X1050_R60_VSP,
646 {1864, 1400, 1400, 464, 1488, 144, 1089, 1050, 1050, 39, 1053,
647 4} },
648 {REFRESH_75, CLK_156_000M, M1400X1050_R75_HSP, M1400X1050_R75_VSP,
649 {1896, 1400, 1400, 496, 1504, 144, 1099, 1050, 1050, 49, 1053, 4} }
650};
651
652/* 1400x1050 (CVT Reduce Blanking) */
653struct crt_mode_table CRTM1400x1050_RB[] = {
654 /* r_rate, vclk, hsp, vsp */
655 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
656 {REFRESH_60, CLK_101_000M, M1400X1050_RB_R60_HSP,
657 M1400X1050_RB_R60_VSP,
658 {1560, 1400, 1400, 160, 1448, 32, 1080, 1050, 1050, 30, 1053, 4} }
659};
660
661/* 960x600 (CVT) */
662struct crt_mode_table CRTM960x600[] = {
663 /* r_rate, vclk, hsp, vsp */
664 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
665 {REFRESH_60, CLK_45_250M, M960X600_R60_HSP, M960X600_R60_VSP,
666 {1216, 960, 960, 256, 992, 96, 624, 600, 600, 24, 603, 6} }
667};
668
669/* 1000x600 (GTF) */
670struct crt_mode_table CRTM1000x600[] = {
671 /* r_rate, vclk, hsp, vsp */
672 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
673 {REFRESH_60, CLK_48_000M, M1000X600_R60_HSP, M1000X600_R60_VSP,
674 {1288, 1000, 1000, 288, 1040, 104, 622, 600, 600, 22, 601, 3} }
675};
676
677/* 1024x576 (GTF) */
678struct crt_mode_table CRTM1024x576[] = {
679 /* r_rate, vclk, hsp, vsp */
680 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
681 {REFRESH_60, CLK_46_996M, M1024X576_R60_HSP, M1024X576_R60_VSP,
682 {1312, 1024, 1024, 288, 1064, 104, 597, 576, 576, 21, 577, 3} }
683};
684
685/* 1088x612 (CVT) */
686struct crt_mode_table CRTM1088x612[] = {
687 /* r_rate, vclk, hsp, vsp */
688 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
689 {REFRESH_60, CLK_52_977M, M1088X612_R60_HSP, M1088X612_R60_VSP,
690 {1392, 1088, 1088, 304, 1136, 104, 636, 612, 612, 24, 615, 5} }
691};
692
693/* 1152x720 (CVT) */
694struct crt_mode_table CRTM1152x720[] = {
695 /* r_rate, vclk, hsp, vsp */
696 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
697 {REFRESH_60, CLK_66_750M, M1152X720_R60_HSP, M1152X720_R60_VSP,
698 {1488, 1152, 1152, 336, 1208, 112, 748, 720, 720, 28, 723, 6} }
699};
700
701/* 1200x720 (GTF) */
702struct crt_mode_table CRTM1200x720[] = {
703 /* r_rate, vclk, hsp, vsp */
704 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
705 {REFRESH_60, CLK_70_159M, M1200X720_R60_HSP, M1200X720_R60_VSP,
706 {1568, 1200, 1200, 368, 1256, 128, 746, 720, 720, 26, 721, 3} }
707};
708
709/* 1280x600 (GTF) */
710struct crt_mode_table CRTM1280x600[] = {
711 /* r_rate, vclk, hsp, vsp */
712 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
713 {REFRESH_60, CLK_61_500M, M1280x600_R60_HSP, M1280x600_R60_VSP,
714 {1648, 1280, 1280, 368, 1336, 128, 622, 600, 600, 22, 601, 3} }
715};
716
717/* 1360x768 (CVT) */
718struct crt_mode_table CRTM1360x768[] = {
719 /* r_rate, vclk, hsp, vsp */
720 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
721 {REFRESH_60, CLK_84_750M, M1360X768_R60_HSP, M1360X768_R60_VSP,
722 {1776, 1360, 1360, 416, 1432, 136, 798, 768, 768, 30, 771, 5} }
723};
724
725/* 1360x768 (CVT Reduce Blanking) */
726struct crt_mode_table CRTM1360x768_RB[] = {
727 /* r_rate, vclk, hsp, vsp */
728 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
729 {REFRESH_60, CLK_72_000M, M1360X768_RB_R60_HSP,
730 M1360X768_RB_R60_VSP,
731 {1520, 1360, 1360, 160, 1408, 32, 790, 768, 768, 22, 771, 5} }
732};
733
734/* 1366x768 (GTF) */
735struct crt_mode_table CRTM1366x768[] = {
736 /* r_rate, vclk, hsp, vsp */
737 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
738 {REFRESH_60, CLK_85_860M, M1368X768_R60_HSP, M1368X768_R60_VSP,
739 {1800, 1368, 1368, 432, 1440, 144, 795, 768, 768, 27, 769, 3} },
740 {REFRESH_50, CLK_69_924M, M1368X768_R50_HSP, M1368X768_R50_VSP,
741 {1768, 1368, 1368, 400, 1424, 144, 791, 768, 768, 23, 769, 3} }
742};
743
744/* 1440x900 (CVT) */
745struct crt_mode_table CRTM1440x900[] = {
746 /* r_rate, vclk, hsp, vsp */
747 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
748 {REFRESH_60, CLK_106_500M, M1440X900_R60_HSP, M1440X900_R60_VSP,
749 {1904, 1440, 1440, 464, 1520, 152, 934, 900, 900, 34, 903, 6} },
750 {REFRESH_75, CLK_136_700M, M1440X900_R75_HSP, M1440X900_R75_VSP,
751 {1936, 1440, 1440, 496, 1536, 152, 942, 900, 900, 42, 903, 6} }
752};
753
754/* 1440x900 (CVT Reduce Blanking) */
755struct crt_mode_table CRTM1440x900_RB[] = {
756 /* r_rate, vclk, hsp, vsp */
757 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
758 {REFRESH_60, CLK_88_750M, M1440X900_RB_R60_HSP,
759 M1440X900_RB_R60_VSP,
760 {1600, 1440, 1440, 160, 1488, 32, 926, 900, 900, 26, 903, 6} }
761};
762
763/* 1600x900 (CVT) */
764struct crt_mode_table CRTM1600x900[] = {
765 /* r_rate, vclk, hsp, vsp */
766 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
767 {REFRESH_60, CLK_118_840M, M1600X900_R60_HSP, M1600X900_R60_VSP,
768 {2112, 1600, 1600, 512, 1688, 168, 934, 900, 900, 34, 903, 5} }
769};
770
771/* 1600x900 (CVT Reduce Blanking) */
772struct crt_mode_table CRTM1600x900_RB[] = {
773 /* r_rate, vclk, hsp, vsp */
774 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
775 {REFRESH_60, CLK_97_750M, M1600X900_RB_R60_HSP,
776 M1600X900_RB_R60_VSP,
777 {1760, 1600, 1600, 160, 1648, 32, 926, 900, 900, 26, 903, 5} }
778};
779
780/* 1600x1024 (GTF) */
781struct crt_mode_table CRTM1600x1024[] = {
782 /* r_rate, vclk, hsp, vsp */
783 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
784 {REFRESH_60, CLK_136_700M, M1600X1024_R60_HSP, M1600X1024_R60_VSP,
785 {2144, 1600, 1600, 544, 1704, 168, 1060, 1024, 1024, 36, 1025, 3} }
786};
787
788/* 1792x1344 (DMT) */
789struct crt_mode_table CRTM1792x1344[] = {
790 /* r_rate, vclk, hsp, vsp */
791 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
792 {REFRESH_60, CLK_204_000M, M1792x1344_R60_HSP, M1792x1344_R60_VSP,
793 {2448, 1792, 1792, 656, 1920, 200, 1394, 1344, 1344, 50, 1345, 3} }
794};
795
796/* 1856x1392 (DMT) */
797struct crt_mode_table CRTM1856x1392[] = {
798 /* r_rate, vclk, hsp, vsp */
799 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
800 {REFRESH_60, CLK_218_500M, M1856x1392_R60_HSP, M1856x1392_R60_VSP,
801 {2528, 1856, 1856, 672, 1952, 224, 1439, 1392, 1392, 47, 1393, 3} }
802};
803
804/* 1920x1200 (CVT) */
805struct crt_mode_table CRTM1920x1200[] = {
806 /* r_rate, vclk, hsp, vsp */
807 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
808 {REFRESH_60, CLK_193_295M, M1920X1200_R60_HSP, M1920X1200_R60_VSP,
809 {2592, 1920, 1920, 672, 2056, 200, 1245, 1200, 1200, 45, 1203, 6} }
810};
811
812/* 1920x1200 (CVT with Reduce Blanking) */
813struct crt_mode_table CRTM1920x1200_RB[] = {
814 /* r_rate, vclk, hsp, vsp */
815 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
816 {REFRESH_60, CLK_153_920M, M1920X1200_RB_R60_HSP,
817 M1920X1200_RB_R60_VSP,
818 {2080, 1920, 1920, 160, 1968, 32, 1235, 1200, 1200, 35, 1203, 6} }
819};
820
821/* 2048x1536 (CVT) */
822struct crt_mode_table CRTM2048x1536[] = {
823 /* r_rate, vclk, hsp, vsp */
824 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
825 {REFRESH_60, CLK_267_250M, M2048x1536_R60_HSP, M2048x1536_R60_VSP,
826 {2800, 2048, 2048, 752, 2200, 224, 1592, 1536, 1536, 56, 1539, 4} }
827};
828
829/* Video Mode Table */
830/* struct VideoModeTable {*/
831/* int ModeIndex;*/
832/* struct crt_mode_table *crtc;*/
833/* int mode_array;*/
834/* };*/
835struct VideoModeTable CLE266Modes[] = {
836 /* Display : 480x640 (GTF) */
837 {VIA_RES_480X640, CRTM480x640, ARRAY_SIZE(CRTM480x640)},
838
839 /* Display : 640x480 */
840 {VIA_RES_640X480, CRTM640x480, ARRAY_SIZE(CRTM640x480)},
841
842 /* Display : 720x480 (GTF) */
843 {VIA_RES_720X480, CRTM720x480, ARRAY_SIZE(CRTM720x480)},
844
845 /* Display : 720x576 (GTF) */
846 {VIA_RES_720X576, CRTM720x576, ARRAY_SIZE(CRTM720x576)},
847
848 /* Display : 800x600 */
849 {VIA_RES_800X600, CRTM800x600, ARRAY_SIZE(CRTM800x600)},
850
851 /* Display : 800x480 (CVT) */
852 {VIA_RES_800X480, CRTM800x480, ARRAY_SIZE(CRTM800x480)},
853
854 /* Display : 848x480 (CVT) */
855 {VIA_RES_848X480, CRTM848x480, ARRAY_SIZE(CRTM848x480)},
856
857 /* Display : 852x480 (GTF) */
858 {VIA_RES_856X480, CRTM852x480, ARRAY_SIZE(CRTM852x480)},
859
860 /* Display : 1024x512 (GTF) */
861 {VIA_RES_1024X512, CRTM1024x512, ARRAY_SIZE(CRTM1024x512)},
862
863 /* Display : 1024x600 */
864 {VIA_RES_1024X600, CRTM1024x600, ARRAY_SIZE(CRTM1024x600)},
865
866 /* Display : 1024x576 (GTF) */
867 /*{ VIA_RES_1024X576, CRTM1024x576, ARRAY_SIZE(CRTM1024x576)}, */
868
869 /* Display : 1024x768 */
870 {VIA_RES_1024X768, CRTM1024x768, ARRAY_SIZE(CRTM1024x768)},
871
872 /* Display : 1152x864 */
873 {VIA_RES_1152X864, CRTM1152x864, ARRAY_SIZE(CRTM1152x864)},
874
875 /* Display : 1280x768 (GTF) */
876 {VIA_RES_1280X768, CRTM1280x768, ARRAY_SIZE(CRTM1280x768)},
877
878 /* Display : 960x600 (CVT) */
879 {VIA_RES_960X600, CRTM960x600, ARRAY_SIZE(CRTM960x600)},
880
881 /* Display : 1000x600 (GTF) */
882 {VIA_RES_1000X600, CRTM1000x600, ARRAY_SIZE(CRTM1000x600)},
883
884 /* Display : 1024x576 (GTF) */
885 {VIA_RES_1024X576, CRTM1024x576, ARRAY_SIZE(CRTM1024x576)},
886
887 /* Display : 1088x612 (GTF) */
888 {VIA_RES_1088X612, CRTM1088x612, ARRAY_SIZE(CRTM1088x612)},
889
890 /* Display : 1152x720 (CVT) */
891 {VIA_RES_1152X720, CRTM1152x720, ARRAY_SIZE(CRTM1152x720)},
892
893 /* Display : 1200x720 (GTF) */
894 {VIA_RES_1200X720, CRTM1200x720, ARRAY_SIZE(CRTM1200x720)},
895
896 /* Display : 1280x600 (GTF) */
897 {VIA_RES_1280X600, CRTM1280x600, ARRAY_SIZE(CRTM1280x600)},
898
899 /* Display : 1280x800 (CVT) */
900 {VIA_RES_1280X800, CRTM1280x800, ARRAY_SIZE(CRTM1280x800)},
901
902 /* Display : 1280x800 (GTF) */
903 /*{ M1280x800, CRTM1280x800, ARRAY_SIZE(CRTM1280x800)}, */
904
905 /* Display : 1280x960 */
906 {VIA_RES_1280X960, CRTM1280x960, ARRAY_SIZE(CRTM1280x960)},
907
908 /* Display : 1280x1024 */
909 {VIA_RES_1280X1024, CRTM1280x1024, ARRAY_SIZE(CRTM1280x1024)},
910
911 /* Display : 1360x768 (CVT) */
912 {VIA_RES_1360X768, CRTM1360x768, ARRAY_SIZE(CRTM1360x768)},
913
914 /* Display : 1360x768 (CVT Reduce Blanking) */
915 {VIA_RES_1360X768_RB, CRTM1360x768_RB,
916 ARRAY_SIZE(CRTM1360x768_RB)},
917
918 /* Display : 1366x768 */
919 {VIA_RES_1366X768, CRTM1366x768, ARRAY_SIZE(CRTM1366x768)},
920
921 /* Display : 1368x768 (GTF) */
922 /*{ M1368x768,CRTM1368x768,ARRAY_SIZE(CRTM1368x768)}, */
923 /* Display : 1368x768 (GTF) */
924 {VIA_RES_1368X768, CRTM1368x768, ARRAY_SIZE(CRTM1368x768)},
925
926 /* Display : 1440x900 (CVT) */
927 {VIA_RES_1440X900, CRTM1440x900, ARRAY_SIZE(CRTM1440x900)},
928
929 /* Display : 1440x900 (CVT Reduce Blanking) */
930 {VIA_RES_1440X900_RB, CRTM1440x900_RB,
931 ARRAY_SIZE(CRTM1440x900_RB)},
932
933 /* Display : 1440x1050 (GTF) */
934 {VIA_RES_1440X1050, CRTM1440x1050, ARRAY_SIZE(CRTM1440x1050)},
935
936 /* Display : 1400x1050 (CVT Reduce Blanking) */
937 {VIA_RES_1400X1050_RB, CRTM1400x1050_RB,
938 ARRAY_SIZE(CRTM1400x1050_RB)},
939
940 /* Display : 1600x900 (CVT) */
941 {VIA_RES_1600X900, CRTM1600x900, ARRAY_SIZE(CRTM1600x900)},
942
943 /* Display : 1600x900 (CVT Reduce Blanking) */
944 {VIA_RES_1600X900_RB, CRTM1600x900_RB,
945 ARRAY_SIZE(CRTM1600x900_RB)},
946
947 /* Display : 1600x1024 (GTF) */
948 {VIA_RES_1600X1024, CRTM1600x1024, ARRAY_SIZE(CRTM1600x1024)},
949
950 /* Display : 1600x1200 */
951 {VIA_RES_1600X1200, CRTM1600x1200, ARRAY_SIZE(CRTM1600x1200)},
952
953 /* Display : 1680x1050 (CVT) */
954 {VIA_RES_1680X1050, CRTM1680x1050, ARRAY_SIZE(CRTM1680x1050)},
955
956 /* Display : 1680x1050 (CVT Reduce Blanking) */
957 {VIA_RES_1680X1050_RB, CRTM1680x1050_RB,
958 ARRAY_SIZE(CRTM1680x1050_RB)},
959
960 /* Display : 1792x1344 (DMT) */
961 {VIA_RES_1792X1344, CRTM1792x1344, ARRAY_SIZE(CRTM1792x1344)},
962
963 /* Display : 1856x1392 (DMT) */
964 {VIA_RES_1856X1392, CRTM1856x1392, ARRAY_SIZE(CRTM1856x1392)},
965
966 /* Display : 1920x1440 */
967 {VIA_RES_1920X1440, CRTM1920x1440, ARRAY_SIZE(CRTM1920x1440)},
968
969 /* Display : 2048x1536 */
970 {VIA_RES_2048X1536, CRTM2048x1536, ARRAY_SIZE(CRTM2048x1536)},
971
972 /* Display : 1280x720 */
973 {VIA_RES_1280X720, CRTM1280x720, ARRAY_SIZE(CRTM1280x720)},
974
975 /* Display : 1920x1080 (CVT) */
976 {VIA_RES_1920X1080, CRTM1920x1080, ARRAY_SIZE(CRTM1920x1080)},
977
978 /* Display : 1920x1080 (CVT Reduce Blanking) */
979 {VIA_RES_1920X1080_RB, CRTM1920x1080_RB,
980 ARRAY_SIZE(CRTM1920x1080_RB)},
981
982 /* Display : 1920x1200 (CVT) */
983 {VIA_RES_1920X1200, CRTM1920x1200, ARRAY_SIZE(CRTM1920x1200)},
984
985 /* Display : 1920x1200 (CVT Reduce Blanking) */
986 {VIA_RES_1920X1200_RB, CRTM1920x1200_RB,
987 ARRAY_SIZE(CRTM1920x1200_RB)},
988
989 /* Display : 1400x1050 (CVT) */
990 {VIA_RES_1400X1050, CRTM1400x1050, ARRAY_SIZE(CRTM1400x1050)}
991};
992struct crt_mode_table CEAM1280x720[] = {
993 {REFRESH_60, CLK_74_270M, M1280X720_CEA_R60_HSP,
994 M1280X720_CEA_R60_VSP,
995 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
996 {1650, 1280, 1280, 370, 1390, 40, 750, 720, 720, 30, 725, 5} }
997};
998struct crt_mode_table CEAM1920x1080[] = {
999 {REFRESH_60, CLK_148_500M, M1920X1080_CEA_R60_HSP,
1000 M1920X1080_CEA_R60_VSP,
1001 /* HT, HA, HBS, HBE, HSS, HSE, VT, VA, VBS, VBE, VSS, VSE */
1002 {2200, 1920, 1920, 300, 2008, 44, 1125, 1080, 1080, 45, 1084, 5} }
1003};
1004struct VideoModeTable CEA_HDMI_Modes[] = {
1005 /* Display : 1280x720 */
1006 {VIA_RES_1280X720, CEAM1280x720, ARRAY_SIZE(CEAM1280x720)},
1007 {VIA_RES_1920X1080, CEAM1920x1080, ARRAY_SIZE(CEAM1920x1080)}
1008};
Florian Tobias Schandinatdeb7aab2009-09-22 16:47:16 -0700[diff] [blame^]1009
1010int NUM_TOTAL_RES_MAP_REFRESH = ARRAY_SIZE(res_map_refresh_tbl);
1011int NUM_TOTAL_CEA_MODES = ARRAY_SIZE(CEA_HDMI_Modes);
1012int NUM_TOTAL_CN400_ModeXregs = ARRAY_SIZE(CN400_ModeXregs);
1013int NUM_TOTAL_CN700_ModeXregs = ARRAY_SIZE(CN700_ModeXregs);
1014int NUM_TOTAL_KM400_ModeXregs = ARRAY_SIZE(KM400_ModeXregs);
1015int NUM_TOTAL_CX700_ModeXregs = ARRAY_SIZE(CX700_ModeXregs);
1016int NUM_TOTAL_CLE266_ModeXregs = ARRAY_SIZE(CLE266_ModeXregs);
1017int NUM_TOTAL_PATCH_MODE = ARRAY_SIZE(res_patch_table);
1018int NUM_TOTAL_MODETABLE = ARRAY_SIZE(CLE266Modes);